[Pkg-clamav-commits] [SCM] Debian repository for ClamAV branch, debian/unstable, updated. debian/0.95+dfsg-1-6156-g094ec9b
Török Edvin
edwin at clamav.net
Sun Apr 4 01:22:15 UTC 2010
The following commit has been merged in the debian/unstable branch:
commit 5f42f86347689c72e6018376dd2a2e7570256953
Author: Török Edvin <edwin at clamav.net>
Date: Sat Mar 6 20:41:32 2010 +0200
Update autogenerated files.
diff --git a/libclamav/c++/ARMGenAsmWriter.inc b/libclamav/c++/ARMGenAsmWriter.inc
index c0909e4..7a289a3 100644
--- a/libclamav/c++/ARMGenAsmWriter.inc
+++ b/libclamav/c++/ARMGenAsmWriter.inc
@@ -25,19 +25,19 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
67108875U, // ADCSSri
67108875U, // ADCSSrr
67108875U, // ADCSSrs
- 134758417U, // ADCri
- 134774801U, // ADCrr
+ 134750225U, // ADCri
+ 134758417U, // ADCrr
202375185U, // ADCrs
- 135839765U, // ADDSri
- 135839765U, // ADDSrr
- 202948629U, // ADDSrs
- 134758426U, // ADDri
- 134774810U, // ADDrr
+ 135815189U, // ADDSri
+ 135815189U, // ADDSrr
+ 202924053U, // ADDSrs
+ 134750234U, // ADDri
+ 134758426U, // ADDrr
202375194U, // ADDrs
69206046U, // ADJCALLSTACKDOWN
69206066U, // ADJCALLSTACKUP
- 134758468U, // ANDri
- 134774852U, // ANDrr
+ 134750276U, // ANDri
+ 134758468U, // ANDrr
202375236U, // ANDrs
271056968U, // ATOMIC_CMP_SWAP_I16
271581256U, // ATOMIC_CMP_SWAP_I32
@@ -64,1622 +64,1969 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
282591304U, // ATOMIC_SWAP_I32
283115592U, // ATOMIC_SWAP_I8
69206089U, // B
- 135839820U, // BFC
- 134758480U, // BICri
- 134774864U, // BICrr
- 202375248U, // BICrs
- 337166420U, // BKPT
- 402653273U, // BL
- 69206109U, // BLX
- 69206109U, // BLXr9
- 337182818U, // BL_pred
- 402653273U, // BLr9
- 337182818U, // BLr9_pred
- 69206117U, // BRIND
- 67108969U, // BR_JTadd
- 469762162U, // BR_JTm
- 82313339U, // BR_JTr
- 69206148U, // BX
- 337166484U, // BXJ
- 552599704U, // BX_RET
- 69206148U, // BXr9
- 337166491U, // Bcc
- 620314781U, // CDP
- 687866017U, // CDP2
- 739819688U, // CLZ
- 739819692U, // CMNzri
- 739819692U, // CMNzrr
- 806928556U, // CMNzrs
- 739819696U, // CMPri
- 739819696U, // CMPrr
- 806928560U, // CMPrs
- 739819696U, // CMPzri
- 739819696U, // CMPzrr
- 806928560U, // CMPzrs
+ 135815244U, // BFC
+ 135815248U, // BFI
+ 134750292U, // BICri
+ 134758484U, // BICrr
+ 202375252U, // BICrs
+ 337141848U, // BKPT
+ 402653277U, // BL
+ 69206113U, // BLX
+ 69206113U, // BLXr9
+ 337150054U, // BL_pred
+ 402653277U, // BLr9
+ 337150054U, // BLr9_pred
+ 69206121U, // BRIND
+ 67108973U, // BR_JTadd
+ 485007478U, // BR_JTm
+ 82362495U, // BR_JTr
+ 69206152U, // BX
+ 337141912U, // BXJ
+ 552599708U, // BX_RET
+ 69206152U, // BXr9
+ 337141919U, // Bcc
+ 620290209U, // CDP
+ 687866021U, // CDP2
+ 172U, // CLREX
+ 739795122U, // CLZ
+ 739795126U, // CMNzri
+ 739795126U, // CMNzrr
+ 806903990U, // CMNzrs
+ 739795130U, // CMPri
+ 739795130U, // CMPrr
+ 806903994U, // CMPrs
+ 739795130U, // CMPzri
+ 739795130U, // CMPzrr
+ 806903994U, // CMPzrs
872415304U, // CONSTPOOL_ENTRY
- 939524276U, // CPS
- 337166520U, // DBG
- 134758588U, // EORri
- 134774972U, // EORrr
- 202375356U, // EORrs
- 755597504U, // FCONSTD
- 756121792U, // FCONSTS
- 555221189U, // FMSTAT
- 85983434U, // Int_MemBarrierV6
- 215U, // Int_MemBarrierV7
- 86507722U, // Int_SyncBarrierV6
- 219U, // Int_SyncBarrierV7
- 87032031U, // Int_eh_sjlj_setjmp
- 1008320745U, // LDM
- 1008320745U, // LDM_RET
- 806928621U, // LDR
- 806928625U, // LDRB
- 202948849U, // LDRBT
- 202948849U, // LDRB_POST
- 202948849U, // LDRB_PRE
- 202948854U, // LDRD
- 739819771U, // LDREX
- 739819777U, // LDREXB
- 135840008U, // LDREXD
- 739819791U, // LDREXH
- 806928662U, // LDRH
- 202948886U, // LDRH_POST
- 202948886U, // LDRH_PRE
- 806928667U, // LDRSB
- 202948891U, // LDRSB_POST
- 202948891U, // LDRSB_PRE
- 806928673U, // LDRSH
- 202948897U, // LDRSH_POST
- 202948897U, // LDRSH_PRE
- 202948903U, // LDRT
- 202948845U, // LDR_POST
- 202948845U, // LDR_PRE
- 806928621U, // LDRcp
- 1094189356U, // LEApcrel
- 1094713644U, // LEApcrelJT
- 620331314U, // MCR
- 671121718U, // MCR2
- 217678141U, // MCRR
- 671121730U, // MCRR2
- 826802506U, // MLA
- 806928718U, // MLS
- 135840082U, // MOVCCi
- 135840082U, // MOVCCr
- 202948946U, // MOVCCs
- 135840086U, // MOVTi16
- 760349010U, // MOVi
- 739819867U, // MOVi16
- 739819858U, // MOVi2pieces
- 739819867U, // MOVi32imm
- 760217938U, // MOVr
- 760217938U, // MOVrx
- 826949970U, // MOVs
- 739819872U, // MOVsra_flag
- 739819872U, // MOVsrl_flag
- 620331365U, // MRC
- 671121769U, // MRC2
- 217678192U, // MRRC
- 671121781U, // MRRC2
- 337166717U, // MRS
- 337166717U, // MRSsys
- 358089085U, // MSR
- 358613373U, // MSRsys
- 134775169U, // MUL
- 760349061U, // MVNi
- 760217989U, // MVNr
- 826950021U, // MVNs
- 538968457U, // NOP
- 134758797U, // ORRri
- 134775181U, // ORRrr
- 202375565U, // ORRrs
- 1164444049U, // PICADD
- 1232077201U, // PICLDR
- 1232601489U, // PICLDRB
- 1233125777U, // PICLDRH
- 1233650065U, // PICLDRSB
- 1234174353U, // PICLDRSH
- 1234698641U, // PICSTR
- 1235222929U, // PICSTRB
- 1235747217U, // PICSTRH
- 806928787U, // PKHBT
- 806928793U, // PKHTB
- 135840159U, // QADD
- 135840164U, // QADD16
- 135840171U, // QADD8
- 135840177U, // QASX
- 135840182U, // QDADD
- 135840188U, // QDSUB
- 135840194U, // QSAX
- 135840199U, // QSUB
- 135840204U, // QSUB16
- 135840211U, // QSUB8
- 739819993U, // RBIT
- 739819998U, // REV
- 739820002U, // REV16
- 739820008U, // REVSH
- 135840238U, // RSBSri
- 202949102U, // RSBSrs
- 134758899U, // RSBri
- 202375667U, // RSBrs
- 67109367U, // RSCSri
- 67109367U, // RSCSrs
- 134758909U, // RSCri
- 202375677U, // RSCrs
- 67109377U, // SBCSSri
- 67109377U, // SBCSSrr
- 67109377U, // SBCSSrs
- 134758919U, // SBCri
- 134775303U, // SBCrr
- 202375687U, // SBCrs
- 806928907U, // SBFX
- 528U, // SETENDBE
- 538U, // SETENDLE
- 538968612U, // SEV
- 806928936U, // SMLABB
- 806928943U, // SMLABT
- 826802742U, // SMLAL
- 806928956U, // SMLALBB
- 806928964U, // SMLALBT
- 806928972U, // SMLALTB
- 806928980U, // SMLALTT
- 806928988U, // SMLATB
- 806928995U, // SMLATT
- 806929002U, // SMLAWB
- 806929009U, // SMLAWT
- 806929016U, // SMMLA
- 806929022U, // SMMLS
- 135840388U, // SMMUL
- 135840394U, // SMULBB
- 135840401U, // SMULBT
- 826802840U, // SMULL
- 135840414U, // SMULTB
- 135840421U, // SMULTT
- 135840428U, // SMULWB
- 135840435U, // SMULWT
- 1008321210U, // STM
- 806929086U, // STR
- 806929090U, // STRB
- 202900167U, // STRBT
- 202900162U, // STRB_POST
- 202900162U, // STRB_PRE
- 202949325U, // STRD
- 135840466U, // STREX
- 135840472U, // STREXB
- 806929119U, // STREXD
- 135840486U, // STREXH
- 806929133U, // STRH
- 202900205U, // STRH_POST
- 202900205U, // STRH_PRE
- 202900210U, // STRT
- 202900158U, // STR_POST
- 202900158U, // STR_PRE
- 135840503U, // SUBSri
- 135840503U, // SUBSrr
- 202949367U, // SUBSrs
- 134759164U, // SUBri
- 134775548U, // SUBrr
- 202375932U, // SUBrs
- 337167104U, // SVC
- 135840516U, // SWP
- 135840520U, // SWPB
- 135840525U, // SXTABrr
- 806929165U, // SXTABrr_rot
- 135840531U, // SXTAHrr
- 806929171U, // SXTAHrr_rot
- 739820313U, // SXTBr
- 135840537U, // SXTBr_rot
- 739820318U, // SXTHr
- 135840542U, // SXTHr_rot
- 739820323U, // TEQri
- 739820323U, // TEQrr
- 806929187U, // TEQrs
- 807U, // TPsoft
- 538968890U, // TRAP
- 739820351U, // TSTri
- 739820351U, // TSTrr
- 806929215U, // TSTrs
- 806929219U, // UBFX
- 806929224U, // UMAAL
- 826803022U, // UMLAL
- 826803028U, // UMULL
- 135840602U, // UQADD16
- 135840610U, // UQADD8
- 135840617U, // UQASX
- 135840623U, // UQSAX
- 135840629U, // UQSUB16
- 135840637U, // UQSUB8
- 135840644U, // UXTABrr
- 806929284U, // UXTABrr_rot
- 135840650U, // UXTAHrr
- 806929290U, // UXTAHrr_rot
- 739820432U, // UXTB16r
- 135840656U, // UXTB16r_rot
- 739820439U, // UXTBr
- 135840663U, // UXTBr_rot
- 739820444U, // UXTHr
- 135840668U, // UXTHr_rot
- 833651617U, // VABALsv2i64
- 834175905U, // VABALsv4i32
- 834700193U, // VABALsv8i16
- 835224481U, // VABALuv2i64
- 835748769U, // VABALuv4i32
- 836273057U, // VABALuv8i16
- 834700199U, // VABAsv16i8
- 833651623U, // VABAsv2i32
- 834175911U, // VABAsv4i16
- 833651623U, // VABAsv4i32
- 834175911U, // VABAsv8i16
- 834700199U, // VABAsv8i8
- 836273063U, // VABAuv16i8
- 835224487U, // VABAuv2i32
- 835748775U, // VABAuv4i16
- 835224487U, // VABAuv4i32
- 835748775U, // VABAuv8i16
- 836273063U, // VABAuv8i8
- 162530220U, // VABDLsv2i64
- 163054508U, // VABDLsv4i32
- 163578796U, // VABDLsv8i16
- 164103084U, // VABDLuv2i64
- 164627372U, // VABDLuv4i32
- 165151660U, // VABDLuv8i16
- 152142770U, // VABDfd
- 152142770U, // VABDfq
- 163578802U, // VABDsv16i8
- 162530226U, // VABDsv2i32
- 163054514U, // VABDsv4i16
- 162530226U, // VABDsv4i32
- 163054514U, // VABDsv8i16
- 163578802U, // VABDsv8i8
- 165151666U, // VABDuv16i8
- 164103090U, // VABDuv2i32
- 164627378U, // VABDuv4i16
- 164103090U, // VABDuv4i32
- 164627378U, // VABDuv8i16
- 165151666U, // VABDuv8i8
- 755598263U, // VABSD
- 756122551U, // VABSS
- 756122551U, // VABSfd
- 756122551U, // VABSfd_sfp
- 756122551U, // VABSfq
- 767558583U, // VABSv16i8
- 766510007U, // VABSv2i32
- 767034295U, // VABSv4i16
- 766510007U, // VABSv4i32
- 767034295U, // VABSv8i16
- 767558583U, // VABSv8i8
- 152142780U, // VACGEd
- 152142780U, // VACGEq
- 152142786U, // VACGTd
- 152142786U, // VACGTq
- 151618504U, // VADDD
- 165675981U, // VADDHNv2i32
- 166200269U, // VADDHNv4i16
- 166724557U, // VADDHNv8i8
- 162530260U, // VADDLsv2i64
- 163054548U, // VADDLsv4i32
- 163578836U, // VADDLsv8i16
- 164103124U, // VADDLuv2i64
- 164627412U, // VADDLuv4i32
- 165151700U, // VADDLuv8i16
- 152142792U, // VADDS
- 162530266U, // VADDWsv2i64
- 163054554U, // VADDWsv4i32
- 163578842U, // VADDWsv8i16
- 164103130U, // VADDWuv2i64
- 164627418U, // VADDWuv4i32
- 165151706U, // VADDWuv8i16
- 152142792U, // VADDfd
- 152142792U, // VADDfd_sfp
- 152142792U, // VADDfq
- 167248840U, // VADDv16i8
- 165675976U, // VADDv1i64
- 166200264U, // VADDv2i32
- 165675976U, // VADDv2i64
- 166724552U, // VADDv4i16
- 166200264U, // VADDv4i32
- 166724552U, // VADDv8i16
- 167248840U, // VADDv8i8
- 135840736U, // VANDd
- 135840736U, // VANDq
- 135840741U, // VBICd
- 135840741U, // VBICq
- 806929386U, // VBIFd
- 806929386U, // VBIFq
- 806929391U, // VBITd
- 806929391U, // VBITq
- 806929396U, // VBSLd
- 806929396U, // VBSLq
- 152142841U, // VCEQfd
- 152142841U, // VCEQfq
- 167248889U, // VCEQv16i8
- 166200313U, // VCEQv2i32
- 166724601U, // VCEQv4i16
- 166200313U, // VCEQv4i32
- 166724601U, // VCEQv8i16
- 167248889U, // VCEQv8i8
- 152142846U, // VCGEfd
- 152142846U, // VCGEfq
- 163578878U, // VCGEsv16i8
- 162530302U, // VCGEsv2i32
- 163054590U, // VCGEsv4i16
- 162530302U, // VCGEsv4i32
- 163054590U, // VCGEsv8i16
- 163578878U, // VCGEsv8i8
- 165151742U, // VCGEuv16i8
- 164103166U, // VCGEuv2i32
- 164627454U, // VCGEuv4i16
- 164103166U, // VCGEuv4i32
- 164627454U, // VCGEuv8i16
- 165151742U, // VCGEuv8i8
- 152142851U, // VCGTfd
- 152142851U, // VCGTfq
- 163578883U, // VCGTsv16i8
- 162530307U, // VCGTsv2i32
- 163054595U, // VCGTsv4i16
- 162530307U, // VCGTsv4i32
- 163054595U, // VCGTsv8i16
- 163578883U, // VCGTsv8i8
- 165151747U, // VCGTuv16i8
- 164103171U, // VCGTuv2i32
- 164627459U, // VCGTuv4i16
- 164103171U, // VCGTuv4i32
- 164627459U, // VCGTuv8i16
- 165151747U, // VCGTuv8i8
- 767558664U, // VCLSv16i8
- 766510088U, // VCLSv2i32
- 767034376U, // VCLSv4i16
- 766510088U, // VCLSv4i32
- 767034376U, // VCLSv8i16
- 767558664U, // VCLSv8i8
- 771228685U, // VCLZv16i8
- 770180109U, // VCLZv2i32
- 770704397U, // VCLZv4i16
- 770180109U, // VCLZv4i32
- 770704397U, // VCLZv8i16
- 771228685U, // VCLZv8i8
- 755598354U, // VCMPD
- 755598359U, // VCMPED
- 756122647U, // VCMPES
- 353010711U, // VCMPEZD
- 353534999U, // VCMPEZS
- 756122642U, // VCMPS
- 353010706U, // VCMPZD
- 353534994U, // VCMPZS
- 771802141U, // VCNTd
- 771802141U, // VCNTq
- 772277282U, // VCVTBHS
- 772801570U, // VCVTBSH
- 773325864U, // VCVTDS
- 773850152U, // VCVTSD
- 772277293U, // VCVTTHS
- 772801581U, // VCVTTSH
- 774554664U, // VCVTf2sd
- 774554664U, // VCVTf2sd_sfp
- 774554664U, // VCVTf2sq
- 775078952U, // VCVTf2ud
- 775078952U, // VCVTf2ud_sfp
- 775078952U, // VCVTf2uq
- 170492968U, // VCVTf2xsd
- 170492968U, // VCVTf2xsq
- 171017256U, // VCVTf2xud
- 171017256U, // VCVTf2xuq
- 775603240U, // VCVTs2fd
- 775603240U, // VCVTs2fd_sfp
- 775603240U, // VCVTs2fq
- 776127528U, // VCVTu2fd
- 776127528U, // VCVTu2fd_sfp
- 776127528U, // VCVTu2fq
- 171541544U, // VCVTxs2fd
- 171541544U, // VCVTxs2fq
- 172065832U, // VCVTxu2fd
- 172065832U, // VCVTxu2fq
- 151618611U, // VDIVD
- 152142899U, // VDIVS
- 776520760U, // VDUP16d
- 776520760U, // VDUP16q
- 777045048U, // VDUP32d
- 777045048U, // VDUP32q
- 771802168U, // VDUP8d
- 771802168U, // VDUP8q
- 172540984U, // VDUPLN16d
- 172540984U, // VDUPLN16q
- 173065272U, // VDUPLN32d
- 173065272U, // VDUPLN32q
- 167822392U, // VDUPLN8d
- 167822392U, // VDUPLN8q
- 173065272U, // VDUPLNfd
- 173065272U, // VDUPLNfq
- 777045048U, // VDUPfd
- 777045048U, // VDUPfdf
- 777045048U, // VDUPfq
- 777045048U, // VDUPfqf
- 135840829U, // VEORd
- 135840829U, // VEORq
- 843629634U, // VEXTd16
- 844153922U, // VEXTd32
- 838911042U, // VEXTd8
- 844153922U, // VEXTdf
- 843629634U, // VEXTq16
- 844153922U, // VEXTq32
- 838911042U, // VEXTq8
- 844153922U, // VEXTqf
- 173064384U, // VGETLNi32
- 163053760U, // VGETLNs16
- 163578048U, // VGETLNs8
- 164626624U, // VGETLNu16
- 165150912U, // VGETLNu8
- 163578951U, // VHADDsv16i8
- 162530375U, // VHADDsv2i32
- 163054663U, // VHADDsv4i16
- 162530375U, // VHADDsv4i32
- 163054663U, // VHADDsv8i16
- 163578951U, // VHADDsv8i8
- 165151815U, // VHADDuv16i8
- 164103239U, // VHADDuv2i32
- 164627527U, // VHADDuv4i16
- 164103239U, // VHADDuv4i32
- 164627527U, // VHADDuv8i16
- 165151815U, // VHADDuv8i8
- 163578957U, // VHSUBsv16i8
- 162530381U, // VHSUBsv2i32
- 163054669U, // VHSUBsv4i16
- 162530381U, // VHSUBsv4i32
- 163054669U, // VHSUBsv8i16
- 163578957U, // VHSUBsv8i8
- 165151821U, // VHSUBuv16i8
- 164103245U, // VHSUBuv2i32
- 164627533U, // VHSUBuv4i16
- 164103245U, // VHSUBuv4i32
- 164627533U, // VHSUBuv8i16
- 165151821U, // VHSUBuv8i8
- 240698451U, // VLD1d16
- 241222739U, // VLD1d32
- 241747027U, // VLD1d64
- 242271315U, // VLD1d8
- 241222739U, // VLD1df
- 239797331U, // VLD1q16
- 240321619U, // VLD1q32
- 242943059U, // VLD1q64
- 235078739U, // VLD1q8
- 240321619U, // VLD1qf
- 1314440280U, // VLD2LNd16
- 1314964568U, // VLD2LNd32
- 1316013144U, // VLD2LNd8
- 1314440280U, // VLD2LNq16a
- 1314440280U, // VLD2LNq16b
- 1314964568U, // VLD2LNq32a
- 1314964568U, // VLD2LNq32b
- 643351640U, // VLD2d16
- 643875928U, // VLD2d32
- 644400211U, // VLD2d64
- 644924504U, // VLD2d8
- 1381549144U, // VLD2q16
- 1382073432U, // VLD2q32
- 1383122008U, // VLD2q8
- 1448658013U, // VLD3LNd16
- 1449182301U, // VLD3LNd32
- 1450230877U, // VLD3LNd8
- 1448658013U, // VLD3LNq16a
- 1448658013U, // VLD3LNq16b
- 1449182301U, // VLD3LNq32a
- 1449182301U, // VLD3LNq32b
- 1515766877U, // VLD3d16
- 1516291165U, // VLD3d32
- 1516815443U, // VLD3d64
- 1517339741U, // VLD3d8
- 1381549149U, // VLD3q16a
- 1381549149U, // VLD3q16b
- 1382073437U, // VLD3q32a
- 1382073437U, // VLD3q32b
- 1383122013U, // VLD3q8a
- 1383122013U, // VLD3q8b
- 1582875746U, // VLD4LNd16
- 1583400034U, // VLD4LNd32
- 1584448610U, // VLD4LNd8
- 1582875746U, // VLD4LNq16a
- 1582875746U, // VLD4LNq16b
- 1583400034U, // VLD4LNq32a
- 1583400034U, // VLD4LNq32b
- 1381549154U, // VLD4d16
- 1382073442U, // VLD4d32
- 1382597715U, // VLD4d64
- 1383122018U, // VLD4d8
- 1314440290U, // VLD4q16a
- 1314440290U, // VLD4q16b
- 1314964578U, // VLD4q32a
- 1314964578U, // VLD4q32b
- 1316013154U, // VLD4q8a
- 1316013154U, // VLD4q8b
- 1610613863U, // VLDMD
- 1610613863U, // VLDMS
- 175686764U, // VLDRD
- 136004721U, // VLDRQ
- 173065324U, // VLDRS
- 152142968U, // VMAXfd
- 152142968U, // VMAXfq
- 163579000U, // VMAXsv16i8
- 162530424U, // VMAXsv2i32
- 163054712U, // VMAXsv4i16
- 162530424U, // VMAXsv4i32
- 163054712U, // VMAXsv8i16
- 163579000U, // VMAXsv8i8
- 165151864U, // VMAXuv16i8
- 164103288U, // VMAXuv2i32
- 164627576U, // VMAXuv4i16
- 164103288U, // VMAXuv4i32
- 164627576U, // VMAXuv8i16
- 165151864U, // VMAXuv8i8
- 152142973U, // VMINfd
- 152142973U, // VMINfq
- 163579005U, // VMINsv16i8
- 162530429U, // VMINsv2i32
- 163054717U, // VMINsv4i16
- 162530429U, // VMINsv4i32
- 163054717U, // VMINsv8i16
- 163579005U, // VMINsv8i8
- 165151869U, // VMINuv16i8
- 164103293U, // VMINuv2i32
- 164627581U, // VMINuv4i16
- 164103293U, // VMINuv4i32
- 164627581U, // VMINuv8i16
- 165151869U, // VMINuv8i8
- 822707330U, // VMLAD
- 229672071U, // VMLALslsv2i32
- 230196359U, // VMLALslsv4i16
- 231244935U, // VMLALsluv2i32
- 231769223U, // VMLALsluv4i16
- 833651847U, // VMLALsv2i64
- 834176135U, // VMLALsv4i32
- 834700423U, // VMLALsv8i16
- 835224711U, // VMLALuv2i64
- 835748999U, // VMLALuv4i32
- 836273287U, // VMLALuv8i16
- 823231618U, // VMLAS
- 823231618U, // VMLAfd
- 823231618U, // VMLAfq
- 219251842U, // VMLAslfd
- 219251842U, // VMLAslfq
- 233342082U, // VMLAslv2i32
- 233866370U, // VMLAslv4i16
- 233342082U, // VMLAslv4i32
- 233866370U, // VMLAslv8i16
- 838370434U, // VMLAv16i8
- 837321858U, // VMLAv2i32
- 837846146U, // VMLAv4i16
- 837321858U, // VMLAv4i32
- 837846146U, // VMLAv8i16
- 838370434U, // VMLAv8i8
- 822707341U, // VMLSD
- 229672082U, // VMLSLslsv2i32
- 230196370U, // VMLSLslsv4i16
- 231244946U, // VMLSLsluv2i32
- 231769234U, // VMLSLsluv4i16
- 833651858U, // VMLSLsv2i64
- 834176146U, // VMLSLsv4i32
- 834700434U, // VMLSLsv8i16
- 835224722U, // VMLSLuv2i64
- 835749010U, // VMLSLuv4i32
- 836273298U, // VMLSLuv8i16
- 823231629U, // VMLSS
- 823231629U, // VMLSfd
- 823231629U, // VMLSfq
- 219251853U, // VMLSslfd
- 219251853U, // VMLSslfq
- 233342093U, // VMLSslv2i32
- 233866381U, // VMLSslv4i16
- 233342093U, // VMLSslv4i32
- 233866381U, // VMLSslv8i16
- 838370445U, // VMLSv16i8
- 837321869U, // VMLSv2i32
- 837846157U, // VMLSv4i16
- 837321869U, // VMLSv4i32
- 837846157U, // VMLSv8i16
- 838370445U, // VMLSv8i8
- 755597504U, // VMOVD
- 135839936U, // VMOVDRR
- 151617728U, // VMOVDcc
- 739819712U, // VMOVDneon
- 766510232U, // VMOVLsv2i64
- 767034520U, // VMOVLsv4i32
- 767558808U, // VMOVLsv8i16
- 768083096U, // VMOVLuv2i64
- 768607384U, // VMOVLuv4i32
- 769131672U, // VMOVLuv8i16
- 769655966U, // VMOVNv2i32
- 770180254U, // VMOVNv4i16
- 770704542U, // VMOVNv8i8
- 739819712U, // VMOVQ
- 135839936U, // VMOVRRD
- 806928576U, // VMOVRRS
- 739819712U, // VMOVRS
- 756121792U, // VMOVS
- 739819712U, // VMOVSR
- 806928576U, // VMOVSRR
- 152142016U, // VMOVScc
- 771457216U, // VMOVv16i8
- 769900736U, // VMOVv1i64
- 770441408U, // VMOVv2i32
- 769900736U, // VMOVv2i64
- 770982080U, // VMOVv4i16
- 770441408U, // VMOVv4i32
- 770982080U, // VMOVv8i16
- 771457216U, // VMOVv8i8
- 337166533U, // VMRS
- 377488548U, // VMSR
- 151618729U, // VMULD
- 176686254U, // VMULLp
- 833619118U, // VMULLslsv2i32
- 834143406U, // VMULLslsv4i16
- 835191982U, // VMULLsluv2i32
- 835716270U, // VMULLsluv4i16
- 162530478U, // VMULLsv2i64
- 163054766U, // VMULLsv4i32
- 163579054U, // VMULLsv8i16
- 164103342U, // VMULLuv2i64
- 164627630U, // VMULLuv4i32
- 165151918U, // VMULLuv8i16
- 152143017U, // VMULS
- 152143017U, // VMULfd
- 152143017U, // VMULfd_sfp
- 152143017U, // VMULfq
- 176686249U, // VMULpd
- 176686249U, // VMULpq
- 823231657U, // VMULslfd
- 823231657U, // VMULslfq
- 837289129U, // VMULslv2i32
- 837813417U, // VMULslv4i16
- 837289129U, // VMULslv4i32
- 837813417U, // VMULslv8i16
- 167249065U, // VMULv16i8
- 166200489U, // VMULv2i32
- 166724777U, // VMULv4i16
- 166200489U, // VMULv4i32
- 166724777U, // VMULv8i16
- 167249065U, // VMULv8i8
- 739820724U, // VMVNd
- 739820724U, // VMVNq
- 755598521U, // VNEGD
- 151618745U, // VNEGDcc
- 756122809U, // VNEGS
- 152143033U, // VNEGScc
- 756122809U, // VNEGf32d
- 756122809U, // VNEGf32d_sfp
- 756122809U, // VNEGf32q
- 767034553U, // VNEGs16d
- 767034553U, // VNEGs16q
- 766510265U, // VNEGs32d
- 766510265U, // VNEGs32q
- 767558841U, // VNEGs8d
- 767558841U, // VNEGs8q
- 822707390U, // VNMLAD
- 823231678U, // VNMLAS
- 822707396U, // VNMLSD
- 823231684U, // VNMLSS
- 151618762U, // VNMULD
- 152143050U, // VNMULS
- 135840976U, // VORNd
- 135840976U, // VORNq
- 135840981U, // VORRd
- 135840981U, // VORRq
- 163611866U, // VPADALsv16i8
- 162563290U, // VPADALsv2i32
- 163087578U, // VPADALsv4i16
- 162563290U, // VPADALsv4i32
- 163087578U, // VPADALsv8i16
- 163611866U, // VPADALsv8i8
- 165184730U, // VPADALuv16i8
- 164136154U, // VPADALuv2i32
- 164660442U, // VPADALuv4i16
- 164136154U, // VPADALuv4i32
- 164660442U, // VPADALuv8i16
- 165184730U, // VPADALuv8i8
- 767558881U, // VPADDLsv16i8
- 766510305U, // VPADDLsv2i32
- 767034593U, // VPADDLsv4i16
- 766510305U, // VPADDLsv4i32
- 767034593U, // VPADDLsv8i16
- 767558881U, // VPADDLsv8i8
- 769131745U, // VPADDLuv16i8
- 768083169U, // VPADDLuv2i32
- 768607457U, // VPADDLuv4i16
- 768083169U, // VPADDLuv4i32
- 768607457U, // VPADDLuv8i16
- 769131745U, // VPADDLuv8i8
- 152143080U, // VPADDf
- 166724840U, // VPADDi16
- 166200552U, // VPADDi32
- 167249128U, // VPADDi8
- 152143086U, // VPMAXf
- 163054830U, // VPMAXs16
- 162530542U, // VPMAXs32
- 163579118U, // VPMAXs8
- 164627694U, // VPMAXu16
- 164103406U, // VPMAXu32
- 165151982U, // VPMAXu8
- 152143092U, // VPMINf
- 163054836U, // VPMINs16
- 162530548U, // VPMINs32
- 163579124U, // VPMINs8
- 164627700U, // VPMINu16
- 164103412U, // VPMINu32
- 165151988U, // VPMINu8
- 767558906U, // VQABSv16i8
- 766510330U, // VQABSv2i32
- 767034618U, // VQABSv4i16
- 766510330U, // VQABSv4i32
- 767034618U, // VQABSv8i16
- 767558906U, // VQABSv8i8
- 163579136U, // VQADDsv16i8
- 177210624U, // VQADDsv1i64
- 162530560U, // VQADDsv2i32
- 177210624U, // VQADDsv2i64
- 163054848U, // VQADDsv4i16
- 162530560U, // VQADDsv4i32
- 163054848U, // VQADDsv8i16
- 163579136U, // VQADDsv8i8
- 165152000U, // VQADDuv16i8
- 177734912U, // VQADDuv1i64
- 164103424U, // VQADDuv2i32
- 177734912U, // VQADDuv2i64
- 164627712U, // VQADDuv4i16
- 164103424U, // VQADDuv4i32
- 164627712U, // VQADDuv8i16
- 165152000U, // VQADDuv8i8
- 229672198U, // VQDMLALslv2i32
- 230196486U, // VQDMLALslv4i16
- 833651974U, // VQDMLALv2i64
- 834176262U, // VQDMLALv4i32
- 229672206U, // VQDMLSLslv2i32
- 230196494U, // VQDMLSLslv4i16
- 833651982U, // VQDMLSLv2i64
- 834176270U, // VQDMLSLv4i32
- 833619222U, // VQDMULHslv2i32
- 834143510U, // VQDMULHslv4i16
- 833619222U, // VQDMULHslv4i32
- 834143510U, // VQDMULHslv8i16
- 162530582U, // VQDMULHv2i32
- 163054870U, // VQDMULHv4i16
- 162530582U, // VQDMULHv4i32
- 163054870U, // VQDMULHv8i16
- 833619230U, // VQDMULLslv2i32
- 834143518U, // VQDMULLslv4i16
- 162530590U, // VQDMULLv2i64
- 163054878U, // VQDMULLv4i32
- 781190438U, // VQMOVNsuv2i32
- 766510374U, // VQMOVNsuv4i16
- 767034662U, // VQMOVNsuv8i8
- 781190446U, // VQMOVNsv2i32
- 766510382U, // VQMOVNsv4i16
- 767034670U, // VQMOVNsv8i8
- 781714734U, // VQMOVNuv2i32
- 768083246U, // VQMOVNuv4i16
- 768607534U, // VQMOVNuv8i8
- 767558965U, // VQNEGv16i8
- 766510389U, // VQNEGv2i32
- 767034677U, // VQNEGv4i16
- 766510389U, // VQNEGv4i32
- 767034677U, // VQNEGv8i16
- 767558965U, // VQNEGv8i8
- 833619259U, // VQRDMULHslv2i32
- 834143547U, // VQRDMULHslv4i16
- 833619259U, // VQRDMULHslv4i32
- 834143547U, // VQRDMULHslv8i16
- 162530619U, // VQRDMULHv2i32
- 163054907U, // VQRDMULHv4i16
- 162530619U, // VQRDMULHv4i32
- 163054907U, // VQRDMULHv8i16
- 163579204U, // VQRSHLsv16i8
- 177210692U, // VQRSHLsv1i64
- 162530628U, // VQRSHLsv2i32
- 177210692U, // VQRSHLsv2i64
- 163054916U, // VQRSHLsv4i16
- 162530628U, // VQRSHLsv4i32
- 163054916U, // VQRSHLsv8i16
- 163579204U, // VQRSHLsv8i8
- 165152068U, // VQRSHLuv16i8
- 177734980U, // VQRSHLuv1i64
- 164103492U, // VQRSHLuv2i32
- 177734980U, // VQRSHLuv2i64
- 164627780U, // VQRSHLuv4i16
- 164103492U, // VQRSHLuv4i32
- 164627780U, // VQRSHLuv8i16
- 165152068U, // VQRSHLuv8i8
- 177210699U, // VQRSHRNsv2i32
- 162530635U, // VQRSHRNsv4i16
- 163054923U, // VQRSHRNsv8i8
- 177734987U, // VQRSHRNuv2i32
- 164103499U, // VQRSHRNuv4i16
- 164627787U, // VQRSHRNuv8i8
- 177210707U, // VQRSHRUNv2i32
- 162530643U, // VQRSHRUNv4i16
- 163054931U, // VQRSHRUNv8i8
- 163579228U, // VQSHLsiv16i8
- 177210716U, // VQSHLsiv1i64
- 162530652U, // VQSHLsiv2i32
- 177210716U, // VQSHLsiv2i64
- 163054940U, // VQSHLsiv4i16
- 162530652U, // VQSHLsiv4i32
- 163054940U, // VQSHLsiv8i16
- 163579228U, // VQSHLsiv8i8
- 163579234U, // VQSHLsuv16i8
- 177210722U, // VQSHLsuv1i64
- 162530658U, // VQSHLsuv2i32
- 177210722U, // VQSHLsuv2i64
- 163054946U, // VQSHLsuv4i16
- 162530658U, // VQSHLsuv4i32
- 163054946U, // VQSHLsuv8i16
- 163579234U, // VQSHLsuv8i8
- 163579228U, // VQSHLsv16i8
- 177210716U, // VQSHLsv1i64
- 162530652U, // VQSHLsv2i32
- 177210716U, // VQSHLsv2i64
- 163054940U, // VQSHLsv4i16
- 162530652U, // VQSHLsv4i32
- 163054940U, // VQSHLsv8i16
- 163579228U, // VQSHLsv8i8
- 165152092U, // VQSHLuiv16i8
- 177735004U, // VQSHLuiv1i64
- 164103516U, // VQSHLuiv2i32
- 177735004U, // VQSHLuiv2i64
- 164627804U, // VQSHLuiv4i16
- 164103516U, // VQSHLuiv4i32
- 164627804U, // VQSHLuiv8i16
- 165152092U, // VQSHLuiv8i8
- 165152092U, // VQSHLuv16i8
- 177735004U, // VQSHLuv1i64
- 164103516U, // VQSHLuv2i32
- 177735004U, // VQSHLuv2i64
- 164627804U, // VQSHLuv4i16
- 164103516U, // VQSHLuv4i32
- 164627804U, // VQSHLuv8i16
- 165152092U, // VQSHLuv8i8
- 177210729U, // VQSHRNsv2i32
- 162530665U, // VQSHRNsv4i16
- 163054953U, // VQSHRNsv8i8
- 177735017U, // VQSHRNuv2i32
- 164103529U, // VQSHRNuv4i16
- 164627817U, // VQSHRNuv8i8
- 177210736U, // VQSHRUNv2i32
- 162530672U, // VQSHRUNv4i16
- 163054960U, // VQSHRUNv8i8
- 163579256U, // VQSUBsv16i8
- 177210744U, // VQSUBsv1i64
- 162530680U, // VQSUBsv2i32
- 177210744U, // VQSUBsv2i64
- 163054968U, // VQSUBsv4i16
- 162530680U, // VQSUBsv4i32
- 163054968U, // VQSUBsv8i16
- 163579256U, // VQSUBsv8i8
- 165152120U, // VQSUBuv16i8
- 177735032U, // VQSUBuv1i64
- 164103544U, // VQSUBuv2i32
- 177735032U, // VQSUBuv2i64
- 164627832U, // VQSUBuv4i16
- 164103544U, // VQSUBuv4i32
- 164627832U, // VQSUBuv8i16
- 165152120U, // VQSUBuv8i8
- 165676414U, // VRADDHNv2i32
- 166200702U, // VRADDHNv4i16
- 166724990U, // VRADDHNv8i8
- 768083334U, // VRECPEd
- 756123014U, // VRECPEfd
- 756123014U, // VRECPEfq
- 768083334U, // VRECPEq
- 152143245U, // VRECPSfd
- 152143245U, // VRECPSfq
- 771802516U, // VREV16d8
- 771802516U, // VREV16q8
- 776521115U, // VREV32d16
- 771802523U, // VREV32d8
- 776521115U, // VREV32q16
- 771802523U, // VREV32q8
- 776521122U, // VREV64d16
- 777045410U, // VREV64d32
- 771802530U, // VREV64d8
- 777045410U, // VREV64df
- 776521122U, // VREV64q16
- 777045410U, // VREV64q32
- 771802530U, // VREV64q8
- 777045410U, // VREV64qf
- 163579305U, // VRHADDsv16i8
- 162530729U, // VRHADDsv2i32
- 163055017U, // VRHADDsv4i16
- 162530729U, // VRHADDsv4i32
- 163055017U, // VRHADDsv8i16
- 163579305U, // VRHADDsv8i8
- 165152169U, // VRHADDuv16i8
- 164103593U, // VRHADDuv2i32
- 164627881U, // VRHADDuv4i16
- 164103593U, // VRHADDuv4i32
- 164627881U, // VRHADDuv8i16
- 165152169U, // VRHADDuv8i8
- 163579312U, // VRSHLsv16i8
- 177210800U, // VRSHLsv1i64
- 162530736U, // VRSHLsv2i32
- 177210800U, // VRSHLsv2i64
- 163055024U, // VRSHLsv4i16
- 162530736U, // VRSHLsv4i32
- 163055024U, // VRSHLsv8i16
- 163579312U, // VRSHLsv8i8
- 165152176U, // VRSHLuv16i8
- 177735088U, // VRSHLuv1i64
- 164103600U, // VRSHLuv2i32
- 177735088U, // VRSHLuv2i64
- 164627888U, // VRSHLuv4i16
- 164103600U, // VRSHLuv4i32
- 164627888U, // VRSHLuv8i16
- 165152176U, // VRSHLuv8i8
- 165676470U, // VRSHRNv2i32
- 166200758U, // VRSHRNv4i16
- 166725046U, // VRSHRNv8i8
- 163579325U, // VRSHRsv16i8
- 177210813U, // VRSHRsv1i64
- 162530749U, // VRSHRsv2i32
- 177210813U, // VRSHRsv2i64
- 163055037U, // VRSHRsv4i16
- 162530749U, // VRSHRsv4i32
- 163055037U, // VRSHRsv8i16
- 163579325U, // VRSHRsv8i8
- 165152189U, // VRSHRuv16i8
- 177735101U, // VRSHRuv1i64
- 164103613U, // VRSHRuv2i32
- 177735101U, // VRSHRuv2i64
- 164627901U, // VRSHRuv4i16
- 164103613U, // VRSHRuv4i32
- 164627901U, // VRSHRuv8i16
- 165152189U, // VRSHRuv8i8
- 768083395U, // VRSQRTEd
- 756123075U, // VRSQRTEfd
- 756123075U, // VRSQRTEfq
- 768083395U, // VRSQRTEq
- 152143307U, // VRSQRTSfd
- 152143307U, // VRSQRTSfq
- 834700755U, // VRSRAsv16i8
- 848332243U, // VRSRAsv1i64
- 833652179U, // VRSRAsv2i32
- 848332243U, // VRSRAsv2i64
- 834176467U, // VRSRAsv4i16
- 833652179U, // VRSRAsv4i32
- 834176467U, // VRSRAsv8i16
- 834700755U, // VRSRAsv8i8
- 836273619U, // VRSRAuv16i8
- 848856531U, // VRSRAuv1i64
- 835225043U, // VRSRAuv2i32
- 848856531U, // VRSRAuv2i64
- 835749331U, // VRSRAuv4i16
- 835225043U, // VRSRAuv4i32
- 835749331U, // VRSRAuv8i16
- 836273619U, // VRSRAuv8i8
- 165676505U, // VRSUBHNv2i32
- 166200793U, // VRSUBHNv4i16
- 166725081U, // VRSUBHNv8i8
- 843628736U, // VSETLNi16
- 844153024U, // VSETLNi32
- 838910144U, // VSETLNi8
- 166725089U, // VSHLLi16
- 166200801U, // VSHLLi32
- 167249377U, // VSHLLi8
- 162530785U, // VSHLLsv2i64
- 163055073U, // VSHLLsv4i32
- 163579361U, // VSHLLsv8i16
- 164103649U, // VSHLLuv2i64
- 164627937U, // VSHLLuv4i32
- 165152225U, // VSHLLuv8i16
- 167249383U, // VSHLiv16i8
- 165676519U, // VSHLiv1i64
- 166200807U, // VSHLiv2i32
- 165676519U, // VSHLiv2i64
- 166725095U, // VSHLiv4i16
- 166200807U, // VSHLiv4i32
- 166725095U, // VSHLiv8i16
- 167249383U, // VSHLiv8i8
- 163579367U, // VSHLsv16i8
- 177210855U, // VSHLsv1i64
- 162530791U, // VSHLsv2i32
- 177210855U, // VSHLsv2i64
- 163055079U, // VSHLsv4i16
- 162530791U, // VSHLsv4i32
- 163055079U, // VSHLsv8i16
- 163579367U, // VSHLsv8i8
- 165152231U, // VSHLuv16i8
- 177735143U, // VSHLuv1i64
- 164103655U, // VSHLuv2i32
- 177735143U, // VSHLuv2i64
- 164627943U, // VSHLuv4i16
- 164103655U, // VSHLuv4i32
- 164627943U, // VSHLuv8i16
- 165152231U, // VSHLuv8i8
- 165676524U, // VSHRNv2i32
- 166200812U, // VSHRNv4i16
- 166725100U, // VSHRNv8i8
- 163579378U, // VSHRsv16i8
- 177210866U, // VSHRsv1i64
- 162530802U, // VSHRsv2i32
- 177210866U, // VSHRsv2i64
- 163055090U, // VSHRsv4i16
- 162530802U, // VSHRsv4i32
- 163055090U, // VSHRsv8i16
- 163579378U, // VSHRsv8i8
- 165152242U, // VSHRuv16i8
- 177735154U, // VSHRuv1i64
- 164103666U, // VSHRuv2i32
- 177735154U, // VSHRuv2i64
- 164627954U, // VSHRuv4i16
- 164103666U, // VSHRuv4i32
- 164627954U, // VSHRuv8i16
- 165152242U, // VSHRuv8i8
- 178258984U, // VSHTOD
- 178783272U, // VSHTOS
- 783467560U, // VSITOD
- 775603240U, // VSITOS
- 838911479U, // VSLIv16i8
- 846775799U, // VSLIv1i64
- 844154359U, // VSLIv2i32
- 846775799U, // VSLIv2i64
- 843630071U, // VSLIv4i16
- 844154359U, // VSLIv4i32
- 843630071U, // VSLIv8i16
- 838911479U, // VSLIv8i8
- 179405864U, // VSLTOD
- 171541544U, // VSLTOS
- 755598844U, // VSQRTD
- 756123132U, // VSQRTS
- 834700802U, // VSRAsv16i8
- 848332290U, // VSRAsv1i64
- 833652226U, // VSRAsv2i32
- 848332290U, // VSRAsv2i64
- 834176514U, // VSRAsv4i16
- 833652226U, // VSRAsv4i32
- 834176514U, // VSRAsv8i16
- 834700802U, // VSRAsv8i8
- 836273666U, // VSRAuv16i8
- 848856578U, // VSRAuv1i64
- 835225090U, // VSRAuv2i32
- 848856578U, // VSRAuv2i64
- 835749378U, // VSRAuv4i16
- 835225090U, // VSRAuv4i32
- 835749378U, // VSRAuv8i16
- 836273666U, // VSRAuv8i8
- 838911495U, // VSRIv16i8
- 846775815U, // VSRIv1i64
- 844154375U, // VSRIv2i32
- 846775815U, // VSRIv2i64
- 843630087U, // VSRIv4i16
- 844154375U, // VSRIv4i32
- 843630087U, // VSRIv8i16
- 838911495U, // VSRIv8i8
- 240944652U, // VST1d16
- 241468940U, // VST1d32
- 241993228U, // VST1d64
- 242517516U, // VST1d8
- 241468940U, // VST1df
- 239912460U, // VST1q16
- 240436748U, // VST1q32
- 243058188U, // VST1q64
- 235193868U, // VST1q8
- 240436748U, // VST1qf
- 1516013073U, // VST2LNd16
- 1516537361U, // VST2LNd32
- 1517585937U, // VST2LNd8
- 1516013073U, // VST2LNq16a
- 1516013073U, // VST2LNq16b
- 1516537361U, // VST2LNq32a
- 1516537361U, // VST2LNq32b
- 643597841U, // VST2d16
- 644122129U, // VST2d32
- 644646412U, // VST2d64
- 645170705U, // VST2d8
- 1381795345U, // VST2q16
- 1382319633U, // VST2q32
- 1383368209U, // VST2q8
- 1381795350U, // VST3LNd16
- 1382319638U, // VST3LNd32
- 1383368214U, // VST3LNd8
- 1381795350U, // VST3LNq16a
- 1381795350U, // VST3LNq16b
- 1382319638U, // VST3LNq32a
- 1382319638U, // VST3LNq32b
- 1516013078U, // VST3d16
- 1516537366U, // VST3d32
- 1517061644U, // VST3d64
- 1517585942U, // VST3d8
- 1381828118U, // VST3q16a
- 1381828118U, // VST3q16b
- 1382352406U, // VST3q32a
- 1382352406U, // VST3q32b
- 1383400982U, // VST3q8a
- 1383400982U, // VST3q8b
- 1314686491U, // VST4LNd16
- 1315210779U, // VST4LNd32
- 1316259355U, // VST4LNd8
- 1314686491U, // VST4LNq16a
- 1314686491U, // VST4LNq16b
- 1315210779U, // VST4LNq32a
- 1315210779U, // VST4LNq32b
- 1381795355U, // VST4d16
- 1382319643U, // VST4d32
- 1382843916U, // VST4d64
- 1383368219U, // VST4d8
- 1314719259U, // VST4q16a
- 1314719259U, // VST4q16b
- 1315243547U, // VST4q32a
- 1315243547U, // VST4q32b
- 1316292123U, // VST4q8a
- 1316292123U, // VST4q8b
- 1610614304U, // VSTMD
- 1610614304U, // VSTMS
- 175687205U, // VSTRD
- 136005162U, // VSTRQ
- 173065765U, // VSTRS
- 151619121U, // VSUBD
- 165676598U, // VSUBHNv2i32
- 166200886U, // VSUBHNv4i16
- 166725174U, // VSUBHNv8i8
- 162530877U, // VSUBLsv2i64
- 163055165U, // VSUBLsv4i32
- 163579453U, // VSUBLsv8i16
- 164103741U, // VSUBLuv2i64
- 164628029U, // VSUBLuv4i32
- 165152317U, // VSUBLuv8i16
- 152143409U, // VSUBS
- 162530883U, // VSUBWsv2i64
- 163055171U, // VSUBWsv4i32
- 163579459U, // VSUBWsv8i16
- 164103747U, // VSUBWuv2i64
- 164628035U, // VSUBWuv4i32
- 165152323U, // VSUBWuv8i16
- 152143409U, // VSUBfd
- 152143409U, // VSUBfd_sfp
- 152143409U, // VSUBfq
- 167249457U, // VSUBv16i8
- 165676593U, // VSUBv1i64
- 166200881U, // VSUBv2i32
- 165676593U, // VSUBv2i64
- 166725169U, // VSUBv4i16
- 166200881U, // VSUBv4i32
- 166725169U, // VSUBv8i16
- 167249457U, // VSUBv8i8
- 167822921U, // VTBL1
- 838911561U, // VTBL2
- 234931785U, // VTBL3
- 637584969U, // VTBL4
- 838911566U, // VTBX1
- 234931790U, // VTBX2
- 637584974U, // VTBX3
- 1510000206U, // VTBX4
- 179831848U, // VTOSHD
- 180356136U, // VTOSHS
- 785040979U, // VTOSIRD
- 774555219U, // VTOSIRS
- 785040424U, // VTOSIZD
- 774554664U, // VTOSIZS
- 180978728U, // VTOSLD
- 170492968U, // VTOSLS
- 181404712U, // VTOUHD
- 181929000U, // VTOUHS
- 786613843U, // VTOUIRD
- 775079507U, // VTOUIRS
- 786613288U, // VTOUIZD
- 775078952U, // VTOUIZS
- 182551592U, // VTOULD
- 171017256U, // VTOULS
- 843630169U, // VTRNd16
- 844154457U, // VTRNd32
- 838911577U, // VTRNd8
- 843630169U, // VTRNq16
- 844154457U, // VTRNq32
- 838911577U, // VTRNq8
- 167822942U, // VTSTv16i8
- 173065822U, // VTSTv2i32
- 172541534U, // VTSTv4i16
- 173065822U, // VTSTv4i32
- 172541534U, // VTSTv8i16
- 167822942U, // VTSTv8i8
- 182977576U, // VUHTOD
- 183501864U, // VUHTOS
- 788186152U, // VUITOD
- 776127528U, // VUITOS
- 184124456U, // VULTOD
- 172065832U, // VULTOS
- 843630179U, // VUZPd16
- 844154467U, // VUZPd32
- 838911587U, // VUZPd8
- 843630179U, // VUZPq16
- 844154467U, // VUZPq32
- 838911587U, // VUZPq8
- 843630184U, // VZIPd16
- 844154472U, // VZIPd32
- 838911592U, // VZIPd8
- 843630184U, // VZIPq16
- 844154472U, // VZIPq32
- 838911592U, // VZIPq8
- 538969709U, // WFE
- 538969713U, // WFI
- 538969717U, // YIELD
- 67108875U, // t2ADCSri
- 67110523U, // t2ADCSrr
- 67110523U, // t2ADCSrs
- 1679343633U, // t2ADCri
- 1728151569U, // t2ADCrr
- 1795260433U, // t2ADCrs
- 184647701U, // t2ADDSri
- 184647701U, // t2ADDSrr
- 855736341U, // t2ADDSrs
- 1728151578U, // t2ADDrSPi
- 135841411U, // t2ADDrSPi12
- 1795260442U, // t2ADDrSPs
- 1728151578U, // t2ADDri
- 1679345283U, // t2ADDri12
- 1728151578U, // t2ADDrr
- 1795260442U, // t2ADDrs
- 1679343684U, // t2ANDri
- 1728151620U, // t2ANDrr
- 1795260484U, // t2ANDrs
- 1728153224U, // t2ASRri
- 1728153224U, // t2ASRrr
- 69207692U, // t2B
- 135839820U, // t2BFC
- 806930065U, // t2BFI
- 1679343696U, // t2BICri
- 1728151632U, // t2BICrr
- 1795260496U, // t2BICrs
- 117964923U, // t2BR_JT
- 386056347U, // t2Bcc
- 739819688U, // t2CLZ
- 788627628U, // t2CMNzri
- 788627628U, // t2CMNzrr
- 184647852U, // t2CMNzrs
- 788627632U, // t2CMPri
- 788627632U, // t2CMPrr
- 184647856U, // t2CMPrs
- 788627632U, // t2CMPzri
- 788627632U, // t2CMPzrr
- 184647856U, // t2CMPzrs
- 1679343804U, // t2EORri
- 1728151740U, // t2EORrr
- 1795260604U, // t2EORrs
- 1811941013U, // t2IT
- 215U, // t2Int_MemBarrierV7
- 219U, // t2Int_SyncBarrierV7
- 1879049880U, // t2Int_eh_sjlj_setjmp
- 1058013417U, // t2LDM
- 1058013417U, // t2LDM_RET
- 806928625U, // t2LDRB_POST
- 806928625U, // t2LDRB_PRE
- 184647921U, // t2LDRBi12
- 135839985U, // t2LDRBi8
- 788627697U, // t2LDRBpci
- 855736561U, // t2LDRBs
- 806928630U, // t2LDRDi8
- 135839990U, // t2LDRDpci
- 739819771U, // t2LDREX
- 739819777U, // t2LDREXB
- 135840008U, // t2LDREXD
- 739819791U, // t2LDREXH
- 806928662U, // t2LDRH_POST
- 806928662U, // t2LDRH_PRE
- 184647958U, // t2LDRHi12
- 135840022U, // t2LDRHi8
- 788627734U, // t2LDRHpci
- 855736598U, // t2LDRHs
- 806928667U, // t2LDRSB_POST
- 806928667U, // t2LDRSB_PRE
- 184647963U, // t2LDRSBi12
- 135840027U, // t2LDRSBi8
- 788627739U, // t2LDRSBpci
- 855736603U, // t2LDRSBs
- 806928673U, // t2LDRSH_POST
- 806928673U, // t2LDRSH_PRE
- 184647969U, // t2LDRSHi12
- 135840033U, // t2LDRSHi8
- 788627745U, // t2LDRSHpci
- 855736609U, // t2LDRSHs
- 806928621U, // t2LDR_POST
- 806928621U, // t2LDR_PRE
- 184647917U, // t2LDRi12
- 135839981U, // t2LDRi8
- 788627693U, // t2LDRpci
- 67110557U, // t2LDRpci_pic
- 855736557U, // t2LDRs
- 788874918U, // t2LEApcrel
- 184895142U, // t2LEApcrelJT
- 1728153258U, // t2LSLri
- 1728153258U, // t2LSLrr
- 1728153262U, // t2LSRri
- 1728153262U, // t2LSRrr
- 806928714U, // t2MLA
- 806928718U, // t2MLS
- 855737992U, // t2MOVCCasr
- 184648018U, // t2MOVCCi
- 855738026U, // t2MOVCClsl
- 855738030U, // t2MOVCClsr
- 184648018U, // t2MOVCCr
- 855738034U, // t2MOVCCror
- 135840086U, // t2MOVTi16
- 1998422354U, // t2MOVi
- 739819867U, // t2MOVi16
- 739819867U, // t2MOVi32imm
- 1998422354U, // t2MOVr
- 1998440118U, // t2MOVrx
- 67110586U, // t2MOVsra_flag
- 67110594U, // t2MOVsrl_flag
- 135840129U, // t2MUL
- 1998438789U, // t2MVNi
- 788627845U, // t2MVNr
- 184648069U, // t2MVNs
- 1679345354U, // t2ORNri
- 1679345354U, // t2ORNrr
- 1746454218U, // t2ORNrs
- 1679344013U, // t2ORRri
- 1728151949U, // t2ORRrr
- 1795260813U, // t2ORRrs
- 806928787U, // t2PKHBT
- 806928793U, // t2PKHTB
- 739819993U, // t2RBIT
- 788627934U, // t2REV
- 788627938U, // t2REV16
- 788627944U, // t2REVSH
- 1728153266U, // t2RORri
- 1728153266U, // t2RORrr
- 2013266419U, // t2RSBSri
- 1947779571U, // t2RSBSrs
- 184648179U, // t2RSBri
- 806928883U, // t2RSBrs
- 67109377U, // t2SBCSri
- 67110606U, // t2SBCSrr
- 67110606U, // t2SBCSrs
- 1679344135U, // t2SBCri
- 1728152071U, // t2SBCrr
- 1795260935U, // t2SBCrs
- 806928907U, // t2SBFX
- 806928936U, // t2SMLABB
- 806928943U, // t2SMLABT
- 806928950U, // t2SMLAL
- 806928988U, // t2SMLATB
- 806928995U, // t2SMLATT
- 806929002U, // t2SMLAWB
- 806929009U, // t2SMLAWT
- 806929016U, // t2SMMLA
- 806929022U, // t2SMMLS
- 135840388U, // t2SMMUL
- 135840394U, // t2SMULBB
- 135840401U, // t2SMULBT
- 806929048U, // t2SMULL
- 135840414U, // t2SMULTB
- 135840421U, // t2SMULTT
- 135840428U, // t2SMULWB
- 135840435U, // t2SMULWT
- 1058013882U, // t2STM
- 806879938U, // t2STRB_POST
- 806879938U, // t2STRB_PRE
- 184648386U, // t2STRBi12
- 135840450U, // t2STRBi8
- 855737026U, // t2STRBs
- 806929101U, // t2STRDi8
- 135840466U, // t2STREX
- 135840472U, // t2STREXB
- 806929119U, // t2STREXD
- 135840486U, // t2STREXH
- 806879981U, // t2STRH_POST
- 806879981U, // t2STRH_PRE
- 184648429U, // t2STRHi12
- 135840493U, // t2STRHi8
- 855737069U, // t2STRHs
- 806879934U, // t2STR_POST
- 806879934U, // t2STR_PRE
- 184648382U, // t2STRi12
- 135840446U, // t2STRi8
- 855737022U, // t2STRs
- 184648439U, // t2SUBSri
- 184648439U, // t2SUBSrr
- 855737079U, // t2SUBSrs
- 1728152316U, // t2SUBrSPi
- 135841494U, // t2SUBrSPi12
- 67110619U, // t2SUBrSPi12_
- 67110627U, // t2SUBrSPi_
- 1746453244U, // t2SUBrSPs
- 67110636U, // t2SUBrSPs_
- 1728152316U, // t2SUBri
- 1679345366U, // t2SUBri12
- 1728152316U, // t2SUBrr
- 1795261180U, // t2SUBrs
- 135840525U, // t2SXTABrr
- 806929165U, // t2SXTABrr_rot
- 135840531U, // t2SXTAHrr
- 806929171U, // t2SXTAHrr_rot
- 788628249U, // t2SXTBr
- 184648473U, // t2SXTBr_rot
- 788628254U, // t2SXTHr
- 184648478U, // t2SXTHr_rot
- 2080376563U, // t2TBB
- 2080376568U, // t2TBH
- 788628259U, // t2TEQri
- 788628259U, // t2TEQrr
- 184648483U, // t2TEQrs
- 807U, // t2TPsoft
- 788628287U, // t2TSTri
- 788628287U, // t2TSTrr
- 184648511U, // t2TSTrs
- 806929219U, // t2UBFX
- 806929224U, // t2UMAAL
- 806929230U, // t2UMLAL
- 806929236U, // t2UMULL
- 135840644U, // t2UXTABrr
- 806929284U, // t2UXTABrr_rot
- 135840650U, // t2UXTAHrr
- 806929290U, // t2UXTAHrr_rot
- 788628368U, // t2UXTB16r
- 184648592U, // t2UXTB16r_rot
- 788628375U, // t2UXTBr
- 184648599U, // t2UXTBr_rot
- 788628380U, // t2UXTHr
- 184648604U, // t2UXTHr_rot
- 2200305681U, // tADC
- 135839770U, // tADDhirr
- 2199945242U, // tADDi3
- 2200305690U, // tADDi8
- 120063741U, // tADDrPCi
- 67143421U, // tADDrSP
- 67110653U, // tADDrSPi
- 2199945242U, // tADDrr
- 67520253U, // tADDspi
- 67143421U, // tADDspr
- 67143426U, // tADDspr_
- 69207817U, // tADJCALLSTACKDOWN
- 69207838U, // tADJCALLSTACKUP
- 2200305732U, // tAND
- 67143473U, // tANDsp
- 2199946888U, // tASRri
- 2200307336U, // tASRrr
+ 939524286U, // CPS
+ 337141954U, // DBG
+ 198U, // DMBish
+ 206U, // DMBishst
+ 216U, // DMBnsh
+ 224U, // DMBnshst
+ 234U, // DMBosh
+ 242U, // DMBoshst
+ 252U, // DMBst
+ 259U, // DSBish
+ 267U, // DSBishst
+ 277U, // DSBnsh
+ 285U, // DSBnshst
+ 295U, // DSBosh
+ 303U, // DSBoshst
+ 313U, // DSBst
+ 134750528U, // EORri
+ 134758720U, // EORrr
+ 202375488U, // EORrs
+ 755556676U, // FCONSTD
+ 756080964U, // FCONSTS
+ 555221321U, // FMSTAT
+ 334U, // ISBsy
+ 85983570U, // Int_MemBarrierV6
+ 351U, // Int_MemBarrierV7
+ 86507858U, // Int_SyncBarrierV6
+ 355U, // Int_SyncBarrierV7
+ 87032167U, // Int_eh_sjlj_setjmp
+ 221831537U, // LDC2L_OFFSET
+ 825819505U, // LDC2L_OPTION
+ 221839729U, // LDC2L_POST
+ 221831537U, // LDC2L_PRE
+ 217653617U, // LDC2_OFFSET
+ 821633393U, // LDC2_OPTION
+ 217653617U, // LDC2_POST
+ 217653617U, // LDC2_PRE
+ 221831542U, // LDCL_OFFSET
+ 825819510U, // LDCL_OPTION
+ 221839734U, // LDCL_POST
+ 221831542U, // LDCL_PRE
+ 217653622U, // LDC_OFFSET
+ 821633398U, // LDC_OPTION
+ 217653622U, // LDC_POST
+ 217653622U, // LDC_PRE
+ 1027686778U, // LDM
+ 1027686778U, // LDM_RET
+ 806904190U, // LDR
+ 806904194U, // LDRB
+ 202924423U, // LDRBT
+ 202924418U, // LDRB_POST
+ 202924418U, // LDRB_PRE
+ 202924429U, // LDRD
+ 605577613U, // LDRD_POST
+ 605577613U, // LDRD_PRE
+ 739795346U, // LDREX
+ 739795352U, // LDREXB
+ 135815583U, // LDREXD
+ 739795366U, // LDREXH
+ 806904237U, // LDRH
+ 202924466U, // LDRHT
+ 202924461U, // LDRH_POST
+ 202924461U, // LDRH_PRE
+ 806904248U, // LDRSB
+ 202924478U, // LDRSBT
+ 202924472U, // LDRSB_POST
+ 202924472U, // LDRSB_PRE
+ 806904261U, // LDRSH
+ 202924491U, // LDRSHT
+ 202924485U, // LDRSH_POST
+ 202924485U, // LDRSH_PRE
+ 202924498U, // LDRT
+ 202924414U, // LDR_POST
+ 202924414U, // LDR_PRE
+ 806904190U, // LDRcp
+ 1095238103U, // LEApcrel
+ 1095762391U, // LEApcrelJT
+ 620290525U, // MCR
+ 671105505U, // MCR2
+ 217637352U, // MCRR
+ 671105517U, // MCRR2
+ 827851253U, // MLA
+ 806904313U, // MLS
+ 135815677U, // MOVCCi
+ 135815677U, // MOVCCr
+ 202924541U, // MOVCCs
+ 135815681U, // MOVTi16
+ 761356797U, // MOVi
+ 739795462U, // MOVi16
+ 739795453U, // MOVi2pieces
+ 739795462U, // MOVi32imm
+ 761266685U, // MOVr
+ 761266685U, // MOVrx
+ 827949565U, // MOVs
+ 739795467U, // MOVsra_flag
+ 739795467U, // MOVsrl_flag
+ 620290576U, // MRC
+ 671105556U, // MRC2
+ 217637403U, // MRRC
+ 671105568U, // MRRC2
+ 337142312U, // MRS
+ 337142312U, // MRSsys
+ 359162412U, // MSR
+ 359244332U, // MSRi
+ 359686700U, // MSRsys
+ 359768620U, // MSRsysi
+ 134758960U, // MUL
+ 761356852U, // MVNi
+ 761266740U, // MVNr
+ 827949620U, // MVNs
+ 538968632U, // NOP
+ 134750780U, // ORRri
+ 134758972U, // ORRrr
+ 202375740U, // ORRrs
+ 1165492800U, // PICADD
+ 1233125952U, // PICLDR
+ 1233650240U, // PICLDRB
+ 1234174528U, // PICLDRH
+ 1234698816U, // PICLDRSB
+ 1235223104U, // PICLDRSH
+ 1235747392U, // PICSTR
+ 1236271680U, // PICSTRB
+ 1236795968U, // PICSTRH
+ 806904386U, // PKHBT
+ 806904392U, // PKHTB
+ 67109454U, // PLDWi
+ 471859797U, // PLDWr
+ 67109467U, // PLDi
+ 471859809U, // PLDr
+ 67109478U, // PLIi
+ 471859820U, // PLIr
+ 135815793U, // QADD
+ 135815798U, // QADD16
+ 135815805U, // QADD8
+ 135815811U, // QASX
+ 135815816U, // QDADD
+ 135815822U, // QDSUB
+ 135815828U, // QSAX
+ 135815833U, // QSUB
+ 135815838U, // QSUB16
+ 135815845U, // QSUB8
+ 739795627U, // RBIT
+ 739795632U, // REV
+ 739795636U, // REV16
+ 739795642U, // REVSH
+ 1008222912U, // RFE
+ 1008222912U, // RFEW
+ 135815876U, // RSBSri
+ 202924740U, // RSBSrs
+ 134750921U, // RSBri
+ 202375881U, // RSBrs
+ 67109581U, // RSCSri
+ 67109581U, // RSCSrs
+ 134750931U, // RSCri
+ 202375891U, // RSCrs
+ 135815895U, // SADD16
+ 135815902U, // SADD8
+ 135815908U, // SASX
+ 67109609U, // SBCSSri
+ 67109609U, // SBCSSrr
+ 67109609U, // SBCSSrs
+ 134750959U, // SBCri
+ 134759151U, // SBCrr
+ 202375919U, // SBCrs
+ 806904563U, // SBFX
+ 135815928U, // SEL
+ 764U, // SETENDBE
+ 774U, // SETENDLE
+ 538968848U, // SEV
+ 135815956U, // SHADD16
+ 135815964U, // SHADD8
+ 135815971U, // SHASX
+ 135815977U, // SHSAX
+ 135815983U, // SHSUB16
+ 135815991U, // SHSUB8
+ 337142590U, // SMC
+ 806904642U, // SMLABB
+ 806904649U, // SMLABT
+ 806904656U, // SMLAD
+ 806904662U, // SMLADX
+ 827851613U, // SMLAL
+ 806904675U, // SMLALBB
+ 806904683U, // SMLALBT
+ 806904691U, // SMLALD
+ 806904698U, // SMLALDX
+ 806904706U, // SMLALTB
+ 806904714U, // SMLALTT
+ 806904722U, // SMLATB
+ 806904729U, // SMLATT
+ 806904736U, // SMLAWB
+ 806904743U, // SMLAWT
+ 806904750U, // SMLSD
+ 806904756U, // SMLSDX
+ 806904763U, // SMLSLD
+ 806904770U, // SMLSLDX
+ 806904778U, // SMMLA
+ 806904784U, // SMMLAR
+ 806904791U, // SMMLS
+ 806904797U, // SMMLSR
+ 135816164U, // SMMUL
+ 135816170U, // SMMULR
+ 135816177U, // SMUAD
+ 135816183U, // SMUADX
+ 135816190U, // SMULBB
+ 135816197U, // SMULBT
+ 827851788U, // SMULL
+ 135816210U, // SMULTB
+ 135816217U, // SMULTT
+ 135816224U, // SMULWB
+ 135816231U, // SMULWT
+ 135816238U, // SMUSD
+ 135816244U, // SMUSDX
+ 1036010555U, // SRS
+ 1036534843U, // SRSW
+ 135816255U, // SSAT16
+ 806904902U, // SSATasr
+ 806904902U, // SSATlsl
+ 135816267U, // SSAX
+ 135816272U, // SSUB16
+ 135816279U, // SSUB8
+ 221832285U, // STC2L_OFFSET
+ 825820253U, // STC2L_OPTION
+ 221840477U, // STC2L_POST
+ 221832285U, // STC2L_PRE
+ 217654365U, // STC2_OFFSET
+ 821634141U, // STC2_OPTION
+ 217654365U, // STC2_POST
+ 217654365U, // STC2_PRE
+ 221832290U, // STCL_OFFSET
+ 825820258U, // STCL_OPTION
+ 221840482U, // STCL_POST
+ 221832290U, // STCL_PRE
+ 217654370U, // STC_OFFSET
+ 821634146U, // STC_OPTION
+ 217654370U, // STC_POST
+ 217654370U, // STC_PRE
+ 1027687526U, // STM
+ 806904938U, // STR
+ 806904942U, // STRB
+ 202900595U, // STRBT
+ 202900590U, // STRB_POST
+ 202900590U, // STRB_PRE
+ 202925177U, // STRD
+ 605553785U, // STRD_POST
+ 605553785U, // STRD_PRE
+ 135816318U, // STREX
+ 135816324U, // STREXB
+ 806904971U, // STREXD
+ 135816338U, // STREXH
+ 806904985U, // STRH
+ 202900638U, // STRHT
+ 202900633U, // STRH_POST
+ 202900633U, // STRH_PRE
+ 202900644U, // STRT
+ 202900586U, // STR_POST
+ 202900586U, // STR_PRE
+ 135816361U, // SUBSri
+ 135816361U, // SUBSrr
+ 202925225U, // SUBSrs
+ 134751406U, // SUBri
+ 134759598U, // SUBrr
+ 202376366U, // SUBrs
+ 337142962U, // SVC
+ 135816374U, // SWP
+ 135816378U, // SWPB
+ 135816383U, // SXTAB16rr
+ 806905023U, // SXTAB16rr_rot
+ 135816391U, // SXTABrr
+ 806905031U, // SXTABrr_rot
+ 135816397U, // SXTAHrr
+ 806905037U, // SXTAHrr_rot
+ 739796179U, // SXTB16r
+ 135816403U, // SXTB16r_rot
+ 739796186U, // SXTBr
+ 135816410U, // SXTBr_rot
+ 739796191U, // SXTHr
+ 135816415U, // SXTHr_rot
+ 739796196U, // TEQri
+ 739796196U, // TEQrr
+ 806905060U, // TEQrs
+ 1256U, // TPsoft
+ 538969339U, // TRAP
+ 739796224U, // TSTri
+ 739796224U, // TSTrr
+ 806905088U, // TSTrs
+ 135816452U, // UADD16
+ 135816459U, // UADD8
+ 135816465U, // UASX
+ 806905110U, // UBFX
+ 135816475U, // UHADD16
+ 135816483U, // UHADD8
+ 135816490U, // UHASX
+ 135816496U, // UHSAX
+ 135816502U, // UHSUB16
+ 135816510U, // UHSUB8
+ 806905157U, // UMAAL
+ 827852107U, // UMLAL
+ 827852113U, // UMULL
+ 135816535U, // UQADD16
+ 135816543U, // UQADD8
+ 135816550U, // UQASX
+ 135816556U, // UQSAX
+ 135816562U, // UQSUB16
+ 135816570U, // UQSUB8
+ 135816577U, // USAD8
+ 806905223U, // USADA8
+ 135816590U, // USAT16
+ 806905237U, // USATasr
+ 806905237U, // USATlsl
+ 135816602U, // USAX
+ 135816607U, // USUB16
+ 135816614U, // USUB8
+ 135816620U, // UXTAB16rr
+ 806905260U, // UXTAB16rr_rot
+ 135816628U, // UXTABrr
+ 806905268U, // UXTABrr_rot
+ 135816634U, // UXTAHrr
+ 806905274U, // UXTAHrr_rot
+ 739796416U, // UXTB16r
+ 135816640U, // UXTB16r_rot
+ 739796423U, // UXTBr
+ 135816647U, // UXTBr_rot
+ 739796428U, // UXTHr
+ 135816652U, // UXTHr_rot
+ 835732945U, // VABALsv2i64
+ 836257233U, // VABALsv4i32
+ 836781521U, // VABALsv8i16
+ 837305809U, // VABALuv2i64
+ 837830097U, // VABALuv4i32
+ 838354385U, // VABALuv8i16
+ 836781527U, // VABAsv16i8
+ 835732951U, // VABAsv2i32
+ 836257239U, // VABAsv4i16
+ 835732951U, // VABAsv4i32
+ 836257239U, // VABAsv8i16
+ 836781527U, // VABAsv8i8
+ 838354391U, // VABAuv16i8
+ 837305815U, // VABAuv2i32
+ 837830103U, // VABAuv4i16
+ 837305815U, // VABAuv4i32
+ 837830103U, // VABAuv8i16
+ 838354391U, // VABAuv8i8
+ 164627932U, // VABDLsv2i64
+ 165152220U, // VABDLsv4i32
+ 165676508U, // VABDLsv8i16
+ 166200796U, // VABDLuv2i64
+ 166725084U, // VABDLuv4i32
+ 167249372U, // VABDLuv8i16
+ 152102370U, // VABDfd
+ 152102370U, // VABDfq
+ 165676514U, // VABDsv16i8
+ 164627938U, // VABDsv2i32
+ 165152226U, // VABDsv4i16
+ 164627938U, // VABDsv4i32
+ 165152226U, // VABDsv8i16
+ 165676514U, // VABDsv8i8
+ 167249378U, // VABDuv16i8
+ 166200802U, // VABDuv2i32
+ 166725090U, // VABDuv4i16
+ 166200802U, // VABDuv4i32
+ 166725090U, // VABDuv8i16
+ 167249378U, // VABDuv8i8
+ 755557863U, // VABSD
+ 756082151U, // VABSS
+ 756082151U, // VABSfd
+ 756082151U, // VABSfd_sfp
+ 756082151U, // VABSfq
+ 769656295U, // VABSv16i8
+ 768607719U, // VABSv2i32
+ 769132007U, // VABSv4i16
+ 768607719U, // VABSv4i32
+ 769132007U, // VABSv8i16
+ 769656295U, // VABSv8i8
+ 152102380U, // VACGEd
+ 152102380U, // VACGEq
+ 152102386U, // VACGTd
+ 152102386U, // VACGTq
+ 151578104U, // VADDD
+ 167773693U, // VADDHNv2i32
+ 168297981U, // VADDHNv4i16
+ 168822269U, // VADDHNv8i8
+ 164627972U, // VADDLsv2i64
+ 165152260U, // VADDLsv4i32
+ 165676548U, // VADDLsv8i16
+ 166200836U, // VADDLuv2i64
+ 166725124U, // VADDLuv4i32
+ 167249412U, // VADDLuv8i16
+ 152102392U, // VADDS
+ 164627978U, // VADDWsv2i64
+ 165152266U, // VADDWsv4i32
+ 165676554U, // VADDWsv8i16
+ 166200842U, // VADDWuv2i64
+ 166725130U, // VADDWuv4i32
+ 167249418U, // VADDWuv8i16
+ 152102392U, // VADDfd
+ 152102392U, // VADDfd_sfp
+ 152102392U, // VADDfq
+ 169346552U, // VADDv16i8
+ 167773688U, // VADDv1i64
+ 168297976U, // VADDv2i32
+ 167773688U, // VADDv2i64
+ 168822264U, // VADDv4i16
+ 168297976U, // VADDv4i32
+ 168822264U, // VADDv8i16
+ 169346552U, // VADDv8i8
+ 135816720U, // VANDd
+ 135816720U, // VANDq
+ 135816725U, // VBICd
+ 135816725U, // VBICq
+ 806905370U, // VBIFd
+ 806905370U, // VBIFq
+ 806905375U, // VBITd
+ 806905375U, // VBITq
+ 806905380U, // VBSLd
+ 806905380U, // VBSLq
+ 152102441U, // VCEQfd
+ 152102441U, // VCEQfq
+ 169346601U, // VCEQv16i8
+ 168298025U, // VCEQv2i32
+ 168822313U, // VCEQv4i16
+ 168298025U, // VCEQv4i32
+ 168822313U, // VCEQv8i16
+ 169346601U, // VCEQv8i8
+ 773326377U, // VCEQzv16i8
+ 756082217U, // VCEQzv2f32
+ 772277801U, // VCEQzv2i32
+ 756082217U, // VCEQzv4f32
+ 772802089U, // VCEQzv4i16
+ 772277801U, // VCEQzv4i32
+ 772802089U, // VCEQzv8i16
+ 773326377U, // VCEQzv8i8
+ 152102446U, // VCGEfd
+ 152102446U, // VCGEfq
+ 165676590U, // VCGEsv16i8
+ 164628014U, // VCGEsv2i32
+ 165152302U, // VCGEsv4i16
+ 164628014U, // VCGEsv4i32
+ 165152302U, // VCGEsv8i16
+ 165676590U, // VCGEsv8i8
+ 167249454U, // VCGEuv16i8
+ 166200878U, // VCGEuv2i32
+ 166725166U, // VCGEuv4i16
+ 166200878U, // VCGEuv4i32
+ 166725166U, // VCGEuv8i16
+ 167249454U, // VCGEuv8i8
+ 769656366U, // VCGEzv16i8
+ 756082222U, // VCGEzv2f32
+ 768607790U, // VCGEzv2i32
+ 756082222U, // VCGEzv4f32
+ 769132078U, // VCGEzv4i16
+ 768607790U, // VCGEzv4i32
+ 769132078U, // VCGEzv8i16
+ 769656366U, // VCGEzv8i8
+ 152102451U, // VCGTfd
+ 152102451U, // VCGTfq
+ 165676595U, // VCGTsv16i8
+ 164628019U, // VCGTsv2i32
+ 165152307U, // VCGTsv4i16
+ 164628019U, // VCGTsv4i32
+ 165152307U, // VCGTsv8i16
+ 165676595U, // VCGTsv8i8
+ 167249459U, // VCGTuv16i8
+ 166200883U, // VCGTuv2i32
+ 166725171U, // VCGTuv4i16
+ 166200883U, // VCGTuv4i32
+ 166725171U, // VCGTuv8i16
+ 167249459U, // VCGTuv8i8
+ 769656371U, // VCGTzv16i8
+ 756082227U, // VCGTzv2f32
+ 768607795U, // VCGTzv2i32
+ 756082227U, // VCGTzv4f32
+ 769132083U, // VCGTzv4i16
+ 768607795U, // VCGTzv4i32
+ 769132083U, // VCGTzv8i16
+ 769656371U, // VCGTzv8i8
+ 769656376U, // VCLEzv16i8
+ 756082232U, // VCLEzv2f32
+ 768607800U, // VCLEzv2i32
+ 756082232U, // VCLEzv4f32
+ 769132088U, // VCLEzv4i16
+ 768607800U, // VCLEzv4i32
+ 769132088U, // VCLEzv8i16
+ 769656376U, // VCLEzv8i8
+ 769656381U, // VCLSv16i8
+ 768607805U, // VCLSv2i32
+ 769132093U, // VCLSv4i16
+ 768607805U, // VCLSv4i32
+ 769132093U, // VCLSv8i16
+ 769656381U, // VCLSv8i8
+ 769656386U, // VCLTzv16i8
+ 756082242U, // VCLTzv2f32
+ 768607810U, // VCLTzv2i32
+ 756082242U, // VCLTzv4f32
+ 769132098U, // VCLTzv4i16
+ 768607810U, // VCLTzv4i32
+ 769132098U, // VCLTzv8i16
+ 769656386U, // VCLTzv8i8
+ 773326407U, // VCLZv16i8
+ 772277831U, // VCLZv2i32
+ 772802119U, // VCLZv4i16
+ 772277831U, // VCLZv4i32
+ 772802119U, // VCLZv8i16
+ 773326407U, // VCLZv8i8
+ 755557964U, // VCMPD
+ 755557969U, // VCMPED
+ 756082257U, // VCMPES
+ 352962129U, // VCMPEZD
+ 353486417U, // VCMPEZS
+ 756082252U, // VCMPS
+ 352962124U, // VCMPZD
+ 353486412U, // VCMPZS
+ 773875287U, // VCNTd
+ 773875287U, // VCNTq
+ 774375004U, // VCVTBHS
+ 774899292U, // VCVTBSH
+ 775423586U, // VCVTDS
+ 775947874U, // VCVTSD
+ 774375015U, // VCVTTHS
+ 774899303U, // VCVTTSH
+ 776595042U, // VCVTf2sd
+ 776595042U, // VCVTf2sd_sfp
+ 776595042U, // VCVTf2sq
+ 777119330U, // VCVTf2ud
+ 777119330U, // VCVTf2ud_sfp
+ 777119330U, // VCVTf2uq
+ 172549730U, // VCVTf2xsd
+ 172549730U, // VCVTf2xsq
+ 173074018U, // VCVTf2xud
+ 173074018U, // VCVTf2xuq
+ 777643618U, // VCVTs2fd
+ 777643618U, // VCVTs2fd_sfp
+ 777643618U, // VCVTs2fq
+ 778167906U, // VCVTu2fd
+ 778167906U, // VCVTu2fd_sfp
+ 778167906U, // VCVTu2fq
+ 173598306U, // VCVTxs2fd
+ 173598306U, // VCVTxs2fq
+ 174122594U, // VCVTxu2fd
+ 174122594U, // VCVTxu2fq
+ 151578221U, // VDIVD
+ 152102509U, // VDIVS
+ 778593906U, // VDUP16d
+ 778593906U, // VDUP16q
+ 779118194U, // VDUP32d
+ 779118194U, // VDUP32q
+ 773875314U, // VDUP8d
+ 773875314U, // VDUP8q
+ 174614130U, // VDUPLN16d
+ 174614130U, // VDUPLN16q
+ 175138418U, // VDUPLN32d
+ 175138418U, // VDUPLN32q
+ 169895538U, // VDUPLN8d
+ 169895538U, // VDUPLN8q
+ 175138418U, // VDUPLNfd
+ 175138418U, // VDUPLNfq
+ 779118194U, // VDUPfd
+ 779118194U, // VDUPfdf
+ 779118194U, // VDUPfq
+ 779118194U, // VDUPfqf
+ 135816823U, // VEORd
+ 135816823U, // VEORq
+ 845702780U, // VEXTd16
+ 846227068U, // VEXTd32
+ 840984188U, // VEXTd8
+ 846227068U, // VEXTdf
+ 845702780U, // VEXTq16
+ 846227068U, // VEXTq32
+ 840984188U, // VEXTq8
+ 846227068U, // VEXTqf
+ 175137092U, // VGETLNi32
+ 165151044U, // VGETLNs16
+ 165675332U, // VGETLNs8
+ 166723908U, // VGETLNu16
+ 167248196U, // VGETLNu8
+ 165676673U, // VHADDsv16i8
+ 164628097U, // VHADDsv2i32
+ 165152385U, // VHADDsv4i16
+ 164628097U, // VHADDsv4i32
+ 165152385U, // VHADDsv8i16
+ 165676673U, // VHADDsv8i8
+ 167249537U, // VHADDuv16i8
+ 166200961U, // VHADDuv2i32
+ 166725249U, // VHADDuv4i16
+ 166200961U, // VHADDuv4i32
+ 166725249U, // VHADDuv8i16
+ 167249537U, // VHADDuv8i8
+ 165676679U, // VHSUBsv16i8
+ 164628103U, // VHSUBsv2i32
+ 165152391U, // VHSUBsv4i16
+ 164628103U, // VHSUBsv4i32
+ 165152391U, // VHSUBsv8i16
+ 165676679U, // VHSUBsv8i8
+ 167249543U, // VHSUBuv16i8
+ 166200967U, // VHSUBuv2i32
+ 166725255U, // VHSUBuv4i16
+ 166200967U, // VHSUBuv4i32
+ 166725255U, // VHSUBuv8i16
+ 167249543U, // VHSUBuv8i8
+ 242771597U, // VLD1d16
+ 1316513421U, // VLD1d16Q
+ 1383622285U, // VLD1d16T
+ 243295885U, // VLD1d32
+ 1317037709U, // VLD1d32Q
+ 1384146573U, // VLD1d32T
+ 243820173U, // VLD1d64
+ 244344461U, // VLD1d8
+ 1318086285U, // VLD1d8Q
+ 1385195149U, // VLD1d8T
+ 243295885U, // VLD1df
+ 241829517U, // VLD1q16
+ 242353805U, // VLD1q32
+ 244975245U, // VLD1q64
+ 237110925U, // VLD1q8
+ 242353805U, // VLD1qf
+ 1450731154U, // VLD2LNd16
+ 1451255442U, // VLD2LNd32
+ 1452304018U, // VLD2LNd8
+ 1450731154U, // VLD2LNq16a
+ 1450731154U, // VLD2LNq16b
+ 1451255442U, // VLD2LNq32a
+ 1451255442U, // VLD2LNq32b
+ 645424786U, // VLD2d16
+ 645424786U, // VLD2d16D
+ 645949074U, // VLD2d32
+ 645949074U, // VLD2d32D
+ 646473357U, // VLD2d64
+ 646997650U, // VLD2d8
+ 646997650U, // VLD2d8D
+ 1316513426U, // VLD2q16
+ 1317037714U, // VLD2q32
+ 1318086290U, // VLD2q8
+ 1517840023U, // VLD3LNd16
+ 1518364311U, // VLD3LNd32
+ 1519412887U, // VLD3LNd8
+ 1517840023U, // VLD3LNq16a
+ 1517840023U, // VLD3LNq16b
+ 1518364311U, // VLD3LNq32a
+ 1518364311U, // VLD3LNq32b
+ 1383622295U, // VLD3d16
+ 1384146583U, // VLD3d32
+ 1384670861U, // VLD3d64
+ 1385195159U, // VLD3d8
+ 1316513431U, // VLD3q16a
+ 1316513431U, // VLD3q16b
+ 1317037719U, // VLD3q32a
+ 1317037719U, // VLD3q32b
+ 1318086295U, // VLD3q8a
+ 1318086295U, // VLD3q8b
+ 1584948892U, // VLD4LNd16
+ 1585473180U, // VLD4LNd32
+ 1586521756U, // VLD4LNd8
+ 1584948892U, // VLD4LNq16a
+ 1584948892U, // VLD4LNq16b
+ 1585473180U, // VLD4LNq32a
+ 1585473180U, // VLD4LNq32b
+ 1316513436U, // VLD4d16
+ 1317037724U, // VLD4d32
+ 1317561997U, // VLD4d64
+ 1318086300U, // VLD4d8
+ 1450731164U, // VLD4q16a
+ 1450731164U, // VLD4q16b
+ 1451255452U, // VLD4q32a
+ 1451255452U, // VLD4q32b
+ 1452304028U, // VLD4q8a
+ 1452304028U, // VLD4q8b
+ 1610614433U, // VLDMD
+ 1610614433U, // VLDMS
+ 177759910U, // VLDRD
+ 135931563U, // VLDRQ
+ 175138470U, // VLDRS
+ 152102578U, // VMAXfd
+ 152102578U, // VMAXfd_sfp
+ 152102578U, // VMAXfq
+ 165676722U, // VMAXsv16i8
+ 164628146U, // VMAXsv2i32
+ 165152434U, // VMAXsv4i16
+ 164628146U, // VMAXsv4i32
+ 165152434U, // VMAXsv8i16
+ 165676722U, // VMAXsv8i8
+ 167249586U, // VMAXuv16i8
+ 166201010U, // VMAXuv2i32
+ 166725298U, // VMAXuv4i16
+ 166201010U, // VMAXuv4i32
+ 166725298U, // VMAXuv8i16
+ 167249586U, // VMAXuv8i8
+ 152102583U, // VMINfd
+ 152102583U, // VMINfd_sfp
+ 152102583U, // VMINfq
+ 165676727U, // VMINsv16i8
+ 164628151U, // VMINsv2i32
+ 165152439U, // VMINsv4i16
+ 164628151U, // VMINsv4i32
+ 165152439U, // VMINsv8i16
+ 165676727U, // VMINsv8i8
+ 167249591U, // VMINuv16i8
+ 166201015U, // VMINuv2i32
+ 166725303U, // VMINuv4i16
+ 166201015U, // VMINuv4i32
+ 166725303U, // VMINuv8i16
+ 167249591U, // VMINuv8i8
+ 822666940U, // VMLAD
+ 231753409U, // VMLALslsv2i32
+ 232277697U, // VMLALslsv4i16
+ 233326273U, // VMLALsluv2i32
+ 233850561U, // VMLALsluv4i16
+ 835733185U, // VMLALsv2i64
+ 836257473U, // VMLALsv4i32
+ 836781761U, // VMLALsv8i16
+ 837306049U, // VMLALuv2i64
+ 837830337U, // VMLALuv4i32
+ 838354625U, // VMLALuv8i16
+ 823191228U, // VMLAS
+ 823191228U, // VMLAfd
+ 823191228U, // VMLAfq
+ 219211452U, // VMLAslfd
+ 219211452U, // VMLAslfq
+ 235423420U, // VMLAslv2i32
+ 235947708U, // VMLAslv4i16
+ 235423420U, // VMLAslv4i32
+ 235947708U, // VMLAslv8i16
+ 840451772U, // VMLAv16i8
+ 839403196U, // VMLAv2i32
+ 839927484U, // VMLAv4i16
+ 839403196U, // VMLAv4i32
+ 839927484U, // VMLAv8i16
+ 840451772U, // VMLAv8i8
+ 822666951U, // VMLSD
+ 231753420U, // VMLSLslsv2i32
+ 232277708U, // VMLSLslsv4i16
+ 233326284U, // VMLSLsluv2i32
+ 233850572U, // VMLSLsluv4i16
+ 835733196U, // VMLSLsv2i64
+ 836257484U, // VMLSLsv4i32
+ 836781772U, // VMLSLsv8i16
+ 837306060U, // VMLSLuv2i64
+ 837830348U, // VMLSLuv4i32
+ 838354636U, // VMLSLuv8i16
+ 823191239U, // VMLSS
+ 823191239U, // VMLSfd
+ 823191239U, // VMLSfq
+ 219211463U, // VMLSslfd
+ 219211463U, // VMLSslfq
+ 235423431U, // VMLSslv2i32
+ 235947719U, // VMLSslv4i16
+ 235423431U, // VMLSslv4i32
+ 235947719U, // VMLSslv8i16
+ 840451783U, // VMLSv16i8
+ 839403207U, // VMLSv2i32
+ 839927495U, // VMLSv4i16
+ 839403207U, // VMLSv4i32
+ 839927495U, // VMLSv8i16
+ 840451783U, // VMLSv8i8
+ 755556676U, // VMOVD
+ 135815492U, // VMOVDRR
+ 151576900U, // VMOVDcc
+ 739795268U, // VMOVDneon
+ 768607954U, // VMOVLsv2i64
+ 769132242U, // VMOVLsv4i32
+ 769656530U, // VMOVLsv8i16
+ 770180818U, // VMOVLuv2i64
+ 770705106U, // VMOVLuv4i32
+ 771229394U, // VMOVLuv8i16
+ 771753688U, // VMOVNv2i32
+ 772277976U, // VMOVNv4i16
+ 772802264U, // VMOVNv8i8
+ 739795268U, // VMOVQ
+ 135815492U, // VMOVRRD
+ 806904132U, // VMOVRRS
+ 739795268U, // VMOVRS
+ 756080964U, // VMOVS
+ 739795268U, // VMOVSR
+ 806904132U, // VMOVSRR
+ 152101188U, // VMOVScc
+ 773472580U, // VMOVv16i8
+ 771907908U, // VMOVv1i64
+ 772440388U, // VMOVv2i32
+ 771907908U, // VMOVv2i64
+ 772972868U, // VMOVv4i16
+ 772440388U, // VMOVv4i32
+ 772972868U, // VMOVv8i16
+ 773472580U, // VMOVv8i8
+ 337142089U, // VMRS
+ 379586270U, // VMSR
+ 151578339U, // VMULD
+ 178783976U, // VMULLp
+ 835716840U, // VMULLslsv2i32
+ 836241128U, // VMULLslsv4i16
+ 837289704U, // VMULLsluv2i32
+ 837813992U, // VMULLsluv4i16
+ 164628200U, // VMULLsv2i64
+ 165152488U, // VMULLsv4i32
+ 165676776U, // VMULLsv8i16
+ 166201064U, // VMULLuv2i64
+ 166725352U, // VMULLuv4i32
+ 167249640U, // VMULLuv8i16
+ 152102627U, // VMULS
+ 152102627U, // VMULfd
+ 152102627U, // VMULfd_sfp
+ 152102627U, // VMULfq
+ 178783971U, // VMULpd
+ 178783971U, // VMULpq
+ 823191267U, // VMULslfd
+ 823191267U, // VMULslfq
+ 839386851U, // VMULslv2i32
+ 839911139U, // VMULslv4i16
+ 839386851U, // VMULslv4i32
+ 839911139U, // VMULslv8i16
+ 169346787U, // VMULv16i8
+ 168298211U, // VMULv2i32
+ 168822499U, // VMULv4i16
+ 168298211U, // VMULv4i32
+ 168822499U, // VMULv8i16
+ 169346787U, // VMULv8i8
+ 739796718U, // VMVNd
+ 739796718U, // VMVNq
+ 755558131U, // VNEGD
+ 151578355U, // VNEGDcc
+ 756082419U, // VNEGS
+ 152102643U, // VNEGScc
+ 756082419U, // VNEGf32q
+ 756082419U, // VNEGfd
+ 756082419U, // VNEGfd_sfp
+ 769132275U, // VNEGs16d
+ 769132275U, // VNEGs16q
+ 768607987U, // VNEGs32d
+ 768607987U, // VNEGs32q
+ 769656563U, // VNEGs8d
+ 769656563U, // VNEGs8q
+ 822667000U, // VNMLAD
+ 823191288U, // VNMLAS
+ 822667006U, // VNMLSD
+ 823191294U, // VNMLSS
+ 151578372U, // VNMULD
+ 152102660U, // VNMULS
+ 135816970U, // VORNd
+ 135816970U, // VORNq
+ 135816975U, // VORRd
+ 135816975U, // VORRq
+ 165693204U, // VPADALsv16i8
+ 164644628U, // VPADALsv2i32
+ 165168916U, // VPADALsv4i16
+ 164644628U, // VPADALsv4i32
+ 165168916U, // VPADALsv8i16
+ 165693204U, // VPADALsv8i8
+ 167266068U, // VPADALuv16i8
+ 166217492U, // VPADALuv2i32
+ 166741780U, // VPADALuv4i16
+ 166217492U, // VPADALuv4i32
+ 166741780U, // VPADALuv8i16
+ 167266068U, // VPADALuv8i8
+ 769656603U, // VPADDLsv16i8
+ 768608027U, // VPADDLsv2i32
+ 769132315U, // VPADDLsv4i16
+ 768608027U, // VPADDLsv4i32
+ 769132315U, // VPADDLsv8i16
+ 769656603U, // VPADDLsv8i8
+ 771229467U, // VPADDLuv16i8
+ 770180891U, // VPADDLuv2i32
+ 770705179U, // VPADDLuv4i16
+ 770180891U, // VPADDLuv4i32
+ 770705179U, // VPADDLuv8i16
+ 771229467U, // VPADDLuv8i8
+ 152102690U, // VPADDf
+ 168822562U, // VPADDi16
+ 168298274U, // VPADDi32
+ 169346850U, // VPADDi8
+ 152102696U, // VPMAXf
+ 165152552U, // VPMAXs16
+ 164628264U, // VPMAXs32
+ 165676840U, // VPMAXs8
+ 166725416U, // VPMAXu16
+ 166201128U, // VPMAXu32
+ 167249704U, // VPMAXu8
+ 152102702U, // VPMINf
+ 165152558U, // VPMINs16
+ 164628270U, // VPMINs32
+ 165676846U, // VPMINs8
+ 166725422U, // VPMINu16
+ 166201134U, // VPMINu32
+ 167249710U, // VPMINu8
+ 769656628U, // VQABSv16i8
+ 768608052U, // VQABSv2i32
+ 769132340U, // VQABSv4i16
+ 768608052U, // VQABSv4i32
+ 769132340U, // VQABSv8i16
+ 769656628U, // VQABSv8i8
+ 165676858U, // VQADDsv16i8
+ 179308346U, // VQADDsv1i64
+ 164628282U, // VQADDsv2i32
+ 179308346U, // VQADDsv2i64
+ 165152570U, // VQADDsv4i16
+ 164628282U, // VQADDsv4i32
+ 165152570U, // VQADDsv8i16
+ 165676858U, // VQADDsv8i8
+ 167249722U, // VQADDuv16i8
+ 179832634U, // VQADDuv1i64
+ 166201146U, // VQADDuv2i32
+ 179832634U, // VQADDuv2i64
+ 166725434U, // VQADDuv4i16
+ 166201146U, // VQADDuv4i32
+ 166725434U, // VQADDuv8i16
+ 167249722U, // VQADDuv8i8
+ 231753536U, // VQDMLALslv2i32
+ 232277824U, // VQDMLALslv4i16
+ 835733312U, // VQDMLALv2i64
+ 836257600U, // VQDMLALv4i32
+ 231753544U, // VQDMLSLslv2i32
+ 232277832U, // VQDMLSLslv4i16
+ 835733320U, // VQDMLSLv2i64
+ 836257608U, // VQDMLSLv4i32
+ 835716944U, // VQDMULHslv2i32
+ 836241232U, // VQDMULHslv4i16
+ 835716944U, // VQDMULHslv4i32
+ 836241232U, // VQDMULHslv8i16
+ 164628304U, // VQDMULHv2i32
+ 165152592U, // VQDMULHv4i16
+ 164628304U, // VQDMULHv4i32
+ 165152592U, // VQDMULHv8i16
+ 835716952U, // VQDMULLslv2i32
+ 836241240U, // VQDMULLslv4i16
+ 164628312U, // VQDMULLv2i64
+ 165152600U, // VQDMULLv4i32
+ 783288160U, // VQMOVNsuv2i32
+ 768608096U, // VQMOVNsuv4i16
+ 769132384U, // VQMOVNsuv8i8
+ 783288168U, // VQMOVNsv2i32
+ 768608104U, // VQMOVNsv4i16
+ 769132392U, // VQMOVNsv8i8
+ 783812456U, // VQMOVNuv2i32
+ 770180968U, // VQMOVNuv4i16
+ 770705256U, // VQMOVNuv8i8
+ 769656687U, // VQNEGv16i8
+ 768608111U, // VQNEGv2i32
+ 769132399U, // VQNEGv4i16
+ 768608111U, // VQNEGv4i32
+ 769132399U, // VQNEGv8i16
+ 769656687U, // VQNEGv8i8
+ 835716981U, // VQRDMULHslv2i32
+ 836241269U, // VQRDMULHslv4i16
+ 835716981U, // VQRDMULHslv4i32
+ 836241269U, // VQRDMULHslv8i16
+ 164628341U, // VQRDMULHv2i32
+ 165152629U, // VQRDMULHv4i16
+ 164628341U, // VQRDMULHv4i32
+ 165152629U, // VQRDMULHv8i16
+ 165676926U, // VQRSHLsv16i8
+ 179308414U, // VQRSHLsv1i64
+ 164628350U, // VQRSHLsv2i32
+ 179308414U, // VQRSHLsv2i64
+ 165152638U, // VQRSHLsv4i16
+ 164628350U, // VQRSHLsv4i32
+ 165152638U, // VQRSHLsv8i16
+ 165676926U, // VQRSHLsv8i8
+ 167249790U, // VQRSHLuv16i8
+ 179832702U, // VQRSHLuv1i64
+ 166201214U, // VQRSHLuv2i32
+ 179832702U, // VQRSHLuv2i64
+ 166725502U, // VQRSHLuv4i16
+ 166201214U, // VQRSHLuv4i32
+ 166725502U, // VQRSHLuv8i16
+ 167249790U, // VQRSHLuv8i8
+ 179308421U, // VQRSHRNsv2i32
+ 164628357U, // VQRSHRNsv4i16
+ 165152645U, // VQRSHRNsv8i8
+ 179832709U, // VQRSHRNuv2i32
+ 166201221U, // VQRSHRNuv4i16
+ 166725509U, // VQRSHRNuv8i8
+ 179308429U, // VQRSHRUNv2i32
+ 164628365U, // VQRSHRUNv4i16
+ 165152653U, // VQRSHRUNv8i8
+ 165676950U, // VQSHLsiv16i8
+ 179308438U, // VQSHLsiv1i64
+ 164628374U, // VQSHLsiv2i32
+ 179308438U, // VQSHLsiv2i64
+ 165152662U, // VQSHLsiv4i16
+ 164628374U, // VQSHLsiv4i32
+ 165152662U, // VQSHLsiv8i16
+ 165676950U, // VQSHLsiv8i8
+ 165676956U, // VQSHLsuv16i8
+ 179308444U, // VQSHLsuv1i64
+ 164628380U, // VQSHLsuv2i32
+ 179308444U, // VQSHLsuv2i64
+ 165152668U, // VQSHLsuv4i16
+ 164628380U, // VQSHLsuv4i32
+ 165152668U, // VQSHLsuv8i16
+ 165676956U, // VQSHLsuv8i8
+ 165676950U, // VQSHLsv16i8
+ 179308438U, // VQSHLsv1i64
+ 164628374U, // VQSHLsv2i32
+ 179308438U, // VQSHLsv2i64
+ 165152662U, // VQSHLsv4i16
+ 164628374U, // VQSHLsv4i32
+ 165152662U, // VQSHLsv8i16
+ 165676950U, // VQSHLsv8i8
+ 167249814U, // VQSHLuiv16i8
+ 179832726U, // VQSHLuiv1i64
+ 166201238U, // VQSHLuiv2i32
+ 179832726U, // VQSHLuiv2i64
+ 166725526U, // VQSHLuiv4i16
+ 166201238U, // VQSHLuiv4i32
+ 166725526U, // VQSHLuiv8i16
+ 167249814U, // VQSHLuiv8i8
+ 167249814U, // VQSHLuv16i8
+ 179832726U, // VQSHLuv1i64
+ 166201238U, // VQSHLuv2i32
+ 179832726U, // VQSHLuv2i64
+ 166725526U, // VQSHLuv4i16
+ 166201238U, // VQSHLuv4i32
+ 166725526U, // VQSHLuv8i16
+ 167249814U, // VQSHLuv8i8
+ 179308451U, // VQSHRNsv2i32
+ 164628387U, // VQSHRNsv4i16
+ 165152675U, // VQSHRNsv8i8
+ 179832739U, // VQSHRNuv2i32
+ 166201251U, // VQSHRNuv4i16
+ 166725539U, // VQSHRNuv8i8
+ 179308458U, // VQSHRUNv2i32
+ 164628394U, // VQSHRUNv4i16
+ 165152682U, // VQSHRUNv8i8
+ 165676978U, // VQSUBsv16i8
+ 179308466U, // VQSUBsv1i64
+ 164628402U, // VQSUBsv2i32
+ 179308466U, // VQSUBsv2i64
+ 165152690U, // VQSUBsv4i16
+ 164628402U, // VQSUBsv4i32
+ 165152690U, // VQSUBsv8i16
+ 165676978U, // VQSUBsv8i8
+ 167249842U, // VQSUBuv16i8
+ 179832754U, // VQSUBuv1i64
+ 166201266U, // VQSUBuv2i32
+ 179832754U, // VQSUBuv2i64
+ 166725554U, // VQSUBuv4i16
+ 166201266U, // VQSUBuv4i32
+ 166725554U, // VQSUBuv8i16
+ 167249842U, // VQSUBuv8i8
+ 167774136U, // VRADDHNv2i32
+ 168298424U, // VRADDHNv4i16
+ 168822712U, // VRADDHNv8i8
+ 770181056U, // VRECPEd
+ 756082624U, // VRECPEfd
+ 756082624U, // VRECPEfq
+ 770181056U, // VRECPEq
+ 152102855U, // VRECPSfd
+ 152102855U, // VRECPSfq
+ 773875662U, // VREV16d8
+ 773875662U, // VREV16q8
+ 778594261U, // VREV32d16
+ 773875669U, // VREV32d8
+ 778594261U, // VREV32q16
+ 773875669U, // VREV32q8
+ 778594268U, // VREV64d16
+ 779118556U, // VREV64d32
+ 773875676U, // VREV64d8
+ 779118556U, // VREV64df
+ 778594268U, // VREV64q16
+ 779118556U, // VREV64q32
+ 773875676U, // VREV64q8
+ 779118556U, // VREV64qf
+ 165677027U, // VRHADDsv16i8
+ 164628451U, // VRHADDsv2i32
+ 165152739U, // VRHADDsv4i16
+ 164628451U, // VRHADDsv4i32
+ 165152739U, // VRHADDsv8i16
+ 165677027U, // VRHADDsv8i8
+ 167249891U, // VRHADDuv16i8
+ 166201315U, // VRHADDuv2i32
+ 166725603U, // VRHADDuv4i16
+ 166201315U, // VRHADDuv4i32
+ 166725603U, // VRHADDuv8i16
+ 167249891U, // VRHADDuv8i8
+ 165677034U, // VRSHLsv16i8
+ 179308522U, // VRSHLsv1i64
+ 164628458U, // VRSHLsv2i32
+ 179308522U, // VRSHLsv2i64
+ 165152746U, // VRSHLsv4i16
+ 164628458U, // VRSHLsv4i32
+ 165152746U, // VRSHLsv8i16
+ 165677034U, // VRSHLsv8i8
+ 167249898U, // VRSHLuv16i8
+ 179832810U, // VRSHLuv1i64
+ 166201322U, // VRSHLuv2i32
+ 179832810U, // VRSHLuv2i64
+ 166725610U, // VRSHLuv4i16
+ 166201322U, // VRSHLuv4i32
+ 166725610U, // VRSHLuv8i16
+ 167249898U, // VRSHLuv8i8
+ 167774192U, // VRSHRNv2i32
+ 168298480U, // VRSHRNv4i16
+ 168822768U, // VRSHRNv8i8
+ 165677047U, // VRSHRsv16i8
+ 179308535U, // VRSHRsv1i64
+ 164628471U, // VRSHRsv2i32
+ 179308535U, // VRSHRsv2i64
+ 165152759U, // VRSHRsv4i16
+ 164628471U, // VRSHRsv4i32
+ 165152759U, // VRSHRsv8i16
+ 165677047U, // VRSHRsv8i8
+ 167249911U, // VRSHRuv16i8
+ 179832823U, // VRSHRuv1i64
+ 166201335U, // VRSHRuv2i32
+ 179832823U, // VRSHRuv2i64
+ 166725623U, // VRSHRuv4i16
+ 166201335U, // VRSHRuv4i32
+ 166725623U, // VRSHRuv8i16
+ 167249911U, // VRSHRuv8i8
+ 770181117U, // VRSQRTEd
+ 756082685U, // VRSQRTEfd
+ 756082685U, // VRSQRTEfq
+ 770181117U, // VRSQRTEq
+ 152102917U, // VRSQRTSfd
+ 152102917U, // VRSQRTSfq
+ 836782093U, // VRSRAsv16i8
+ 850413581U, // VRSRAsv1i64
+ 835733517U, // VRSRAsv2i32
+ 850413581U, // VRSRAsv2i64
+ 836257805U, // VRSRAsv4i16
+ 835733517U, // VRSRAsv4i32
+ 836257805U, // VRSRAsv8i16
+ 836782093U, // VRSRAsv8i8
+ 838354957U, // VRSRAuv16i8
+ 850937869U, // VRSRAuv1i64
+ 837306381U, // VRSRAuv2i32
+ 850937869U, // VRSRAuv2i64
+ 837830669U, // VRSRAuv4i16
+ 837306381U, // VRSRAuv4i32
+ 837830669U, // VRSRAuv8i16
+ 838354957U, // VRSRAuv8i8
+ 167774227U, // VRSUBHNv2i32
+ 168298515U, // VRSUBHNv4i16
+ 168822803U, // VRSUBHNv8i8
+ 845701444U, // VSETLNi16
+ 846225732U, // VSETLNi32
+ 840982852U, // VSETLNi8
+ 168822811U, // VSHLLi16
+ 168298523U, // VSHLLi32
+ 169347099U, // VSHLLi8
+ 164628507U, // VSHLLsv2i64
+ 165152795U, // VSHLLsv4i32
+ 165677083U, // VSHLLsv8i16
+ 166201371U, // VSHLLuv2i64
+ 166725659U, // VSHLLuv4i32
+ 167249947U, // VSHLLuv8i16
+ 169347105U, // VSHLiv16i8
+ 167774241U, // VSHLiv1i64
+ 168298529U, // VSHLiv2i32
+ 167774241U, // VSHLiv2i64
+ 168822817U, // VSHLiv4i16
+ 168298529U, // VSHLiv4i32
+ 168822817U, // VSHLiv8i16
+ 169347105U, // VSHLiv8i8
+ 165677089U, // VSHLsv16i8
+ 179308577U, // VSHLsv1i64
+ 164628513U, // VSHLsv2i32
+ 179308577U, // VSHLsv2i64
+ 165152801U, // VSHLsv4i16
+ 164628513U, // VSHLsv4i32
+ 165152801U, // VSHLsv8i16
+ 165677089U, // VSHLsv8i8
+ 167249953U, // VSHLuv16i8
+ 179832865U, // VSHLuv1i64
+ 166201377U, // VSHLuv2i32
+ 179832865U, // VSHLuv2i64
+ 166725665U, // VSHLuv4i16
+ 166201377U, // VSHLuv4i32
+ 166725665U, // VSHLuv8i16
+ 167249953U, // VSHLuv8i8
+ 167774246U, // VSHRNv2i32
+ 168298534U, // VSHRNv4i16
+ 168822822U, // VSHRNv8i8
+ 165677100U, // VSHRsv16i8
+ 179308588U, // VSHRsv1i64
+ 164628524U, // VSHRsv2i32
+ 179308588U, // VSHRsv2i64
+ 165152812U, // VSHRsv4i16
+ 164628524U, // VSHRsv4i32
+ 165152812U, // VSHRsv8i16
+ 165677100U, // VSHRsv8i8
+ 167249964U, // VSHRuv16i8
+ 179832876U, // VSHRuv1i64
+ 166201388U, // VSHRuv2i32
+ 179832876U, // VSHRuv2i64
+ 166725676U, // VSHRuv4i16
+ 166201388U, // VSHRuv4i32
+ 166725676U, // VSHRuv8i16
+ 167249964U, // VSHRuv8i8
+ 180356706U, // VSHTOD
+ 180880994U, // VSHTOS
+ 785507938U, // VSITOD
+ 777643618U, // VSITOS
+ 840984625U, // VSLIv16i8
+ 848848945U, // VSLIv1i64
+ 846227505U, // VSLIv2i32
+ 848848945U, // VSLIv2i64
+ 845703217U, // VSLIv4i16
+ 846227505U, // VSLIv4i32
+ 845703217U, // VSLIv8i16
+ 840984625U, // VSLIv8i8
+ 181462626U, // VSLTOD
+ 173598306U, // VSLTOS
+ 755558454U, // VSQRTD
+ 756082742U, // VSQRTS
+ 836782140U, // VSRAsv16i8
+ 850413628U, // VSRAsv1i64
+ 835733564U, // VSRAsv2i32
+ 850413628U, // VSRAsv2i64
+ 836257852U, // VSRAsv4i16
+ 835733564U, // VSRAsv4i32
+ 836257852U, // VSRAsv8i16
+ 836782140U, // VSRAsv8i8
+ 838355004U, // VSRAuv16i8
+ 850937916U, // VSRAuv1i64
+ 837306428U, // VSRAuv2i32
+ 850937916U, // VSRAuv2i64
+ 837830716U, // VSRAuv4i16
+ 837306428U, // VSRAuv4i32
+ 837830716U, // VSRAuv8i16
+ 838355004U, // VSRAuv8i8
+ 840984641U, // VSRIv16i8
+ 848848961U, // VSRIv1i64
+ 846227521U, // VSRIv2i32
+ 848848961U, // VSRIv2i64
+ 845703233U, // VSRIv4i16
+ 846227521U, // VSRIv4i32
+ 845703233U, // VSRIv8i16
+ 840984641U, // VSRIv8i8
+ 242927686U, // VST1d16
+ 1316669510U, // VST1d16Q
+ 1383778374U, // VST1d16T
+ 243451974U, // VST1d32
+ 1317193798U, // VST1d32Q
+ 1384302662U, // VST1d32T
+ 243976262U, // VST1d64
+ 244500550U, // VST1d8
+ 1318242374U, // VST1d8Q
+ 1385351238U, // VST1d8T
+ 243451974U, // VST1df
+ 241887302U, // VST1q16
+ 242411590U, // VST1q32
+ 245033030U, // VST1q64
+ 237168710U, // VST1q8
+ 242411590U, // VST1qf
+ 1383778379U, // VST2LNd16
+ 1384302667U, // VST2LNd32
+ 1385351243U, // VST2LNd8
+ 1383778379U, // VST2LNq16a
+ 1383778379U, // VST2LNq16b
+ 1384302667U, // VST2LNq32a
+ 1384302667U, // VST2LNq32b
+ 645580875U, // VST2d16
+ 645580875U, // VST2d16D
+ 646105163U, // VST2d32
+ 646105163U, // VST2d32D
+ 646629446U, // VST2d64
+ 647153739U, // VST2d8
+ 647153739U, // VST2d8D
+ 1316669515U, // VST2q16
+ 1317193803U, // VST2q32
+ 1318242379U, // VST2q8
+ 1316669520U, // VST3LNd16
+ 1317193808U, // VST3LNd32
+ 1318242384U, // VST3LNd8
+ 1316669520U, // VST3LNq16a
+ 1316669520U, // VST3LNq16b
+ 1317193808U, // VST3LNq32a
+ 1317193808U, // VST3LNq32b
+ 1383778384U, // VST3d16
+ 1384302672U, // VST3d32
+ 1384826950U, // VST3d64
+ 1385351248U, // VST3d8
+ 1316685904U, // VST3q16a
+ 1316685904U, // VST3q16b
+ 1317210192U, // VST3q32a
+ 1317210192U, // VST3q32b
+ 1318258768U, // VST3q8a
+ 1318258768U, // VST3q8b
+ 1450887253U, // VST4LNd16
+ 1451411541U, // VST4LNd32
+ 1452460117U, // VST4LNd8
+ 1450887253U, // VST4LNq16a
+ 1450887253U, // VST4LNq16b
+ 1451411541U, // VST4LNq32a
+ 1451411541U, // VST4LNq32b
+ 1316669525U, // VST4d16
+ 1317193813U, // VST4d32
+ 1317718086U, // VST4d64
+ 1318242389U, // VST4d8
+ 1450903637U, // VST4q16a
+ 1450903637U, // VST4q16b
+ 1451427925U, // VST4q32a
+ 1451427925U, // VST4q32b
+ 1452476501U, // VST4q8a
+ 1452476501U, // VST4q8b
+ 1610614874U, // VSTMD
+ 1610614874U, // VSTMS
+ 177760351U, // VSTRD
+ 135932004U, // VSTRQ
+ 175138911U, // VSTRS
+ 151578731U, // VSUBD
+ 167774320U, // VSUBHNv2i32
+ 168298608U, // VSUBHNv4i16
+ 168822896U, // VSUBHNv8i8
+ 164628599U, // VSUBLsv2i64
+ 165152887U, // VSUBLsv4i32
+ 165677175U, // VSUBLsv8i16
+ 166201463U, // VSUBLuv2i64
+ 166725751U, // VSUBLuv4i32
+ 167250039U, // VSUBLuv8i16
+ 152103019U, // VSUBS
+ 164628605U, // VSUBWsv2i64
+ 165152893U, // VSUBWsv4i32
+ 165677181U, // VSUBWsv8i16
+ 166201469U, // VSUBWuv2i64
+ 166725757U, // VSUBWuv4i32
+ 167250045U, // VSUBWuv8i16
+ 152103019U, // VSUBfd
+ 152103019U, // VSUBfd_sfp
+ 152103019U, // VSUBfq
+ 169347179U, // VSUBv16i8
+ 167774315U, // VSUBv1i64
+ 168298603U, // VSUBv2i32
+ 167774315U, // VSUBv2i64
+ 168822891U, // VSUBv4i16
+ 168298603U, // VSUBv4i32
+ 168822891U, // VSUBv8i16
+ 169347179U, // VSUBv8i8
+ 739797123U, // VSWPd
+ 739797123U, // VSWPq
+ 169896072U, // VTBL1
+ 840984712U, // VTBL2
+ 237004936U, // VTBL3
+ 639658120U, // VTBL4
+ 840984717U, // VTBX1
+ 237004941U, // VTBX2
+ 639658125U, // VTBX3
+ 1377855629U, // VTBX4
+ 181929570U, // VTOSHD
+ 182453858U, // VTOSHS
+ 787081362U, // VTOSIRD
+ 776595602U, // VTOSIRS
+ 787080802U, // VTOSIZD
+ 776595042U, // VTOSIZS
+ 183035490U, // VTOSLD
+ 172549730U, // VTOSLS
+ 183502434U, // VTOUHD
+ 184026722U, // VTOUHS
+ 788654226U, // VTOUIRD
+ 777119890U, // VTOUIRS
+ 788653666U, // VTOUIZD
+ 777119330U, // VTOUIZS
+ 184608354U, // VTOULD
+ 173074018U, // VTOULS
+ 845703320U, // VTRNd16
+ 846227608U, // VTRNd32
+ 840984728U, // VTRNd8
+ 845703320U, // VTRNq16
+ 846227608U, // VTRNq32
+ 840984728U, // VTRNq8
+ 169896093U, // VTSTv16i8
+ 175138973U, // VTSTv2i32
+ 174614685U, // VTSTv4i16
+ 175138973U, // VTSTv4i32
+ 174614685U, // VTSTv8i16
+ 169896093U, // VTSTv8i8
+ 185075298U, // VUHTOD
+ 185599586U, // VUHTOS
+ 790226530U, // VUITOD
+ 778167906U, // VUITOS
+ 186181218U, // VULTOD
+ 174122594U, // VULTOS
+ 845703330U, // VUZPd16
+ 846227618U, // VUZPd32
+ 840984738U, // VUZPd8
+ 845703330U, // VUZPq16
+ 846227618U, // VUZPq32
+ 840984738U, // VUZPq8
+ 845703335U, // VZIPd16
+ 846227623U, // VZIPd32
+ 840984743U, // VZIPd8
+ 845703335U, // VZIPq16
+ 846227623U, // VZIPq32
+ 840984743U, // VZIPq8
+ 538970284U, // WFE
+ 538970288U, // WFI
+ 538970292U, // YIELD
+ 1679319057U, // t2ADCSri
+ 1730207761U, // t2ADCSrr
+ 1797316625U, // t2ADCSrs
+ 1679319057U, // t2ADCri
+ 1730207761U, // t2ADCrr
+ 1797316625U, // t2ADCrs
+ 186703893U, // t2ADDSri
+ 186703893U, // t2ADDSrr
+ 857792533U, // t2ADDSrs
+ 1730207770U, // t2ADDrSPi
+ 135817402U, // t2ADDrSPi12
+ 1797316634U, // t2ADDrSPs
+ 1730207770U, // t2ADDri
+ 1679321274U, // t2ADDri12
+ 1730207770U, // t2ADDrr
+ 1797316634U, // t2ADDrs
+ 1679319108U, // t2ANDri
+ 1730207812U, // t2ANDrr
+ 1797316676U, // t2ANDrs
+ 1730209983U, // t2ASRri
+ 1730209983U, // t2ASRrr
+ 69208259U, // t2B
+ 135815244U, // t2BFC
+ 806903888U, // t2BFI
+ 1679319124U, // t2BICri
+ 1730207828U, // t2BICrr
+ 1797316692U, // t2BICrs
+ 120062079U, // t2BR_JT
+ 337141912U, // t2BXJ
+ 388096159U, // t2Bcc
+ 538968236U, // t2CLREX
+ 739795122U, // t2CLZ
+ 790683830U, // t2CMNzri
+ 790683830U, // t2CMNzrr
+ 186704054U, // t2CMNzrs
+ 790683834U, // t2CMPri
+ 790683834U, // t2CMPrr
+ 186704058U, // t2CMPrs
+ 790683834U, // t2CMPzri
+ 790683834U, // t2CMPzrr
+ 186704058U, // t2CMPzrs
+ 939524286U, // t2CPS
+ 337141954U, // t2DBG
+ 590348639U, // t2DMBish
+ 590872927U, // t2DMBishst
+ 591397215U, // t2DMBnsh
+ 591921503U, // t2DMBnshst
+ 592445791U, // t2DMBosh
+ 592970079U, // t2DMBoshst
+ 593494367U, // t2DMBst
+ 590348643U, // t2DSBish
+ 590872931U, // t2DSBishst
+ 591397219U, // t2DSBnsh
+ 591921507U, // t2DSBnshst
+ 592445795U, // t2DSBosh
+ 592970083U, // t2DSBoshst
+ 593494371U, // t2DSBst
+ 1679319360U, // t2EORri
+ 1730208064U, // t2EORrr
+ 1797316928U, // t2EORrs
+ 538968398U, // t2ISBsy
+ 1811941576U, // t2IT
+ 351U, // t2Int_MemBarrierV7
+ 355U, // t2Int_SyncBarrierV7
+ 1879050443U, // t2Int_eh_sjlj_setjmp
+ 1027809658U, // t2LDM
+ 1027809658U, // t2LDM_RET
+ 135815559U, // t2LDRBT
+ 806904194U, // t2LDRB_POST
+ 806904194U, // t2LDRB_PRE
+ 186704258U, // t2LDRBi12
+ 135815554U, // t2LDRBi8
+ 790684034U, // t2LDRBpci
+ 857792898U, // t2LDRBs
+ 806904205U, // t2LDRDi8
+ 135815565U, // t2LDRDpci
+ 739795346U, // t2LDREX
+ 739795352U, // t2LDREXB
+ 135815583U, // t2LDREXD
+ 739795366U, // t2LDREXH
+ 135815602U, // t2LDRHT
+ 806904237U, // t2LDRH_POST
+ 806904237U, // t2LDRH_PRE
+ 186704301U, // t2LDRHi12
+ 135815597U, // t2LDRHi8
+ 790684077U, // t2LDRHpci
+ 857792941U, // t2LDRHs
+ 135815614U, // t2LDRSBT
+ 806904248U, // t2LDRSB_POST
+ 806904248U, // t2LDRSB_PRE
+ 186704312U, // t2LDRSBi12
+ 135815608U, // t2LDRSBi8
+ 790684088U, // t2LDRSBpci
+ 857792952U, // t2LDRSBs
+ 135815627U, // t2LDRSHT
+ 806904261U, // t2LDRSH_POST
+ 806904261U, // t2LDRSH_PRE
+ 186704325U, // t2LDRSHi12
+ 135815621U, // t2LDRSHi8
+ 790684101U, // t2LDRSHpci
+ 857792965U, // t2LDRSHs
+ 135815634U, // t2LDRT
+ 806904190U, // t2LDR_POST
+ 806904190U, // t2LDR_PRE
+ 186704254U, // t2LDRi12
+ 135815550U, // t2LDRi8
+ 790684030U, // t2LDRpci
+ 67111120U, // t2LDRpci_pic
+ 857792894U, // t2LDRs
+ 790841561U, // t2LEApcrel
+ 186861785U, // t2LEApcrelJT
+ 1730210013U, // t2LSLri
+ 1730210013U, // t2LSLrr
+ 1730210017U, // t2LSRri
+ 1730210017U, // t2LSRrr
+ 806904309U, // t2MLA
+ 806904313U, // t2MLS
+ 857794751U, // t2MOVCCasr
+ 186704381U, // t2MOVCCi
+ 857794781U, // t2MOVCClsl
+ 857794785U, // t2MOVCClsr
+ 186704381U, // t2MOVCCr
+ 857794789U, // t2MOVCCror
+ 135815681U, // t2MOVTi16
+ 1967350269U, // t2MOVi
+ 739795462U, // t2MOVi16
+ 739795462U, // t2MOVi32imm
+ 1967350269U, // t2MOVr
+ 1967212777U, // t2MOVrx
+ 67111149U, // t2MOVsra_flag
+ 67111157U, // t2MOVsrl_flag
+ 337142312U, // t2MRS
+ 337142312U, // t2MRSsys
+ 359162412U, // t2MSR
+ 359686700U, // t2MSRsys
+ 135815728U, // t2MUL
+ 1967211060U, // t2MVNi
+ 790684212U, // t2MVNr
+ 186704436U, // t2MVNs
+ 594018872U, // t2NOP
+ 1679321341U, // t2ORNri
+ 1679321341U, // t2ORNrr
+ 1746430205U, // t2ORNrs
+ 1679319612U, // t2ORRri
+ 1730208316U, // t2ORRrr
+ 1797317180U, // t2ORRrs
+ 806904386U, // t2PKHBT
+ 806904392U, // t2PKHTB
+ 740002049U, // t2PLDWi12
+ 740010241U, // t2PLDWi8
+ 795871489U, // t2PLDWpci
+ 796641537U, // t2PLDWr
+ 192669953U, // t2PLDWs
+ 740002054U, // t2PLDi12
+ 740010246U, // t2PLDi8
+ 795871494U, // t2PLDpci
+ 796641542U, // t2PLDr
+ 192669958U, // t2PLDs
+ 740002058U, // t2PLIi12
+ 740010250U, // t2PLIi8
+ 795871498U, // t2PLIpci
+ 796641546U, // t2PLIr
+ 192669962U, // t2PLIs
+ 135815793U, // t2QADD
+ 135815798U, // t2QADD16
+ 135815805U, // t2QADD8
+ 135815811U, // t2QASX
+ 135815816U, // t2QDADD
+ 135815822U, // t2QDSUB
+ 135815828U, // t2QSAX
+ 135815833U, // t2QSUB
+ 135815838U, // t2QSUB16
+ 135815845U, // t2QSUB8
+ 739795627U, // t2RBIT
+ 790684336U, // t2REV
+ 790684340U, // t2REV16
+ 790684346U, // t2REVSH
+ 337144078U, // t2RFEDB
+ 337144084U, // t2RFEDBW
+ 337144090U, // t2RFEIA
+ 337144090U, // t2RFEIAW
+ 1730210021U, // t2RORri
+ 1730210021U, // t2RORrr
+ 2013266633U, // t2RSBSri
+ 1947755209U, // t2RSBSrs
+ 186704585U, // t2RSBri
+ 806904521U, // t2RSBrs
+ 135815895U, // t2SADD16
+ 135815902U, // t2SADD8
+ 135815908U, // t2SASX
+ 1679319791U, // t2SBCSri
+ 1730208495U, // t2SBCSrr
+ 1797317359U, // t2SBCSrs
+ 1679319791U, // t2SBCri
+ 1730208495U, // t2SBCrr
+ 1797317359U, // t2SBCrs
+ 806904563U, // t2SBFX
+ 135817504U, // t2SDIV
+ 135815928U, // t2SEL
+ 594019088U, // t2SEV
+ 135815956U, // t2SHADD16
+ 135815964U, // t2SHADD8
+ 135815971U, // t2SHASX
+ 135815977U, // t2SHSAX
+ 135815983U, // t2SHSUB16
+ 135815991U, // t2SHSUB8
+ 337142590U, // t2SMC
+ 806904642U, // t2SMLABB
+ 806904649U, // t2SMLABT
+ 806904656U, // t2SMLAD
+ 806904662U, // t2SMLADX
+ 806904669U, // t2SMLAL
+ 806904675U, // t2SMLALBB
+ 806904683U, // t2SMLALBT
+ 806904691U, // t2SMLALD
+ 806904698U, // t2SMLALDX
+ 806904706U, // t2SMLALTB
+ 806904714U, // t2SMLALTT
+ 806904722U, // t2SMLATB
+ 806904729U, // t2SMLATT
+ 806904736U, // t2SMLAWB
+ 806904743U, // t2SMLAWT
+ 806904750U, // t2SMLSD
+ 806904756U, // t2SMLSDX
+ 806904763U, // t2SMLSLD
+ 806904770U, // t2SMLSLDX
+ 806904778U, // t2SMMLA
+ 806904784U, // t2SMMLAR
+ 806904791U, // t2SMMLS
+ 806904797U, // t2SMMLSR
+ 135816164U, // t2SMMUL
+ 135816170U, // t2SMMULR
+ 135816177U, // t2SMUAD
+ 135816183U, // t2SMUADX
+ 135816190U, // t2SMULBB
+ 135816197U, // t2SMULBT
+ 806904844U, // t2SMULL
+ 135816210U, // t2SMULTB
+ 135816217U, // t2SMULTT
+ 135816224U, // t2SMULWB
+ 135816231U, // t2SMULWT
+ 135816238U, // t2SMUSD
+ 135816244U, // t2SMUSDX
+ 364931365U, // t2SRSDB
+ 365455653U, // t2SRSDBW
+ 364931371U, // t2SRSIA
+ 365455659U, // t2SRSIAW
+ 135816255U, // t2SSAT16
+ 806904902U, // t2SSATasr
+ 806904902U, // t2SSATlsl
+ 135816267U, // t2SSAX
+ 135816272U, // t2SSUB16
+ 135816279U, // t2SSUB8
+ 1027810406U, // t2STM
+ 135816307U, // t2STRBT
+ 806880366U, // t2STRB_POST
+ 806880366U, // t2STRB_PRE
+ 186705006U, // t2STRBi12
+ 135816302U, // t2STRBi8
+ 857793646U, // t2STRBs
+ 806904953U, // t2STRDi8
+ 135816318U, // t2STREX
+ 135816324U, // t2STREXB
+ 806904971U, // t2STREXD
+ 135816338U, // t2STREXH
+ 135816350U, // t2STRHT
+ 806880409U, // t2STRH_POST
+ 806880409U, // t2STRH_PRE
+ 186705049U, // t2STRHi12
+ 135816345U, // t2STRHi8
+ 857793689U, // t2STRHs
+ 135816356U, // t2STRT
+ 806880362U, // t2STR_POST
+ 806880362U, // t2STR_PRE
+ 186705002U, // t2STRi12
+ 135816298U, // t2STRi8
+ 857793642U, // t2STRs
+ 186705065U, // t2SUBSri
+ 186705065U, // t2SUBSrr
+ 857793705U, // t2SUBSrs
+ 1730208942U, // t2SUBrSPi
+ 135817521U, // t2SUBrSPi12
+ 67111222U, // t2SUBrSPi12_
+ 67111230U, // t2SUBrSPi_
+ 1746429102U, // t2SUBrSPs
+ 67111239U, // t2SUBrSPs_
+ 1730208942U, // t2SUBri
+ 1679321393U, // t2SUBri12
+ 1730208942U, // t2SUBrr
+ 1797317806U, // t2SUBrs
+ 135816383U, // t2SXTAB16rr
+ 806905023U, // t2SXTAB16rr_rot
+ 135816391U, // t2SXTABrr
+ 806905031U, // t2SXTABrr_rot
+ 135816397U, // t2SXTAHrr
+ 806905037U, // t2SXTAHrr_rot
+ 739796179U, // t2SXTB16r
+ 135816403U, // t2SXTB16r_rot
+ 790684890U, // t2SXTBr
+ 186705114U, // t2SXTBr_rot
+ 790684895U, // t2SXTHr
+ 186705119U, // t2SXTHr_rot
+ 2080377166U, // t2TBB
+ 796641619U, // t2TBBgen
+ 2080377175U, // t2TBH
+ 796658012U, // t2TBHgen
+ 790684900U, // t2TEQri
+ 790684900U, // t2TEQrr
+ 186705124U, // t2TEQrs
+ 1256U, // t2TPsoft
+ 790684928U, // t2TSTri
+ 790684928U, // t2TSTrr
+ 186705152U, // t2TSTrs
+ 135816452U, // t2UADD16
+ 135816459U, // t2UADD8
+ 135816465U, // t2UASX
+ 806905110U, // t2UBFX
+ 135817568U, // t2UDIV
+ 135816475U, // t2UHADD16
+ 135816483U, // t2UHADD8
+ 135816490U, // t2UHASX
+ 135816496U, // t2UHSAX
+ 135816502U, // t2UHSUB16
+ 135816510U, // t2UHSUB8
+ 806905157U, // t2UMAAL
+ 806905163U, // t2UMLAL
+ 806905169U, // t2UMULL
+ 135816535U, // t2UQADD16
+ 135816543U, // t2UQADD8
+ 135816550U, // t2UQASX
+ 135816556U, // t2UQSAX
+ 135816562U, // t2UQSUB16
+ 135816570U, // t2UQSUB8
+ 135816577U, // t2USAD8
+ 806905223U, // t2USADA8
+ 135816590U, // t2USAT16
+ 806905237U, // t2USATasr
+ 806905237U, // t2USATlsl
+ 135816602U, // t2USAX
+ 135816607U, // t2USUB16
+ 135816614U, // t2USUB8
+ 135816620U, // t2UXTAB16rr
+ 806905260U, // t2UXTAB16rr_rot
+ 135816628U, // t2UXTABrr
+ 806905268U, // t2UXTABrr_rot
+ 135816634U, // t2UXTAHrr
+ 806905274U, // t2UXTAHrr_rot
+ 739796416U, // t2UXTB16r
+ 135816640U, // t2UXTB16r_rot
+ 790685127U, // t2UXTBr
+ 186705351U, // t2UXTBr_rot
+ 790685132U, // t2UXTHr
+ 186705356U, // t2UXTHr_rot
+ 594020524U, // t2WFE
+ 594020528U, // t2WFI
+ 594020532U, // t2YIELD
+ 2206474257U, // tADC
+ 135815194U, // tADDhirr
+ 2206220314U, // tADDi3
+ 2206474266U, // tADDi8
+ 126355813U, // tADDrPCi
+ 67127653U, // tADDrSP
+ 67111269U, // tADDrSPi
+ 2206220314U, // tADDrr
+ 67389797U, // tADDspi
+ 67127653U, // tADDspr
+ 67127658U, // tADDspr_
+ 69208433U, // tADJCALLSTACKDOWN
+ 69208454U, // tADJCALLSTACKUP
+ 2206474308U, // tAND
+ 67127705U, // tANDsp
+ 2206222527U, // tASRri
+ 2206476479U, // tASRrr
69206089U, // tB
- 2200305744U, // tBIC
- 69207864U, // tBKPT
- 402653273U, // tBL
- 402653277U, // tBLXi
- 402653277U, // tBLXi_r9
- 69206109U, // tBLXr
- 69206109U, // tBLXr_r9
- 402653273U, // tBLr9
- 69206139U, // tBRIND
- 120586363U, // tBR_JTr
- 69206148U, // tBX
- 1854U, // tBX_RET
- 69206117U, // tBX_RET_vararg
- 69206148U, // tBXr9
- 337166491U, // tBcc
- 121110617U, // tBfar
- 67110724U, // tCBNZ
- 67110730U, // tCBZ
- 739819692U, // tCMNz
- 739819696U, // tCMPhir
- 739819696U, // tCMPi8
- 739819696U, // tCMPr
- 739819696U, // tCMPzhir
- 739819696U, // tCMPzi8
- 739819696U, // tCMPzr
- 2200305852U, // tEOR
- 1879049880U, // tInt_eh_sjlj_setjmp
- 1008320745U, // tLDM
- 806928621U, // tLDR
- 806928625U, // tLDRB
- 806928625U, // tLDRBi
- 806928662U, // tLDRH
- 806928662U, // tLDRHi
- 135840027U, // tLDRSB
- 135840033U, // tLDRSH
- 739819757U, // tLDRcp
- 806928621U, // tLDRi
- 792723693U, // tLDRpci
- 67110735U, // tLDRpci_pic
- 135839981U, // tLDRspi
- 739821222U, // tLEApcrel
- 135841446U, // tLEApcrelJT
- 2199946922U, // tLSLri
- 2200307370U, // tLSLrr
- 2199946926U, // tLSRri
- 2200307374U, // tLSRrr
- 135840082U, // tMOVCCi
- 135840082U, // tMOVCCr
- 136316760U, // tMOVCCr_pseudo
- 67110755U, // tMOVSr
- 67110761U, // tMOVgpr2gpr
- 67110761U, // tMOVgpr2tgpr
- 2202714450U, // tMOVi8
- 67110761U, // tMOVr
- 67110761U, // tMOVtgpr2gpr
- 2200306049U, // tMUL
- 2202714501U, // tMVN
- 2200306061U, // tORR
- 1196425617U, // tPICADD
- 538871662U, // tPOP
- 538871662U, // tPOP_RET
- 538871666U, // tPUSH
- 739819998U, // tREV
- 739820002U, // tREV16
- 739820008U, // tREVSH
- 2200307378U, // tROR
- 2202698227U, // tRSB
- 135839981U, // tRestore
- 2200306183U, // tSBC
- 1008321210U, // tSTM
- 806929086U, // tSTR
- 806929090U, // tSTRB
- 806929090U, // tSTRBi
- 806929133U, // tSTRH
- 806929133U, // tSTRHi
- 806929086U, // tSTRi
- 135840446U, // tSTRspi
- 2199945980U, // tSUBi3
- 2200306428U, // tSUBi8
- 2199945980U, // tSUBrr
- 67520375U, // tSUBspi
- 67520236U, // tSUBspi_
- 739820313U, // tSXTB
- 739820318U, // tSXTH
- 135840446U, // tSpill
- 807U, // tTPsoft
- 739820351U, // tTST
- 739820439U, // tUXTB
- 739820444U, // tUXTH
+ 2206474324U, // tBIC
+ 69208480U, // tBKPT
+ 402653277U, // tBL
+ 402653281U, // tBLXi
+ 402653281U, // tBLXi_r9
+ 69206113U, // tBLXr
+ 69206113U, // tBLXr_r9
+ 402653277U, // tBLr9
+ 69206143U, // tBRIND
+ 126877823U, // tBR_JTr
+ 69206152U, // tBX
+ 2470U, // tBX_RET
+ 69206121U, // tBX_RET_vararg
+ 69206152U, // tBXr9
+ 337141919U, // tBcc
+ 127402077U, // tBfar
+ 67111340U, // tCBNZ
+ 67111346U, // tCBZ
+ 739795126U, // tCMNz
+ 739795130U, // tCMPhir
+ 739795130U, // tCMPi8
+ 739795130U, // tCMPr
+ 739795130U, // tCMPzhir
+ 739795130U, // tCMPzi8
+ 739795130U, // tCMPzr
+ 939524286U, // tCPS
+ 2206474560U, // tEOR
+ 1879050443U, // tInt_eh_sjlj_setjmp
+ 1027686778U, // tLDM
+ 806904190U, // tLDR
+ 806904194U, // tLDRB
+ 806904194U, // tLDRBi
+ 806904237U, // tLDRH
+ 806904237U, // tLDRHi
+ 135815608U, // tLDRSB
+ 135815621U, // tLDRSH
+ 739795326U, // tLDRcp
+ 806904190U, // tLDRi
+ 799015294U, // tLDRpci
+ 67111351U, // tLDRpci_pic
+ 135815550U, // tLDRspi
+ 739797209U, // tLEApcrel
+ 135817433U, // tLEApcrelJT
+ 2206222557U, // tLSLri
+ 2206476509U, // tLSLrr
+ 2206222561U, // tLSRri
+ 2206476513U, // tLSRrr
+ 135815677U, // tMOVCCi
+ 135815677U, // tMOVCCr
+ 136317376U, // tMOVCCr_pseudo
+ 67111371U, // tMOVSr
+ 67111377U, // tMOVgpr2gpr
+ 67111377U, // tMOVgpr2tgpr
+ 2208948733U, // tMOVi8
+ 67111377U, // tMOVr
+ 67111377U, // tMOVtgpr2gpr
+ 2206474800U, // tMUL
+ 2208948788U, // tMVN
+ 538968632U, // tNOP
+ 2206474812U, // tORR
+ 1202717248U, // tPICADD
+ 538733014U, // tPOP
+ 538733014U, // tPOP_RET
+ 538733018U, // tPUSH
+ 739795632U, // tREV
+ 739795636U, // tREV16
+ 739795642U, // tREVSH
+ 2206476517U, // tROR
+ 2208940745U, // tRSB
+ 135815550U, // tRestore
+ 2206474991U, // tSBC
+ 764U, // tSETENDBE
+ 774U, // tSETENDLE
+ 538968848U, // tSEV
+ 1027687526U, // tSTM
+ 806904938U, // tSTR
+ 806904942U, // tSTRB
+ 806904942U, // tSTRBi
+ 806904985U, // tSTRH
+ 806904985U, // tSTRHi
+ 806904938U, // tSTRi
+ 135816298U, // tSTRspi
+ 2206221486U, // tSUBi3
+ 2206475438U, // tSUBi8
+ 2206221486U, // tSUBrr
+ 67389919U, // tSUBspi
+ 67389767U, // tSUBspi_
+ 337142962U, // tSVC
+ 739796186U, // tSXTB
+ 739796191U, // tSXTH
+ 135816298U, // tSpill
+ 1256U, // tTPsoft
+ 1275U, // tTRAP
+ 739796224U, // tTST
+ 739796423U, // tUXTB
+ 739796428U, // tUXTH
+ 538970284U, // tWFE
+ 538970288U, // tWFI
+ 538970292U, // tYIELD
0U
};
const char *AsmStrs =
"DBG_VALUE\000adcs\t\000adc\000adds\000add\000@ ADJCALLSTACKDOWN \000@ A"
- "DJCALLSTACKUP \000and\000\000b\t\000bfc\000bic\000bkpt\000bl\t\000blx\t"
- "\000bl\000bx\t\000add\tpc, \000ldr\tpc, \000mov\tpc, \000mov\tlr, pc\n\t"
- "bx\t\000bxj\000bx\000b\000cdp\000cdp2\tp\000clz\000cmn\000cmp\000cps\000"
- "dbg\000eor\000vmov\000vmrs\000mcr\tp15, 0, \000dmb\000dsb\000str\tsp, ["
- "\000ldm\000ldr\000ldrb\000ldrd\000ldrex\000ldrexb\000ldrexd\000ldrexh\000"
- "ldrh\000ldrsb\000ldrsh\000ldrt\000.set \000mcr\000mcr2\tp\000mcrr\000mc"
- "rr2\tp\000mla\000mls\000mov\000movt\000movw\000movs\000mrc\000mrc2\tp\000"
- "mrrc\000mrrc2\tp\000mrs\000mul\000mvn\000nop\000orr\000\n\000pkhbt\000p"
- "khtb\000qadd\000qadd16\000qadd8\000qasx\000qdadd\000qdsub\000qsax\000qs"
- "ub\000qsub16\000qsub8\000rbit\000rev\000rev16\000revsh\000rsbs\000rsb\000"
- "rscs\t\000rsc\000sbcs\t\000sbc\000sbfx\000setend\tbe\000setend\tle\000s"
- "ev\000smlabb\000smlabt\000smlal\000smlalbb\000smlalbt\000smlaltb\000sml"
- "altt\000smlatb\000smlatt\000smlawb\000smlawt\000smmla\000smmls\000smmul"
- "\000smulbb\000smulbt\000smull\000smultb\000smultt\000smulwb\000smulwt\000"
- "stm\000str\000strb\000strbt\000strd\000strex\000strexb\000strexd\000str"
- "exh\000strh\000strt\000subs\000sub\000svc\000swp\000swpb\000sxtab\000sx"
- "tah\000sxtb\000sxth\000teq\000bl\t__aeabi_read_tp\000trap\000tst\000ubf"
- "x\000umaal\000umlal\000umull\000uqadd16\000uqadd8\000uqasx\000uqsax\000"
- "uqsub16\000uqsub8\000uxtab\000uxtah\000uxtb16\000uxtb\000uxth\000vabal\000"
- "vaba\000vabdl\000vabd\000vabs\000vacge\000vacgt\000vadd\000vaddhn\000va"
- "ddl\000vaddw\000vand\000vbic\000vbif\000vbit\000vbsl\000vceq\000vcge\000"
- "vcgt\000vcls\000vclz\000vcmp\000vcmpe\000vcnt\000vcvtb\000vcvt\000vcvtt"
- "\000vdiv\000vdup\000veor\000vext\000vhadd\000vhsub\000vld1\000vld2\000v"
- "ld3\000vld4\000vldm\000vldr\000vldmia\000vmax\000vmin\000vmla\000vmlal\000"
- "vmls\000vmlsl\000vmovl\000vmovn\000vmsr\000vmul\000vmull\000vmvn\000vne"
- "g\000vnmla\000vnmls\000vnmul\000vorn\000vorr\000vpadal\000vpaddl\000vpa"
- "dd\000vpmax\000vpmin\000vqabs\000vqadd\000vqdmlal\000vqdmlsl\000vqdmulh"
- "\000vqdmull\000vqmovun\000vqmovn\000vqneg\000vqrdmulh\000vqrshl\000vqrs"
- "hrn\000vqrshrun\000vqshl\000vqshlu\000vqshrn\000vqshrun\000vqsub\000vra"
- "ddhn\000vrecpe\000vrecps\000vrev16\000vrev32\000vrev64\000vrhadd\000vrs"
- "hl\000vrshrn\000vrshr\000vrsqrte\000vrsqrts\000vrsra\000vrsubhn\000vshl"
- "l\000vshl\000vshrn\000vshr\000vsli\000vsqrt\000vsra\000vsri\000vst1\000"
- "vst2\000vst3\000vst4\000vstm\000vstr\000vstmia\000vsub\000vsubhn\000vsu"
- "bl\000vsubw\000vtbl\000vtbx\000vcvtr\000vtrn\000vtst\000vuzp\000vzip\000"
- "wfe\000wfi\000yield\000adcs.w\t\000addw\000asr\000b.w\t\000bfi\000it\000"
- "str\t\000@ ldr.w\t\000adr\000lsl\000lsr\000ror\000rrx\000asrs.w\t\000ls"
- "rs.w\t\000orn\000sbcs.w\t\000subw\000@ subw\t\000@ sub.w\t\000@ sub\t\000"
- "tbb\t\000tbh\t\000add\t\000@ add\t\000@ tADJCALLSTACKDOWN \000@ tADJCAL"
- "LSTACKUP \000@ and\t\000bkpt\t\000bx\tlr\000cbnz\t\000cbz\t\000@ ldr.n\t"
- "\000@ tMOVCCr \000movs\t\000mov\t\000pop\000push\000sub\t\000";
+ "DJCALLSTACKUP \000and\000\000b\t\000bfc\000bfi\000bic\000bkpt\000bl\t\000"
+ "blx\t\000bl\000bx\t\000add\tpc, \000ldr\tpc, \000mov\tpc, \000mov\tlr, "
+ "pc\n\tbx\t\000bxj\000bx\000b\000cdp\000cdp2\tp\000clrex\000clz\000cmn\000"
+ "cmp\000cps\000dbg\000dmb\tish\000dmb\tishst\000dmb\tnsh\000dmb\tnshst\000"
+ "dmb\tosh\000dmb\toshst\000dmb\tst\000dsb\tish\000dsb\tishst\000dsb\tnsh"
+ "\000dsb\tnshst\000dsb\tosh\000dsb\toshst\000dsb\tst\000eor\000vmov\000v"
+ "mrs\000isb\000mcr\tp15, 0, \000dmb\000dsb\000str\tsp, [\000ldc2\000ldc\000"
+ "ldm\000ldr\000ldrb\000ldrbt\000ldrd\000ldrex\000ldrexb\000ldrexd\000ldr"
+ "exh\000ldrh\000ldrht\000ldrsb\000ldrsbt\000ldrsh\000ldrsht\000ldrt\000."
+ "set \000mcr\000mcr2\tp\000mcrr\000mcrr2\tp\000mla\000mls\000mov\000movt"
+ "\000movw\000movs\000mrc\000mrc2\tp\000mrrc\000mrrc2\tp\000mrs\000msr\000"
+ "mul\000mvn\000nop\000orr\000\n\000pkhbt\000pkhtb\000pldw\t[\000pldw\t\000"
+ "pld\t[\000pld\t\000pli\t[\000pli\t\000qadd\000qadd16\000qadd8\000qasx\000"
+ "qdadd\000qdsub\000qsax\000qsub\000qsub16\000qsub8\000rbit\000rev\000rev"
+ "16\000revsh\000rfe\000rsbs\000rsb\000rscs\t\000rsc\000sadd16\000sadd8\000"
+ "sasx\000sbcs\t\000sbc\000sbfx\000sel\000setend\tbe\000setend\tle\000sev"
+ "\000shadd16\000shadd8\000shasx\000shsax\000shsub16\000shsub8\000smc\000"
+ "smlabb\000smlabt\000smlad\000smladx\000smlal\000smlalbb\000smlalbt\000s"
+ "mlald\000smlaldx\000smlaltb\000smlaltt\000smlatb\000smlatt\000smlawb\000"
+ "smlawt\000smlsd\000smlsdx\000smlsld\000smlsldx\000smmla\000smmlar\000sm"
+ "mls\000smmlsr\000smmul\000smmulr\000smuad\000smuadx\000smulbb\000smulbt"
+ "\000smull\000smultb\000smultt\000smulwb\000smulwt\000smusd\000smusdx\000"
+ "srs\000ssat16\000ssat\000ssax\000ssub16\000ssub8\000stc2\000stc\000stm\000"
+ "str\000strb\000strbt\000strd\000strex\000strexb\000strexd\000strexh\000"
+ "strh\000strht\000strt\000subs\000sub\000svc\000swp\000swpb\000sxtab16\000"
+ "sxtab\000sxtah\000sxtb16\000sxtb\000sxth\000teq\000bl\t__aeabi_read_tp\000"
+ "trap\000tst\000uadd16\000uadd8\000uasx\000ubfx\000uhadd16\000uhadd8\000"
+ "uhasx\000uhsax\000uhsub16\000uhsub8\000umaal\000umlal\000umull\000uqadd"
+ "16\000uqadd8\000uqasx\000uqsax\000uqsub16\000uqsub8\000usad8\000usada8\000"
+ "usat16\000usat\000usax\000usub16\000usub8\000uxtab16\000uxtab\000uxtah\000"
+ "uxtb16\000uxtb\000uxth\000vabal\000vaba\000vabdl\000vabd\000vabs\000vac"
+ "ge\000vacgt\000vadd\000vaddhn\000vaddl\000vaddw\000vand\000vbic\000vbif"
+ "\000vbit\000vbsl\000vceq\000vcge\000vcgt\000vcle\000vcls\000vclt\000vcl"
+ "z\000vcmp\000vcmpe\000vcnt\000vcvtb\000vcvt\000vcvtt\000vdiv\000vdup\000"
+ "veor\000vext\000vhadd\000vhsub\000vld1\000vld2\000vld3\000vld4\000vldm\000"
+ "vldr\000vldmia\000vmax\000vmin\000vmla\000vmlal\000vmls\000vmlsl\000vmo"
+ "vl\000vmovn\000vmsr\000vmul\000vmull\000vmvn\000vneg\000vnmla\000vnmls\000"
+ "vnmul\000vorn\000vorr\000vpadal\000vpaddl\000vpadd\000vpmax\000vpmin\000"
+ "vqabs\000vqadd\000vqdmlal\000vqdmlsl\000vqdmulh\000vqdmull\000vqmovun\000"
+ "vqmovn\000vqneg\000vqrdmulh\000vqrshl\000vqrshrn\000vqrshrun\000vqshl\000"
+ "vqshlu\000vqshrn\000vqshrun\000vqsub\000vraddhn\000vrecpe\000vrecps\000"
+ "vrev16\000vrev32\000vrev64\000vrhadd\000vrshl\000vrshrn\000vrshr\000vrs"
+ "qrte\000vrsqrts\000vrsra\000vrsubhn\000vshll\000vshl\000vshrn\000vshr\000"
+ "vsli\000vsqrt\000vsra\000vsri\000vst1\000vst2\000vst3\000vst4\000vstm\000"
+ "vstr\000vstmia\000vsub\000vsubhn\000vsubl\000vsubw\000vswp\000vtbl\000v"
+ "tbx\000vcvtr\000vtrn\000vtst\000vuzp\000vzip\000wfe\000wfi\000yield\000"
+ "addw\000asr\000b.w\t\000it\000str\t\000@ ldr.w\t\000adr\000lsl\000lsr\000"
+ "ror\000rrx\000asrs.w\t\000lsrs.w\t\000orn\000pldw\000pld\000pli\000rfea"
+ "b\000rfedb\000rfeia\000sdiv\000srsdb\000srsia\000subw\000@ subw\t\000@ "
+ "sub.w\t\000@ sub\t\000tbb\t\000tbb\000tbh\t\000tbh\000udiv\000add\t\000"
+ "@ add\t\000@ tADJCALLSTACKDOWN \000@ tADJCALLSTACKUP \000@ and\t\000bkp"
+ "t\t\000bx\tlr\000cbnz\t\000cbz\t\000@ ldr.n\t\000@ tMOVCCr \000movs\t\000"
+ "mov\t\000pop\000push\000sub\t\000";
O << "\t";
// Emit the opcode for the instruction.
unsigned Bits = OpInfo[MI->getOpcode()];
assert(Bits != 0 && "Cannot print this instruction.");
- O << AsmStrs+(Bits & 2047)-1;
+ O << AsmStrs+(Bits & 4095)-1;
// Fragment 0 encoded into 6 bits for 33 unique commands.
switch ((Bits >> 26) & 63) {
default: // unreachable.
case 0:
- // DBG_VALUE, Int_MemBarrierV7, Int_SyncBarrierV7, SETENDBE, SETENDLE, TP...
+ // DBG_VALUE, CLREX, DMBish, DMBishst, DMBnsh, DMBnshst, DMBosh, DMBoshst...
return;
break;
case 1:
@@ -1687,11 +2034,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 0);
break;
case 2:
- // ADCri, ADCrr, ADDSri, ADDSrr, ADDri, ADDrr, ANDri, ANDrr, BFC, BICri, ...
+ // ADCri, ADCrr, ADDSri, ADDSrr, ADDri, ADDrr, ANDri, ANDrr, BFC, BFI, BI...
printPredicateOperand(MI, 3);
break;
case 3:
- // ADCrs, ADDSrs, ADDrs, ANDrs, BICrs, EORrs, LDRBT, LDRB_POST, LDRB_PRE,...
+ // ADCrs, ADDSrs, ADDrs, ANDrs, BICrs, EORrs, LDC2L_OFFSET, LDC2L_POST, L...
printPredicateOperand(MI, 5);
break;
case 4:
@@ -1699,7 +2046,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
PrintSpecial(MI, "comment");
break;
case 5:
- // BKPT, BL_pred, BLr9_pred, BXJ, Bcc, DBG, MRS, MRSsys, MSR, MSRsys, SVC...
+ // BKPT, BL_pred, BLr9_pred, BXJ, Bcc, DBG, MRS, MRSsys, MSR, MSRi, MSRsy...
printPredicateOperand(MI, 1);
break;
case 6:
@@ -1708,18 +2055,15 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 7:
- // BR_JTm
+ // BR_JTm, PLDWr, PLDr, PLIr
printAddrMode2Operand(MI, 0);
- O << " \n";
- printJTBlockOperand(MI, 3);
- return;
break;
case 8:
- // BX_RET, FMSTAT, NOP, SEV, TRAP, WFE, WFI, YIELD, tPOP, tPOP_RET, tPUSH
+ // BX_RET, FMSTAT, NOP, SEV, TRAP, WFE, WFI, YIELD, t2CLREX, t2DMBish, t2...
printPredicateOperand(MI, 0);
break;
case 9:
- // CDP, MCR, MRC, VLD2d16, VLD2d32, VLD2d64, VLD2d8, VST2d16, VST2d32, VS...
+ // CDP, LDRD_POST, LDRD_PRE, MCR, MRC, STRD_POST, STRD_PRE, VLD2d16, VLD2...
printPredicateOperand(MI, 6);
break;
case 10:
@@ -1733,7 +2077,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printPredicateOperand(MI, 2);
break;
case 12:
- // CMNzrs, CMPrs, CMPzrs, LDR, LDRB, LDRH, LDRSB, LDRSH, LDRcp, MLA, MLS,...
+ // CMNzrs, CMPrs, CMPzrs, LDC2L_OPTION, LDC2_OPTION, LDCL_OPTION, LDC_OPT...
printPredicateOperand(MI, 4);
break;
case 13:
@@ -1744,14 +2088,13 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 14:
- // CPS
+ // CPS, t2CPS, tCPS
printOperand(MI, 0, "cps");
return;
break;
case 15:
- // LDM, LDM_RET, STM, t2LDM, t2LDM_RET, t2STM, tLDM, tSTM
+ // LDM, LDM_RET, RFE, RFEW, SRS, SRSW, STM, t2LDM, t2LDM_RET, t2STM, tLDM...
printAddrMode4Operand(MI, 0, "submode");
- printPredicateOperand(MI, 2);
break;
case 16:
// LEApcrel, LEApcrelJT
@@ -1770,20 +2113,20 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1, "label");
break;
case 19:
- // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16a, VLD2LNq16b, VLD2LNq32a, VL...
- printPredicateOperand(MI, 9);
+ // VLD1d16Q, VLD1d32Q, VLD1d8Q, VLD2q16, VLD2q32, VLD2q8, VLD3q16a, VLD3q...
+ printPredicateOperand(MI, 8);
break;
case 20:
- // VLD2q16, VLD2q32, VLD2q8, VLD3q16a, VLD3q16b, VLD3q32a, VLD3q32b, VLD3...
- printPredicateOperand(MI, 8);
+ // VLD1d16T, VLD1d32T, VLD1d8T, VLD3d16, VLD3d32, VLD3d64, VLD3d8, VST1d1...
+ printPredicateOperand(MI, 7);
break;
case 21:
- // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16a, VLD3LNq16b, VLD3LNq32a, VL...
- printPredicateOperand(MI, 11);
+ // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16a, VLD2LNq16b, VLD2LNq32a, VL...
+ printPredicateOperand(MI, 9);
break;
case 22:
- // VLD3d16, VLD3d32, VLD3d64, VLD3d8, VST2LNd16, VST2LNd32, VST2LNd8, VST...
- printPredicateOperand(MI, 7);
+ // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16a, VLD3LNq16b, VLD3LNq32a, VL...
+ printPredicateOperand(MI, 11);
break;
case 23:
// VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16a, VLD4LNq16b, VLD4LNq32a, VL...
@@ -1800,12 +2143,12 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 25:
- // t2ADCri, t2ADCrr, t2ADDrSPi, t2ADDri, t2ADDri12, t2ADDrr, t2ANDri, t2A...
+ // t2ADCSri, t2ADCSrr, t2ADCri, t2ADCrr, t2ADDrSPi, t2ADDri, t2ADDri12, t...
printSBitModifierOperand(MI, 5);
printPredicateOperand(MI, 3);
break;
case 26:
- // t2ADCrs, t2ADDrSPs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORR...
+ // t2ADCSrs, t2ADCrs, t2ADDrSPs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2OR...
printSBitModifierOperand(MI, 6);
printPredicateOperand(MI, 4);
break;
@@ -1813,7 +2156,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
// t2IT
printThumbITMask(MI, 1);
O << "\t";
- printPredicateOperand(MI, 0);
+ printMandatoryPredicateOperand(MI, 0);
return;
break;
case 28:
@@ -1861,11 +2204,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
}
- // Fragment 1 encoded into 7 bits for 107 unique commands.
+ // Fragment 1 encoded into 7 bits for 119 unique commands.
switch ((Bits >> 19) & 127) {
default: // unreachable.
case 0:
- // ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MCR2, MCRR2, MRC2, MRRC2, RSCSri,...
+ // ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MCR2, MCRR2, MRC2, MRRC2, PLDWi, ...
O << ", ";
break;
case 1:
@@ -1889,7 +2232,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 3:
- // ADDSri, ADDSrr, ADDSrs, BFC, BKPT, BL_pred, BLr9_pred, BXJ, Bcc, CLZ, ...
+ // ADDSri, ADDSrr, ADDSrs, BFC, BFI, BKPT, BL_pred, BLr9_pred, BXJ, Bcc, ...
O << "\t";
break;
case 4:
@@ -2017,10 +2360,8 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 29:
- // BR_JTr
+ // BR_JTm, BR_JTr
O << " \n";
- printJTBlockOperand(MI, 1);
- return;
break;
case 30:
// BX_RET
@@ -2028,11 +2369,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 31:
- // CDP, MCR, MCRR, MRC, MRRC
+ // CDP, LDC2_OFFSET, LDC2_OPTION, LDC2_POST, LDC2_PRE, LDC_OFFSET, LDC_OP...
O << "\tp";
printNoHashImmediate(MI, 0);
- O << ", ";
- printOperand(MI, 1);
break;
case 32:
// CDP2
@@ -2083,6 +2422,17 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 39:
+ // LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDCL_OFFSET, LDCL_O...
+ O << "l\tp";
+ printNoHashImmediate(MI, 0);
+ O << ", cr";
+ printNoHashImmediate(MI, 1);
+ break;
+ case 40:
+ // LDM, LDM_RET, STM, t2LDM, t2LDM_RET, t2MOVi, t2MOVr, t2MOVrx, t2MVNi, ...
+ printPredicateOperand(MI, 2);
+ break;
+ case 41:
// LEApcrel
O << "-(";
PrintSpecial(MI, "private");
@@ -2102,7 +2452,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
PrintSpecial(MI, "uid");
return;
break;
- case 40:
+ case 42:
// LEApcrelJT
O << '_';
printNoHashImmediate(MI, 2);
@@ -2124,33 +2474,29 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
PrintSpecial(MI, "uid");
return;
break;
- case 41:
+ case 43:
// MLA, MOVs, MVNs, SMLAL, SMULL, UMLAL, UMULL
printSBitModifierOperand(MI, 6);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
- case 42:
+ case 44:
// MOVi, MOVr, MOVrx, MVNi, MVNr
printSBitModifierOperand(MI, 4);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
- case 43:
- // MSR
+ case 45:
+ // MSR, MSRi, t2MSR
O << "\tcpsr, ";
- printOperand(MI, 0);
- return;
break;
- case 44:
- // MSRsys
+ case 46:
+ // MSRsys, MSRsysi, t2MSRsys
O << "\tspsr, ";
- printOperand(MI, 0);
- return;
break;
- case 45:
+ case 47:
// PICADD
O << ":\n\tadd";
printPredicateOperand(MI, 3);
@@ -2160,7 +2506,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 46:
+ case 48:
// PICLDR
O << ":\n\tldr";
printPredicateOperand(MI, 3);
@@ -2170,7 +2516,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 47:
+ case 49:
// PICLDRB
O << ":\n\tldrb";
printPredicateOperand(MI, 3);
@@ -2180,7 +2526,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 48:
+ case 50:
// PICLDRH
O << ":\n\tldrh";
printPredicateOperand(MI, 3);
@@ -2190,7 +2536,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 49:
+ case 51:
// PICLDRSB
O << ":\n\tldrsb";
printPredicateOperand(MI, 3);
@@ -2200,7 +2546,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 50:
+ case 52:
// PICLDRSH
O << ":\n\tldrsh";
printPredicateOperand(MI, 3);
@@ -2210,7 +2556,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 51:
+ case 53:
// PICSTR
O << ":\n\tstr";
printPredicateOperand(MI, 3);
@@ -2220,7 +2566,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 52:
+ case 54:
// PICSTRB
O << ":\n\tstrb";
printPredicateOperand(MI, 3);
@@ -2230,7 +2576,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 53:
+ case 55:
// PICSTRH
O << ":\n\tstrh";
printPredicateOperand(MI, 3);
@@ -2240,71 +2586,79 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 54:
+ case 56:
+ // SRS, t2SRSDB, t2SRSIA
+ O << "\tsp, ";
+ break;
+ case 57:
+ // SRSW, t2SRSDBW, t2SRSIAW
+ O << "\tsp!, ";
+ break;
+ case 58:
// VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i...
O << ".s32\t";
printOperand(MI, 0);
O << ", ";
break;
- case 55:
+ case 59:
// VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i...
O << ".s16\t";
printOperand(MI, 0);
O << ", ";
break;
- case 56:
+ case 60:
// VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8...
O << ".s8\t";
printOperand(MI, 0);
O << ", ";
break;
- case 57:
+ case 61:
// VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i...
O << ".u32\t";
printOperand(MI, 0);
O << ", ";
break;
- case 58:
+ case 62:
// VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i...
O << ".u16\t";
printOperand(MI, 0);
O << ", ";
break;
- case 59:
+ case 63:
// VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8...
O << ".u8\t";
printOperand(MI, 0);
O << ", ";
break;
- case 60:
+ case 64:
// VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V...
O << ".i64\t";
printOperand(MI, 0);
O << ", ";
break;
- case 61:
- // VADDHNv4i16, VADDv2i32, VADDv4i32, VCEQv2i32, VCEQv4i32, VCLZv2i32, VC...
+ case 65:
+ // VADDHNv4i16, VADDv2i32, VADDv4i32, VCEQv2i32, VCEQv4i32, VCEQzv2i32, V...
O << ".i32\t";
printOperand(MI, 0);
O << ", ";
break;
- case 62:
- // VADDHNv8i8, VADDv4i16, VADDv8i16, VCEQv4i16, VCEQv8i16, VCLZv4i16, VCL...
+ case 66:
+ // VADDHNv8i8, VADDv4i16, VADDv8i16, VCEQv4i16, VCEQv8i16, VCEQzv4i16, VC...
O << ".i16\t";
printOperand(MI, 0);
O << ", ";
break;
- case 63:
- // VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCLZv16i8, VCLZv8i8, VMLAv16...
+ case 67:
+ // VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCEQzv16i8, VCEQzv8i8, VCLZv...
O << ".i8\t";
printOperand(MI, 0);
O << ", ";
break;
- case 64:
+ case 68:
// VCNTd, VCNTq, VDUP8d, VDUP8q, VDUPLN8d, VDUPLN8q, VEXTd8, VEXTq8, VLD1...
O << ".8\t";
break;
- case 65:
+ case 69:
// VCVTBHS, VCVTTHS
O << ".f16.f32\t";
printOperand(MI, 0);
@@ -2312,7 +2666,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 66:
+ case 70:
// VCVTBSH, VCVTTSH
O << ".f32.f16\t";
printOperand(MI, 0);
@@ -2320,7 +2674,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 67:
+ case 71:
// VCVTDS
O << ".f64.f32\t";
printOperand(MI, 0);
@@ -2328,7 +2682,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 68:
+ case 72:
// VCVTSD
O << ".f32.f64\t";
printOperand(MI, 0);
@@ -2336,69 +2690,69 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 69:
+ case 73:
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSI...
O << ".s32.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 70:
+ case 74:
// VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUI...
O << ".u32.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 71:
+ case 75:
// VCVTs2fd, VCVTs2fd_sfp, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS
O << ".f32.s32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 72:
+ case 76:
// VCVTu2fd, VCVTu2fd_sfp, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS
O << ".f32.u32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 73:
+ case 77:
// VDUP16d, VDUP16q, VDUPLN16d, VDUPLN16q, VEXTd16, VEXTq16, VLD1q16, VRE...
O << ".16\t";
break;
- case 74:
+ case 78:
// VDUP32d, VDUP32q, VDUPLN32d, VDUPLN32q, VDUPLNfd, VDUPLNfq, VDUPfd, VD...
O << ".32\t";
break;
- case 75:
- // VLD1d16, VLD2LNd16, VLD2LNq16a, VLD2LNq16b, VLD2d16, VLD2q16, VLD3LNd1...
+ case 79:
+ // VLD1d16, VLD1d16Q, VLD1d16T, VLD2LNd16, VLD2LNq16a, VLD2LNq16b, VLD2d1...
O << ".16\t{";
break;
- case 76:
- // VLD1d32, VLD1df, VLD2LNd32, VLD2LNq32a, VLD2LNq32b, VLD2d32, VLD2q32, ...
+ case 80:
+ // VLD1d32, VLD1d32Q, VLD1d32T, VLD1df, VLD2LNd32, VLD2LNq32a, VLD2LNq32b...
O << ".32\t{";
break;
- case 77:
+ case 81:
// VLD1d64, VLD2d64, VLD3d64, VLD4d64, VST1d64, VST2d64, VST3d64, VST4d64
O << ".64\t{";
break;
- case 78:
- // VLD1d8, VLD2LNd8, VLD2d8, VLD2q8, VLD3LNd8, VLD3d8, VLD3q8a, VLD3q8b, ...
+ case 82:
+ // VLD1d8, VLD1d8Q, VLD1d8T, VLD2LNd8, VLD2d8, VLD2d8D, VLD2q8, VLD3LNd8,...
O << ".8\t{";
break;
- case 79:
+ case 83:
// VLD1q64, VLDRD, VSLIv1i64, VSLIv2i64, VSRIv1i64, VSRIv2i64, VST1q64, V...
O << ".64\t";
break;
- case 80:
+ case 84:
// VMSR
O << "\tfpscr, ";
printOperand(MI, 0);
return;
break;
- case 81:
+ case 85:
// VMULLp, VMULpd, VMULpq
O << ".p8\t";
printOperand(MI, 0);
@@ -2408,19 +2762,19 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 82:
+ case 86:
// VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
O << ".s64\t";
printOperand(MI, 0);
O << ", ";
break;
- case 83:
+ case 87:
// VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ...
O << ".u64\t";
printOperand(MI, 0);
O << ", ";
break;
- case 84:
+ case 88:
// VSHTOD
O << ".f64.s16\t";
printOperand(MI, 0);
@@ -2430,7 +2784,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 85:
+ case 89:
// VSHTOS
O << ".f32.s16\t";
printOperand(MI, 0);
@@ -2440,14 +2794,14 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 86:
+ case 90:
// VSITOD, VSLTOD
O << ".f64.s32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 87:
+ case 91:
// VTOSHD
O << ".s16.f64\t";
printOperand(MI, 0);
@@ -2457,7 +2811,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 88:
+ case 92:
// VTOSHS
O << ".s16.f32\t";
printOperand(MI, 0);
@@ -2467,14 +2821,14 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 89:
+ case 93:
// VTOSIRD, VTOSIZD, VTOSLD
O << ".s32.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 90:
+ case 94:
// VTOUHD
O << ".u16.f64\t";
printOperand(MI, 0);
@@ -2484,7 +2838,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 91:
+ case 95:
// VTOUHS
O << ".u16.f32\t";
printOperand(MI, 0);
@@ -2494,14 +2848,14 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 92:
+ case 96:
// VTOUIRD, VTOUIZD, VTOULD
O << ".u32.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 93:
+ case 97:
// VUHTOD
O << ".f64.u16\t";
printOperand(MI, 0);
@@ -2511,7 +2865,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 94:
+ case 98:
// VUHTOS
O << ".f32.u16\t";
printOperand(MI, 0);
@@ -2521,62 +2875,103 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 95:
+ case 99:
// VUITOD, VULTOD
O << ".f64.u32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 96:
- // t2ADCrr, t2ADCrs, t2ADDSri, t2ADDSrr, t2ADDSrs, t2ADDrSPi, t2ADDrSPs, ...
+ case 100:
+ // t2ADCSrr, t2ADCSrs, t2ADCrr, t2ADCrs, t2ADDSri, t2ADDSrr, t2ADDSrs, t2...
O << ".w\t";
printOperand(MI, 0);
break;
- case 97:
+ case 101:
// t2BR_JT
O << "\n";
printJT2BlockOperand(MI, 2);
return;
break;
- case 98:
- // t2LDM, t2LDM_RET, t2STM
- printAddrMode4Operand(MI, 0, "wide");
- O << "\t";
- printAddrMode4Operand(MI, 0);
- O << ", ";
- printRegisterList(MI, 4);
+ case 102:
+ // t2DMBish, t2DSBish
+ O << "\tish";
return;
break;
- case 99:
- // t2MOVi, t2MOVr, t2MOVrx, t2MVNi
- printPredicateOperand(MI, 2);
+ case 103:
+ // t2DMBishst, t2DSBishst
+ O << "\tishst";
+ return;
break;
- case 100:
+ case 104:
+ // t2DMBnsh, t2DSBnsh
+ O << "\tnsh";
+ return;
+ break;
+ case 105:
+ // t2DMBnshst, t2DSBnshst
+ O << "\tnshst";
+ return;
+ break;
+ case 106:
+ // t2DMBosh, t2DSBosh
+ O << "\tosh";
+ return;
+ break;
+ case 107:
+ // t2DMBoshst, t2DSBoshst
+ O << "\toshst";
+ return;
+ break;
+ case 108:
+ // t2DMBst, t2DSBst
+ O << "\tst";
+ return;
+ break;
+ case 109:
+ // t2NOP, t2SEV, t2WFE, t2WFI, t2YIELD
+ O << ".w";
+ return;
+ break;
+ case 110:
+ // t2PLDWpci, t2PLDpci, t2PLIpci
+ O << "\t[pc, ";
+ printOperand(MI, 1, "negzero");
+ O << ']';
+ return;
+ break;
+ case 111:
+ // t2PLDWr, t2PLDWs, t2PLDr, t2PLDs, t2PLIr, t2PLIs, t2TBBgen, t2TBHgen
+ O << "\t[";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ break;
+ case 112:
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
printPredicateOperand(MI, 4);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
- case 101:
+ case 113:
// tADDrPCi
O << ", pc, ";
printThumbS4ImmOperand(MI, 1);
return;
break;
- case 102:
+ case 114:
// tBR_JTr
O << "\n\t.align\t2\n";
printJTBlockOperand(MI, 1);
return;
break;
- case 103:
+ case 115:
// tBfar
O << "\t@ far jump";
return;
break;
- case 104:
+ case 116:
// tLDRpci
O << ".n\t";
printOperand(MI, 0);
@@ -2584,7 +2979,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 105:
+ case 117:
// tMOVi8, tMVN, tRSB
printPredicateOperand(MI, 3);
O << "\t";
@@ -2592,7 +2987,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << ", ";
printOperand(MI, 2);
break;
- case 106:
+ case 118:
// tPICADD
O << ":\n\tadd\t";
printOperand(MI, 0);
@@ -2602,11 +2997,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
}
- // Fragment 2 encoded into 5 bits for 27 unique commands.
- switch ((Bits >> 14) & 31) {
+ // Fragment 2 encoded into 6 bits for 36 unique commands.
+ switch ((Bits >> 13) & 63) {
default: // unreachable.
case 0:
- // ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MLA, MOVr, MOVrx, MVNr, RSCSri, R...
+ // ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MLA, MOVr, MOVrx, MVNr, PLDWi, PL...
printOperand(MI, 1);
break;
case 1:
@@ -2619,7 +3014,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
break;
case 3:
- // ADDSri, ADDSrr, ADDSrs, BFC, BKPT, BXJ, Bcc, CLZ, CMNzri, CMNzrr, CMNz...
+ // ADDSri, ADDSrr, ADDSrs, BFC, BFI, BKPT, BXJ, Bcc, CLZ, CMNzri, CMNzrr,...
printOperand(MI, 0);
break;
case 4:
@@ -2628,93 +3023,104 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 5:
- // CDP
- O << ", cr";
- printNoHashImmediate(MI, 2);
- O << ", cr";
- printNoHashImmediate(MI, 3);
- O << ", cr";
- printNoHashImmediate(MI, 4);
- O << ", ";
- printOperand(MI, 5);
+ // BR_JTm
+ printJTBlockOperand(MI, 3);
return;
break;
case 6:
- // FCONSTD, FCONSTS, MCR, MCRR, MRC, MRRC, VABDfd, VABDfq, VABSD, VABSS, ...
- O << ", ";
+ // BR_JTr
+ printJTBlockOperand(MI, 1);
+ return;
break;
case 7:
- // LDM, LDM_RET, STM, tLDM, tSTM
- printAddrMode4Operand(MI, 0);
+ // CDP, FCONSTD, FCONSTS, LDC2L_OFFSET, LDC2L_PRE, LDCL_OFFSET, LDCL_PRE,...
O << ", ";
- printRegisterList(MI, 4);
- return;
break;
case 8:
+ // LDC2L_OPTION, LDC2L_POST, LDCL_OPTION, LDCL_POST, STC2L_OPTION, STC2L_...
+ O << ", [";
+ printOperand(MI, 2);
+ O << "], ";
+ break;
+ case 9:
+ // LDC2_OFFSET, LDC2_OPTION, LDC2_POST, LDC2_PRE, LDC_OFFSET, LDC_OPTION,...
+ O << ", cr";
+ printNoHashImmediate(MI, 1);
+ break;
+ case 10:
+ // LDM, LDM_RET, STM, t2MOVrx, t2MVNi, tLDM, tSTM
+ O << "\t";
+ break;
+ case 11:
// MOVi, MVNi
printSOImmOperand(MI, 1);
return;
break;
- case 9:
+ case 12:
// MOVs, MVNs
printSORegOperand(MI, 1);
return;
break;
- case 10:
+ case 13:
+ // MSRi, MSRsysi
+ printSOImmOperand(MI, 0);
+ return;
+ break;
+ case 14:
// VCMPEZD, VCMPEZS, VCMPZD, VCMPZS, tRSB
O << ", #0";
return;
break;
- case 11:
+ case 15:
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VC...
return;
break;
- case 12:
+ case 16:
// VLD1q16, VLD1q32, VLD1q64, VLD1q8, VLD1qf
printOperand(MI, 0, "dregpair");
O << ", ";
printAddrMode6Operand(MI, 1);
return;
break;
- case 13:
+ case 17:
// VLDRQ, VSTRQ
printAddrMode4Operand(MI, 1);
O << ", ";
printOperand(MI, 0, "dregpair");
return;
break;
- case 14:
+ case 18:
// VMOVv16i8, VMOVv8i8
printHex8ImmOperand(MI, 1);
return;
break;
- case 15:
+ case 19:
// VMOVv1i64, VMOVv2i64
printHex64ImmOperand(MI, 1);
return;
break;
- case 16:
+ case 20:
// VMOVv2i32, VMOVv4i32
printHex32ImmOperand(MI, 1);
return;
break;
- case 17:
+ case 21:
// VMOVv4i16, VMOVv8i16
printHex16ImmOperand(MI, 1);
return;
break;
- case 18:
- // VST1d16, VST1d32, VST1d64, VST1d8, VST1df, VST2LNd16, VST2LNd32, VST2L...
+ case 22:
+ // VST1d16, VST1d16Q, VST1d16T, VST1d32, VST1d32Q, VST1d32T, VST1d64, VST...
printOperand(MI, 4);
break;
- case 19:
+ case 23:
// VST1q16, VST1q32, VST1q64, VST1q8, VST1qf
printOperand(MI, 4, "dregpair");
O << ", ";
printAddrMode6Operand(MI, 0);
return;
break;
- case 20:
+ case 24:
// VST3q16a, VST3q16b, VST3q32a, VST3q32b, VST3q8a, VST3q8b, VST4q16a, VS...
printOperand(MI, 5);
O << ", ";
@@ -2722,12 +3128,21 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << ", ";
printOperand(MI, 7);
break;
- case 21:
+ case 25:
+ // t2LDM, t2LDM_RET, t2STM
+ printAddrMode4Operand(MI, 0, "wide");
+ O << "\t";
+ printAddrMode4Operand(MI, 0);
+ O << ", ";
+ printRegisterList(MI, 4);
+ return;
+ break;
+ case 26:
// t2LEApcrel, t2LEApcrelJT
O << ", #";
printOperand(MI, 1);
break;
- case 22:
+ case 27:
// t2MOVi, t2MOVr
O << ".w\t";
printOperand(MI, 0);
@@ -2735,25 +3150,43 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 23:
- // t2MOVrx, t2MVNi
- O << "\t";
- printOperand(MI, 0);
- O << ", ";
- printOperand(MI, 1);
+ case 28:
+ // t2PLDWi12, t2PLDi12, t2PLIi12
+ printT2AddrModeImm12Operand(MI, 0);
return;
break;
- case 24:
+ case 29:
+ // t2PLDWi8, t2PLDi8, t2PLIi8
+ printT2AddrModeImm8Operand(MI, 0);
+ return;
+ break;
+ case 30:
+ // t2PLDWr, t2PLDr, t2PLIr, t2TBBgen
+ O << ']';
+ return;
+ break;
+ case 31:
+ // t2PLDWs, t2PLDs, t2PLIs
+ O << ", lsl ";
+ printOperand(MI, 2);
+ O << ']';
+ return;
+ break;
+ case 32:
+ // t2TBHgen
+ O << ", lsl #1]";
+ return;
+ break;
+ case 33:
// tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tMUL, tORR, tR...
printOperand(MI, 3);
- return;
break;
- case 25:
+ case 34:
// tADDspi, tSUBspi, tSUBspi_
printThumbS4ImmOperand(MI, 2);
return;
break;
- case 26:
+ case 35:
// tPOP, tPOP_RET, tPUSH
printRegisterList(MI, 2);
return;
@@ -2775,6 +3208,8 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::CMPzri:
case ARM::CMPzrr:
case ARM::CMPzrs:
+ case ARM::LDC2_OFFSET:
+ case ARM::LDC_OFFSET:
case ARM::LDR:
case ARM::LDRB:
case ARM::LDRD:
@@ -2797,10 +3232,13 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::SBCSSri:
case ARM::SBCSSrr:
case ARM::SBCSSrs:
+ case ARM::STC2_OFFSET:
+ case ARM::STC_OFFSET:
case ARM::STR:
case ARM::STRB:
case ARM::STRD:
case ARM::STRH:
+ case ARM::SXTB16r:
case ARM::SXTBr:
case ARM::SXTHr:
case ARM::TEQri:
@@ -3316,6 +3754,8 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VSUBv4i32:
case ARM::VSUBv8i16:
case ARM::VSUBv8i8:
+ case ARM::VSWPd:
+ case ARM::VSWPq:
case ARM::VTRNd16:
case ARM::VTRNd32:
case ARM::VTRNd8:
@@ -3334,31 +3774,35 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VZIPq16:
case ARM::VZIPq32:
case ARM::VZIPq8:
- case ARM::t2ADCSri:
- case ARM::t2ADCSrr:
- case ARM::t2ADCSrs:
case ARM::t2BFC:
case ARM::t2CLZ:
+ case ARM::t2LDRBT:
case ARM::t2LDRBi8:
case ARM::t2LDRDi8:
case ARM::t2LDRDpci:
+ case ARM::t2LDRHT:
case ARM::t2LDRHi8:
+ case ARM::t2LDRSBT:
case ARM::t2LDRSBi8:
+ case ARM::t2LDRSHT:
case ARM::t2LDRSHi8:
+ case ARM::t2LDRT:
case ARM::t2LDRi8:
case ARM::t2MOVTi16:
case ARM::t2MOVi16:
case ARM::t2RBIT:
- case ARM::t2SBCSri:
- case ARM::t2SBCSrr:
- case ARM::t2SBCSrs:
+ case ARM::t2STRBT:
case ARM::t2STRBi8:
case ARM::t2STRDi8:
+ case ARM::t2STRHT:
case ARM::t2STRHi8:
+ case ARM::t2STRT:
case ARM::t2STRi8:
case ARM::t2SUBrSPi12_:
case ARM::t2SUBrSPi_:
case ARM::t2SUBrSPs_:
+ case ARM::t2SXTB16r:
+ case ARM::t2UXTB16r:
case ARM::tADDhirr:
case ARM::tADDi3:
case ARM::tADDrSPi:
@@ -3385,6 +3829,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::tLSRri:
case ARM::tMOVCCi:
case ARM::tMOVCCr:
+ case ARM::tMUL:
case ARM::tREV:
case ARM::tREV16:
case ARM::tREVSH:
@@ -3804,12 +4249,8 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VSUBv4i32:
case ARM::VSUBv8i16:
case ARM::VSUBv8i8:
- case ARM::t2ADCSri:
- case ARM::t2ADCSrr:
case ARM::t2LDRDpci:
case ARM::t2MOVTi16:
- case ARM::t2SBCSri:
- case ARM::t2SBCSrr:
case ARM::t2SUBrSPi12_:
case ARM::t2SUBrSPi_:
case ARM::tADDhirr:
@@ -3830,6 +4271,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::REV:
case ARM::REV16:
case ARM::REVSH:
+ case ARM::SXTB16r:
case ARM::SXTBr:
case ARM::SXTHr:
case ARM::TEQrr:
@@ -3867,6 +4309,8 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VREV64q32:
case ARM::VREV64q8:
case ARM::VREV64qf:
+ case ARM::VSWPd:
+ case ARM::VSWPq:
case ARM::VTRNd16:
case ARM::VTRNd32:
case ARM::VTRNd8:
@@ -3888,6 +4332,8 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2CLZ:
case ARM::t2MOVi16:
case ARM::t2RBIT:
+ case ARM::t2SXTB16r:
+ case ARM::t2UXTB16r:
case ARM::tCMNz:
case ARM::tCMPhir:
case ARM::tCMPi8:
@@ -3914,6 +4360,10 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::CMPzrs:
case ARM::TEQrs:
case ARM::TSTrs: printSORegOperand(MI, 1); break;
+ case ARM::LDC2_OFFSET:
+ case ARM::LDC_OFFSET:
+ case ARM::STC2_OFFSET:
+ case ARM::STC_OFFSET: printAddrMode2Operand(MI, 2); break;
case ARM::LDR:
case ARM::LDRB:
case ARM::LDRcp:
@@ -4017,19 +4467,25 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VLDRS:
case ARM::VSTRD:
case ARM::VSTRS: printAddrMode5Operand(MI, 1); break;
- case ARM::t2ADCSrs:
- case ARM::t2SBCSrs:
- case ARM::t2SUBrSPs_: printT2SOOperand(MI, 2); break;
+ case ARM::t2LDRBT:
case ARM::t2LDRBi8:
+ case ARM::t2LDRHT:
case ARM::t2LDRHi8:
+ case ARM::t2LDRSBT:
case ARM::t2LDRSBi8:
+ case ARM::t2LDRSHT:
case ARM::t2LDRSHi8:
+ case ARM::t2LDRT:
case ARM::t2LDRi8:
+ case ARM::t2STRBT:
case ARM::t2STRBi8:
+ case ARM::t2STRHT:
case ARM::t2STRHi8:
+ case ARM::t2STRT:
case ARM::t2STRi8: printT2AddrModeImm8Operand(MI, 1); break;
case ARM::t2LDRDi8:
case ARM::t2STRDi8: printT2AddrModeImm8s4Operand(MI, 2); break;
+ case ARM::t2SUBrSPs_: printT2SOOperand(MI, 2); break;
case ARM::tADDrSPi: printThumbS4ImmOperand(MI, 2); break;
case ARM::tLDR:
case ARM::tLDRi:
@@ -4049,6 +4505,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::tRestore:
case ARM::tSTRspi:
case ARM::tSpill: printThumbAddrModeSPOperand(MI, 1); break;
+ case ARM::tMUL: printOperand(MI, 0); break;
}
return;
break;
@@ -4062,10 +4519,16 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::DBG:
case ARM::EORrr:
case ARM::MOVr:
+ case ARM::MSR:
+ case ARM::MSRsys:
case ARM::MUL:
case ARM::MVNr:
case ARM::ORRrr:
+ case ARM::RFE:
case ARM::SBCrr:
+ case ARM::SMC:
+ case ARM::SRS:
+ case ARM::SRSW:
case ARM::SUBrr:
case ARM::SVC:
case ARM::VABSv16i8:
@@ -4150,24 +4613,49 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VRECPEq:
case ARM::VRSQRTEd:
case ARM::VRSQRTEq:
+ case ARM::t2BXJ:
+ case ARM::t2DBG:
case ARM::t2LEApcrel:
+ case ARM::t2MSR:
+ case ARM::t2MSRsys:
+ case ARM::t2RFEDB:
+ case ARM::t2RFEIA:
+ case ARM::t2SMC:
+ case ARM::t2SRSDB:
+ case ARM::t2SRSDBW:
+ case ARM::t2SRSIA:
+ case ARM::t2SRSIAW:
+ case ARM::tADC:
+ case ARM::tADDi8:
case ARM::tADDrSP:
case ARM::tADDspr:
case ARM::tADDspr_:
+ case ARM::tAND:
case ARM::tANDsp:
+ case ARM::tASRrr:
+ case ARM::tBIC:
case ARM::tBcc:
case ARM::tCBNZ:
case ARM::tCBZ:
+ case ARM::tEOR:
+ case ARM::tLSLrr:
+ case ARM::tLSRrr:
case ARM::tMOVSr:
case ARM::tMOVgpr2gpr:
case ARM::tMOVgpr2tgpr:
case ARM::tMOVr:
case ARM::tMOVtgpr2gpr:
+ case ARM::tORR:
+ case ARM::tROR:
+ case ARM::tSBC:
+ case ARM::tSUBi8:
+ case ARM::tSVC:
return;
break;
case ARM::ADDSri:
case ARM::ADDSrr:
case ARM::ADDSrs:
+ case ARM::BFI:
case ARM::QADD:
case ARM::QADD16:
case ARM::QADD8:
@@ -4180,24 +4668,59 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::QSUB8:
case ARM::RSBSri:
case ARM::RSBSrs:
+ case ARM::SADD16:
+ case ARM::SADD8:
+ case ARM::SASX:
+ case ARM::SEL:
+ case ARM::SHADD16:
+ case ARM::SHADD8:
+ case ARM::SHASX:
+ case ARM::SHSAX:
+ case ARM::SHSUB16:
+ case ARM::SHSUB8:
case ARM::SMMUL:
+ case ARM::SMMULR:
+ case ARM::SMUAD:
+ case ARM::SMUADX:
case ARM::SMULBB:
case ARM::SMULBT:
case ARM::SMULTB:
case ARM::SMULTT:
case ARM::SMULWB:
case ARM::SMULWT:
+ case ARM::SMUSD:
+ case ARM::SMUSDX:
+ case ARM::SSAT16:
+ case ARM::SSAX:
+ case ARM::SSUB16:
+ case ARM::SSUB8:
case ARM::SUBSri:
case ARM::SUBSrr:
case ARM::SUBSrs:
+ case ARM::SXTAB16rr:
case ARM::SXTABrr:
case ARM::SXTAHrr:
+ case ARM::UADD16:
+ case ARM::UADD8:
+ case ARM::UASX:
+ case ARM::UHADD16:
+ case ARM::UHADD8:
+ case ARM::UHASX:
+ case ARM::UHSAX:
+ case ARM::UHSUB16:
+ case ARM::UHSUB8:
case ARM::UQADD16:
case ARM::UQADD8:
case ARM::UQASX:
case ARM::UQSAX:
case ARM::UQSUB16:
case ARM::UQSUB8:
+ case ARM::USAD8:
+ case ARM::USAT16:
+ case ARM::USAX:
+ case ARM::USUB16:
+ case ARM::USUB8:
+ case ARM::UXTAB16rr:
case ARM::UXTABrr:
case ARM::UXTAHrr:
case ARM::VANDd:
@@ -4218,6 +4741,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VTSTv4i32:
case ARM::VTSTv8i16:
case ARM::VTSTv8i8:
+ case ARM::t2ADCSri:
case ARM::t2ADCri:
case ARM::t2ADDrSPi12:
case ARM::t2ADDri12:
@@ -4229,21 +4753,75 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2ORNrr:
case ARM::t2ORNrs:
case ARM::t2ORRri:
+ case ARM::t2QADD:
+ case ARM::t2QADD16:
+ case ARM::t2QADD8:
+ case ARM::t2QASX:
+ case ARM::t2QDADD:
+ case ARM::t2QDSUB:
+ case ARM::t2QSAX:
+ case ARM::t2QSUB:
+ case ARM::t2QSUB16:
+ case ARM::t2QSUB8:
case ARM::t2RSBSrs:
case ARM::t2RSBrs:
+ case ARM::t2SADD16:
+ case ARM::t2SADD8:
+ case ARM::t2SASX:
+ case ARM::t2SBCSri:
case ARM::t2SBCri:
+ case ARM::t2SDIV:
+ case ARM::t2SEL:
+ case ARM::t2SHADD16:
+ case ARM::t2SHADD8:
+ case ARM::t2SHASX:
+ case ARM::t2SHSAX:
+ case ARM::t2SHSUB16:
+ case ARM::t2SHSUB8:
case ARM::t2SMMUL:
+ case ARM::t2SMMULR:
+ case ARM::t2SMUAD:
+ case ARM::t2SMUADX:
case ARM::t2SMULBB:
case ARM::t2SMULBT:
case ARM::t2SMULTB:
case ARM::t2SMULTT:
case ARM::t2SMULWB:
case ARM::t2SMULWT:
+ case ARM::t2SMUSD:
+ case ARM::t2SMUSDX:
+ case ARM::t2SSAT16:
+ case ARM::t2SSAX:
+ case ARM::t2SSUB16:
+ case ARM::t2SSUB8:
case ARM::t2SUBrSPi12:
case ARM::t2SUBrSPs:
case ARM::t2SUBri12:
+ case ARM::t2SXTAB16rr:
case ARM::t2SXTABrr:
case ARM::t2SXTAHrr:
+ case ARM::t2UADD16:
+ case ARM::t2UADD8:
+ case ARM::t2UASX:
+ case ARM::t2UDIV:
+ case ARM::t2UHADD16:
+ case ARM::t2UHADD8:
+ case ARM::t2UHASX:
+ case ARM::t2UHSAX:
+ case ARM::t2UHSUB16:
+ case ARM::t2UHSUB8:
+ case ARM::t2UQADD16:
+ case ARM::t2UQADD8:
+ case ARM::t2UQASX:
+ case ARM::t2UQSAX:
+ case ARM::t2UQSUB16:
+ case ARM::t2UQSUB8:
+ case ARM::t2USAD8:
+ case ARM::t2USAT16:
+ case ARM::t2USAX:
+ case ARM::t2USUB16:
+ case ARM::t2USUB8:
+ case ARM::t2UXTAB16rr:
case ARM::t2UXTABrr:
case ARM::t2UXTAHrr:
O << ", ";
@@ -4264,22 +4842,57 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::QSUB:
case ARM::QSUB16:
case ARM::QSUB8:
+ case ARM::SADD16:
+ case ARM::SADD8:
+ case ARM::SASX:
+ case ARM::SEL:
+ case ARM::SHADD16:
+ case ARM::SHADD8:
+ case ARM::SHASX:
+ case ARM::SHSAX:
+ case ARM::SHSUB16:
+ case ARM::SHSUB8:
case ARM::SMMUL:
+ case ARM::SMMULR:
+ case ARM::SMUAD:
+ case ARM::SMUADX:
case ARM::SMULBB:
case ARM::SMULBT:
case ARM::SMULTB:
case ARM::SMULTT:
case ARM::SMULWB:
case ARM::SMULWT:
+ case ARM::SMUSD:
+ case ARM::SMUSDX:
+ case ARM::SSAT16:
+ case ARM::SSAX:
+ case ARM::SSUB16:
+ case ARM::SSUB8:
case ARM::SUBSrr:
+ case ARM::SXTAB16rr:
case ARM::SXTABrr:
case ARM::SXTAHrr:
+ case ARM::UADD16:
+ case ARM::UADD8:
+ case ARM::UASX:
+ case ARM::UHADD16:
+ case ARM::UHADD8:
+ case ARM::UHASX:
+ case ARM::UHSAX:
+ case ARM::UHSUB16:
+ case ARM::UHSUB8:
case ARM::UQADD16:
case ARM::UQADD8:
case ARM::UQASX:
case ARM::UQSAX:
case ARM::UQSUB16:
case ARM::UQSUB8:
+ case ARM::USAD8:
+ case ARM::USAT16:
+ case ARM::USAX:
+ case ARM::USUB16:
+ case ARM::USUB8:
+ case ARM::UXTAB16rr:
case ARM::UXTABrr:
case ARM::UXTAHrr:
case ARM::VANDd:
@@ -4300,6 +4913,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VTSTv4i32:
case ARM::VTSTv8i16:
case ARM::VTSTv8i8:
+ case ARM::t2ADCSri:
case ARM::t2ADCri:
case ARM::t2ADDrSPi12:
case ARM::t2ADDri12:
@@ -4310,23 +4924,78 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2ORNri:
case ARM::t2ORNrr:
case ARM::t2ORRri:
+ case ARM::t2QADD:
+ case ARM::t2QADD16:
+ case ARM::t2QADD8:
+ case ARM::t2QASX:
+ case ARM::t2QDADD:
+ case ARM::t2QDSUB:
+ case ARM::t2QSAX:
+ case ARM::t2QSUB:
+ case ARM::t2QSUB16:
+ case ARM::t2QSUB8:
+ case ARM::t2SADD16:
+ case ARM::t2SADD8:
+ case ARM::t2SASX:
+ case ARM::t2SBCSri:
case ARM::t2SBCri:
+ case ARM::t2SDIV:
+ case ARM::t2SEL:
+ case ARM::t2SHADD16:
+ case ARM::t2SHADD8:
+ case ARM::t2SHASX:
+ case ARM::t2SHSAX:
+ case ARM::t2SHSUB16:
+ case ARM::t2SHSUB8:
case ARM::t2SMMUL:
+ case ARM::t2SMMULR:
+ case ARM::t2SMUAD:
+ case ARM::t2SMUADX:
case ARM::t2SMULBB:
case ARM::t2SMULBT:
case ARM::t2SMULTB:
case ARM::t2SMULTT:
case ARM::t2SMULWB:
case ARM::t2SMULWT:
+ case ARM::t2SMUSD:
+ case ARM::t2SMUSDX:
+ case ARM::t2SSAT16:
+ case ARM::t2SSAX:
+ case ARM::t2SSUB16:
+ case ARM::t2SSUB8:
case ARM::t2SUBrSPi12:
case ARM::t2SUBri12:
+ case ARM::t2SXTAB16rr:
case ARM::t2SXTABrr:
case ARM::t2SXTAHrr:
+ case ARM::t2UADD16:
+ case ARM::t2UADD8:
+ case ARM::t2UASX:
+ case ARM::t2UDIV:
+ case ARM::t2UHADD16:
+ case ARM::t2UHADD8:
+ case ARM::t2UHASX:
+ case ARM::t2UHSAX:
+ case ARM::t2UHSUB16:
+ case ARM::t2UHSUB8:
+ case ARM::t2UQADD16:
+ case ARM::t2UQADD8:
+ case ARM::t2UQASX:
+ case ARM::t2UQSAX:
+ case ARM::t2UQSUB16:
+ case ARM::t2UQSUB8:
+ case ARM::t2USAD8:
+ case ARM::t2USAT16:
+ case ARM::t2USAX:
+ case ARM::t2USUB16:
+ case ARM::t2USUB8:
+ case ARM::t2UXTAB16rr:
case ARM::t2UXTABrr:
case ARM::t2UXTAHrr: printOperand(MI, 2); break;
case ARM::ADDSrs:
case ARM::RSBSrs:
case ARM::SUBSrs: printSORegOperand(MI, 2); break;
+ case ARM::BFI: printBitfieldInvMaskImmOperand(MI, 2); break;
case ARM::t2ORNrs:
case ARM::t2RSBSrs:
case ARM::t2RSBrs:
@@ -4339,16 +5008,74 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printJTBlockOperand(MI, 2);
return;
break;
+ case ARM::CDP:
+ printOperand(MI, 1);
+ O << ", cr";
+ printNoHashImmediate(MI, 2);
+ O << ", cr";
+ printNoHashImmediate(MI, 3);
+ O << ", cr";
+ printNoHashImmediate(MI, 4);
+ O << ", ";
+ printOperand(MI, 5);
+ return;
+ break;
case ARM::FCONSTD:
case ARM::FCONSTS:
+ case ARM::LDC2L_OFFSET:
+ case ARM::LDC2L_OPTION:
+ case ARM::LDC2L_POST:
+ case ARM::LDCL_OFFSET:
+ case ARM::LDCL_OPTION:
+ case ARM::LDCL_POST:
case ARM::MOVrx:
case ARM::MRS:
case ARM::MRSsys:
+ case ARM::PLDWi:
+ case ARM::PLDi:
+ case ARM::PLIi:
+ case ARM::RFEW:
+ case ARM::STC2L_OFFSET:
+ case ARM::STC2L_OPTION:
+ case ARM::STC2L_POST:
+ case ARM::STCL_OFFSET:
+ case ARM::STCL_OPTION:
+ case ARM::STCL_POST:
case ARM::VABSD:
case ARM::VABSS:
case ARM::VABSfd:
case ARM::VABSfd_sfp:
case ARM::VABSfq:
+ case ARM::VCEQzv16i8:
+ case ARM::VCEQzv2i32:
+ case ARM::VCEQzv4i16:
+ case ARM::VCEQzv4i32:
+ case ARM::VCEQzv8i16:
+ case ARM::VCEQzv8i8:
+ case ARM::VCGEzv16i8:
+ case ARM::VCGEzv2i32:
+ case ARM::VCGEzv4i16:
+ case ARM::VCGEzv4i32:
+ case ARM::VCGEzv8i16:
+ case ARM::VCGEzv8i8:
+ case ARM::VCGTzv16i8:
+ case ARM::VCGTzv2i32:
+ case ARM::VCGTzv4i16:
+ case ARM::VCGTzv4i32:
+ case ARM::VCGTzv8i16:
+ case ARM::VCGTzv8i8:
+ case ARM::VCLEzv16i8:
+ case ARM::VCLEzv2i32:
+ case ARM::VCLEzv4i16:
+ case ARM::VCLEzv4i32:
+ case ARM::VCLEzv8i16:
+ case ARM::VCLEzv8i8:
+ case ARM::VCLTzv16i8:
+ case ARM::VCLTzv2i32:
+ case ARM::VCLTzv4i16:
+ case ARM::VCLTzv4i32:
+ case ARM::VCLTzv8i16:
+ case ARM::VCLTzv8i8:
case ARM::VCMPD:
case ARM::VCMPED:
case ARM::VCMPES:
@@ -4370,9 +5097,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VNEGDcc:
case ARM::VNEGS:
case ARM::VNEGScc:
- case ARM::VNEGf32d:
- case ARM::VNEGf32d_sfp:
case ARM::VNEGf32q:
+ case ARM::VNEGfd:
+ case ARM::VNEGfd_sfp:
case ARM::VRECPEfd:
case ARM::VRECPEfq:
case ARM::VRSQRTEfd:
@@ -4415,11 +5142,15 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2MOVCCr:
case ARM::t2MOVsra_flag:
case ARM::t2MOVsrl_flag:
+ case ARM::t2MRS:
+ case ARM::t2MRSsys:
case ARM::t2MVNr:
case ARM::t2MVNs:
case ARM::t2REV:
case ARM::t2REV16:
case ARM::t2REVSH:
+ case ARM::t2RFEDBW:
+ case ARM::t2RFEIAW:
case ARM::t2STRBi12:
case ARM::t2STRBs:
case ARM::t2STRHi12:
@@ -4434,15 +5165,34 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2TSTri:
case ARM::t2TSTrr:
case ARM::t2TSTrs:
- case ARM::t2UXTB16r:
case ARM::t2UXTBr:
case ARM::t2UXTHr:
switch (MI->getOpcode()) {
case ARM::FCONSTD: printVFPf64ImmOperand(MI, 1); break;
case ARM::FCONSTS: printVFPf32ImmOperand(MI, 1); break;
+ case ARM::LDC2L_OFFSET:
+ case ARM::LDCL_OFFSET:
+ case ARM::STC2L_OFFSET:
+ case ARM::STCL_OFFSET: printAddrMode2Operand(MI, 2); break;
+ case ARM::LDC2L_OPTION:
+ case ARM::LDCL_OPTION:
+ case ARM::STC2L_OPTION:
+ case ARM::STCL_OPTION: printNoHashImmediate(MI, 3); break;
+ case ARM::LDC2L_POST:
+ case ARM::LDCL_POST:
+ case ARM::STC2L_POST:
+ case ARM::STCL_POST: printAddrMode2OffsetOperand(MI, 3); break;
case ARM::MOVrx: O << ", rrx"; break;
- case ARM::MRS: O << ", cpsr"; break;
- case ARM::MRSsys: O << ", spsr"; break;
+ case ARM::MRS:
+ case ARM::t2MRS: O << ", cpsr"; break;
+ case ARM::MRSsys:
+ case ARM::t2MRSsys: O << ", spsr"; break;
+ case ARM::PLDWi:
+ case ARM::PLDi:
+ case ARM::PLIi: O << ']'; break;
+ case ARM::RFEW:
+ case ARM::t2RFEDBW:
+ case ARM::t2RFEIAW: O << '!'; break;
case ARM::VABSD:
case ARM::VABSS:
case ARM::VABSfd:
@@ -4456,9 +5206,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VMOVS:
case ARM::VNEGD:
case ARM::VNEGS:
- case ARM::VNEGf32d:
- case ARM::VNEGf32d_sfp:
case ARM::VNEGf32q:
+ case ARM::VNEGfd:
+ case ARM::VNEGfd_sfp:
case ARM::VRECPEfd:
case ARM::VRECPEfq:
case ARM::VRSQRTEfd:
@@ -4486,9 +5236,38 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2TEQrr:
case ARM::t2TSTri:
case ARM::t2TSTrr:
- case ARM::t2UXTB16r:
case ARM::t2UXTBr:
case ARM::t2UXTHr: printOperand(MI, 1); break;
+ case ARM::VCEQzv16i8:
+ case ARM::VCEQzv2i32:
+ case ARM::VCEQzv4i16:
+ case ARM::VCEQzv4i32:
+ case ARM::VCEQzv8i16:
+ case ARM::VCEQzv8i8:
+ case ARM::VCGEzv16i8:
+ case ARM::VCGEzv2i32:
+ case ARM::VCGEzv4i16:
+ case ARM::VCGEzv4i32:
+ case ARM::VCGEzv8i16:
+ case ARM::VCGEzv8i8:
+ case ARM::VCGTzv16i8:
+ case ARM::VCGTzv2i32:
+ case ARM::VCGTzv4i16:
+ case ARM::VCGTzv4i32:
+ case ARM::VCGTzv8i16:
+ case ARM::VCGTzv8i8:
+ case ARM::VCLEzv16i8:
+ case ARM::VCLEzv2i32:
+ case ARM::VCLEzv4i16:
+ case ARM::VCLEzv4i32:
+ case ARM::VCLEzv8i16:
+ case ARM::VCLEzv8i8:
+ case ARM::VCLTzv16i8:
+ case ARM::VCLTzv2i32:
+ case ARM::VCLTzv4i16:
+ case ARM::VCLTzv4i32:
+ case ARM::VCLTzv8i16:
+ case ARM::VCLTzv8i8: O << ", #0"; break;
case ARM::VCVTf2xsd:
case ARM::VCVTf2xsq:
case ARM::VCVTf2xud:
@@ -4539,15 +5318,35 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
}
return;
break;
+ case ARM::LDC2L_PRE:
+ case ARM::LDCL_PRE:
+ case ARM::STC2L_PRE:
+ case ARM::STCL_PRE:
+ printAddrMode2Operand(MI, 2);
+ O << '!';
+ return;
+ break;
+ case ARM::LDC2_OPTION:
+ case ARM::LDC2_POST:
+ case ARM::LDC_OPTION:
+ case ARM::LDC_POST:
case ARM::LDRBT:
case ARM::LDRB_POST:
+ case ARM::LDRHT:
case ARM::LDRH_POST:
+ case ARM::LDRSBT:
case ARM::LDRSB_POST:
+ case ARM::LDRSHT:
case ARM::LDRSH_POST:
case ARM::LDRT:
case ARM::LDR_POST:
+ case ARM::STC2_OPTION:
+ case ARM::STC2_POST:
+ case ARM::STC_OPTION:
+ case ARM::STC_POST:
case ARM::STRBT:
case ARM::STRB_POST:
+ case ARM::STRHT:
case ARM::STRH_POST:
case ARM::STRT:
case ARM::STR_POST:
@@ -4563,17 +5362,29 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
O << "], ";
switch (MI->getOpcode()) {
+ case ARM::LDC2_OPTION:
+ case ARM::LDC_OPTION:
+ case ARM::STC2_OPTION:
+ case ARM::STC_OPTION: printOperand(MI, 3); break;
+ case ARM::LDC2_POST:
+ case ARM::LDC_POST:
case ARM::LDRBT:
case ARM::LDRB_POST:
+ case ARM::LDRSBT:
case ARM::LDRT:
case ARM::LDR_POST:
+ case ARM::STC2_POST:
+ case ARM::STC_POST:
case ARM::STRBT:
case ARM::STRB_POST:
case ARM::STRT:
case ARM::STR_POST: printAddrMode2OffsetOperand(MI, 3); break;
+ case ARM::LDRHT:
case ARM::LDRH_POST:
case ARM::LDRSB_POST:
+ case ARM::LDRSHT:
case ARM::LDRSH_POST:
+ case ARM::STRHT:
case ARM::STRH_POST: printAddrMode3OffsetOperand(MI, 3); break;
case ARM::t2LDRB_POST:
case ARM::t2LDRH_POST:
@@ -4586,11 +5397,15 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
}
return;
break;
+ case ARM::LDC2_PRE:
+ case ARM::LDC_PRE:
case ARM::LDRB_PRE:
case ARM::LDRH_PRE:
case ARM::LDRSB_PRE:
case ARM::LDRSH_PRE:
case ARM::LDR_PRE:
+ case ARM::STC2_PRE:
+ case ARM::STC_PRE:
case ARM::t2LDRB_PRE:
case ARM::t2LDRH_PRE:
case ARM::t2LDRSB_PRE:
@@ -4598,8 +5413,12 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2LDR_PRE:
O << ", ";
switch (MI->getOpcode()) {
+ case ARM::LDC2_PRE:
+ case ARM::LDC_PRE:
case ARM::LDRB_PRE:
- case ARM::LDR_PRE: printAddrMode2Operand(MI, 2); break;
+ case ARM::LDR_PRE:
+ case ARM::STC2_PRE:
+ case ARM::STC_PRE: printAddrMode2Operand(MI, 2); break;
case ARM::LDRH_PRE:
case ARM::LDRSB_PRE:
case ARM::LDRSH_PRE: printAddrMode3Operand(MI, 2); break;
@@ -4612,6 +5431,37 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << '!';
return;
break;
+ case ARM::LDM:
+ case ARM::LDM_RET:
+ case ARM::STM:
+ case ARM::tLDM:
+ case ARM::tSTM:
+ printAddrMode4Operand(MI, 0);
+ O << ", ";
+ printRegisterList(MI, 4);
+ return;
+ break;
+ case ARM::LDRD_POST:
+ case ARM::STRD_POST:
+ O << ", ";
+ switch (MI->getOpcode()) {
+ case ARM::LDRD_POST: printOperand(MI, 1); break;
+ case ARM::STRD_POST: printOperand(MI, 2); break;
+ }
+ O << ", [";
+ printOperand(MI, 3);
+ O << "], ";
+ printAddrMode3OffsetOperand(MI, 4);
+ return;
+ break;
+ case ARM::LDRD_PRE:
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printAddrMode3Operand(MI, 3);
+ O << '!';
+ return;
+ break;
case ARM::LDREX:
case ARM::LDREXB:
case ARM::LDREXH:
@@ -4642,6 +5492,8 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
break;
case ARM::MCR:
case ARM::MRC:
+ printOperand(MI, 1);
+ O << ", ";
printOperand(MI, 2);
O << ", cr";
printNoHashImmediate(MI, 3);
@@ -4663,6 +5515,8 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
break;
case ARM::MCRR:
case ARM::MRRC:
+ printOperand(MI, 1);
+ O << ", ";
printOperand(MI, 2);
O << ", ";
printOperand(MI, 3);
@@ -4717,20 +5571,37 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::SBFX:
case ARM::SMLABB:
case ARM::SMLABT:
+ case ARM::SMLAD:
+ case ARM::SMLADX:
case ARM::SMLALBB:
case ARM::SMLALBT:
+ case ARM::SMLALD:
+ case ARM::SMLALDX:
case ARM::SMLALTB:
case ARM::SMLALTT:
case ARM::SMLATB:
case ARM::SMLATT:
case ARM::SMLAWB:
case ARM::SMLAWT:
+ case ARM::SMLSD:
+ case ARM::SMLSDX:
+ case ARM::SMLSLD:
+ case ARM::SMLSLDX:
case ARM::SMMLA:
+ case ARM::SMMLAR:
case ARM::SMMLS:
+ case ARM::SMMLSR:
+ case ARM::SSATasr:
+ case ARM::SSATlsl:
+ case ARM::SXTAB16rr_rot:
case ARM::SXTABrr_rot:
case ARM::SXTAHrr_rot:
case ARM::UBFX:
case ARM::UMAAL:
+ case ARM::USADA8:
+ case ARM::USATasr:
+ case ARM::USATlsl:
+ case ARM::UXTAB16rr_rot:
case ARM::UXTABrr_rot:
case ARM::UXTAHrr_rot:
case ARM::VEXTd16:
@@ -4751,20 +5622,41 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2SBFX:
case ARM::t2SMLABB:
case ARM::t2SMLABT:
+ case ARM::t2SMLAD:
+ case ARM::t2SMLADX:
case ARM::t2SMLAL:
+ case ARM::t2SMLALBB:
+ case ARM::t2SMLALBT:
+ case ARM::t2SMLALD:
+ case ARM::t2SMLALDX:
+ case ARM::t2SMLALTB:
+ case ARM::t2SMLALTT:
case ARM::t2SMLATB:
case ARM::t2SMLATT:
case ARM::t2SMLAWB:
case ARM::t2SMLAWT:
+ case ARM::t2SMLSD:
+ case ARM::t2SMLSDX:
+ case ARM::t2SMLSLD:
+ case ARM::t2SMLSLDX:
case ARM::t2SMMLA:
+ case ARM::t2SMMLAR:
case ARM::t2SMMLS:
+ case ARM::t2SMMLSR:
case ARM::t2SMULL:
+ case ARM::t2SSATasr:
+ case ARM::t2SSATlsl:
+ case ARM::t2SXTAB16rr_rot:
case ARM::t2SXTABrr_rot:
case ARM::t2SXTAHrr_rot:
case ARM::t2UBFX:
case ARM::t2UMAAL:
case ARM::t2UMLAL:
case ARM::t2UMULL:
+ case ARM::t2USADA8:
+ case ARM::t2USATasr:
+ case ARM::t2USATlsl:
+ case ARM::t2UXTAB16rr_rot:
case ARM::t2UXTABrr_rot:
case ARM::t2UXTAHrr_rot:
O << ", ";
@@ -4776,18 +5668,29 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::SBFX:
case ARM::SMLABB:
case ARM::SMLABT:
+ case ARM::SMLAD:
+ case ARM::SMLADX:
case ARM::SMLALBB:
case ARM::SMLALBT:
+ case ARM::SMLALD:
+ case ARM::SMLALDX:
case ARM::SMLALTB:
case ARM::SMLALTT:
case ARM::SMLATB:
case ARM::SMLATT:
case ARM::SMLAWB:
case ARM::SMLAWT:
+ case ARM::SMLSD:
+ case ARM::SMLSDX:
+ case ARM::SMLSLD:
+ case ARM::SMLSLDX:
case ARM::SMMLA:
+ case ARM::SMMLAR:
case ARM::SMMLS:
+ case ARM::SMMLSR:
case ARM::UBFX:
case ARM::UMAAL:
+ case ARM::USADA8:
case ARM::VEXTd16:
case ARM::VEXTd32:
case ARM::VEXTd8:
@@ -4804,28 +5707,55 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2SBFX:
case ARM::t2SMLABB:
case ARM::t2SMLABT:
+ case ARM::t2SMLAD:
+ case ARM::t2SMLADX:
case ARM::t2SMLAL:
+ case ARM::t2SMLALBB:
+ case ARM::t2SMLALBT:
+ case ARM::t2SMLALD:
+ case ARM::t2SMLALDX:
+ case ARM::t2SMLALTB:
+ case ARM::t2SMLALTT:
case ARM::t2SMLATB:
case ARM::t2SMLATT:
case ARM::t2SMLAWB:
case ARM::t2SMLAWT:
+ case ARM::t2SMLSD:
+ case ARM::t2SMLSDX:
+ case ARM::t2SMLSLD:
+ case ARM::t2SMLSLDX:
case ARM::t2SMMLA:
+ case ARM::t2SMMLAR:
case ARM::t2SMMLS:
+ case ARM::t2SMMLSR:
case ARM::t2SMULL:
case ARM::t2UBFX:
case ARM::t2UMAAL:
case ARM::t2UMLAL:
- case ARM::t2UMULL: O << ", "; break;
+ case ARM::t2UMULL:
+ case ARM::t2USADA8: O << ", "; break;
case ARM::PKHBT:
- case ARM::t2PKHBT: O << ", LSL "; break;
+ case ARM::SSATlsl:
+ case ARM::USATlsl:
+ case ARM::t2PKHBT:
+ case ARM::t2SSATlsl:
+ case ARM::t2USATlsl: O << ", lsl "; break;
case ARM::PKHTB:
- case ARM::t2PKHTB: O << ", ASR "; break;
+ case ARM::SSATasr:
+ case ARM::USATasr:
+ case ARM::t2PKHTB:
+ case ARM::t2SSATasr:
+ case ARM::t2USATasr: O << ", asr "; break;
+ case ARM::SXTAB16rr_rot:
case ARM::SXTABrr_rot:
case ARM::SXTAHrr_rot:
+ case ARM::UXTAB16rr_rot:
case ARM::UXTABrr_rot:
case ARM::UXTAHrr_rot:
+ case ARM::t2SXTAB16rr_rot:
case ARM::t2SXTABrr_rot:
case ARM::t2SXTAHrr_rot:
+ case ARM::t2UXTAB16rr_rot:
case ARM::t2UXTABrr_rot:
case ARM::t2UXTAHrr_rot: O << ", ror "; break;
}
@@ -4874,6 +5804,16 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << "]!";
return;
break;
+ case ARM::STRD_PRE:
+ O << ", ";
+ printOperand(MI, 2);
+ O << ", [";
+ printOperand(MI, 3);
+ O << ", ";
+ printAddrMode3OffsetOperand(MI, 4);
+ O << "]!";
+ return;
+ break;
case ARM::STREXD:
case ARM::t2STREXD:
O << ", ";
@@ -4885,11 +5825,14 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << ']';
return;
break;
+ case ARM::SXTB16r_rot:
case ARM::SXTBr_rot:
case ARM::SXTHr_rot:
case ARM::UXTB16r_rot:
case ARM::UXTBr_rot:
case ARM::UXTHr_rot:
+ case ARM::t2SXTB16r_rot:
+ case ARM::t2UXTB16r_rot:
O << ", ";
printOperand(MI, 1);
O << ", ror ";
@@ -4916,8 +5859,10 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VDIVD:
case ARM::VDIVS:
case ARM::VMAXfd:
+ case ARM::VMAXfd_sfp:
case ARM::VMAXfq:
case ARM::VMINfd:
+ case ARM::VMINfd_sfp:
case ARM::VMINfq:
case ARM::VMULD:
case ARM::VMULS:
@@ -4938,6 +5883,8 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VSUBfd:
case ARM::VSUBfd_sfp:
case ARM::VSUBfq:
+ case ARM::t2ADCSrr:
+ case ARM::t2ADCSrs:
case ARM::t2ADCrr:
case ARM::t2ADCrs:
case ARM::t2ADDSri:
@@ -4965,6 +5912,8 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2RORri:
case ARM::t2RORrr:
case ARM::t2RSBri:
+ case ARM::t2SBCSrr:
+ case ARM::t2SBCSrs:
case ARM::t2SBCrr:
case ARM::t2SBCrs:
case ARM::t2SUBSri:
@@ -4997,8 +5946,10 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VDIVD:
case ARM::VDIVS:
case ARM::VMAXfd:
+ case ARM::VMAXfd_sfp:
case ARM::VMAXfq:
case ARM::VMINfd:
+ case ARM::VMINfd_sfp:
case ARM::VMINfq:
case ARM::VMULD:
case ARM::VMULS:
@@ -5019,6 +5970,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VSUBfd:
case ARM::VSUBfd_sfp:
case ARM::VSUBfq:
+ case ARM::t2ADCSrr:
case ARM::t2ADCrr:
case ARM::t2ADDSri:
case ARM::t2ADDSrr:
@@ -5038,12 +5990,14 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2RORri:
case ARM::t2RORrr:
case ARM::t2RSBri:
+ case ARM::t2SBCSrr:
case ARM::t2SBCrr:
case ARM::t2SUBSri:
case ARM::t2SUBSrr:
case ARM::t2SUBrSPi:
case ARM::t2SUBri:
case ARM::t2SUBrr: printOperand(MI, 2); break;
+ case ARM::t2ADCSrs:
case ARM::t2ADCrs:
case ARM::t2ADDSrs:
case ARM::t2ADDrSPs:
@@ -5052,12 +6006,27 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2BICrs:
case ARM::t2EORrs:
case ARM::t2ORRrs:
+ case ARM::t2SBCSrs:
case ARM::t2SBCrs:
case ARM::t2SUBSrs:
case ARM::t2SUBrs: printT2SOOperand(MI, 2); break;
}
return;
break;
+ case ARM::VCEQzv2f32:
+ case ARM::VCEQzv4f32:
+ case ARM::VCGEzv2f32:
+ case ARM::VCGEzv4f32:
+ case ARM::VCGTzv2f32:
+ case ARM::VCGTzv4f32:
+ case ARM::VCLEzv2f32:
+ case ARM::VCLEzv4f32:
+ case ARM::VCLTzv2f32:
+ case ARM::VCLTzv4f32:
+ printOperand(MI, 1);
+ O << ", #0";
+ return;
+ break;
case ARM::VDUPLN16d:
case ARM::VDUPLN16q:
case ARM::VDUPLN32d:
@@ -5120,33 +6089,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
}
return;
break;
- case ARM::VLD2LNd16:
- case ARM::VLD2LNd32:
- case ARM::VLD2LNd8:
- case ARM::VLD2LNq16a:
- case ARM::VLD2LNq16b:
- case ARM::VLD2LNq32a:
- case ARM::VLD2LNq32b:
- O << '[';
- printNoHashImmediate(MI, 8);
- O << "], ";
- printOperand(MI, 1);
- O << '[';
- printNoHashImmediate(MI, 8);
- O << "]}, ";
- printAddrMode6Operand(MI, 2);
- return;
- break;
- case ARM::VLD2d16:
- case ARM::VLD2d32:
- case ARM::VLD2d64:
- case ARM::VLD2d8:
- O << ", ";
- printOperand(MI, 1);
- O << "}, ";
- printAddrMode6Operand(MI, 2);
- return;
- break;
+ case ARM::VLD1d16Q:
+ case ARM::VLD1d32Q:
+ case ARM::VLD1d8Q:
case ARM::VLD2q16:
case ARM::VLD2q32:
case ARM::VLD2q8:
@@ -5168,6 +6113,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 3);
O << "}, ";
switch (MI->getOpcode()) {
+ case ARM::VLD1d16Q:
+ case ARM::VLD1d32Q:
+ case ARM::VLD1d8Q:
case ARM::VLD2q16:
case ARM::VLD2q32:
case ARM::VLD2q8:
@@ -5184,27 +6132,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
}
return;
break;
- case ARM::VLD3LNd16:
- case ARM::VLD3LNd32:
- case ARM::VLD3LNd8:
- case ARM::VLD3LNq16a:
- case ARM::VLD3LNq16b:
- case ARM::VLD3LNq32a:
- case ARM::VLD3LNq32b:
- O << '[';
- printNoHashImmediate(MI, 10);
- O << "], ";
- printOperand(MI, 1);
- O << '[';
- printNoHashImmediate(MI, 10);
- O << "], ";
- printOperand(MI, 2);
- O << '[';
- printNoHashImmediate(MI, 10);
- O << "]}, ";
- printAddrMode6Operand(MI, 3);
- return;
- break;
+ case ARM::VLD1d16T:
+ case ARM::VLD1d32T:
+ case ARM::VLD1d8T:
case ARM::VLD3d16:
case ARM::VLD3d32:
case ARM::VLD3d64:
@@ -5221,6 +6151,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
O << "}, ";
switch (MI->getOpcode()) {
+ case ARM::VLD1d16T:
+ case ARM::VLD1d32T:
+ case ARM::VLD1d8T:
case ARM::VLD3d16:
case ARM::VLD3d32:
case ARM::VLD3d64:
@@ -5234,6 +6167,57 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
}
return;
break;
+ case ARM::VLD2LNd16:
+ case ARM::VLD2LNd32:
+ case ARM::VLD2LNd8:
+ case ARM::VLD2LNq16a:
+ case ARM::VLD2LNq16b:
+ case ARM::VLD2LNq32a:
+ case ARM::VLD2LNq32b:
+ O << '[';
+ printNoHashImmediate(MI, 8);
+ O << "], ";
+ printOperand(MI, 1);
+ O << '[';
+ printNoHashImmediate(MI, 8);
+ O << "]}, ";
+ printAddrMode6Operand(MI, 2);
+ return;
+ break;
+ case ARM::VLD2d16:
+ case ARM::VLD2d16D:
+ case ARM::VLD2d32:
+ case ARM::VLD2d32D:
+ case ARM::VLD2d64:
+ case ARM::VLD2d8:
+ case ARM::VLD2d8D:
+ O << ", ";
+ printOperand(MI, 1);
+ O << "}, ";
+ printAddrMode6Operand(MI, 2);
+ return;
+ break;
+ case ARM::VLD3LNd16:
+ case ARM::VLD3LNd32:
+ case ARM::VLD3LNd8:
+ case ARM::VLD3LNq16a:
+ case ARM::VLD3LNq16b:
+ case ARM::VLD3LNq32a:
+ case ARM::VLD3LNq32b:
+ O << '[';
+ printNoHashImmediate(MI, 10);
+ O << "], ";
+ printOperand(MI, 1);
+ O << '[';
+ printNoHashImmediate(MI, 10);
+ O << "], ";
+ printOperand(MI, 2);
+ O << '[';
+ printNoHashImmediate(MI, 10);
+ O << "]}, ";
+ printAddrMode6Operand(MI, 3);
+ return;
+ break;
case ARM::VLD4LNd16:
case ARM::VLD4LNd32:
case ARM::VLD4LNd8:
@@ -5363,6 +6347,41 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
+ case ARM::VST1d16Q:
+ case ARM::VST1d32Q:
+ case ARM::VST1d8Q:
+ case ARM::VST2q16:
+ case ARM::VST2q32:
+ case ARM::VST2q8:
+ case ARM::VST4d16:
+ case ARM::VST4d32:
+ case ARM::VST4d64:
+ case ARM::VST4d8:
+ O << ", ";
+ printOperand(MI, 5);
+ O << ", ";
+ printOperand(MI, 6);
+ O << ", ";
+ printOperand(MI, 7);
+ O << "}, ";
+ printAddrMode6Operand(MI, 0);
+ return;
+ break;
+ case ARM::VST1d16T:
+ case ARM::VST1d32T:
+ case ARM::VST1d8T:
+ case ARM::VST3d16:
+ case ARM::VST3d32:
+ case ARM::VST3d64:
+ case ARM::VST3d8:
+ O << ", ";
+ printOperand(MI, 5);
+ O << ", ";
+ printOperand(MI, 6);
+ O << "}, ";
+ printAddrMode6Operand(MI, 0);
+ return;
+ break;
case ARM::VST2LNd16:
case ARM::VST2LNd32:
case ARM::VST2LNd8:
@@ -5381,32 +6400,18 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case ARM::VST2d16:
+ case ARM::VST2d16D:
case ARM::VST2d32:
+ case ARM::VST2d32D:
case ARM::VST2d64:
case ARM::VST2d8:
+ case ARM::VST2d8D:
O << ", ";
printOperand(MI, 5);
O << "}, ";
printAddrMode6Operand(MI, 0);
return;
break;
- case ARM::VST2q16:
- case ARM::VST2q32:
- case ARM::VST2q8:
- case ARM::VST4d16:
- case ARM::VST4d32:
- case ARM::VST4d64:
- case ARM::VST4d8:
- O << ", ";
- printOperand(MI, 5);
- O << ", ";
- printOperand(MI, 6);
- O << ", ";
- printOperand(MI, 7);
- O << "}, ";
- printAddrMode6Operand(MI, 0);
- return;
- break;
case ARM::VST3LNd16:
case ARM::VST3LNd32:
case ARM::VST3LNd8:
@@ -5428,18 +6433,6 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrMode6Operand(MI, 0);
return;
break;
- case ARM::VST3d16:
- case ARM::VST3d32:
- case ARM::VST3d64:
- case ARM::VST3d8:
- O << ", ";
- printOperand(MI, 5);
- O << ", ";
- printOperand(MI, 6);
- O << "}, ";
- printAddrMode6Operand(MI, 0);
- return;
- break;
case ARM::VST4LNd16:
case ARM::VST4LNd32:
case ARM::VST4LNd8:
@@ -5571,9 +6564,15 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printNoHashImmediate(MI, 2);
return;
break;
+ case ARM::t2MOVrx:
+ case ARM::t2MVNi:
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
case ARM::t2SXTBr_rot:
case ARM::t2SXTHr_rot:
- case ARM::t2UXTB16r_rot:
case ARM::t2UXTBr_rot:
case ARM::t2UXTHr_rot:
printOperand(MI, 1);
@@ -5637,125 +6636,148 @@ const char *ARMAsmPrinter::getRegisterName(unsigned RegNo) {
/// from the instruction set description. This returns the enum name of the
/// specified instruction.
const char *ARMAsmPrinter::getInstructionName(unsigned Opcode) {
- assert(Opcode < 1611 && "Invalid instruction number!");
+ assert(Opcode < 1945 && "Invalid instruction number!");
static const unsigned InstAsmOffset[] = {
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 138,
146, 154, 160, 166, 172, 179, 186, 193, 199, 205, 211, 228, 243, 249,
255, 261, 281, 301, 320, 340, 360, 379, 399, 419, 438, 459, 480, 500,
519, 538, 556, 576, 596, 615, 635, 655, 674, 690, 706, 721, 723, 727,
- 733, 739, 745, 750, 753, 757, 763, 771, 776, 786, 792, 801, 808, 815,
- 818, 822, 829, 834, 838, 842, 847, 851, 858, 865, 872, 878, 884, 890,
- 897, 904, 911, 927, 931, 935, 941, 947, 953, 961, 969, 976, 993, 1010,
- 1028, 1046, 1065, 1069, 1077, 1081, 1086, 1092, 1102, 1111, 1116, 1122, 1129, 1136,
- 1143, 1148, 1158, 1167, 1173, 1184, 1194, 1200, 1211, 1221, 1226, 1235, 1243, 1249,
- 1258, 1269, 1273, 1278, 1283, 1289, 1293, 1297, 1304, 1311, 1318, 1326, 1331, 1338,
- 1350, 1360, 1365, 1371, 1376, 1388, 1400, 1404, 1409, 1414, 1420, 1424, 1431, 1435,
- 1442, 1446, 1451, 1456, 1461, 1465, 1471, 1477, 1483, 1490, 1497, 1505, 1513, 1522,
- 1531, 1538, 1546, 1554, 1560, 1566, 1571, 1578, 1584, 1589, 1595, 1601, 1606, 1611,
- 1618, 1624, 1629, 1633, 1639, 1645, 1652, 1659, 1665, 1671, 1678, 1685, 1691, 1697,
- 1705, 1713, 1721, 1727, 1733, 1739, 1744, 1753, 1762, 1766, 1773, 1780, 1786, 1794,
- 1802, 1810, 1818, 1825, 1832, 1839, 1846, 1852, 1858, 1864, 1871, 1878, 1884, 1891,
- 1898, 1905, 1912, 1916, 1920, 1925, 1931, 1941, 1950, 1955, 1961, 1968, 1975, 1982,
- 1987, 1997, 2006, 2011, 2020, 2028, 2035, 2042, 2049, 2055, 2061, 2067, 2071, 2075,
- 2080, 2088, 2100, 2108, 2120, 2126, 2136, 2142, 2152, 2158, 2164, 2170, 2177, 2182,
- 2188, 2194, 2200, 2205, 2211, 2217, 2223, 2231, 2238, 2244, 2250, 2258, 2265, 2273,
- 2285, 2293, 2305, 2313, 2325, 2331, 2341, 2347, 2357, 2369, 2381, 2393, 2405, 2417,
- 2429, 2440, 2451, 2462, 2473, 2484, 2494, 2505, 2516, 2527, 2538, 2549, 2559, 2571,
- 2583, 2595, 2607, 2619, 2631, 2638, 2645, 2656, 2667, 2678, 2689, 2700, 2710, 2721,
- 2732, 2743, 2754, 2765, 2775, 2781, 2787, 2794, 2805, 2812, 2822, 2832, 2842, 2852,
- 2862, 2871, 2878, 2885, 2892, 2899, 2905, 2917, 2929, 2940, 2952, 2964, 2976, 2988,
- 3000, 3012, 3018, 3030, 3042, 3054, 3066, 3078, 3090, 3097, 3108, 3115, 3125, 3135,
- 3145, 3155, 3165, 3175, 3185, 3194, 3200, 3206, 3212, 3218, 3224, 3230, 3236, 3242,
- 3248, 3254, 3261, 3268, 3278, 3288, 3298, 3308, 3318, 3327, 3334, 3341, 3352, 3363,
- 3374, 3385, 3396, 3406, 3417, 3428, 3439, 3450, 3461, 3471, 3478, 3485, 3496, 3507,
- 3518, 3529, 3540, 3550, 3561, 3572, 3583, 3594, 3605, 3615, 3625, 3635, 3645, 3655,
- 3665, 3674, 3684, 3694, 3704, 3714, 3724, 3733, 3739, 3746, 3753, 3761, 3769, 3775,
- 3782, 3789, 3795, 3801, 3809, 3817, 3824, 3831, 3839, 3847, 3856, 3869, 3878, 3887,
- 3900, 3909, 3919, 3929, 3939, 3949, 3958, 3971, 3980, 3989, 4002, 4011, 4021, 4031,
- 4041, 4051, 4057, 4063, 4071, 4079, 4087, 4095, 4102, 4109, 4119, 4129, 4139, 4149,
- 4158, 4167, 4176, 4185, 4192, 4200, 4207, 4215, 4221, 4227, 4235, 4243, 4250, 4257,
- 4265, 4273, 4280, 4287, 4297, 4307, 4316, 4326, 4335, 4347, 4359, 4371, 4383, 4395,
- 4406, 4418, 4430, 4442, 4454, 4466, 4477, 4489, 4501, 4513, 4525, 4537, 4548, 4560,
- 4572, 4584, 4596, 4608, 4619, 4627, 4635, 4643, 4650, 4657, 4665, 4673, 4681, 4688,
- 4695, 4705, 4715, 4724, 4735, 4746, 4757, 4768, 4776, 4784, 4792, 4799, 4807, 4815,
- 4822, 4832, 4842, 4851, 4862, 4873, 4884, 4895, 4903, 4911, 4919, 4926, 4935, 4944,
- 4953, 4962, 4970, 4978, 4988, 4998, 5007, 5018, 5029, 5040, 5051, 5059, 5067, 5075,
- 5082, 5091, 5100, 5109, 5118, 5126, 5134, 5140, 5146, 5152, 5158, 5164, 5171, 5178,
- 5189, 5200, 5211, 5222, 5233, 5243, 5254, 5265, 5276, 5287, 5298, 5308, 5315, 5322,
- 5333, 5344, 5355, 5366, 5377, 5387, 5398, 5409, 5420, 5431, 5442, 5452, 5458, 5472,
- 5486, 5500, 5514, 5526, 5538, 5550, 5562, 5574, 5586, 5592, 5599, 5606, 5615, 5624,
- 5636, 5648, 5660, 5672, 5682, 5692, 5702, 5712, 5722, 5731, 5737, 5751, 5765, 5779,
- 5793, 5805, 5817, 5829, 5841, 5853, 5865, 5871, 5878, 5885, 5894, 5903, 5915, 5927,
- 5939, 5951, 5961, 5971, 5981, 5991, 6001, 6010, 6016, 6024, 6032, 6042, 6054, 6066,
- 6078, 6090, 6102, 6114, 6125, 6136, 6146, 6152, 6160, 6168, 6175, 6181, 6188, 6196,
- 6204, 6214, 6224, 6234, 6244, 6254, 6264, 6274, 6283, 6288, 6293, 6299, 6306, 6320,
- 6334, 6348, 6362, 6374, 6386, 6398, 6410, 6422, 6434, 6440, 6447, 6458, 6465, 6472,
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+ 15757, 15766, 15774, 15782, 15791, 15800, 15808, 15816, 15825, 15833, 15840, 15849, 15858, 15867,
+ 15875, 15883, 15891, 15898, 15905, 15911, 15917, 15927, 15936, 15944, 15952, 15962, 15971, 15977,
+ 15986, 15995, 16003, 16012, 16020, 16030, 16040, 16049, 16059, 16069, 16079, 16088, 16097, 16106,
+ 16115, 16123, 16132, 16141, 16151, 16159, 16168, 16176, 16185, 16193, 16202, 16210, 16219, 16228,
+ 16237, 16245, 16254, 16263, 16272, 16281, 16289, 16298, 16306, 16315, 16323, 16332, 16341, 16351,
+ 16361, 16368, 16377, 16385, 16391, 16399, 16411, 16422, 16432, 16441, 16449, 16458, 16466, 16475,
+ 16484, 16493, 16501, 16513, 16524, 16534, 16543, 16551, 16558, 16569, 16579, 16588, 16596, 16603,
+ 16612, 16621, 16630, 16640, 16652, 16665, 16676, 16686, 16697, 16705, 16715, 16723, 16731, 16743,
+ 16759, 16769, 16783, 16793, 16807, 16817, 16831, 16839, 16851, 16859, 16871, 16877, 16886, 16892,
+ 16901, 16909, 16917, 16925, 16934, 16942, 16950, 16958, 16967, 16975, 16982, 16989, 16996, 17006,
+ 17015, 17023, 17031, 17041, 17050, 17058, 17066, 17074, 17084, 17093, 17101, 17109, 17119, 17128,
+ 17136, 17145, 17154, 17164, 17174, 17181, 17190, 17198, 17210, 17226, 17236, 17250, 17260, 17274,
+ 17284, 17298, 17306, 17318, 17326, 17338, 17344, 17350, 17358, 17363, 17372, 17379, 17386, 17395,
+ 17403, 17412, 17419, 17427, 17435, 17444, 17462, 17478, 17483, 17490, 17497, 17504, 17507, 17512,
+ 17518, 17522, 17528, 17537, 17543, 17552, 17558, 17565, 17573, 17577, 17585, 17600, 17606, 17611,
+ 17617, 17623, 17628, 17634, 17642, 17649, 17655, 17664, 17672, 17679, 17684, 17689, 17709, 17714,
+ 17719, 17725, 17732, 17738, 17745, 17752, 17759, 17766, 17772, 17780, 17792, 17800, 17810, 17822,
+ 17829, 17836, 17843, 17850, 17858, 17866, 17881, 17888, 17900, 17913, 17920, 17926, 17939, 17944,
+ 17949, 17954, 17959, 17967, 17972, 17981, 17987, 17992, 17999, 18006, 18011, 18016, 18025, 18030,
+ 18040, 18050, 18055, 18060, 18065, 18071, 18078, 18084, 18091, 18097, 18105, 18112, 18119, 18126,
+ 18134, 18143, 18148, 18154, 18160, 18167, 18175, 18181, 18186, 18192, 18198, 18203, 18208, 0
};
const char *Strs =
@@ -5771,276 +6793,331 @@ const char *ARMAsmPrinter::getInstructionName(unsigned Opcode) {
"16\000ATOMIC_LOAD_OR_I32\000ATOMIC_LOAD_OR_I8\000ATOMIC_LOAD_SUB_I16\000"
"ATOMIC_LOAD_SUB_I32\000ATOMIC_LOAD_SUB_I8\000ATOMIC_LOAD_XOR_I16\000ATO"
"MIC_LOAD_XOR_I32\000ATOMIC_LOAD_XOR_I8\000ATOMIC_SWAP_I16\000ATOMIC_SWA"
- "P_I32\000ATOMIC_SWAP_I8\000B\000BFC\000BICri\000BICrr\000BICrs\000BKPT\000"
- "BL\000BLX\000BLXr9\000BL_pred\000BLr9\000BLr9_pred\000BRIND\000BR_JTadd"
- "\000BR_JTm\000BR_JTr\000BX\000BXJ\000BX_RET\000BXr9\000Bcc\000CDP\000CD"
- "P2\000CLZ\000CMNzri\000CMNzrr\000CMNzrs\000CMPri\000CMPrr\000CMPrs\000C"
- "MPzri\000CMPzrr\000CMPzrs\000CONSTPOOL_ENTRY\000CPS\000DBG\000EORri\000"
- "EORrr\000EORrs\000FCONSTD\000FCONSTS\000FMSTAT\000Int_MemBarrierV6\000I"
- "nt_MemBarrierV7\000Int_SyncBarrierV6\000Int_SyncBarrierV7\000Int_eh_sjl"
- "j_setjmp\000LDM\000LDM_RET\000LDR\000LDRB\000LDRBT\000LDRB_POST\000LDRB"
- "_PRE\000LDRD\000LDREX\000LDREXB\000LDREXD\000LDREXH\000LDRH\000LDRH_POS"
- "T\000LDRH_PRE\000LDRSB\000LDRSB_POST\000LDRSB_PRE\000LDRSH\000LDRSH_POS"
- "T\000LDRSH_PRE\000LDRT\000LDR_POST\000LDR_PRE\000LDRcp\000LEApcrel\000L"
- "EApcrelJT\000MCR\000MCR2\000MCRR\000MCRR2\000MLA\000MLS\000MOVCCi\000MO"
- "VCCr\000MOVCCs\000MOVTi16\000MOVi\000MOVi16\000MOVi2pieces\000MOVi32imm"
- "\000MOVr\000MOVrx\000MOVs\000MOVsra_flag\000MOVsrl_flag\000MRC\000MRC2\000"
- "MRRC\000MRRC2\000MRS\000MRSsys\000MSR\000MSRsys\000MUL\000MVNi\000MVNr\000"
- "MVNs\000NOP\000ORRri\000ORRrr\000ORRrs\000PICADD\000PICLDR\000PICLDRB\000"
- "PICLDRH\000PICLDRSB\000PICLDRSH\000PICSTR\000PICSTRB\000PICSTRH\000PKHB"
- "T\000PKHTB\000QADD\000QADD16\000QADD8\000QASX\000QDADD\000QDSUB\000QSAX"
- "\000QSUB\000QSUB16\000QSUB8\000RBIT\000REV\000REV16\000REVSH\000RSBSri\000"
- "RSBSrs\000RSBri\000RSBrs\000RSCSri\000RSCSrs\000RSCri\000RSCrs\000SBCSS"
- "ri\000SBCSSrr\000SBCSSrs\000SBCri\000SBCrr\000SBCrs\000SBFX\000SETENDBE"
- "\000SETENDLE\000SEV\000SMLABB\000SMLABT\000SMLAL\000SMLALBB\000SMLALBT\000"
- "SMLALTB\000SMLALTT\000SMLATB\000SMLATT\000SMLAWB\000SMLAWT\000SMMLA\000"
- "SMMLS\000SMMUL\000SMULBB\000SMULBT\000SMULL\000SMULTB\000SMULTT\000SMUL"
- "WB\000SMULWT\000STM\000STR\000STRB\000STRBT\000STRB_POST\000STRB_PRE\000"
- "STRD\000STREX\000STREXB\000STREXD\000STREXH\000STRH\000STRH_POST\000STR"
- "H_PRE\000STRT\000STR_POST\000STR_PRE\000SUBSri\000SUBSrr\000SUBSrs\000S"
- "UBri\000SUBrr\000SUBrs\000SVC\000SWP\000SWPB\000SXTABrr\000SXTABrr_rot\000"
- "SXTAHrr\000SXTAHrr_rot\000SXTBr\000SXTBr_rot\000SXTHr\000SXTHr_rot\000T"
- "EQri\000TEQrr\000TEQrs\000TPsoft\000TRAP\000TSTri\000TSTrr\000TSTrs\000"
- "UBFX\000UMAAL\000UMLAL\000UMULL\000UQADD16\000UQADD8\000UQASX\000UQSAX\000"
- "UQSUB16\000UQSUB8\000UXTABrr\000UXTABrr_rot\000UXTAHrr\000UXTAHrr_rot\000"
- "UXTB16r\000UXTB16r_rot\000UXTBr\000UXTBr_rot\000UXTHr\000UXTHr_rot\000V"
- "ABALsv2i64\000VABALsv4i32\000VABALsv8i16\000VABALuv2i64\000VABALuv4i32\000"
- "VABALuv8i16\000VABAsv16i8\000VABAsv2i32\000VABAsv4i16\000VABAsv4i32\000"
- "VABAsv8i16\000VABAsv8i8\000VABAuv16i8\000VABAuv2i32\000VABAuv4i16\000VA"
- "BAuv4i32\000VABAuv8i16\000VABAuv8i8\000VABDLsv2i64\000VABDLsv4i32\000VA"
- "BDLsv8i16\000VABDLuv2i64\000VABDLuv4i32\000VABDLuv8i16\000VABDfd\000VAB"
- "Dfq\000VABDsv16i8\000VABDsv2i32\000VABDsv4i16\000VABDsv4i32\000VABDsv8i"
- "16\000VABDsv8i8\000VABDuv16i8\000VABDuv2i32\000VABDuv4i16\000VABDuv4i32"
- "\000VABDuv8i16\000VABDuv8i8\000VABSD\000VABSS\000VABSfd\000VABSfd_sfp\000"
- "VABSfq\000VABSv16i8\000VABSv2i32\000VABSv4i16\000VABSv4i32\000VABSv8i16"
- "\000VABSv8i8\000VACGEd\000VACGEq\000VACGTd\000VACGTq\000VADDD\000VADDHN"
- "v2i32\000VADDHNv4i16\000VADDHNv8i8\000VADDLsv2i64\000VADDLsv4i32\000VAD"
- "DLsv8i16\000VADDLuv2i64\000VADDLuv4i32\000VADDLuv8i16\000VADDS\000VADDW"
- "sv2i64\000VADDWsv4i32\000VADDWsv8i16\000VADDWuv2i64\000VADDWuv4i32\000V"
- "ADDWuv8i16\000VADDfd\000VADDfd_sfp\000VADDfq\000VADDv16i8\000VADDv1i64\000"
- "VADDv2i32\000VADDv2i64\000VADDv4i16\000VADDv4i32\000VADDv8i16\000VADDv8"
- "i8\000VANDd\000VANDq\000VBICd\000VBICq\000VBIFd\000VBIFq\000VBITd\000VB"
- "ITq\000VBSLd\000VBSLq\000VCEQfd\000VCEQfq\000VCEQv16i8\000VCEQv2i32\000"
- "VCEQv4i16\000VCEQv4i32\000VCEQv8i16\000VCEQv8i8\000VCGEfd\000VCGEfq\000"
- "VCGEsv16i8\000VCGEsv2i32\000VCGEsv4i16\000VCGEsv4i32\000VCGEsv8i16\000V"
- "CGEsv8i8\000VCGEuv16i8\000VCGEuv2i32\000VCGEuv4i16\000VCGEuv4i32\000VCG"
- "Euv8i16\000VCGEuv8i8\000VCGTfd\000VCGTfq\000VCGTsv16i8\000VCGTsv2i32\000"
- "VCGTsv4i16\000VCGTsv4i32\000VCGTsv8i16\000VCGTsv8i8\000VCGTuv16i8\000VC"
- "GTuv2i32\000VCGTuv4i16\000VCGTuv4i32\000VCGTuv8i16\000VCGTuv8i8\000VCLS"
- "v16i8\000VCLSv2i32\000VCLSv4i16\000VCLSv4i32\000VCLSv8i16\000VCLSv8i8\000"
- "VCLZv16i8\000VCLZv2i32\000VCLZv4i16\000VCLZv4i32\000VCLZv8i16\000VCLZv8"
- "i8\000VCMPD\000VCMPED\000VCMPES\000VCMPEZD\000VCMPEZS\000VCMPS\000VCMPZ"
- "D\000VCMPZS\000VCNTd\000VCNTq\000VCVTBHS\000VCVTBSH\000VCVTDS\000VCVTSD"
- "\000VCVTTHS\000VCVTTSH\000VCVTf2sd\000VCVTf2sd_sfp\000VCVTf2sq\000VCVTf"
- "2ud\000VCVTf2ud_sfp\000VCVTf2uq\000VCVTf2xsd\000VCVTf2xsq\000VCVTf2xud\000"
- "VCVTf2xuq\000VCVTs2fd\000VCVTs2fd_sfp\000VCVTs2fq\000VCVTu2fd\000VCVTu2"
- "fd_sfp\000VCVTu2fq\000VCVTxs2fd\000VCVTxs2fq\000VCVTxu2fd\000VCVTxu2fq\000"
- "VDIVD\000VDIVS\000VDUP16d\000VDUP16q\000VDUP32d\000VDUP32q\000VDUP8d\000"
- "VDUP8q\000VDUPLN16d\000VDUPLN16q\000VDUPLN32d\000VDUPLN32q\000VDUPLN8d\000"
- "VDUPLN8q\000VDUPLNfd\000VDUPLNfq\000VDUPfd\000VDUPfdf\000VDUPfq\000VDUP"
- "fqf\000VEORd\000VEORq\000VEXTd16\000VEXTd32\000VEXTd8\000VEXTdf\000VEXT"
- "q16\000VEXTq32\000VEXTq8\000VEXTqf\000VGETLNi32\000VGETLNs16\000VGETLNs"
- "8\000VGETLNu16\000VGETLNu8\000VHADDsv16i8\000VHADDsv2i32\000VHADDsv4i16"
- "\000VHADDsv4i32\000VHADDsv8i16\000VHADDsv8i8\000VHADDuv16i8\000VHADDuv2"
- "i32\000VHADDuv4i16\000VHADDuv4i32\000VHADDuv8i16\000VHADDuv8i8\000VHSUB"
- "sv16i8\000VHSUBsv2i32\000VHSUBsv4i16\000VHSUBsv4i32\000VHSUBsv8i16\000V"
- "HSUBsv8i8\000VHSUBuv16i8\000VHSUBuv2i32\000VHSUBuv4i16\000VHSUBuv4i32\000"
- "VHSUBuv8i16\000VHSUBuv8i8\000VLD1d16\000VLD1d32\000VLD1d64\000VLD1d8\000"
- "VLD1df\000VLD1q16\000VLD1q32\000VLD1q64\000VLD1q8\000VLD1qf\000VLD2LNd1"
- "6\000VLD2LNd32\000VLD2LNd8\000VLD2LNq16a\000VLD2LNq16b\000VLD2LNq32a\000"
- "VLD2LNq32b\000VLD2d16\000VLD2d32\000VLD2d64\000VLD2d8\000VLD2q16\000VLD"
- "2q32\000VLD2q8\000VLD3LNd16\000VLD3LNd32\000VLD3LNd8\000VLD3LNq16a\000V"
- "LD3LNq16b\000VLD3LNq32a\000VLD3LNq32b\000VLD3d16\000VLD3d32\000VLD3d64\000"
- "VLD3d8\000VLD3q16a\000VLD3q16b\000VLD3q32a\000VLD3q32b\000VLD3q8a\000VL"
- "D3q8b\000VLD4LNd16\000VLD4LNd32\000VLD4LNd8\000VLD4LNq16a\000VLD4LNq16b"
- "\000VLD4LNq32a\000VLD4LNq32b\000VLD4d16\000VLD4d32\000VLD4d64\000VLD4d8"
- "\000VLD4q16a\000VLD4q16b\000VLD4q32a\000VLD4q32b\000VLD4q8a\000VLD4q8b\000"
- "VLDMD\000VLDMS\000VLDRD\000VLDRQ\000VLDRS\000VMAXfd\000VMAXfq\000VMAXsv"
- "16i8\000VMAXsv2i32\000VMAXsv4i16\000VMAXsv4i32\000VMAXsv8i16\000VMAXsv8"
- "i8\000VMAXuv16i8\000VMAXuv2i32\000VMAXuv4i16\000VMAXuv4i32\000VMAXuv8i1"
- "6\000VMAXuv8i8\000VMINfd\000VMINfq\000VMINsv16i8\000VMINsv2i32\000VMINs"
- "v4i16\000VMINsv4i32\000VMINsv8i16\000VMINsv8i8\000VMINuv16i8\000VMINuv2"
- "i32\000VMINuv4i16\000VMINuv4i32\000VMINuv8i16\000VMINuv8i8\000VMLAD\000"
- "VMLALslsv2i32\000VMLALslsv4i16\000VMLALsluv2i32\000VMLALsluv4i16\000VML"
- "ALsv2i64\000VMLALsv4i32\000VMLALsv8i16\000VMLALuv2i64\000VMLALuv4i32\000"
- "VMLALuv8i16\000VMLAS\000VMLAfd\000VMLAfq\000VMLAslfd\000VMLAslfq\000VML"
- "Aslv2i32\000VMLAslv4i16\000VMLAslv4i32\000VMLAslv8i16\000VMLAv16i8\000V"
- "MLAv2i32\000VMLAv4i16\000VMLAv4i32\000VMLAv8i16\000VMLAv8i8\000VMLSD\000"
- "VMLSLslsv2i32\000VMLSLslsv4i16\000VMLSLsluv2i32\000VMLSLsluv4i16\000VML"
- "SLsv2i64\000VMLSLsv4i32\000VMLSLsv8i16\000VMLSLuv2i64\000VMLSLuv4i32\000"
- "VMLSLuv8i16\000VMLSS\000VMLSfd\000VMLSfq\000VMLSslfd\000VMLSslfq\000VML"
- "Sslv2i32\000VMLSslv4i16\000VMLSslv4i32\000VMLSslv8i16\000VMLSv16i8\000V"
- "MLSv2i32\000VMLSv4i16\000VMLSv4i32\000VMLSv8i16\000VMLSv8i8\000VMOVD\000"
- "VMOVDRR\000VMOVDcc\000VMOVDneon\000VMOVLsv2i64\000VMOVLsv4i32\000VMOVLs"
- "v8i16\000VMOVLuv2i64\000VMOVLuv4i32\000VMOVLuv8i16\000VMOVNv2i32\000VMO"
- "VNv4i16\000VMOVNv8i8\000VMOVQ\000VMOVRRD\000VMOVRRS\000VMOVRS\000VMOVS\000"
- "VMOVSR\000VMOVSRR\000VMOVScc\000VMOVv16i8\000VMOVv1i64\000VMOVv2i32\000"
- "VMOVv2i64\000VMOVv4i16\000VMOVv4i32\000VMOVv8i16\000VMOVv8i8\000VMRS\000"
- "VMSR\000VMULD\000VMULLp\000VMULLslsv2i32\000VMULLslsv4i16\000VMULLsluv2"
- "i32\000VMULLsluv4i16\000VMULLsv2i64\000VMULLsv4i32\000VMULLsv8i16\000VM"
- "ULLuv2i64\000VMULLuv4i32\000VMULLuv8i16\000VMULS\000VMULfd\000VMULfd_sf"
- "p\000VMULfq\000VMULpd\000VMULpq\000VMULslfd\000VMULslfq\000VMULslv2i32\000"
- "VMULslv4i16\000VMULslv4i32\000VMULslv8i16\000VMULv16i8\000VMULv2i32\000"
- "VMULv4i16\000VMULv4i32\000VMULv8i16\000VMULv8i8\000VMVNd\000VMVNq\000VN"
- "EGD\000VNEGDcc\000VNEGS\000VNEGScc\000VNEGf32d\000VNEGf32d_sfp\000VNEGf"
- "32q\000VNEGs16d\000VNEGs16q\000VNEGs32d\000VNEGs32q\000VNEGs8d\000VNEGs"
- "8q\000VNMLAD\000VNMLAS\000VNMLSD\000VNMLSS\000VNMULD\000VNMULS\000VORNd"
- "\000VORNq\000VORRd\000VORRq\000VPADALsv16i8\000VPADALsv2i32\000VPADALsv"
- "4i16\000VPADALsv4i32\000VPADALsv8i16\000VPADALsv8i8\000VPADALuv16i8\000"
- "VPADALuv2i32\000VPADALuv4i16\000VPADALuv4i32\000VPADALuv8i16\000VPADALu"
- "v8i8\000VPADDLsv16i8\000VPADDLsv2i32\000VPADDLsv4i16\000VPADDLsv4i32\000"
- "VPADDLsv8i16\000VPADDLsv8i8\000VPADDLuv16i8\000VPADDLuv2i32\000VPADDLuv"
- "4i16\000VPADDLuv4i32\000VPADDLuv8i16\000VPADDLuv8i8\000VPADDf\000VPADDi"
- "16\000VPADDi32\000VPADDi8\000VPMAXf\000VPMAXs16\000VPMAXs32\000VPMAXs8\000"
- "VPMAXu16\000VPMAXu32\000VPMAXu8\000VPMINf\000VPMINs16\000VPMINs32\000VP"
- "MINs8\000VPMINu16\000VPMINu32\000VPMINu8\000VQABSv16i8\000VQABSv2i32\000"
- "VQABSv4i16\000VQABSv4i32\000VQABSv8i16\000VQABSv8i8\000VQADDsv16i8\000V"
- "QADDsv1i64\000VQADDsv2i32\000VQADDsv2i64\000VQADDsv4i16\000VQADDsv4i32\000"
- "VQADDsv8i16\000VQADDsv8i8\000VQADDuv16i8\000VQADDuv1i64\000VQADDuv2i32\000"
- "VQADDuv2i64\000VQADDuv4i16\000VQADDuv4i32\000VQADDuv8i16\000VQADDuv8i8\000"
- "VQDMLALslv2i32\000VQDMLALslv4i16\000VQDMLALv2i64\000VQDMLALv4i32\000VQD"
- "MLSLslv2i32\000VQDMLSLslv4i16\000VQDMLSLv2i64\000VQDMLSLv4i32\000VQDMUL"
- "Hslv2i32\000VQDMULHslv4i16\000VQDMULHslv4i32\000VQDMULHslv8i16\000VQDMU"
- "LHv2i32\000VQDMULHv4i16\000VQDMULHv4i32\000VQDMULHv8i16\000VQDMULLslv2i"
- "32\000VQDMULLslv4i16\000VQDMULLv2i64\000VQDMULLv4i32\000VQMOVNsuv2i32\000"
- "VQMOVNsuv4i16\000VQMOVNsuv8i8\000VQMOVNsv2i32\000VQMOVNsv4i16\000VQMOVN"
- "sv8i8\000VQMOVNuv2i32\000VQMOVNuv4i16\000VQMOVNuv8i8\000VQNEGv16i8\000V"
- "QNEGv2i32\000VQNEGv4i16\000VQNEGv4i32\000VQNEGv8i16\000VQNEGv8i8\000VQR"
- "DMULHslv2i32\000VQRDMULHslv4i16\000VQRDMULHslv4i32\000VQRDMULHslv8i16\000"
- "VQRDMULHv2i32\000VQRDMULHv4i16\000VQRDMULHv4i32\000VQRDMULHv8i16\000VQR"
- "SHLsv16i8\000VQRSHLsv1i64\000VQRSHLsv2i32\000VQRSHLsv2i64\000VQRSHLsv4i"
- "16\000VQRSHLsv4i32\000VQRSHLsv8i16\000VQRSHLsv8i8\000VQRSHLuv16i8\000VQ"
- "RSHLuv1i64\000VQRSHLuv2i32\000VQRSHLuv2i64\000VQRSHLuv4i16\000VQRSHLuv4"
- "i32\000VQRSHLuv8i16\000VQRSHLuv8i8\000VQRSHRNsv2i32\000VQRSHRNsv4i16\000"
- "VQRSHRNsv8i8\000VQRSHRNuv2i32\000VQRSHRNuv4i16\000VQRSHRNuv8i8\000VQRSH"
- "RUNv2i32\000VQRSHRUNv4i16\000VQRSHRUNv8i8\000VQSHLsiv16i8\000VQSHLsiv1i"
- "64\000VQSHLsiv2i32\000VQSHLsiv2i64\000VQSHLsiv4i16\000VQSHLsiv4i32\000V"
- "QSHLsiv8i16\000VQSHLsiv8i8\000VQSHLsuv16i8\000VQSHLsuv1i64\000VQSHLsuv2"
- "i32\000VQSHLsuv2i64\000VQSHLsuv4i16\000VQSHLsuv4i32\000VQSHLsuv8i16\000"
- "VQSHLsuv8i8\000VQSHLsv16i8\000VQSHLsv1i64\000VQSHLsv2i32\000VQSHLsv2i64"
- "\000VQSHLsv4i16\000VQSHLsv4i32\000VQSHLsv8i16\000VQSHLsv8i8\000VQSHLuiv"
- "16i8\000VQSHLuiv1i64\000VQSHLuiv2i32\000VQSHLuiv2i64\000VQSHLuiv4i16\000"
- "VQSHLuiv4i32\000VQSHLuiv8i16\000VQSHLuiv8i8\000VQSHLuv16i8\000VQSHLuv1i"
- "64\000VQSHLuv2i32\000VQSHLuv2i64\000VQSHLuv4i16\000VQSHLuv4i32\000VQSHL"
- "uv8i16\000VQSHLuv8i8\000VQSHRNsv2i32\000VQSHRNsv4i16\000VQSHRNsv8i8\000"
- "VQSHRNuv2i32\000VQSHRNuv4i16\000VQSHRNuv8i8\000VQSHRUNv2i32\000VQSHRUNv"
- "4i16\000VQSHRUNv8i8\000VQSUBsv16i8\000VQSUBsv1i64\000VQSUBsv2i32\000VQS"
- "UBsv2i64\000VQSUBsv4i16\000VQSUBsv4i32\000VQSUBsv8i16\000VQSUBsv8i8\000"
- "VQSUBuv16i8\000VQSUBuv1i64\000VQSUBuv2i32\000VQSUBuv2i64\000VQSUBuv4i16"
- "\000VQSUBuv4i32\000VQSUBuv8i16\000VQSUBuv8i8\000VRADDHNv2i32\000VRADDHN"
- "v4i16\000VRADDHNv8i8\000VRECPEd\000VRECPEfd\000VRECPEfq\000VRECPEq\000V"
- "RECPSfd\000VRECPSfq\000VREV16d8\000VREV16q8\000VREV32d16\000VREV32d8\000"
- "VREV32q16\000VREV32q8\000VREV64d16\000VREV64d32\000VREV64d8\000VREV64df"
- "\000VREV64q16\000VREV64q32\000VREV64q8\000VREV64qf\000VRHADDsv16i8\000V"
- "RHADDsv2i32\000VRHADDsv4i16\000VRHADDsv4i32\000VRHADDsv8i16\000VRHADDsv"
- "8i8\000VRHADDuv16i8\000VRHADDuv2i32\000VRHADDuv4i16\000VRHADDuv4i32\000"
- "VRHADDuv8i16\000VRHADDuv8i8\000VRSHLsv16i8\000VRSHLsv1i64\000VRSHLsv2i3"
- "2\000VRSHLsv2i64\000VRSHLsv4i16\000VRSHLsv4i32\000VRSHLsv8i16\000VRSHLs"
- "v8i8\000VRSHLuv16i8\000VRSHLuv1i64\000VRSHLuv2i32\000VRSHLuv2i64\000VRS"
- "HLuv4i16\000VRSHLuv4i32\000VRSHLuv8i16\000VRSHLuv8i8\000VRSHRNv2i32\000"
- "VRSHRNv4i16\000VRSHRNv8i8\000VRSHRsv16i8\000VRSHRsv1i64\000VRSHRsv2i32\000"
- "VRSHRsv2i64\000VRSHRsv4i16\000VRSHRsv4i32\000VRSHRsv8i16\000VRSHRsv8i8\000"
- "VRSHRuv16i8\000VRSHRuv1i64\000VRSHRuv2i32\000VRSHRuv2i64\000VRSHRuv4i16"
- "\000VRSHRuv4i32\000VRSHRuv8i16\000VRSHRuv8i8\000VRSQRTEd\000VRSQRTEfd\000"
- "VRSQRTEfq\000VRSQRTEq\000VRSQRTSfd\000VRSQRTSfq\000VRSRAsv16i8\000VRSRA"
- "sv1i64\000VRSRAsv2i32\000VRSRAsv2i64\000VRSRAsv4i16\000VRSRAsv4i32\000V"
- "RSRAsv8i16\000VRSRAsv8i8\000VRSRAuv16i8\000VRSRAuv1i64\000VRSRAuv2i32\000"
- "VRSRAuv2i64\000VRSRAuv4i16\000VRSRAuv4i32\000VRSRAuv8i16\000VRSRAuv8i8\000"
- "VRSUBHNv2i32\000VRSUBHNv4i16\000VRSUBHNv8i8\000VSETLNi16\000VSETLNi32\000"
- "VSETLNi8\000VSHLLi16\000VSHLLi32\000VSHLLi8\000VSHLLsv2i64\000VSHLLsv4i"
- "32\000VSHLLsv8i16\000VSHLLuv2i64\000VSHLLuv4i32\000VSHLLuv8i16\000VSHLi"
- "v16i8\000VSHLiv1i64\000VSHLiv2i32\000VSHLiv2i64\000VSHLiv4i16\000VSHLiv"
- "4i32\000VSHLiv8i16\000VSHLiv8i8\000VSHLsv16i8\000VSHLsv1i64\000VSHLsv2i"
- "32\000VSHLsv2i64\000VSHLsv4i16\000VSHLsv4i32\000VSHLsv8i16\000VSHLsv8i8"
- "\000VSHLuv16i8\000VSHLuv1i64\000VSHLuv2i32\000VSHLuv2i64\000VSHLuv4i16\000"
- "VSHLuv4i32\000VSHLuv8i16\000VSHLuv8i8\000VSHRNv2i32\000VSHRNv4i16\000VS"
- "HRNv8i8\000VSHRsv16i8\000VSHRsv1i64\000VSHRsv2i32\000VSHRsv2i64\000VSHR"
- "sv4i16\000VSHRsv4i32\000VSHRsv8i16\000VSHRsv8i8\000VSHRuv16i8\000VSHRuv"
- "1i64\000VSHRuv2i32\000VSHRuv2i64\000VSHRuv4i16\000VSHRuv4i32\000VSHRuv8"
- "i16\000VSHRuv8i8\000VSHTOD\000VSHTOS\000VSITOD\000VSITOS\000VSLIv16i8\000"
- "VSLIv1i64\000VSLIv2i32\000VSLIv2i64\000VSLIv4i16\000VSLIv4i32\000VSLIv8"
- "i16\000VSLIv8i8\000VSLTOD\000VSLTOS\000VSQRTD\000VSQRTS\000VSRAsv16i8\000"
- "VSRAsv1i64\000VSRAsv2i32\000VSRAsv2i64\000VSRAsv4i16\000VSRAsv4i32\000V"
- "SRAsv8i16\000VSRAsv8i8\000VSRAuv16i8\000VSRAuv1i64\000VSRAuv2i32\000VSR"
- "Auv2i64\000VSRAuv4i16\000VSRAuv4i32\000VSRAuv8i16\000VSRAuv8i8\000VSRIv"
- "16i8\000VSRIv1i64\000VSRIv2i32\000VSRIv2i64\000VSRIv4i16\000VSRIv4i32\000"
- "VSRIv8i16\000VSRIv8i8\000VST1d16\000VST1d32\000VST1d64\000VST1d8\000VST"
- "1df\000VST1q16\000VST1q32\000VST1q64\000VST1q8\000VST1qf\000VST2LNd16\000"
- "VST2LNd32\000VST2LNd8\000VST2LNq16a\000VST2LNq16b\000VST2LNq32a\000VST2"
- "LNq32b\000VST2d16\000VST2d32\000VST2d64\000VST2d8\000VST2q16\000VST2q32"
- "\000VST2q8\000VST3LNd16\000VST3LNd32\000VST3LNd8\000VST3LNq16a\000VST3L"
- "Nq16b\000VST3LNq32a\000VST3LNq32b\000VST3d16\000VST3d32\000VST3d64\000V"
- "ST3d8\000VST3q16a\000VST3q16b\000VST3q32a\000VST3q32b\000VST3q8a\000VST"
- "3q8b\000VST4LNd16\000VST4LNd32\000VST4LNd8\000VST4LNq16a\000VST4LNq16b\000"
- "VST4LNq32a\000VST4LNq32b\000VST4d16\000VST4d32\000VST4d64\000VST4d8\000"
- "VST4q16a\000VST4q16b\000VST4q32a\000VST4q32b\000VST4q8a\000VST4q8b\000V"
- "STMD\000VSTMS\000VSTRD\000VSTRQ\000VSTRS\000VSUBD\000VSUBHNv2i32\000VSU"
- "BHNv4i16\000VSUBHNv8i8\000VSUBLsv2i64\000VSUBLsv4i32\000VSUBLsv8i16\000"
- "VSUBLuv2i64\000VSUBLuv4i32\000VSUBLuv8i16\000VSUBS\000VSUBWsv2i64\000VS"
- "UBWsv4i32\000VSUBWsv8i16\000VSUBWuv2i64\000VSUBWuv4i32\000VSUBWuv8i16\000"
- "VSUBfd\000VSUBfd_sfp\000VSUBfq\000VSUBv16i8\000VSUBv1i64\000VSUBv2i32\000"
- "VSUBv2i64\000VSUBv4i16\000VSUBv4i32\000VSUBv8i16\000VSUBv8i8\000VTBL1\000"
- "VTBL2\000VTBL3\000VTBL4\000VTBX1\000VTBX2\000VTBX3\000VTBX4\000VTOSHD\000"
- "VTOSHS\000VTOSIRD\000VTOSIRS\000VTOSIZD\000VTOSIZS\000VTOSLD\000VTOSLS\000"
- "VTOUHD\000VTOUHS\000VTOUIRD\000VTOUIRS\000VTOUIZD\000VTOUIZS\000VTOULD\000"
- "VTOULS\000VTRNd16\000VTRNd32\000VTRNd8\000VTRNq16\000VTRNq32\000VTRNq8\000"
- "VTSTv16i8\000VTSTv2i32\000VTSTv4i16\000VTSTv4i32\000VTSTv8i16\000VTSTv8"
- "i8\000VUHTOD\000VUHTOS\000VUITOD\000VUITOS\000VULTOD\000VULTOS\000VUZPd"
- "16\000VUZPd32\000VUZPd8\000VUZPq16\000VUZPq32\000VUZPq8\000VZIPd16\000V"
- "ZIPd32\000VZIPd8\000VZIPq16\000VZIPq32\000VZIPq8\000WFE\000WFI\000YIELD"
- "\000t2ADCSri\000t2ADCSrr\000t2ADCSrs\000t2ADCri\000t2ADCrr\000t2ADCrs\000"
- "t2ADDSri\000t2ADDSrr\000t2ADDSrs\000t2ADDrSPi\000t2ADDrSPi12\000t2ADDrS"
- "Ps\000t2ADDri\000t2ADDri12\000t2ADDrr\000t2ADDrs\000t2ANDri\000t2ANDrr\000"
- "t2ANDrs\000t2ASRri\000t2ASRrr\000t2B\000t2BFC\000t2BFI\000t2BICri\000t2"
- "BICrr\000t2BICrs\000t2BR_JT\000t2Bcc\000t2CLZ\000t2CMNzri\000t2CMNzrr\000"
- "t2CMNzrs\000t2CMPri\000t2CMPrr\000t2CMPrs\000t2CMPzri\000t2CMPzrr\000t2"
- "CMPzrs\000t2EORri\000t2EORrr\000t2EORrs\000t2IT\000t2Int_MemBarrierV7\000"
- "t2Int_SyncBarrierV7\000t2Int_eh_sjlj_setjmp\000t2LDM\000t2LDM_RET\000t2"
- "LDRB_POST\000t2LDRB_PRE\000t2LDRBi12\000t2LDRBi8\000t2LDRBpci\000t2LDRB"
- "s\000t2LDRDi8\000t2LDRDpci\000t2LDREX\000t2LDREXB\000t2LDREXD\000t2LDRE"
- "XH\000t2LDRH_POST\000t2LDRH_PRE\000t2LDRHi12\000t2LDRHi8\000t2LDRHpci\000"
- "t2LDRHs\000t2LDRSB_POST\000t2LDRSB_PRE\000t2LDRSBi12\000t2LDRSBi8\000t2"
- "LDRSBpci\000t2LDRSBs\000t2LDRSH_POST\000t2LDRSH_PRE\000t2LDRSHi12\000t2"
- "LDRSHi8\000t2LDRSHpci\000t2LDRSHs\000t2LDR_POST\000t2LDR_PRE\000t2LDRi1"
- "2\000t2LDRi8\000t2LDRpci\000t2LDRpci_pic\000t2LDRs\000t2LEApcrel\000t2L"
- "EApcrelJT\000t2LSLri\000t2LSLrr\000t2LSRri\000t2LSRrr\000t2MLA\000t2MLS"
- "\000t2MOVCCasr\000t2MOVCCi\000t2MOVCClsl\000t2MOVCClsr\000t2MOVCCr\000t"
- "2MOVCCror\000t2MOVTi16\000t2MOVi\000t2MOVi16\000t2MOVi32imm\000t2MOVr\000"
- "t2MOVrx\000t2MOVsra_flag\000t2MOVsrl_flag\000t2MUL\000t2MVNi\000t2MVNr\000"
- "t2MVNs\000t2ORNri\000t2ORNrr\000t2ORNrs\000t2ORRri\000t2ORRrr\000t2ORRr"
- "s\000t2PKHBT\000t2PKHTB\000t2RBIT\000t2REV\000t2REV16\000t2REVSH\000t2R"
- "ORri\000t2RORrr\000t2RSBSri\000t2RSBSrs\000t2RSBri\000t2RSBrs\000t2SBCS"
- "ri\000t2SBCSrr\000t2SBCSrs\000t2SBCri\000t2SBCrr\000t2SBCrs\000t2SBFX\000"
- "t2SMLABB\000t2SMLABT\000t2SMLAL\000t2SMLATB\000t2SMLATT\000t2SMLAWB\000"
- "t2SMLAWT\000t2SMMLA\000t2SMMLS\000t2SMMUL\000t2SMULBB\000t2SMULBT\000t2"
- "SMULL\000t2SMULTB\000t2SMULTT\000t2SMULWB\000t2SMULWT\000t2STM\000t2STR"
- "B_POST\000t2STRB_PRE\000t2STRBi12\000t2STRBi8\000t2STRBs\000t2STRDi8\000"
- "t2STREX\000t2STREXB\000t2STREXD\000t2STREXH\000t2STRH_POST\000t2STRH_PR"
- "E\000t2STRHi12\000t2STRHi8\000t2STRHs\000t2STR_POST\000t2STR_PRE\000t2S"
- "TRi12\000t2STRi8\000t2STRs\000t2SUBSri\000t2SUBSrr\000t2SUBSrs\000t2SUB"
- "rSPi\000t2SUBrSPi12\000t2SUBrSPi12_\000t2SUBrSPi_\000t2SUBrSPs\000t2SUB"
- "rSPs_\000t2SUBri\000t2SUBri12\000t2SUBrr\000t2SUBrs\000t2SXTABrr\000t2S"
- "XTABrr_rot\000t2SXTAHrr\000t2SXTAHrr_rot\000t2SXTBr\000t2SXTBr_rot\000t"
- "2SXTHr\000t2SXTHr_rot\000t2TBB\000t2TBH\000t2TEQri\000t2TEQrr\000t2TEQr"
- "s\000t2TPsoft\000t2TSTri\000t2TSTrr\000t2TSTrs\000t2UBFX\000t2UMAAL\000"
- "t2UMLAL\000t2UMULL\000t2UXTABrr\000t2UXTABrr_rot\000t2UXTAHrr\000t2UXTA"
- "Hrr_rot\000t2UXTB16r\000t2UXTB16r_rot\000t2UXTBr\000t2UXTBr_rot\000t2UX"
- "THr\000t2UXTHr_rot\000tADC\000tADDhirr\000tADDi3\000tADDi8\000tADDrPCi\000"
- "tADDrSP\000tADDrSPi\000tADDrr\000tADDspi\000tADDspr\000tADDspr_\000tADJ"
- "CALLSTACKDOWN\000tADJCALLSTACKUP\000tAND\000tANDsp\000tASRri\000tASRrr\000"
- "tB\000tBIC\000tBKPT\000tBL\000tBLXi\000tBLXi_r9\000tBLXr\000tBLXr_r9\000"
- "tBLr9\000tBRIND\000tBR_JTr\000tBX\000tBX_RET\000tBX_RET_vararg\000tBXr9"
- "\000tBcc\000tBfar\000tCBNZ\000tCBZ\000tCMNz\000tCMPhir\000tCMPi8\000tCM"
- "Pr\000tCMPzhir\000tCMPzi8\000tCMPzr\000tEOR\000tInt_eh_sjlj_setjmp\000t"
- "LDM\000tLDR\000tLDRB\000tLDRBi\000tLDRH\000tLDRHi\000tLDRSB\000tLDRSH\000"
- "tLDRcp\000tLDRi\000tLDRpci\000tLDRpci_pic\000tLDRspi\000tLEApcrel\000tL"
- "EApcrelJT\000tLSLri\000tLSLrr\000tLSRri\000tLSRrr\000tMOVCCi\000tMOVCCr"
- "\000tMOVCCr_pseudo\000tMOVSr\000tMOVgpr2gpr\000tMOVgpr2tgpr\000tMOVi8\000"
- "tMOVr\000tMOVtgpr2gpr\000tMUL\000tMVN\000tORR\000tPICADD\000tPOP\000tPO"
- "P_RET\000tPUSH\000tREV\000tREV16\000tREVSH\000tROR\000tRSB\000tRestore\000"
- "tSBC\000tSTM\000tSTR\000tSTRB\000tSTRBi\000tSTRH\000tSTRHi\000tSTRi\000"
- "tSTRspi\000tSUBi3\000tSUBi8\000tSUBrr\000tSUBspi\000tSUBspi_\000tSXTB\000"
- "tSXTH\000tSpill\000tTPsoft\000tTST\000tUXTB\000tUXTH\000";
+ "P_I32\000ATOMIC_SWAP_I8\000B\000BFC\000BFI\000BICri\000BICrr\000BICrs\000"
+ "BKPT\000BL\000BLX\000BLXr9\000BL_pred\000BLr9\000BLr9_pred\000BRIND\000"
+ "BR_JTadd\000BR_JTm\000BR_JTr\000BX\000BXJ\000BX_RET\000BXr9\000Bcc\000C"
+ "DP\000CDP2\000CLREX\000CLZ\000CMNzri\000CMNzrr\000CMNzrs\000CMPri\000CM"
+ "Prr\000CMPrs\000CMPzri\000CMPzrr\000CMPzrs\000CONSTPOOL_ENTRY\000CPS\000"
+ "DBG\000DMBish\000DMBishst\000DMBnsh\000DMBnshst\000DMBosh\000DMBoshst\000"
+ "DMBst\000DSBish\000DSBishst\000DSBnsh\000DSBnshst\000DSBosh\000DSBoshst"
+ "\000DSBst\000EORri\000EORrr\000EORrs\000FCONSTD\000FCONSTS\000FMSTAT\000"
+ "ISBsy\000Int_MemBarrierV6\000Int_MemBarrierV7\000Int_SyncBarrierV6\000I"
+ "nt_SyncBarrierV7\000Int_eh_sjlj_setjmp\000LDC2L_OFFSET\000LDC2L_OPTION\000"
+ "LDC2L_POST\000LDC2L_PRE\000LDC2_OFFSET\000LDC2_OPTION\000LDC2_POST\000L"
+ "DC2_PRE\000LDCL_OFFSET\000LDCL_OPTION\000LDCL_POST\000LDCL_PRE\000LDC_O"
+ "FFSET\000LDC_OPTION\000LDC_POST\000LDC_PRE\000LDM\000LDM_RET\000LDR\000"
+ "LDRB\000LDRBT\000LDRB_POST\000LDRB_PRE\000LDRD\000LDRD_POST\000LDRD_PRE"
+ "\000LDREX\000LDREXB\000LDREXD\000LDREXH\000LDRH\000LDRHT\000LDRH_POST\000"
+ "LDRH_PRE\000LDRSB\000LDRSBT\000LDRSB_POST\000LDRSB_PRE\000LDRSH\000LDRS"
+ "HT\000LDRSH_POST\000LDRSH_PRE\000LDRT\000LDR_POST\000LDR_PRE\000LDRcp\000"
+ "LEApcrel\000LEApcrelJT\000MCR\000MCR2\000MCRR\000MCRR2\000MLA\000MLS\000"
+ "MOVCCi\000MOVCCr\000MOVCCs\000MOVTi16\000MOVi\000MOVi16\000MOVi2pieces\000"
+ "MOVi32imm\000MOVr\000MOVrx\000MOVs\000MOVsra_flag\000MOVsrl_flag\000MRC"
+ "\000MRC2\000MRRC\000MRRC2\000MRS\000MRSsys\000MSR\000MSRi\000MSRsys\000"
+ "MSRsysi\000MUL\000MVNi\000MVNr\000MVNs\000NOP\000ORRri\000ORRrr\000ORRr"
+ "s\000PICADD\000PICLDR\000PICLDRB\000PICLDRH\000PICLDRSB\000PICLDRSH\000"
+ "PICSTR\000PICSTRB\000PICSTRH\000PKHBT\000PKHTB\000PLDWi\000PLDWr\000PLD"
+ "i\000PLDr\000PLIi\000PLIr\000QADD\000QADD16\000QADD8\000QASX\000QDADD\000"
+ "QDSUB\000QSAX\000QSUB\000QSUB16\000QSUB8\000RBIT\000REV\000REV16\000REV"
+ "SH\000RFE\000RFEW\000RSBSri\000RSBSrs\000RSBri\000RSBrs\000RSCSri\000RS"
+ "CSrs\000RSCri\000RSCrs\000SADD16\000SADD8\000SASX\000SBCSSri\000SBCSSrr"
+ "\000SBCSSrs\000SBCri\000SBCrr\000SBCrs\000SBFX\000SEL\000SETENDBE\000SE"
+ "TENDLE\000SEV\000SHADD16\000SHADD8\000SHASX\000SHSAX\000SHSUB16\000SHSU"
+ "B8\000SMC\000SMLABB\000SMLABT\000SMLAD\000SMLADX\000SMLAL\000SMLALBB\000"
+ "SMLALBT\000SMLALD\000SMLALDX\000SMLALTB\000SMLALTT\000SMLATB\000SMLATT\000"
+ "SMLAWB\000SMLAWT\000SMLSD\000SMLSDX\000SMLSLD\000SMLSLDX\000SMMLA\000SM"
+ "MLAR\000SMMLS\000SMMLSR\000SMMUL\000SMMULR\000SMUAD\000SMUADX\000SMULBB"
+ "\000SMULBT\000SMULL\000SMULTB\000SMULTT\000SMULWB\000SMULWT\000SMUSD\000"
+ "SMUSDX\000SRS\000SRSW\000SSAT16\000SSATasr\000SSATlsl\000SSAX\000SSUB16"
+ "\000SSUB8\000STC2L_OFFSET\000STC2L_OPTION\000STC2L_POST\000STC2L_PRE\000"
+ "STC2_OFFSET\000STC2_OPTION\000STC2_POST\000STC2_PRE\000STCL_OFFSET\000S"
+ "TCL_OPTION\000STCL_POST\000STCL_PRE\000STC_OFFSET\000STC_OPTION\000STC_"
+ "POST\000STC_PRE\000STM\000STR\000STRB\000STRBT\000STRB_POST\000STRB_PRE"
+ "\000STRD\000STRD_POST\000STRD_PRE\000STREX\000STREXB\000STREXD\000STREX"
+ "H\000STRH\000STRHT\000STRH_POST\000STRH_PRE\000STRT\000STR_POST\000STR_"
+ "PRE\000SUBSri\000SUBSrr\000SUBSrs\000SUBri\000SUBrr\000SUBrs\000SVC\000"
+ "SWP\000SWPB\000SXTAB16rr\000SXTAB16rr_rot\000SXTABrr\000SXTABrr_rot\000"
+ "SXTAHrr\000SXTAHrr_rot\000SXTB16r\000SXTB16r_rot\000SXTBr\000SXTBr_rot\000"
+ "SXTHr\000SXTHr_rot\000TEQri\000TEQrr\000TEQrs\000TPsoft\000TRAP\000TSTr"
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+ "1i64\000VSHLuv2i32\000VSHLuv2i64\000VSHLuv4i16\000VSHLuv4i32\000VSHLuv8"
+ "i16\000VSHLuv8i8\000VSHRNv2i32\000VSHRNv4i16\000VSHRNv8i8\000VSHRsv16i8"
+ "\000VSHRsv1i64\000VSHRsv2i32\000VSHRsv2i64\000VSHRsv4i16\000VSHRsv4i32\000"
+ "VSHRsv8i16\000VSHRsv8i8\000VSHRuv16i8\000VSHRuv1i64\000VSHRuv2i32\000VS"
+ "HRuv2i64\000VSHRuv4i16\000VSHRuv4i32\000VSHRuv8i16\000VSHRuv8i8\000VSHT"
+ "OD\000VSHTOS\000VSITOD\000VSITOS\000VSLIv16i8\000VSLIv1i64\000VSLIv2i32"
+ "\000VSLIv2i64\000VSLIv4i16\000VSLIv4i32\000VSLIv8i16\000VSLIv8i8\000VSL"
+ "TOD\000VSLTOS\000VSQRTD\000VSQRTS\000VSRAsv16i8\000VSRAsv1i64\000VSRAsv"
+ "2i32\000VSRAsv2i64\000VSRAsv4i16\000VSRAsv4i32\000VSRAsv8i16\000VSRAsv8"
+ "i8\000VSRAuv16i8\000VSRAuv1i64\000VSRAuv2i32\000VSRAuv2i64\000VSRAuv4i1"
+ "6\000VSRAuv4i32\000VSRAuv8i16\000VSRAuv8i8\000VSRIv16i8\000VSRIv1i64\000"
+ "VSRIv2i32\000VSRIv2i64\000VSRIv4i16\000VSRIv4i32\000VSRIv8i16\000VSRIv8"
+ "i8\000VST1d16\000VST1d16Q\000VST1d16T\000VST1d32\000VST1d32Q\000VST1d32"
+ "T\000VST1d64\000VST1d8\000VST1d8Q\000VST1d8T\000VST1df\000VST1q16\000VS"
+ "T1q32\000VST1q64\000VST1q8\000VST1qf\000VST2LNd16\000VST2LNd32\000VST2L"
+ "Nd8\000VST2LNq16a\000VST2LNq16b\000VST2LNq32a\000VST2LNq32b\000VST2d16\000"
+ "VST2d16D\000VST2d32\000VST2d32D\000VST2d64\000VST2d8\000VST2d8D\000VST2"
+ "q16\000VST2q32\000VST2q8\000VST3LNd16\000VST3LNd32\000VST3LNd8\000VST3L"
+ "Nq16a\000VST3LNq16b\000VST3LNq32a\000VST3LNq32b\000VST3d16\000VST3d32\000"
+ "VST3d64\000VST3d8\000VST3q16a\000VST3q16b\000VST3q32a\000VST3q32b\000VS"
+ "T3q8a\000VST3q8b\000VST4LNd16\000VST4LNd32\000VST4LNd8\000VST4LNq16a\000"
+ "VST4LNq16b\000VST4LNq32a\000VST4LNq32b\000VST4d16\000VST4d32\000VST4d64"
+ "\000VST4d8\000VST4q16a\000VST4q16b\000VST4q32a\000VST4q32b\000VST4q8a\000"
+ "VST4q8b\000VSTMD\000VSTMS\000VSTRD\000VSTRQ\000VSTRS\000VSUBD\000VSUBHN"
+ "v2i32\000VSUBHNv4i16\000VSUBHNv8i8\000VSUBLsv2i64\000VSUBLsv4i32\000VSU"
+ "BLsv8i16\000VSUBLuv2i64\000VSUBLuv4i32\000VSUBLuv8i16\000VSUBS\000VSUBW"
+ "sv2i64\000VSUBWsv4i32\000VSUBWsv8i16\000VSUBWuv2i64\000VSUBWuv4i32\000V"
+ "SUBWuv8i16\000VSUBfd\000VSUBfd_sfp\000VSUBfq\000VSUBv16i8\000VSUBv1i64\000"
+ "VSUBv2i32\000VSUBv2i64\000VSUBv4i16\000VSUBv4i32\000VSUBv8i16\000VSUBv8"
+ "i8\000VSWPd\000VSWPq\000VTBL1\000VTBL2\000VTBL3\000VTBL4\000VTBX1\000VT"
+ "BX2\000VTBX3\000VTBX4\000VTOSHD\000VTOSHS\000VTOSIRD\000VTOSIRS\000VTOS"
+ "IZD\000VTOSIZS\000VTOSLD\000VTOSLS\000VTOUHD\000VTOUHS\000VTOUIRD\000VT"
+ "OUIRS\000VTOUIZD\000VTOUIZS\000VTOULD\000VTOULS\000VTRNd16\000VTRNd32\000"
+ "VTRNd8\000VTRNq16\000VTRNq32\000VTRNq8\000VTSTv16i8\000VTSTv2i32\000VTS"
+ "Tv4i16\000VTSTv4i32\000VTSTv8i16\000VTSTv8i8\000VUHTOD\000VUHTOS\000VUI"
+ "TOD\000VUITOS\000VULTOD\000VULTOS\000VUZPd16\000VUZPd32\000VUZPd8\000VU"
+ "ZPq16\000VUZPq32\000VUZPq8\000VZIPd16\000VZIPd32\000VZIPd8\000VZIPq16\000"
+ "VZIPq32\000VZIPq8\000WFE\000WFI\000YIELD\000t2ADCSri\000t2ADCSrr\000t2A"
+ "DCSrs\000t2ADCri\000t2ADCrr\000t2ADCrs\000t2ADDSri\000t2ADDSrr\000t2ADD"
+ "Srs\000t2ADDrSPi\000t2ADDrSPi12\000t2ADDrSPs\000t2ADDri\000t2ADDri12\000"
+ "t2ADDrr\000t2ADDrs\000t2ANDri\000t2ANDrr\000t2ANDrs\000t2ASRri\000t2ASR"
+ "rr\000t2B\000t2BFC\000t2BFI\000t2BICri\000t2BICrr\000t2BICrs\000t2BR_JT"
+ "\000t2BXJ\000t2Bcc\000t2CLREX\000t2CLZ\000t2CMNzri\000t2CMNzrr\000t2CMN"
+ "zrs\000t2CMPri\000t2CMPrr\000t2CMPrs\000t2CMPzri\000t2CMPzrr\000t2CMPzr"
+ "s\000t2CPS\000t2DBG\000t2DMBish\000t2DMBishst\000t2DMBnsh\000t2DMBnshst"
+ "\000t2DMBosh\000t2DMBoshst\000t2DMBst\000t2DSBish\000t2DSBishst\000t2DS"
+ "Bnsh\000t2DSBnshst\000t2DSBosh\000t2DSBoshst\000t2DSBst\000t2EORri\000t"
+ "2EORrr\000t2EORrs\000t2ISBsy\000t2IT\000t2Int_MemBarrierV7\000t2Int_Syn"
+ "cBarrierV7\000t2Int_eh_sjlj_setjmp\000t2LDM\000t2LDM_RET\000t2LDRBT\000"
+ "t2LDRB_POST\000t2LDRB_PRE\000t2LDRBi12\000t2LDRBi8\000t2LDRBpci\000t2LD"
+ "RBs\000t2LDRDi8\000t2LDRDpci\000t2LDREX\000t2LDREXB\000t2LDREXD\000t2LD"
+ "REXH\000t2LDRHT\000t2LDRH_POST\000t2LDRH_PRE\000t2LDRHi12\000t2LDRHi8\000"
+ "t2LDRHpci\000t2LDRHs\000t2LDRSBT\000t2LDRSB_POST\000t2LDRSB_PRE\000t2LD"
+ "RSBi12\000t2LDRSBi8\000t2LDRSBpci\000t2LDRSBs\000t2LDRSHT\000t2LDRSH_PO"
+ "ST\000t2LDRSH_PRE\000t2LDRSHi12\000t2LDRSHi8\000t2LDRSHpci\000t2LDRSHs\000"
+ "t2LDRT\000t2LDR_POST\000t2LDR_PRE\000t2LDRi12\000t2LDRi8\000t2LDRpci\000"
+ "t2LDRpci_pic\000t2LDRs\000t2LEApcrel\000t2LEApcrelJT\000t2LSLri\000t2LS"
+ "Lrr\000t2LSRri\000t2LSRrr\000t2MLA\000t2MLS\000t2MOVCCasr\000t2MOVCCi\000"
+ "t2MOVCClsl\000t2MOVCClsr\000t2MOVCCr\000t2MOVCCror\000t2MOVTi16\000t2MO"
+ "Vi\000t2MOVi16\000t2MOVi32imm\000t2MOVr\000t2MOVrx\000t2MOVsra_flag\000"
+ "t2MOVsrl_flag\000t2MRS\000t2MRSsys\000t2MSR\000t2MSRsys\000t2MUL\000t2M"
+ "VNi\000t2MVNr\000t2MVNs\000t2NOP\000t2ORNri\000t2ORNrr\000t2ORNrs\000t2"
+ "ORRri\000t2ORRrr\000t2ORRrs\000t2PKHBT\000t2PKHTB\000t2PLDWi12\000t2PLD"
+ "Wi8\000t2PLDWpci\000t2PLDWr\000t2PLDWs\000t2PLDi12\000t2PLDi8\000t2PLDp"
+ "ci\000t2PLDr\000t2PLDs\000t2PLIi12\000t2PLIi8\000t2PLIpci\000t2PLIr\000"
+ "t2PLIs\000t2QADD\000t2QADD16\000t2QADD8\000t2QASX\000t2QDADD\000t2QDSUB"
+ "\000t2QSAX\000t2QSUB\000t2QSUB16\000t2QSUB8\000t2RBIT\000t2REV\000t2REV"
+ "16\000t2REVSH\000t2RFEDB\000t2RFEDBW\000t2RFEIA\000t2RFEIAW\000t2RORri\000"
+ "t2RORrr\000t2RSBSri\000t2RSBSrs\000t2RSBri\000t2RSBrs\000t2SADD16\000t2"
+ "SADD8\000t2SASX\000t2SBCSri\000t2SBCSrr\000t2SBCSrs\000t2SBCri\000t2SBC"
+ "rr\000t2SBCrs\000t2SBFX\000t2SDIV\000t2SEL\000t2SEV\000t2SHADD16\000t2S"
+ "HADD8\000t2SHASX\000t2SHSAX\000t2SHSUB16\000t2SHSUB8\000t2SMC\000t2SMLA"
+ "BB\000t2SMLABT\000t2SMLAD\000t2SMLADX\000t2SMLAL\000t2SMLALBB\000t2SMLA"
+ "LBT\000t2SMLALD\000t2SMLALDX\000t2SMLALTB\000t2SMLALTT\000t2SMLATB\000t"
+ "2SMLATT\000t2SMLAWB\000t2SMLAWT\000t2SMLSD\000t2SMLSDX\000t2SMLSLD\000t"
+ "2SMLSLDX\000t2SMMLA\000t2SMMLAR\000t2SMMLS\000t2SMMLSR\000t2SMMUL\000t2"
+ "SMMULR\000t2SMUAD\000t2SMUADX\000t2SMULBB\000t2SMULBT\000t2SMULL\000t2S"
+ "MULTB\000t2SMULTT\000t2SMULWB\000t2SMULWT\000t2SMUSD\000t2SMUSDX\000t2S"
+ "RSDB\000t2SRSDBW\000t2SRSIA\000t2SRSIAW\000t2SSAT16\000t2SSATasr\000t2S"
+ "SATlsl\000t2SSAX\000t2SSUB16\000t2SSUB8\000t2STM\000t2STRBT\000t2STRB_P"
+ "OST\000t2STRB_PRE\000t2STRBi12\000t2STRBi8\000t2STRBs\000t2STRDi8\000t2"
+ "STREX\000t2STREXB\000t2STREXD\000t2STREXH\000t2STRHT\000t2STRH_POST\000"
+ "t2STRH_PRE\000t2STRHi12\000t2STRHi8\000t2STRHs\000t2STRT\000t2STR_POST\000"
+ "t2STR_PRE\000t2STRi12\000t2STRi8\000t2STRs\000t2SUBSri\000t2SUBSrr\000t"
+ "2SUBSrs\000t2SUBrSPi\000t2SUBrSPi12\000t2SUBrSPi12_\000t2SUBrSPi_\000t2"
+ "SUBrSPs\000t2SUBrSPs_\000t2SUBri\000t2SUBri12\000t2SUBrr\000t2SUBrs\000"
+ "t2SXTAB16rr\000t2SXTAB16rr_rot\000t2SXTABrr\000t2SXTABrr_rot\000t2SXTAH"
+ "rr\000t2SXTAHrr_rot\000t2SXTB16r\000t2SXTB16r_rot\000t2SXTBr\000t2SXTBr"
+ "_rot\000t2SXTHr\000t2SXTHr_rot\000t2TBB\000t2TBBgen\000t2TBH\000t2TBHge"
+ "n\000t2TEQri\000t2TEQrr\000t2TEQrs\000t2TPsoft\000t2TSTri\000t2TSTrr\000"
+ "t2TSTrs\000t2UADD16\000t2UADD8\000t2UASX\000t2UBFX\000t2UDIV\000t2UHADD"
+ "16\000t2UHADD8\000t2UHASX\000t2UHSAX\000t2UHSUB16\000t2UHSUB8\000t2UMAA"
+ "L\000t2UMLAL\000t2UMULL\000t2UQADD16\000t2UQADD8\000t2UQASX\000t2UQSAX\000"
+ "t2UQSUB16\000t2UQSUB8\000t2USAD8\000t2USADA8\000t2USAT16\000t2USATasr\000"
+ "t2USATlsl\000t2USAX\000t2USUB16\000t2USUB8\000t2UXTAB16rr\000t2UXTAB16r"
+ "r_rot\000t2UXTABrr\000t2UXTABrr_rot\000t2UXTAHrr\000t2UXTAHrr_rot\000t2"
+ "UXTB16r\000t2UXTB16r_rot\000t2UXTBr\000t2UXTBr_rot\000t2UXTHr\000t2UXTH"
+ "r_rot\000t2WFE\000t2WFI\000t2YIELD\000tADC\000tADDhirr\000tADDi3\000tAD"
+ "Di8\000tADDrPCi\000tADDrSP\000tADDrSPi\000tADDrr\000tADDspi\000tADDspr\000"
+ "tADDspr_\000tADJCALLSTACKDOWN\000tADJCALLSTACKUP\000tAND\000tANDsp\000t"
+ "ASRri\000tASRrr\000tB\000tBIC\000tBKPT\000tBL\000tBLXi\000tBLXi_r9\000t"
+ "BLXr\000tBLXr_r9\000tBLr9\000tBRIND\000tBR_JTr\000tBX\000tBX_RET\000tBX"
+ "_RET_vararg\000tBXr9\000tBcc\000tBfar\000tCBNZ\000tCBZ\000tCMNz\000tCMP"
+ "hir\000tCMPi8\000tCMPr\000tCMPzhir\000tCMPzi8\000tCMPzr\000tCPS\000tEOR"
+ "\000tInt_eh_sjlj_setjmp\000tLDM\000tLDR\000tLDRB\000tLDRBi\000tLDRH\000"
+ "tLDRHi\000tLDRSB\000tLDRSH\000tLDRcp\000tLDRi\000tLDRpci\000tLDRpci_pic"
+ "\000tLDRspi\000tLEApcrel\000tLEApcrelJT\000tLSLri\000tLSLrr\000tLSRri\000"
+ "tLSRrr\000tMOVCCi\000tMOVCCr\000tMOVCCr_pseudo\000tMOVSr\000tMOVgpr2gpr"
+ "\000tMOVgpr2tgpr\000tMOVi8\000tMOVr\000tMOVtgpr2gpr\000tMUL\000tMVN\000"
+ "tNOP\000tORR\000tPICADD\000tPOP\000tPOP_RET\000tPUSH\000tREV\000tREV16\000"
+ "tREVSH\000tROR\000tRSB\000tRestore\000tSBC\000tSETENDBE\000tSETENDLE\000"
+ "tSEV\000tSTM\000tSTR\000tSTRB\000tSTRBi\000tSTRH\000tSTRHi\000tSTRi\000"
+ "tSTRspi\000tSUBi3\000tSUBi8\000tSUBrr\000tSUBspi\000tSUBspi_\000tSVC\000"
+ "tSXTB\000tSXTH\000tSpill\000tTPsoft\000tTRAP\000tTST\000tUXTB\000tUXTH\000"
+ "tWFE\000tWFI\000tYIELD\000";
return Strs+InstAsmOffset[Opcode];
}
diff --git a/libclamav/c++/ARMGenCodeEmitter.inc b/libclamav/c++/ARMGenCodeEmitter.inc
index 8ba99a8..616f024 100644
--- a/libclamav/c++/ARMGenCodeEmitter.inc
+++ b/libclamav/c++/ARMGenCodeEmitter.inc
@@ -63,6 +63,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
0U, // ATOMIC_SWAP_I8
167772160U, // B
130023455U, // BFC
+ 130023440U, // BFI
62914560U, // BICri
29360128U, // BICrr
29360128U, // BICrs
@@ -84,6 +85,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
167772160U, // Bcc
234881024U, // CDP
4261412864U, // CDP2
+ 4117757968U, // CLREX
24055568U, // CLZ
57671680U, // CMNzri
24117248U, // CMNzrr
@@ -97,17 +99,48 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
0U, // CONSTPOOL_ENTRY
4043309056U, // CPS
52429040U, // DBG
+ 4117758043U, // DMBish
+ 4117758042U, // DMBishst
+ 4117758039U, // DMBnsh
+ 4117758038U, // DMBnshst
+ 4117758035U, // DMBosh
+ 4117758034U, // DMBoshst
+ 4117758046U, // DMBst
+ 4117758027U, // DSBish
+ 4117758026U, // DSBishst
+ 4117758023U, // DSBnsh
+ 4117758022U, // DSBnshst
+ 4117758019U, // DSBosh
+ 4117758018U, // DSBoshst
+ 4117758030U, // DSBst
35651584U, // EORri
2097152U, // EORrr
2097152U, // EORrs
246418176U, // FCONSTD
246417920U, // FCONSTS
250739216U, // FMSTAT
+ 4117758063U, // ISBsy
0U, // Int_MemBarrierV6
4118802527U, // Int_MemBarrierV7
0U, // Int_SyncBarrierV6
4118802511U, // Int_SyncBarrierV7
0U, // Int_eh_sjlj_setjmp
+ 4249878528U, // LDC2L_OFFSET
+ 4241489920U, // LDC2L_OPTION
+ 4235198464U, // LDC2L_POST
+ 4251975680U, // LDC2L_PRE
+ 4245684224U, // LDC2_OFFSET
+ 4237295616U, // LDC2_OPTION
+ 4231004160U, // LDC2_POST
+ 4247781376U, // LDC2_PRE
+ 223346688U, // LDCL_OFFSET
+ 214958080U, // LDCL_OPTION
+ 208666624U, // LDCL_POST
+ 225443840U, // LDCL_PRE
+ 219152384U, // LDC_OFFSET
+ 210763776U, // LDC_OPTION
+ 204472320U, // LDC_POST
+ 221249536U, // LDC_PRE
135266304U, // LDM
135266304U, // LDM_RET
84934656U, // LDR
@@ -116,18 +149,23 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
72351744U, // LDRB_POST
91226112U, // LDRB_PRE
16777424U, // LDRD
+ 208U, // LDRD_POST
+ 18874576U, // LDRD_PRE
26218399U, // LDREX
30412703U, // LDREXB
28315551U, // LDREXD
32509855U, // LDREXH
17825968U, // LDRH
- 3145904U, // LDRH_POST
+ 3145904U, // LDRHT
+ 1048752U, // LDRH_POST
19923120U, // LDRH_PRE
17826000U, // LDRSB
- 3145936U, // LDRSB_POST
+ 3145936U, // LDRSBT
+ 1048784U, // LDRSB_POST
19923152U, // LDRSB_PRE
17826032U, // LDRSH
- 3145968U, // LDRSH_POST
+ 3145968U, // LDRSHT
+ 1048816U, // LDRSH_POST
19923184U, // LDRSH_PRE
70254592U, // LDRT
68157440U, // LDR_POST
@@ -161,7 +199,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
16777216U, // MRS
20971520U, // MRSsys
18874368U, // MSR
+ 52428800U, // MSRi
23068672U, // MSRsys
+ 56623104U, // MSRsysi
144U, // MUL
65011712U, // MVNi
31457280U, // MVNr
@@ -181,6 +221,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
16777392U, // PICSTRH
109051920U, // PKHBT
109051984U, // PKHTB
+ 4111466496U, // PLDWi
+ 4145020928U, // PLDWr
+ 4115660800U, // PLDi
+ 4149215232U, // PLDr
+ 4098883584U, // PLIi
+ 4132438016U, // PLIr
16777296U, // QADD
102760464U, // QADD16
102760592U, // QADD8
@@ -195,6 +241,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
113184560U, // REV
113184688U, // REV16
117378992U, // REVSH
+ 4161798144U, // RFE
+ 4163895296U, // RFEW
40894464U, // RSBSri
7340032U, // RSBSrs
39845888U, // RSBri
@@ -203,6 +251,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
15728640U, // RSCSrs
48234496U, // RSCri
14680064U, // RSCrs
+ 101711888U, // SADD16
+ 101712016U, // SADD8
+ 101711920U, // SASX
47185920U, // SBCSSri
13631488U, // SBCSSrr
13631488U, // SBCSSrs
@@ -210,23 +261,44 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
12582912U, // SBCrr
12582912U, // SBCrs
127926352U, // SBFX
+ 109052080U, // SEL
4043375104U, // SETENDBE
4043374592U, // SETENDLE
52428804U, // SEV
+ 103809040U, // SHADD16
+ 103809168U, // SHADD8
+ 103809072U, // SHASX
+ 103809104U, // SHSAX
+ 103809136U, // SHSUB16
+ 103809264U, // SHSUB8
+ 23068784U, // SMC
16777344U, // SMLABB
16777408U, // SMLABT
+ 117440528U, // SMLAD
+ 117440560U, // SMLADX
14680208U, // SMLAL
20971648U, // SMLALBB
20971712U, // SMLALBT
+ 121634832U, // SMLALD
+ 121634864U, // SMLALDX
20971680U, // SMLALTB
20971744U, // SMLALTT
16777376U, // SMLATB
16777440U, // SMLATT
18874496U, // SMLAWB
18874560U, // SMLAWT
+ 117440592U, // SMLSD
+ 117440624U, // SMLSDX
+ 121634896U, // SMLSLD
+ 121634928U, // SMLSLDX
122683408U, // SMMLA
+ 122683440U, // SMMLAR
122683600U, // SMMLS
+ 122683632U, // SMMLSR
122744848U, // SMMUL
+ 122744880U, // SMMULR
+ 117501968U, // SMUAD
+ 117502000U, // SMUADX
23068800U, // SMULBB
23068864U, // SMULBT
12583056U, // SMULL
@@ -234,6 +306,32 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
23068896U, // SMULTT
18874528U, // SMULWB
18874592U, // SMULWT
+ 117502032U, // SMUSD
+ 117502064U, // SMUSDX
+ 4164943872U, // SRS
+ 4167041024U, // SRSW
+ 111149104U, // SSAT16
+ 111149136U, // SSATasr
+ 111149072U, // SSATlsl
+ 101711952U, // SSAX
+ 101711984U, // SSUB16
+ 101712112U, // SSUB8
+ 4248829952U, // STC2L_OFFSET
+ 4240441344U, // STC2L_OPTION
+ 4234149888U, // STC2L_POST
+ 4250927104U, // STC2L_PRE
+ 4244635648U, // STC2_OFFSET
+ 4236247040U, // STC2_OPTION
+ 4229955584U, // STC2_POST
+ 4246732800U, // STC2_PRE
+ 222298112U, // STCL_OFFSET
+ 213909504U, // STCL_OPTION
+ 207618048U, // STCL_POST
+ 224395264U, // STCL_PRE
+ 218103808U, // STC_OFFSET
+ 209715200U, // STC_OPTION
+ 203423744U, // STC_POST
+ 220200960U, // STC_PRE
134217728U, // STM
83886080U, // STR
88080384U, // STRB
@@ -241,12 +339,15 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
71303168U, // STRB_POST
90177536U, // STRB_PRE
16777456U, // STRD
+ 240U, // STRD_POST
+ 18874608U, // STRD_PRE
25169808U, // STREX
29364112U, // STREXB
27266960U, // STREXD
31461264U, // STREXH
16777392U, // STRH
- 2097328U, // STRH_POST
+ 2097328U, // STRHT
+ 176U, // STRH_POST
18874544U, // STRH_PRE
69206016U, // STRT
67108864U, // STR_POST
@@ -260,10 +361,14 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
251658240U, // SVC
16777360U, // SWP
20971664U, // SWPB
+ 109052016U, // SXTAB16rr
+ 109052016U, // SXTAB16rr_rot
111149168U, // SXTABrr
111149168U, // SXTABrr_rot
112197744U, // SXTAHrr
112197744U, // SXTAHrr_rot
+ 110035056U, // SXTB16r
+ 110035056U, // SXTB16r_rot
112132208U, // SXTBr
112132208U, // SXTBr_rot
113180784U, // SXTHr
@@ -276,7 +381,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
51380224U, // TSTri
17825792U, // TSTrr
17825792U, // TSTrs
+ 105906192U, // UADD16
+ 105906320U, // UADD8
+ 105906224U, // UASX
132120656U, // UBFX
+ 108003344U, // UHADD16
+ 108003472U, // UHADD8
+ 108003376U, // UHASX
+ 108003408U, // UHSAX
+ 108003440U, // UHSUB16
+ 108003568U, // UHSUB8
4194448U, // UMAAL
10485904U, // UMLAL
8388752U, // UMULL
@@ -286,6 +400,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
106954832U, // UQSAX
106954864U, // UQSUB16
106954992U, // UQSUB8
+ 125890576U, // USAD8
+ 125829136U, // USADA8
+ 115343408U, // USAT16
+ 115343440U, // USATasr
+ 115343376U, // USATlsl
+ 105906256U, // USAX
+ 105906288U, // USUB16
+ 105906416U, // USUB8
+ 113246320U, // UXTAB16rr
+ 113246320U, // UXTAB16rr_rot
115343472U, // UXTABrr
115343472U, // UXTABrr_rot
116392048U, // UXTAHrr
@@ -395,6 +519,14 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4078962768U, // VCEQv4i32
4077914192U, // VCEQv8i16
4076865552U, // VCEQv8i8
+ 4088463680U, // VCEQzv16i8
+ 4088988928U, // VCEQzv2f32
+ 4088987904U, // VCEQzv2i32
+ 4088988992U, // VCEQzv4f32
+ 4088725760U, // VCEQzv4i16
+ 4088987968U, // VCEQzv4i32
+ 4088725824U, // VCEQzv8i16
+ 4088463616U, // VCEQzv8i8
4076867072U, // VCGEfd
4076867136U, // VCGEfq
4060087120U, // VCGEsv16i8
@@ -409,6 +541,14 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4078961488U, // VCGEuv4i32
4077912912U, // VCGEuv8i16
4076864272U, // VCGEuv8i8
+ 4088463552U, // VCGEzv16i8
+ 4088988800U, // VCGEzv2f32
+ 4088987776U, // VCGEzv2i32
+ 4088988864U, // VCGEzv4f32
+ 4088725632U, // VCGEzv4i16
+ 4088987840U, // VCGEzv4i32
+ 4088725696U, // VCGEzv8i16
+ 4088463488U, // VCGEzv8i8
4078964224U, // VCGTfd
4078964288U, // VCGTfq
4060087104U, // VCGTsv16i8
@@ -423,12 +563,36 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4078961472U, // VCGTuv4i32
4077912896U, // VCGTuv8i16
4076864256U, // VCGTuv8i8
+ 4088463424U, // VCGTzv16i8
+ 4088988672U, // VCGTzv2f32
+ 4088987648U, // VCGTzv2i32
+ 4088988736U, // VCGTzv4f32
+ 4088725504U, // VCGTzv4i16
+ 4088987712U, // VCGTzv4i32
+ 4088725568U, // VCGTzv8i16
+ 4088463360U, // VCGTzv8i8
+ 4088463808U, // VCLEzv16i8
+ 4088989056U, // VCLEzv2f32
+ 4088988032U, // VCLEzv2i32
+ 4088989120U, // VCLEzv4f32
+ 4088725888U, // VCLEzv4i16
+ 4088988096U, // VCLEzv4i32
+ 4088725952U, // VCLEzv8i16
+ 4088463744U, // VCLEzv8i8
4088398912U, // VCLSv16i8
4088923136U, // VCLSv2i32
4088660992U, // VCLSv4i16
4088923200U, // VCLSv4i32
4088661056U, // VCLSv8i16
4088398848U, // VCLSv8i8
+ 4088463936U, // VCLTzv16i8
+ 4088989184U, // VCLTzv2f32
+ 4088988160U, // VCLTzv2i32
+ 4088989248U, // VCLTzv4f32
+ 4088726016U, // VCLTzv4i16
+ 4088988224U, // VCLTzv4i32
+ 4088726080U, // VCLTzv8i16
+ 4088463872U, // VCLTzv8i8
4088399040U, // VCLZv16i8
4088923264U, // VCLZv2i32
4088661120U, // VCLZv4i16
@@ -531,9 +695,15 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4077912640U, // VHSUBuv8i16
4076864000U, // VHSUBuv8i8
4095739712U, // VLD1d16
+ 4095738432U, // VLD1d16Q
+ 4095739456U, // VLD1d16T
4095739776U, // VLD1d32
+ 4095738496U, // VLD1d32Q
+ 4095739520U, // VLD1d32T
4095739840U, // VLD1d64
4095739648U, // VLD1d8
+ 4095738368U, // VLD1d8Q
+ 4095739392U, // VLD1d8T
4095739776U, // VLD1df
4095740480U, // VLD1q16
4095740544U, // VLD1q32
@@ -548,9 +718,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4104128832U, // VLD2LNq32a
4104128832U, // VLD2LNq32b
4095739968U, // VLD2d16
+ 4095740224U, // VLD2d16D
4095740032U, // VLD2d32
+ 4095740288U, // VLD2d32D
4095740608U, // VLD2d64
4095739904U, // VLD2d8
+ 4095740160U, // VLD2d8D
4095738688U, // VLD2q16
4095738752U, // VLD2q32
4095738624U, // VLD2q8
@@ -594,6 +767,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
210766592U, // VLDRQ
219154944U, // VLDRS
4060090112U, // VMAXfd
+ 4060090112U, // VMAXfd_sfp
4060090176U, // VMAXfq
4060087872U, // VMAXsv16i8
4062184960U, // VMAXsv2i32
@@ -608,6 +782,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4077913664U, // VMAXuv8i16
4076865024U, // VMAXuv8i8
4062187264U, // VMINfd
+ 4060090112U, // VMINfd_sfp
4062187328U, // VMINfq
4060087888U, // VMINsv16i8
4062184976U, // VMINsv2i32
@@ -740,9 +915,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
246483776U, // VNEGDcc
246483520U, // VNEGS
246483520U, // VNEGScc
- 4088989568U, // VNEGf32d
- 4088989568U, // VNEGf32d_sfp
4088989632U, // VNEGf32q
+ 4088989568U, // VNEGfd
+ 4088989568U, // VNEGfd_sfp
4088726400U, // VNEGs16d
4088726464U, // VNEGs16q
4088988544U, // VNEGs32d
@@ -1147,9 +1322,15 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4086301776U, // VSRIv8i16
4085777424U, // VSRIv8i8
4093642560U, // VST1d16
+ 4093641280U, // VST1d16Q
+ 4093642304U, // VST1d16T
4093642624U, // VST1d32
+ 4093641344U, // VST1d32Q
+ 4093642368U, // VST1d32T
4093642688U, // VST1d64
4093642496U, // VST1d8
+ 4093641216U, // VST1d8Q
+ 4093642240U, // VST1d8T
4093642624U, // VST1df
4093643328U, // VST1q16
4093643392U, // VST1q32
@@ -1164,9 +1345,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4102031680U, // VST2LNq32a
4102031680U, // VST2LNq32b
4093642816U, // VST2d16
+ 4093643072U, // VST2d16D
4093642880U, // VST2d32
+ 4093643136U, // VST2d32D
4093643456U, // VST2d64
4093642752U, // VST2d8
+ 4093643008U, // VST2d8D
4093641536U, // VST2q16
4093641600U, // VST2q32
4093641472U, // VST2q8
@@ -1237,6 +1421,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4078962752U, // VSUBv4i32
4077914176U, // VSUBv8i16
4076865536U, // VSUBv8i8
+ 4088528896U, // VSWPd
+ 4088528960U, // VSWPq
4088399872U, // VTBL1
4088400128U, // VTBL2
4088400384U, // VTBL3
@@ -1322,7 +1508,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
3927965696U, // t2BICrr
3927965696U, // t2BICrs
3931049728U, // t2BR_JT
+ 4089479168U, // t2BXJ
4026564608U, // t2Bcc
+ 4088430624U, // t2CLREX
4205899904U, // t2CLZ
4044361472U, // t2CMNzri
3943698176U, // t2CMNzrr
@@ -1333,15 +1521,33 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4054847232U, // t2CMPzri
3954183936U, // t2CMPzrr
3954183936U, // t2CMPzrs
+ 4087382016U, // t2CPS
+ 4087382256U, // t2DBG
+ 4088430683U, // t2DMBish
+ 4088430682U, // t2DMBishst
+ 4088430679U, // t2DMBnsh
+ 4088430678U, // t2DMBnshst
+ 4088430675U, // t2DMBosh
+ 4088430674U, // t2DMBoshst
+ 4088430686U, // t2DMBst
+ 4088430667U, // t2DSBish
+ 4088430666U, // t2DSBishst
+ 4088430663U, // t2DSBnsh
+ 4088430662U, // t2DSBnshst
+ 4088430659U, // t2DSBosh
+ 4088430658U, // t2DSBoshst
+ 4088430670U, // t2DSBst
4034920448U, // t2EORri
3934257152U, // t2EORrr
3934257152U, // t2EORrs
+ 4088430703U, // t2ISBsy
48896U, // t2IT
4089417567U, // t2Int_MemBarrierV7
4089417551U, // t2Int_SyncBarrierV7
0U, // t2Int_eh_sjlj_setjmp
3893362688U, // t2LDM
3893362688U, // t2LDM_RET
+ 4161801728U, // t2LDRBT
4161800448U, // t2LDRB_POST
4161801472U, // t2LDRB_PRE
4170186752U, // t2LDRBi12
@@ -1354,24 +1560,28 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
3905949519U, // t2LDREXB
3905945727U, // t2LDREXD
3905949535U, // t2LDREXH
+ 4163898880U, // t2LDRHT
4163897600U, // t2LDRH_POST
4163898624U, // t2LDRH_PRE
4172283904U, // t2LDRHi12
4163898368U, // t2LDRHi8
4164878336U, // t2LDRHpci
4163895296U, // t2LDRHs
+ 4178578944U, // t2LDRSBT
4178577664U, // t2LDRSB_POST
4178578688U, // t2LDRSB_PRE
4186963968U, // t2LDRSBi12
4178578432U, // t2LDRSBi8
4179558400U, // t2LDRSBpci
4178575360U, // t2LDRSBs
+ 4180676096U, // t2LDRSHT
4180674816U, // t2LDRSH_POST
4180675840U, // t2LDRSH_PRE
4189061120U, // t2LDRSHi12
4180675584U, // t2LDRSHi8
4181655552U, // t2LDRSHpci
4180672512U, // t2LDRSHs
+ 4165996032U, // t2LDRT
4165994752U, // t2LDR_POST
4165995776U, // t2LDR_PRE
4174381056U, // t2LDRi12
@@ -1401,10 +1611,15 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
3931045936U, // t2MOVrx
3932094560U, // t2MOVsra_flag
3932094544U, // t2MOVsrl_flag
+ 4091576320U, // t2MRS
+ 4092624896U, // t2MRSsys
+ 4085284864U, // t2MSR
+ 4086333440U, // t2MSRsys
4211142656U, // t2MUL
4033806336U, // t2MVNi
3933143040U, // t2MVNr
3933143040U, // t2MVNs
+ 4087382016U, // t2NOP
4032823296U, // t2ORNri
3932160000U, // t2ORNrr
3932160000U, // t2ORNrs
@@ -1413,16 +1628,48 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
3930062848U, // t2ORRrs
3938451456U, // t2PKHBT
3938451488U, // t2PKHTB
+ 4172345344U, // t2PLDWi12
+ 4163959808U, // t2PLDWi8
+ 4164939776U, // t2PLDWpci
+ 4163956736U, // t2PLDWr
+ 4163956736U, // t2PLDWs
+ 4170248192U, // t2PLDi12
+ 4161862656U, // t2PLDi8
+ 4162842624U, // t2PLDpci
+ 4161859584U, // t2PLDr
+ 4161859584U, // t2PLDs
+ 4187025408U, // t2PLIi12
+ 4178639872U, // t2PLIi8
+ 4179619840U, // t2PLIpci
+ 4178636800U, // t2PLIr
+ 4178636800U, // t2PLIs
+ 4202754176U, // t2QADD
+ 4203802640U, // t2QADD16
+ 4202754064U, // t2QADD8
+ 4204851216U, // t2QASX
+ 4202754192U, // t2QDADD
+ 4202754224U, // t2QDSUB
+ 4209045520U, // t2QSAX
+ 4202754208U, // t2QSUB
+ 4207996944U, // t2QSUB16
+ 4206948368U, // t2QSUB8
4203802784U, // t2RBIT
4203802752U, // t2REV
4203802768U, // t2REV16
4203802800U, // t2REVSH
+ 3893362688U, // t2RFEDB
+ 3895459840U, // t2RFEDBW
+ 3918528512U, // t2RFEIA
+ 3920625664U, // t2RFEIAW
3931045936U, // t2RORri
4200656896U, // t2RORrr
4056940544U, // t2RSBSri
3956277248U, // t2RSBSrs
4055891968U, // t2RSBri
3955228672U, // t2RSBrs
+ 4203802624U, // t2SADD16
+ 4202754048U, // t2SADD8
+ 4204851200U, // t2SASX
4050649088U, // t2SBCSri
3949985792U, // t2SBCSrr
3949985792U, // t2SBCSrs
@@ -1430,16 +1677,43 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
3948937216U, // t2SBCrr
3948937216U, // t2SBCrs
4081057792U, // t2SBFX
+ 4220580080U, // t2SDIV
+ 4204851328U, // t2SEL
+ 4087382020U, // t2SEV
+ 4203802656U, // t2SHADD16
+ 4202754080U, // t2SHADD8
+ 4204851232U, // t2SHASX
+ 4209045536U, // t2SHSAX
+ 4207996960U, // t2SHSUB16
+ 4206948384U, // t2SHSUB8
+ 4159733760U, // t2SMC
4212129792U, // t2SMLABB
4212129808U, // t2SMLABT
+ 4213178368U, // t2SMLAD
+ 4213178384U, // t2SMLADX
4223664128U, // t2SMLAL
+ 4223664256U, // t2SMLALBB
+ 4223664272U, // t2SMLALBT
+ 4223664320U, // t2SMLALD
+ 4223664336U, // t2SMLALDX
+ 4223664288U, // t2SMLALTB
+ 4223664304U, // t2SMLALTT
4212129824U, // t2SMLATB
4212129840U, // t2SMLATT
4214226944U, // t2SMLAWB
4214226960U, // t2SMLAWT
+ 4215275520U, // t2SMLSD
+ 4215275536U, // t2SMLSDX
+ 4224712896U, // t2SMLSLD
+ 4224712912U, // t2SMLSLDX
4216324096U, // t2SMMLA
+ 4216324112U, // t2SMMLAR
4217372672U, // t2SMMLS
+ 4217372688U, // t2SMMLSR
4216385536U, // t2SMMUL
+ 4216385552U, // t2SMMULR
+ 4213239808U, // t2SMUAD
+ 4213239824U, // t2SMUADX
4212191232U, // t2SMULBB
4212191248U, // t2SMULBT
4219469824U, // t2SMULL
@@ -1447,7 +1721,20 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4212191280U, // t2SMULTT
4214288384U, // t2SMULWB
4214288400U, // t2SMULWT
+ 4215336960U, // t2SMUSD
+ 4215336976U, // t2SMUSDX
+ 3892314112U, // t2SRSDB
+ 3894411264U, // t2SRSDBW
+ 3917479936U, // t2SRSIA
+ 3919577088U, // t2SRSIAW
+ 4078960640U, // t2SSAT16
+ 4078960640U, // t2SSATasr
+ 4076863488U, // t2SSATlsl
+ 4209045504U, // t2SSAX
+ 4207996928U, // t2SSUB16
+ 4206948352U, // t2SSUB8
3892314112U, // t2STM
+ 4160753152U, // t2STRBT
4160751872U, // t2STRB_POST
4160752896U, // t2STRB_PRE
4169138176U, // t2STRBi12
@@ -1458,11 +1745,13 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
3904900928U, // t2STREXB
3904897136U, // t2STREXD
3904900944U, // t2STREXH
+ 4162850304U, // t2STRHT
4162849024U, // t2STRH_POST
4162850048U, // t2STRH_PRE
4171235328U, // t2STRHi12
4162849792U, // t2STRHi8
4162846720U, // t2STRHs
+ 4164947456U, // t2STRT
4164946176U, // t2STR_POST
4164947200U, // t2STR_PRE
4173332480U, // t2STRi12
@@ -1481,16 +1770,22 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4070572032U, // t2SUBri12
3953131520U, // t2SUBrr
3953131520U, // t2SUBrs
+ 4196462720U, // t2SXTAB16rr
+ 4196462720U, // t2SXTAB16rr_rot
4198559872U, // t2SXTABrr
4198559872U, // t2SXTABrr_rot
4194365568U, // t2SXTAHrr
4194365568U, // t2SXTAHrr_rot
+ 4197445760U, // t2SXTB16r
+ 4197445760U, // t2SXTB16r_rot
4199542912U, // t2SXTBr
4199542912U, // t2SXTBr_rot
4195348608U, // t2SXTHr
4195348608U, // t2SXTHr_rot
3906990080U, // t2TBB
+ 3906007040U, // t2TBBgen
3906990096U, // t2TBH
+ 3906007056U, // t2TBHgen
4035972864U, // t2TEQri
3935309568U, // t2TEQrr
3935309568U, // t2TEQrs
@@ -1498,10 +1793,36 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4027584256U, // t2TSTri
3926920960U, // t2TSTrr
3926920960U, // t2TSTrs
+ 4203802688U, // t2UADD16
+ 4202754112U, // t2UADD8
+ 4204851264U, // t2UASX
4089446400U, // t2UBFX
+ 4222677232U, // t2UDIV
+ 4203802720U, // t2UHADD16
+ 4202754144U, // t2UHADD8
+ 4204851296U, // t2UHASX
+ 4209045600U, // t2UHSAX
+ 4207997024U, // t2UHSUB16
+ 4206948448U, // t2UHSUB8
4225761376U, // t2UMAAL
4225761280U, // t2UMLAL
4221566976U, // t2UMULL
+ 4203802704U, // t2UQADD16
+ 4202754128U, // t2UQADD8
+ 4204851280U, // t2UQASX
+ 4209045584U, // t2UQSAX
+ 4207997008U, // t2UQSUB16
+ 4206948432U, // t2UQSUB8
+ 4218482688U, // t2USAD8
+ 4218421248U, // t2USADA8
+ 4087349248U, // t2USAT16
+ 4087349248U, // t2USATasr
+ 4085252096U, // t2USATlsl
+ 4209045568U, // t2USAX
+ 4207996992U, // t2USUB16
+ 4206948416U, // t2USUB8
+ 4197511296U, // t2UXTAB16rr
+ 4197511296U, // t2UXTAB16rr_rot
4199608448U, // t2UXTABrr
4199608448U, // t2UXTABrr_rot
4195414144U, // t2UXTAHrr
@@ -1512,6 +1833,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4200591488U, // t2UXTBr_rot
4196397184U, // t2UXTHr
4196397184U, // t2UXTHr_rot
+ 4087382018U, // t2WFE
+ 4087382019U, // t2WFI
+ 4087382017U, // t2YIELD
16704U, // tADC
17408U, // tADDhirr
7168U, // tADDi3
@@ -1555,6 +1879,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
17664U, // tCMPzhir
10240U, // tCMPzi8
17024U, // tCMPzr
+ 46688U, // tCPS
16448U, // tEOR
0U, // tInt_eh_sjlj_setjmp
51200U, // tLDM
@@ -1587,6 +1912,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
17920U, // tMOVtgpr2gpr
17216U, // tMUL
17344U, // tMVN
+ 48896U, // tNOP
17152U, // tORR
17528U, // tPICADD
48128U, // tPOP
@@ -1599,6 +1925,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
16960U, // tRSB
38912U, // tRestore
16768U, // tSBC
+ 46664U, // tSETENDBE
+ 46656U, // tSETENDLE
+ 48960U, // tSEV
49152U, // tSTM
20480U, // tSTR
21504U, // tSTRB
@@ -1612,13 +1941,18 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
6656U, // tSUBrr
45184U, // tSUBspi
0U, // tSUBspi_
+ 57088U, // tSVC
45632U, // tSXTB
45568U, // tSXTH
36864U, // tSpill
4026585088U, // tTPsoft
+ 56832U, // tTRAP
16896U, // tTST
45760U, // tUXTB
45696U, // tUXTH
+ 48928U, // tWFE
+ 48944U, // tWFI
+ 48912U, // tYIELD
0U
};
const unsigned opcode = MI.getOpcode();
@@ -1669,6 +2003,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::ATOMIC_SWAP_I8:
case ARM::B:
case ARM::BFC:
+ case ARM::BFI:
case ARM::BICri:
case ARM::BICrr:
case ARM::BICrs:
@@ -1690,6 +2025,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::Bcc:
case ARM::CDP:
case ARM::CDP2:
+ case ARM::CLREX:
case ARM::CLZ:
case ARM::CMNzri:
case ARM::CMNzrr:
@@ -1703,17 +2039,48 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::CONSTPOOL_ENTRY:
case ARM::CPS:
case ARM::DBG:
+ case ARM::DMBish:
+ case ARM::DMBishst:
+ case ARM::DMBnsh:
+ case ARM::DMBnshst:
+ case ARM::DMBosh:
+ case ARM::DMBoshst:
+ case ARM::DMBst:
+ case ARM::DSBish:
+ case ARM::DSBishst:
+ case ARM::DSBnsh:
+ case ARM::DSBnshst:
+ case ARM::DSBosh:
+ case ARM::DSBoshst:
+ case ARM::DSBst:
case ARM::EORri:
case ARM::EORrr:
case ARM::EORrs:
case ARM::FCONSTD:
case ARM::FCONSTS:
case ARM::FMSTAT:
+ case ARM::ISBsy:
case ARM::Int_MemBarrierV6:
case ARM::Int_MemBarrierV7:
case ARM::Int_SyncBarrierV6:
case ARM::Int_SyncBarrierV7:
case ARM::Int_eh_sjlj_setjmp:
+ case ARM::LDC2L_OFFSET:
+ case ARM::LDC2L_OPTION:
+ case ARM::LDC2L_POST:
+ case ARM::LDC2L_PRE:
+ case ARM::LDC2_OFFSET:
+ case ARM::LDC2_OPTION:
+ case ARM::LDC2_POST:
+ case ARM::LDC2_PRE:
+ case ARM::LDCL_OFFSET:
+ case ARM::LDCL_OPTION:
+ case ARM::LDCL_POST:
+ case ARM::LDCL_PRE:
+ case ARM::LDC_OFFSET:
+ case ARM::LDC_OPTION:
+ case ARM::LDC_POST:
+ case ARM::LDC_PRE:
case ARM::LDM:
case ARM::LDM_RET:
case ARM::LDR:
@@ -1722,17 +2089,22 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::LDRB_POST:
case ARM::LDRB_PRE:
case ARM::LDRD:
+ case ARM::LDRD_POST:
+ case ARM::LDRD_PRE:
case ARM::LDREX:
case ARM::LDREXB:
case ARM::LDREXD:
case ARM::LDREXH:
case ARM::LDRH:
+ case ARM::LDRHT:
case ARM::LDRH_POST:
case ARM::LDRH_PRE:
case ARM::LDRSB:
+ case ARM::LDRSBT:
case ARM::LDRSB_POST:
case ARM::LDRSB_PRE:
case ARM::LDRSH:
+ case ARM::LDRSHT:
case ARM::LDRSH_POST:
case ARM::LDRSH_PRE:
case ARM::LDRT:
@@ -1767,7 +2139,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::MRS:
case ARM::MRSsys:
case ARM::MSR:
+ case ARM::MSRi:
case ARM::MSRsys:
+ case ARM::MSRsysi:
case ARM::MUL:
case ARM::MVNi:
case ARM::MVNr:
@@ -1787,6 +2161,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::PICSTRH:
case ARM::PKHBT:
case ARM::PKHTB:
+ case ARM::PLDWi:
+ case ARM::PLDWr:
+ case ARM::PLDi:
+ case ARM::PLDr:
+ case ARM::PLIi:
+ case ARM::PLIr:
case ARM::QADD:
case ARM::QADD16:
case ARM::QADD8:
@@ -1801,6 +2181,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::REV:
case ARM::REV16:
case ARM::REVSH:
+ case ARM::RFE:
+ case ARM::RFEW:
case ARM::RSBSri:
case ARM::RSBSrs:
case ARM::RSBri:
@@ -1809,6 +2191,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::RSCSrs:
case ARM::RSCri:
case ARM::RSCrs:
+ case ARM::SADD16:
+ case ARM::SADD8:
+ case ARM::SASX:
case ARM::SBCSSri:
case ARM::SBCSSrr:
case ARM::SBCSSrs:
@@ -1816,23 +2201,44 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::SBCrr:
case ARM::SBCrs:
case ARM::SBFX:
+ case ARM::SEL:
case ARM::SETENDBE:
case ARM::SETENDLE:
case ARM::SEV:
+ case ARM::SHADD16:
+ case ARM::SHADD8:
+ case ARM::SHASX:
+ case ARM::SHSAX:
+ case ARM::SHSUB16:
+ case ARM::SHSUB8:
+ case ARM::SMC:
case ARM::SMLABB:
case ARM::SMLABT:
+ case ARM::SMLAD:
+ case ARM::SMLADX:
case ARM::SMLAL:
case ARM::SMLALBB:
case ARM::SMLALBT:
+ case ARM::SMLALD:
+ case ARM::SMLALDX:
case ARM::SMLALTB:
case ARM::SMLALTT:
case ARM::SMLATB:
case ARM::SMLATT:
case ARM::SMLAWB:
case ARM::SMLAWT:
+ case ARM::SMLSD:
+ case ARM::SMLSDX:
+ case ARM::SMLSLD:
+ case ARM::SMLSLDX:
case ARM::SMMLA:
+ case ARM::SMMLAR:
case ARM::SMMLS:
+ case ARM::SMMLSR:
case ARM::SMMUL:
+ case ARM::SMMULR:
+ case ARM::SMUAD:
+ case ARM::SMUADX:
case ARM::SMULBB:
case ARM::SMULBT:
case ARM::SMULL:
@@ -1840,6 +2246,32 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::SMULTT:
case ARM::SMULWB:
case ARM::SMULWT:
+ case ARM::SMUSD:
+ case ARM::SMUSDX:
+ case ARM::SRS:
+ case ARM::SRSW:
+ case ARM::SSAT16:
+ case ARM::SSATasr:
+ case ARM::SSATlsl:
+ case ARM::SSAX:
+ case ARM::SSUB16:
+ case ARM::SSUB8:
+ case ARM::STC2L_OFFSET:
+ case ARM::STC2L_OPTION:
+ case ARM::STC2L_POST:
+ case ARM::STC2L_PRE:
+ case ARM::STC2_OFFSET:
+ case ARM::STC2_OPTION:
+ case ARM::STC2_POST:
+ case ARM::STC2_PRE:
+ case ARM::STCL_OFFSET:
+ case ARM::STCL_OPTION:
+ case ARM::STCL_POST:
+ case ARM::STCL_PRE:
+ case ARM::STC_OFFSET:
+ case ARM::STC_OPTION:
+ case ARM::STC_POST:
+ case ARM::STC_PRE:
case ARM::STM:
case ARM::STR:
case ARM::STRB:
@@ -1847,11 +2279,14 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::STRB_POST:
case ARM::STRB_PRE:
case ARM::STRD:
+ case ARM::STRD_POST:
+ case ARM::STRD_PRE:
case ARM::STREX:
case ARM::STREXB:
case ARM::STREXD:
case ARM::STREXH:
case ARM::STRH:
+ case ARM::STRHT:
case ARM::STRH_POST:
case ARM::STRH_PRE:
case ARM::STRT:
@@ -1866,10 +2301,14 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::SVC:
case ARM::SWP:
case ARM::SWPB:
+ case ARM::SXTAB16rr:
+ case ARM::SXTAB16rr_rot:
case ARM::SXTABrr:
case ARM::SXTABrr_rot:
case ARM::SXTAHrr:
case ARM::SXTAHrr_rot:
+ case ARM::SXTB16r:
+ case ARM::SXTB16r_rot:
case ARM::SXTBr:
case ARM::SXTBr_rot:
case ARM::SXTHr:
@@ -1882,7 +2321,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::TSTri:
case ARM::TSTrr:
case ARM::TSTrs:
+ case ARM::UADD16:
+ case ARM::UADD8:
+ case ARM::UASX:
case ARM::UBFX:
+ case ARM::UHADD16:
+ case ARM::UHADD8:
+ case ARM::UHASX:
+ case ARM::UHSAX:
+ case ARM::UHSUB16:
+ case ARM::UHSUB8:
case ARM::UMAAL:
case ARM::UMLAL:
case ARM::UMULL:
@@ -1892,6 +2340,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::UQSAX:
case ARM::UQSUB16:
case ARM::UQSUB8:
+ case ARM::USAD8:
+ case ARM::USADA8:
+ case ARM::USAT16:
+ case ARM::USATasr:
+ case ARM::USATlsl:
+ case ARM::USAX:
+ case ARM::USUB16:
+ case ARM::USUB8:
+ case ARM::UXTAB16rr:
+ case ARM::UXTAB16rr_rot:
case ARM::UXTABrr:
case ARM::UXTABrr_rot:
case ARM::UXTAHrr:
@@ -2001,6 +2459,14 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VCEQv4i32:
case ARM::VCEQv8i16:
case ARM::VCEQv8i8:
+ case ARM::VCEQzv16i8:
+ case ARM::VCEQzv2f32:
+ case ARM::VCEQzv2i32:
+ case ARM::VCEQzv4f32:
+ case ARM::VCEQzv4i16:
+ case ARM::VCEQzv4i32:
+ case ARM::VCEQzv8i16:
+ case ARM::VCEQzv8i8:
case ARM::VCGEfd:
case ARM::VCGEfq:
case ARM::VCGEsv16i8:
@@ -2015,6 +2481,14 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VCGEuv4i32:
case ARM::VCGEuv8i16:
case ARM::VCGEuv8i8:
+ case ARM::VCGEzv16i8:
+ case ARM::VCGEzv2f32:
+ case ARM::VCGEzv2i32:
+ case ARM::VCGEzv4f32:
+ case ARM::VCGEzv4i16:
+ case ARM::VCGEzv4i32:
+ case ARM::VCGEzv8i16:
+ case ARM::VCGEzv8i8:
case ARM::VCGTfd:
case ARM::VCGTfq:
case ARM::VCGTsv16i8:
@@ -2029,12 +2503,36 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VCGTuv4i32:
case ARM::VCGTuv8i16:
case ARM::VCGTuv8i8:
+ case ARM::VCGTzv16i8:
+ case ARM::VCGTzv2f32:
+ case ARM::VCGTzv2i32:
+ case ARM::VCGTzv4f32:
+ case ARM::VCGTzv4i16:
+ case ARM::VCGTzv4i32:
+ case ARM::VCGTzv8i16:
+ case ARM::VCGTzv8i8:
+ case ARM::VCLEzv16i8:
+ case ARM::VCLEzv2f32:
+ case ARM::VCLEzv2i32:
+ case ARM::VCLEzv4f32:
+ case ARM::VCLEzv4i16:
+ case ARM::VCLEzv4i32:
+ case ARM::VCLEzv8i16:
+ case ARM::VCLEzv8i8:
case ARM::VCLSv16i8:
case ARM::VCLSv2i32:
case ARM::VCLSv4i16:
case ARM::VCLSv4i32:
case ARM::VCLSv8i16:
case ARM::VCLSv8i8:
+ case ARM::VCLTzv16i8:
+ case ARM::VCLTzv2f32:
+ case ARM::VCLTzv2i32:
+ case ARM::VCLTzv4f32:
+ case ARM::VCLTzv4i16:
+ case ARM::VCLTzv4i32:
+ case ARM::VCLTzv8i16:
+ case ARM::VCLTzv8i8:
case ARM::VCLZv16i8:
case ARM::VCLZv2i32:
case ARM::VCLZv4i16:
@@ -2137,9 +2635,15 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VHSUBuv8i16:
case ARM::VHSUBuv8i8:
case ARM::VLD1d16:
+ case ARM::VLD1d16Q:
+ case ARM::VLD1d16T:
case ARM::VLD1d32:
+ case ARM::VLD1d32Q:
+ case ARM::VLD1d32T:
case ARM::VLD1d64:
case ARM::VLD1d8:
+ case ARM::VLD1d8Q:
+ case ARM::VLD1d8T:
case ARM::VLD1df:
case ARM::VLD1q16:
case ARM::VLD1q32:
@@ -2154,9 +2658,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VLD2LNq32a:
case ARM::VLD2LNq32b:
case ARM::VLD2d16:
+ case ARM::VLD2d16D:
case ARM::VLD2d32:
+ case ARM::VLD2d32D:
case ARM::VLD2d64:
case ARM::VLD2d8:
+ case ARM::VLD2d8D:
case ARM::VLD2q16:
case ARM::VLD2q32:
case ARM::VLD2q8:
@@ -2200,6 +2707,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VLDRQ:
case ARM::VLDRS:
case ARM::VMAXfd:
+ case ARM::VMAXfd_sfp:
case ARM::VMAXfq:
case ARM::VMAXsv16i8:
case ARM::VMAXsv2i32:
@@ -2214,6 +2722,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VMAXuv8i16:
case ARM::VMAXuv8i8:
case ARM::VMINfd:
+ case ARM::VMINfd_sfp:
case ARM::VMINfq:
case ARM::VMINsv16i8:
case ARM::VMINsv2i32:
@@ -2346,9 +2855,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VNEGDcc:
case ARM::VNEGS:
case ARM::VNEGScc:
- case ARM::VNEGf32d:
- case ARM::VNEGf32d_sfp:
case ARM::VNEGf32q:
+ case ARM::VNEGfd:
+ case ARM::VNEGfd_sfp:
case ARM::VNEGs16d:
case ARM::VNEGs16q:
case ARM::VNEGs32d:
@@ -2753,9 +3262,15 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VSRIv8i16:
case ARM::VSRIv8i8:
case ARM::VST1d16:
+ case ARM::VST1d16Q:
+ case ARM::VST1d16T:
case ARM::VST1d32:
+ case ARM::VST1d32Q:
+ case ARM::VST1d32T:
case ARM::VST1d64:
case ARM::VST1d8:
+ case ARM::VST1d8Q:
+ case ARM::VST1d8T:
case ARM::VST1df:
case ARM::VST1q16:
case ARM::VST1q32:
@@ -2770,9 +3285,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VST2LNq32a:
case ARM::VST2LNq32b:
case ARM::VST2d16:
+ case ARM::VST2d16D:
case ARM::VST2d32:
+ case ARM::VST2d32D:
case ARM::VST2d64:
case ARM::VST2d8:
+ case ARM::VST2d8D:
case ARM::VST2q16:
case ARM::VST2q32:
case ARM::VST2q8:
@@ -2843,6 +3361,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VSUBv4i32:
case ARM::VSUBv8i16:
case ARM::VSUBv8i8:
+ case ARM::VSWPd:
+ case ARM::VSWPq:
case ARM::VTBL1:
case ARM::VTBL2:
case ARM::VTBL3:
@@ -2928,7 +3448,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2BICrr:
case ARM::t2BICrs:
case ARM::t2BR_JT:
+ case ARM::t2BXJ:
case ARM::t2Bcc:
+ case ARM::t2CLREX:
case ARM::t2CLZ:
case ARM::t2CMNzri:
case ARM::t2CMNzrr:
@@ -2939,15 +3461,33 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2CMPzri:
case ARM::t2CMPzrr:
case ARM::t2CMPzrs:
+ case ARM::t2CPS:
+ case ARM::t2DBG:
+ case ARM::t2DMBish:
+ case ARM::t2DMBishst:
+ case ARM::t2DMBnsh:
+ case ARM::t2DMBnshst:
+ case ARM::t2DMBosh:
+ case ARM::t2DMBoshst:
+ case ARM::t2DMBst:
+ case ARM::t2DSBish:
+ case ARM::t2DSBishst:
+ case ARM::t2DSBnsh:
+ case ARM::t2DSBnshst:
+ case ARM::t2DSBosh:
+ case ARM::t2DSBoshst:
+ case ARM::t2DSBst:
case ARM::t2EORri:
case ARM::t2EORrr:
case ARM::t2EORrs:
+ case ARM::t2ISBsy:
case ARM::t2IT:
case ARM::t2Int_MemBarrierV7:
case ARM::t2Int_SyncBarrierV7:
case ARM::t2Int_eh_sjlj_setjmp:
case ARM::t2LDM:
case ARM::t2LDM_RET:
+ case ARM::t2LDRBT:
case ARM::t2LDRB_POST:
case ARM::t2LDRB_PRE:
case ARM::t2LDRBi12:
@@ -2960,24 +3500,28 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2LDREXB:
case ARM::t2LDREXD:
case ARM::t2LDREXH:
+ case ARM::t2LDRHT:
case ARM::t2LDRH_POST:
case ARM::t2LDRH_PRE:
case ARM::t2LDRHi12:
case ARM::t2LDRHi8:
case ARM::t2LDRHpci:
case ARM::t2LDRHs:
+ case ARM::t2LDRSBT:
case ARM::t2LDRSB_POST:
case ARM::t2LDRSB_PRE:
case ARM::t2LDRSBi12:
case ARM::t2LDRSBi8:
case ARM::t2LDRSBpci:
case ARM::t2LDRSBs:
+ case ARM::t2LDRSHT:
case ARM::t2LDRSH_POST:
case ARM::t2LDRSH_PRE:
case ARM::t2LDRSHi12:
case ARM::t2LDRSHi8:
case ARM::t2LDRSHpci:
case ARM::t2LDRSHs:
+ case ARM::t2LDRT:
case ARM::t2LDR_POST:
case ARM::t2LDR_PRE:
case ARM::t2LDRi12:
@@ -3007,10 +3551,15 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2MOVrx:
case ARM::t2MOVsra_flag:
case ARM::t2MOVsrl_flag:
+ case ARM::t2MRS:
+ case ARM::t2MRSsys:
+ case ARM::t2MSR:
+ case ARM::t2MSRsys:
case ARM::t2MUL:
case ARM::t2MVNi:
case ARM::t2MVNr:
case ARM::t2MVNs:
+ case ARM::t2NOP:
case ARM::t2ORNri:
case ARM::t2ORNrr:
case ARM::t2ORNrs:
@@ -3019,16 +3568,48 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2ORRrs:
case ARM::t2PKHBT:
case ARM::t2PKHTB:
+ case ARM::t2PLDWi12:
+ case ARM::t2PLDWi8:
+ case ARM::t2PLDWpci:
+ case ARM::t2PLDWr:
+ case ARM::t2PLDWs:
+ case ARM::t2PLDi12:
+ case ARM::t2PLDi8:
+ case ARM::t2PLDpci:
+ case ARM::t2PLDr:
+ case ARM::t2PLDs:
+ case ARM::t2PLIi12:
+ case ARM::t2PLIi8:
+ case ARM::t2PLIpci:
+ case ARM::t2PLIr:
+ case ARM::t2PLIs:
+ case ARM::t2QADD:
+ case ARM::t2QADD16:
+ case ARM::t2QADD8:
+ case ARM::t2QASX:
+ case ARM::t2QDADD:
+ case ARM::t2QDSUB:
+ case ARM::t2QSAX:
+ case ARM::t2QSUB:
+ case ARM::t2QSUB16:
+ case ARM::t2QSUB8:
case ARM::t2RBIT:
case ARM::t2REV:
case ARM::t2REV16:
case ARM::t2REVSH:
+ case ARM::t2RFEDB:
+ case ARM::t2RFEDBW:
+ case ARM::t2RFEIA:
+ case ARM::t2RFEIAW:
case ARM::t2RORri:
case ARM::t2RORrr:
case ARM::t2RSBSri:
case ARM::t2RSBSrs:
case ARM::t2RSBri:
case ARM::t2RSBrs:
+ case ARM::t2SADD16:
+ case ARM::t2SADD8:
+ case ARM::t2SASX:
case ARM::t2SBCSri:
case ARM::t2SBCSrr:
case ARM::t2SBCSrs:
@@ -3036,16 +3617,43 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2SBCrr:
case ARM::t2SBCrs:
case ARM::t2SBFX:
+ case ARM::t2SDIV:
+ case ARM::t2SEL:
+ case ARM::t2SEV:
+ case ARM::t2SHADD16:
+ case ARM::t2SHADD8:
+ case ARM::t2SHASX:
+ case ARM::t2SHSAX:
+ case ARM::t2SHSUB16:
+ case ARM::t2SHSUB8:
+ case ARM::t2SMC:
case ARM::t2SMLABB:
case ARM::t2SMLABT:
+ case ARM::t2SMLAD:
+ case ARM::t2SMLADX:
case ARM::t2SMLAL:
+ case ARM::t2SMLALBB:
+ case ARM::t2SMLALBT:
+ case ARM::t2SMLALD:
+ case ARM::t2SMLALDX:
+ case ARM::t2SMLALTB:
+ case ARM::t2SMLALTT:
case ARM::t2SMLATB:
case ARM::t2SMLATT:
case ARM::t2SMLAWB:
case ARM::t2SMLAWT:
+ case ARM::t2SMLSD:
+ case ARM::t2SMLSDX:
+ case ARM::t2SMLSLD:
+ case ARM::t2SMLSLDX:
case ARM::t2SMMLA:
+ case ARM::t2SMMLAR:
case ARM::t2SMMLS:
+ case ARM::t2SMMLSR:
case ARM::t2SMMUL:
+ case ARM::t2SMMULR:
+ case ARM::t2SMUAD:
+ case ARM::t2SMUADX:
case ARM::t2SMULBB:
case ARM::t2SMULBT:
case ARM::t2SMULL:
@@ -3053,7 +3661,20 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2SMULTT:
case ARM::t2SMULWB:
case ARM::t2SMULWT:
+ case ARM::t2SMUSD:
+ case ARM::t2SMUSDX:
+ case ARM::t2SRSDB:
+ case ARM::t2SRSDBW:
+ case ARM::t2SRSIA:
+ case ARM::t2SRSIAW:
+ case ARM::t2SSAT16:
+ case ARM::t2SSATasr:
+ case ARM::t2SSATlsl:
+ case ARM::t2SSAX:
+ case ARM::t2SSUB16:
+ case ARM::t2SSUB8:
case ARM::t2STM:
+ case ARM::t2STRBT:
case ARM::t2STRB_POST:
case ARM::t2STRB_PRE:
case ARM::t2STRBi12:
@@ -3064,11 +3685,13 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2STREXB:
case ARM::t2STREXD:
case ARM::t2STREXH:
+ case ARM::t2STRHT:
case ARM::t2STRH_POST:
case ARM::t2STRH_PRE:
case ARM::t2STRHi12:
case ARM::t2STRHi8:
case ARM::t2STRHs:
+ case ARM::t2STRT:
case ARM::t2STR_POST:
case ARM::t2STR_PRE:
case ARM::t2STRi12:
@@ -3087,16 +3710,22 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2SUBri12:
case ARM::t2SUBrr:
case ARM::t2SUBrs:
+ case ARM::t2SXTAB16rr:
+ case ARM::t2SXTAB16rr_rot:
case ARM::t2SXTABrr:
case ARM::t2SXTABrr_rot:
case ARM::t2SXTAHrr:
case ARM::t2SXTAHrr_rot:
+ case ARM::t2SXTB16r:
+ case ARM::t2SXTB16r_rot:
case ARM::t2SXTBr:
case ARM::t2SXTBr_rot:
case ARM::t2SXTHr:
case ARM::t2SXTHr_rot:
case ARM::t2TBB:
+ case ARM::t2TBBgen:
case ARM::t2TBH:
+ case ARM::t2TBHgen:
case ARM::t2TEQri:
case ARM::t2TEQrr:
case ARM::t2TEQrs:
@@ -3104,10 +3733,36 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2TSTri:
case ARM::t2TSTrr:
case ARM::t2TSTrs:
+ case ARM::t2UADD16:
+ case ARM::t2UADD8:
+ case ARM::t2UASX:
case ARM::t2UBFX:
+ case ARM::t2UDIV:
+ case ARM::t2UHADD16:
+ case ARM::t2UHADD8:
+ case ARM::t2UHASX:
+ case ARM::t2UHSAX:
+ case ARM::t2UHSUB16:
+ case ARM::t2UHSUB8:
case ARM::t2UMAAL:
case ARM::t2UMLAL:
case ARM::t2UMULL:
+ case ARM::t2UQADD16:
+ case ARM::t2UQADD8:
+ case ARM::t2UQASX:
+ case ARM::t2UQSAX:
+ case ARM::t2UQSUB16:
+ case ARM::t2UQSUB8:
+ case ARM::t2USAD8:
+ case ARM::t2USADA8:
+ case ARM::t2USAT16:
+ case ARM::t2USATasr:
+ case ARM::t2USATlsl:
+ case ARM::t2USAX:
+ case ARM::t2USUB16:
+ case ARM::t2USUB8:
+ case ARM::t2UXTAB16rr:
+ case ARM::t2UXTAB16rr_rot:
case ARM::t2UXTABrr:
case ARM::t2UXTABrr_rot:
case ARM::t2UXTAHrr:
@@ -3118,6 +3773,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2UXTBr_rot:
case ARM::t2UXTHr:
case ARM::t2UXTHr_rot:
+ case ARM::t2WFE:
+ case ARM::t2WFI:
+ case ARM::t2YIELD:
case ARM::tADC:
case ARM::tADDhirr:
case ARM::tADDi3:
@@ -3161,6 +3819,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::tCMPzhir:
case ARM::tCMPzi8:
case ARM::tCMPzr:
+ case ARM::tCPS:
case ARM::tEOR:
case ARM::tInt_eh_sjlj_setjmp:
case ARM::tLDM:
@@ -3193,6 +3852,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::tMOVtgpr2gpr:
case ARM::tMUL:
case ARM::tMVN:
+ case ARM::tNOP:
case ARM::tORR:
case ARM::tPICADD:
case ARM::tPOP:
@@ -3205,6 +3865,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::tRSB:
case ARM::tRestore:
case ARM::tSBC:
+ case ARM::tSETENDBE:
+ case ARM::tSETENDLE:
+ case ARM::tSEV:
case ARM::tSTM:
case ARM::tSTR:
case ARM::tSTRB:
@@ -3218,13 +3881,18 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::tSUBrr:
case ARM::tSUBspi:
case ARM::tSUBspi_:
+ case ARM::tSVC:
case ARM::tSXTB:
case ARM::tSXTH:
case ARM::tSpill:
case ARM::tTPsoft:
+ case ARM::tTRAP:
case ARM::tTST:
case ARM::tUXTB:
- case ARM::tUXTH: {
+ case ARM::tUXTH:
+ case ARM::tWFE:
+ case ARM::tWFI:
+ case ARM::tYIELD: {
break;
}
default:
diff --git a/libclamav/c++/ARMGenDAGISel.inc b/libclamav/c++/ARMGenDAGISel.inc
index 5ba1ab4..7dbce8a 100644
--- a/libclamav/c++/ARMGenDAGISel.inc
+++ b/libclamav/c++/ARMGenDAGISel.inc
@@ -9,450 +9,257 @@
// *** NOTE: This file is #included into the middle of the target
// *** instruction selector class. These functions are really methods.
-// Include standard, target-independent definitions and methods used
-// by the instruction selector.
-#include "llvm/CodeGen/DAGISelHeader.h"
-
-
-// Node transformations.
-inline SDValue Transform_DSubReg_f64_other_reg(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
-
-}
-inline SDValue Transform_DSubReg_f64_reg(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
-
-}
-inline SDValue Transform_DSubReg_i16_reg(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
-
-}
-inline SDValue Transform_DSubReg_i32_reg(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
-
-}
-inline SDValue Transform_DSubReg_i8_reg(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
-
-}
-inline SDValue Transform_SSubReg_f32_reg(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
-
-}
-inline SDValue Transform_SubReg_i16_lane(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
-
-}
-inline SDValue Transform_SubReg_i32_lane(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
-
-}
-inline SDValue Transform_SubReg_i8_lane(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
-
-}
-inline SDValue Transform_VMOV_get_imm16(SDNode *N) {
-
- return ARM::getVMOVImm(N, 2, *CurDAG);
-
-}
-inline SDValue Transform_VMOV_get_imm32(SDNode *N) {
-
- return ARM::getVMOVImm(N, 4, *CurDAG);
-
-}
-inline SDValue Transform_VMOV_get_imm64(SDNode *N) {
-
- return ARM::getVMOVImm(N, 8, *CurDAG);
-
-}
-inline SDValue Transform_VMOV_get_imm8(SDNode *N) {
-
- return ARM::getVMOVImm(N, 1, *CurDAG);
-
-}
-inline SDValue Transform_hi16(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
-
-}
-inline SDValue Transform_imm_comp_XFORM(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
-
-}
-inline SDValue Transform_imm_neg_XFORM(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
-
-}
-inline SDValue Transform_lo16(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
- MVT::i32);
-
-}
-inline SDValue Transform_so_imm2part_1(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
-
-}
-inline SDValue Transform_so_imm2part_2(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
-
-}
-inline SDValue Transform_so_imm_neg_XFORM(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
-
-}
-inline SDValue Transform_so_imm_not_XFORM(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
-
-}
-inline SDValue Transform_so_neg_imm2part_1(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
-
-}
-inline SDValue Transform_so_neg_imm2part_2(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
-
-}
-inline SDValue Transform_t2_so_imm2part_1(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
-
-}
-inline SDValue Transform_t2_so_imm2part_2(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
-
-}
-inline SDValue Transform_t2_so_imm_neg_XFORM(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
-
-}
-inline SDValue Transform_t2_so_imm_not_XFORM(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
-
-}
-inline SDValue Transform_t2_so_neg_imm2part_1(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
-
-}
-inline SDValue Transform_t2_so_neg_imm2part_2(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
-
-}
-inline SDValue Transform_thumb_immshifted_shamt(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
+// Predicate functions.
+inline bool Predicate_adde_dead_carry(SDNode *N) const {
+return !N->hasAnyUseOfValue(1);
}
-inline SDValue Transform_thumb_immshifted_val(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
-
+inline bool Predicate_adde_live_carry(SDNode *N) const {
+return N->hasAnyUseOfValue(1);
}
-
-// Predicate functions.
-inline bool Predicate_atomic_cmp_swap_16(SDNode *N) {
+inline bool Predicate_atomic_cmp_swap_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_cmp_swap_32(SDNode *N) {
+inline bool Predicate_atomic_cmp_swap_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_cmp_swap_64(SDNode *N) {
+inline bool Predicate_atomic_cmp_swap_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_cmp_swap_8(SDNode *N) {
+inline bool Predicate_atomic_cmp_swap_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_add_16(SDNode *N) {
+inline bool Predicate_atomic_load_add_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_add_32(SDNode *N) {
+inline bool Predicate_atomic_load_add_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_add_64(SDNode *N) {
+inline bool Predicate_atomic_load_add_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_add_8(SDNode *N) {
+inline bool Predicate_atomic_load_add_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_and_16(SDNode *N) {
+inline bool Predicate_atomic_load_and_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_and_32(SDNode *N) {
+inline bool Predicate_atomic_load_and_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_and_64(SDNode *N) {
+inline bool Predicate_atomic_load_and_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_and_8(SDNode *N) {
+inline bool Predicate_atomic_load_and_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_max_16(SDNode *N) {
+inline bool Predicate_atomic_load_max_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_max_32(SDNode *N) {
+inline bool Predicate_atomic_load_max_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_max_64(SDNode *N) {
+inline bool Predicate_atomic_load_max_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_max_8(SDNode *N) {
+inline bool Predicate_atomic_load_max_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_min_16(SDNode *N) {
+inline bool Predicate_atomic_load_min_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_min_32(SDNode *N) {
+inline bool Predicate_atomic_load_min_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_min_64(SDNode *N) {
+inline bool Predicate_atomic_load_min_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_min_8(SDNode *N) {
+inline bool Predicate_atomic_load_min_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_nand_16(SDNode *N) {
+inline bool Predicate_atomic_load_nand_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_nand_32(SDNode *N) {
+inline bool Predicate_atomic_load_nand_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_nand_64(SDNode *N) {
+inline bool Predicate_atomic_load_nand_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_nand_8(SDNode *N) {
+inline bool Predicate_atomic_load_nand_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_or_16(SDNode *N) {
+inline bool Predicate_atomic_load_or_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_or_32(SDNode *N) {
+inline bool Predicate_atomic_load_or_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_or_64(SDNode *N) {
+inline bool Predicate_atomic_load_or_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_or_8(SDNode *N) {
+inline bool Predicate_atomic_load_or_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_sub_16(SDNode *N) {
+inline bool Predicate_atomic_load_sub_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_sub_32(SDNode *N) {
+inline bool Predicate_atomic_load_sub_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_sub_64(SDNode *N) {
+inline bool Predicate_atomic_load_sub_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_sub_8(SDNode *N) {
+inline bool Predicate_atomic_load_sub_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_umax_16(SDNode *N) {
+inline bool Predicate_atomic_load_umax_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_umax_32(SDNode *N) {
+inline bool Predicate_atomic_load_umax_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_umax_64(SDNode *N) {
+inline bool Predicate_atomic_load_umax_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_umax_8(SDNode *N) {
+inline bool Predicate_atomic_load_umax_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_umin_16(SDNode *N) {
+inline bool Predicate_atomic_load_umin_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_umin_32(SDNode *N) {
+inline bool Predicate_atomic_load_umin_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_umin_64(SDNode *N) {
+inline bool Predicate_atomic_load_umin_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_umin_8(SDNode *N) {
+inline bool Predicate_atomic_load_umin_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_xor_16(SDNode *N) {
+inline bool Predicate_atomic_load_xor_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_xor_32(SDNode *N) {
+inline bool Predicate_atomic_load_xor_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_xor_64(SDNode *N) {
+inline bool Predicate_atomic_load_xor_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_xor_8(SDNode *N) {
+inline bool Predicate_atomic_load_xor_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_swap_16(SDNode *N) {
+inline bool Predicate_atomic_swap_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_swap_32(SDNode *N) {
+inline bool Predicate_atomic_swap_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_swap_64(SDNode *N) {
+inline bool Predicate_atomic_swap_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_swap_8(SDNode *N) {
+inline bool Predicate_atomic_swap_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_bf_inv_mask_imm(SDNode *inN) {
+inline bool Predicate_bf_inv_mask_imm(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
+
uint32_t v = (uint32_t)N->getZExtValue();
if (v == 0xffffffff)
return 0;
@@ -468,38503 +275,27007 @@ inline bool Predicate_bf_inv_mask_imm(SDNode *inN) {
return 1;
}
-inline bool Predicate_cvtff(SDNode *N) {
+inline bool Predicate_cvtff(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
}
-inline bool Predicate_cvtfs(SDNode *N) {
+inline bool Predicate_cvtfs(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
}
-inline bool Predicate_cvtfu(SDNode *N) {
+inline bool Predicate_cvtfu(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
}
-inline bool Predicate_cvtsf(SDNode *N) {
+inline bool Predicate_cvtsf(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
}
-inline bool Predicate_cvtss(SDNode *N) {
+inline bool Predicate_cvtss(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
}
-inline bool Predicate_cvtsu(SDNode *N) {
+inline bool Predicate_cvtsu(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
}
-inline bool Predicate_cvtuf(SDNode *N) {
+inline bool Predicate_cvtuf(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
}
-inline bool Predicate_cvtus(SDNode *N) {
+inline bool Predicate_cvtus(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
}
-inline bool Predicate_cvtuu(SDNode *N) {
+inline bool Predicate_cvtuu(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
}
-inline bool Predicate_extload(SDNode *N) {
+inline bool Predicate_extload(SDNode *N) const {
return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
}
-inline bool Predicate_extloadf32(SDNode *N) {
+inline bool Predicate_extloadf32(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
}
-inline bool Predicate_extloadf64(SDNode *N) {
+inline bool Predicate_extloadf64(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
}
-inline bool Predicate_extloadi1(SDNode *N) {
+inline bool Predicate_extloadi1(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_extloadi16(SDNode *N) {
+inline bool Predicate_extloadi16(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_extloadi32(SDNode *N) {
+inline bool Predicate_extloadi32(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_extloadi8(SDNode *N) {
+inline bool Predicate_extloadi8(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_imm0_255(SDNode *inN) {
+inline bool Predicate_imm0_255(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return (uint32_t)N->getZExtValue() < 256;
}
-inline bool Predicate_imm0_255_comp(SDNode *inN) {
+inline bool Predicate_imm0_255_comp(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return ~((uint32_t)N->getZExtValue()) < 256;
}
-inline bool Predicate_imm0_255_neg(SDNode *inN) {
+inline bool Predicate_imm0_255_neg(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return (uint32_t)(-N->getZExtValue()) < 255;
}
-inline bool Predicate_imm0_31(SDNode *inN) {
+inline bool Predicate_imm0_31(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return (int32_t)N->getZExtValue() < 32;
}
-inline bool Predicate_imm0_4095(SDNode *inN) {
+inline bool Predicate_imm0_4095(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return (uint32_t)N->getZExtValue() < 4096;
}
-inline bool Predicate_imm0_4095_neg(SDNode *inN) {
+inline bool Predicate_imm0_4095_neg(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- return (uint32_t)(-N->getZExtValue()) < 4096;
+
+ return (uint32_t)(-N->getZExtValue()) < 4096;
}
-inline bool Predicate_imm0_65535(SDNode *inN) {
+inline bool Predicate_imm0_65535(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return (uint32_t)N->getZExtValue() < 65536;
}
-inline bool Predicate_imm0_7(SDNode *inN) {
+inline bool Predicate_imm0_7(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return (uint32_t)N->getZExtValue() < 8;
}
-inline bool Predicate_imm0_7_neg(SDNode *inN) {
+inline bool Predicate_imm0_7_neg(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return (uint32_t)-N->getZExtValue() < 8;
}
-inline bool Predicate_imm16_31(SDNode *inN) {
+inline bool Predicate_imm16_31(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
}
-inline bool Predicate_imm1_15(SDNode *inN) {
+inline bool Predicate_imm1_15(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
}
-inline bool Predicate_imm1_31(SDNode *inN) {
+inline bool Predicate_imm1_31(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
}
-inline bool Predicate_imm8_255(SDNode *inN) {
+inline bool Predicate_imm8_255(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
}
-inline bool Predicate_imm8_255_neg(SDNode *inN) {
+inline bool Predicate_imm8_255_neg(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
unsigned Val = -N->getZExtValue();
return Val >= 8 && Val < 256;
}
-inline bool Predicate_immAllOnes(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
- return N->isAllOnesValue();
-}
-inline bool Predicate_immAllOnesV(SDNode *N) {
+inline bool Predicate_immAllOnesV(SDNode *N) const {
return ISD::isBuildVectorAllOnes(N);
}
-inline bool Predicate_immAllOnesV_bc(SDNode *N) {
+inline bool Predicate_immAllOnesV_bc(SDNode *N) const {
return ISD::isBuildVectorAllOnes(N);
}
-inline bool Predicate_immAllZerosV(SDNode *N) {
+inline bool Predicate_immAllZerosV(SDNode *N) const {
return ISD::isBuildVectorAllZeros(N);
}
-inline bool Predicate_immAllZerosV_bc(SDNode *N) {
+inline bool Predicate_immAllZerosV_bc(SDNode *N) const {
return ISD::isBuildVectorAllZeros(N);
}
-inline bool Predicate_istore(SDNode *N) {
+inline bool Predicate_istore(SDNode *N) const {
return !cast<StoreSDNode>(N)->isTruncatingStore();
}
-inline bool Predicate_itruncstore(SDNode *N) {
+inline bool Predicate_itruncstore(SDNode *N) const {
return cast<StoreSDNode>(N)->isTruncatingStore();
}
-inline bool Predicate_lo16AllZero(SDNode *inN) {
+inline bool Predicate_lo16AllZero(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
// Returns true if all low 16-bits are 0.
return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
}
-inline bool Predicate_load(SDNode *N) {
+inline bool Predicate_load(SDNode *N) const {
return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
}
-inline bool Predicate_post_store(SDNode *N) {
+inline bool Predicate_post_store(SDNode *N) const {
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::POST_INC || AM == ISD::POST_DEC;
}
-inline bool Predicate_post_truncst(SDNode *N) {
+inline bool Predicate_post_truncst(SDNode *N) const {
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::POST_INC || AM == ISD::POST_DEC;
}
-inline bool Predicate_post_truncstf32(SDNode *N) {
+inline bool Predicate_post_truncstf32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}
-inline bool Predicate_post_truncsti1(SDNode *N) {
+inline bool Predicate_post_truncsti1(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_post_truncsti16(SDNode *N) {
+inline bool Predicate_post_truncsti16(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_post_truncsti32(SDNode *N) {
+inline bool Predicate_post_truncsti32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_post_truncsti8(SDNode *N) {
+inline bool Predicate_post_truncsti8(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_pre_store(SDNode *N) {
+inline bool Predicate_pre_store(SDNode *N) const {
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
}
-inline bool Predicate_pre_truncst(SDNode *N) {
+inline bool Predicate_pre_truncst(SDNode *N) const {
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
}
-inline bool Predicate_pre_truncstf32(SDNode *N) {
+inline bool Predicate_pre_truncstf32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}
-inline bool Predicate_pre_truncsti1(SDNode *N) {
+inline bool Predicate_pre_truncsti1(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_pre_truncsti16(SDNode *N) {
+inline bool Predicate_pre_truncsti16(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_pre_truncsti32(SDNode *N) {
+inline bool Predicate_pre_truncsti32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_pre_truncsti8(SDNode *N) {
+inline bool Predicate_pre_truncsti8(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_rot_imm(SDNode *inN) {
+inline bool Predicate_rot_imm(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
int32_t v = (int32_t)N->getZExtValue();
return v == 8 || v == 16 || v == 24;
}
-inline bool Predicate_sext_16_node(SDNode *N) {
+inline bool Predicate_sext_16_node(SDNode *N) const {
return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
}
-inline bool Predicate_sextload(SDNode *N) {
+inline bool Predicate_sextload(SDNode *N) const {
return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
}
-inline bool Predicate_sextloadi1(SDNode *N) {
+inline bool Predicate_sextloadi1(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_sextloadi16(SDNode *N) {
+inline bool Predicate_sextloadi16(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_sextloadi32(SDNode *N) {
+inline bool Predicate_sextloadi32(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_sextloadi8(SDNode *N) {
+inline bool Predicate_sextloadi8(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_so_imm(SDNode *inN) {
+inline bool Predicate_so_imm(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
}
-inline bool Predicate_so_imm2part(SDNode *inN) {
+inline bool Predicate_so_imm2part(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
}
-inline bool Predicate_so_imm_neg(SDNode *inN) {
+inline bool Predicate_so_imm_neg(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
}
-inline bool Predicate_so_imm_not(SDNode *inN) {
+inline bool Predicate_so_imm_not(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
}
-inline bool Predicate_so_neg_imm2part(SDNode *inN) {
+inline bool Predicate_so_neg_imm2part(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
}
-inline bool Predicate_store(SDNode *N) {
+inline bool Predicate_store(SDNode *N) const {
return !cast<StoreSDNode>(N)->isTruncatingStore();
}
-inline bool Predicate_t2_so_imm(SDNode *inN) {
+inline bool Predicate_sube_dead_carry(SDNode *N) const {
+return !N->hasAnyUseOfValue(1);
+}
+inline bool Predicate_sube_live_carry(SDNode *N) const {
+return N->hasAnyUseOfValue(1);
+}
+inline bool Predicate_t2_so_imm(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
- return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
+ return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
}
-inline bool Predicate_t2_so_imm2part(SDNode *inN) {
+inline bool Predicate_t2_so_imm2part(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
}
-inline bool Predicate_t2_so_imm_neg(SDNode *inN) {
+inline bool Predicate_t2_so_imm_neg(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
}
-inline bool Predicate_t2_so_imm_not(SDNode *inN) {
+inline bool Predicate_t2_so_imm_not(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
}
-inline bool Predicate_t2_so_neg_imm2part(SDNode *inN) {
+inline bool Predicate_t2_so_neg_imm2part(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
}
-inline bool Predicate_thumb_immshifted(SDNode *inN) {
+inline bool Predicate_thumb_immshifted(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
}
-inline bool Predicate_truncstore(SDNode *N) {
+inline bool Predicate_truncstore(SDNode *N) const {
return cast<StoreSDNode>(N)->isTruncatingStore();
}
-inline bool Predicate_truncstoref32(SDNode *N) {
+inline bool Predicate_truncstoref32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}
-inline bool Predicate_truncstoref64(SDNode *N) {
+inline bool Predicate_truncstoref64(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
}
-inline bool Predicate_truncstorei16(SDNode *N) {
+inline bool Predicate_truncstorei16(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_truncstorei32(SDNode *N) {
+inline bool Predicate_truncstorei32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_truncstorei8(SDNode *N) {
+inline bool Predicate_truncstorei8(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_unindexedload(SDNode *N) {
+inline bool Predicate_unindexedload(SDNode *N) const {
return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}
-inline bool Predicate_unindexedstore(SDNode *N) {
+inline bool Predicate_unindexedstore(SDNode *N) const {
return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}
-inline bool Predicate_vfp_f32imm(SDNode *inN) {
+inline bool Predicate_vfp_f32imm(SDNode *inN) const {
ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
}
-inline bool Predicate_vfp_f64imm(SDNode *inN) {
+inline bool Predicate_vfp_f64imm(SDNode *inN) const {
ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
}
-inline bool Predicate_vmovImm16(SDNode *N) {
+inline bool Predicate_vmovImm16(SDNode *N) const {
return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
}
-inline bool Predicate_vmovImm32(SDNode *N) {
+inline bool Predicate_vmovImm32(SDNode *N) const {
return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
}
-inline bool Predicate_vmovImm64(SDNode *N) {
+inline bool Predicate_vmovImm64(SDNode *N) const {
return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
}
-inline bool Predicate_vmovImm8(SDNode *N) {
+inline bool Predicate_vmovImm8(SDNode *N) const {
return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
}
-inline bool Predicate_vtFP(SDNode *inN) {
+inline bool Predicate_vtFP(SDNode *inN) const {
VTSDNode *N = cast<VTSDNode>(inN);
return N->getVT().isFloatingPoint();
}
-inline bool Predicate_vtInt(SDNode *inN) {
+inline bool Predicate_vtInt(SDNode *inN) const {
VTSDNode *N = cast<VTSDNode>(inN);
return N->getVT().isInteger();
}
-inline bool Predicate_zextload(SDNode *N) {
+inline bool Predicate_zextload(SDNode *N) const {
return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
}
-inline bool Predicate_zextloadi1(SDNode *N) {
+inline bool Predicate_zextloadi1(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_zextloadi16(SDNode *N) {
+inline bool Predicate_zextloadi16(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_zextloadi32(SDNode *N) {
+inline bool Predicate_zextloadi32(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_zextloadi8(SDNode *N) {
+inline bool Predicate_zextloadi8(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}
-DISABLE_INLINE SDNode *Emit_0(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N4)->getZExtValue()), MVT::i32);
- SDValue Ops0[] = { N1, N2, N3, Tmp3, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 5);
-}
-SDNode *Select_ARMISD_BR2_JT(SDNode *N) {
- if ((Subtarget->isThumb2())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N4 = N->getOperand(4);
- if (N4.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_0(N, ARM::t2BR_JT);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_1(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
- SDValue Ops0[] = { N1, N2, Tmp2, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_2(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N1.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain1);
- Chain1 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, N2, Tmp2, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
- Chain1 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- const SDValue Froms[] = {
- SDValue(N1.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain1.getNode(), Chain1.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_3(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
- SDValue Ops0[] = { N10, N11, N2, Tmp3, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 5);
-}
-SDNode *Select_ARMISD_BR_JT(SDNode *N) {
- if ((!Subtarget->isThumb())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (ARMbrjt:isVoid (ld:i32 addrmode2:i32:$target)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (tjumptable:i32):$jt, (imm:i32):$id)
- // Emits: (BR_JTm:isVoid addrmode2:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
- // Pattern complexity = 25 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N) &&
- (Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- if (SelectAddrMode2(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_2(N, ARM::BR_JTm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMbrjt:isVoid (add:i32 GPR:i32:$target, GPR:i32:$idx), (tjumptable:i32):$jt, (imm:i32):$id)
- // Emits: (BR_JTadd:isVoid GPR:i32:$target, GPR:i32:$idx, (tjumptable:i32):$jt, (imm:i32):$id)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::ADD) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, ARM::BR_JTadd);
- return Result;
- }
- }
- }
-
- // Pattern: (ARMbrjt:isVoid GPR:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
- // Emits: (BR_JTr:isVoid GPR:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
- // Pattern complexity = 9 cost = 1 size = 0
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_1(N, ARM::BR_JTr);
- return Result;
- }
- }
- }
-
- // Pattern: (ARMbrjt:isVoid tGPR:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
- // Emits: (tBR_JTr:isVoid tGPR:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
- // Pattern complexity = 9 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_1(N, ARM::tBR_JTr);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_4(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(N1);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_ARMISD_CALL(SDNode *N) {
-
- // Pattern: (ARMcall:isVoid (tglobaladdr:iPTR):$func)
- // Emits: (BL:isVoid (tglobaladdr:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_4(N, ARM::BL, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall:isVoid (tglobaladdr:iPTR):$func)
- // Emits: (BLr9:isVoid (tglobaladdr:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_4(N, ARM::BLr9, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall:isVoid (tglobaladdr:iPTR):$func)
- // Emits: (tBLXi:isVoid (tglobaladdr:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_4(N, ARM::tBLXi, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall:isVoid (tglobaladdr:iPTR):$func)
- // Emits: (tBLXi_r9:isVoid (tglobaladdr:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_4(N, ARM::tBLXi_r9, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall:isVoid (texternalsym:iPTR):$func)
- // Emits: (tBLXi:isVoid (texternalsym:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_4(N, ARM::tBLXi, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall:isVoid (texternalsym:iPTR):$func)
- // Emits: (tBLXi_r9:isVoid (texternalsym:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_4(N, ARM::tBLXi_r9, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall:isVoid (texternalsym:iPTR):$func)
- // Emits: (BL:isVoid (texternalsym:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_4(N, ARM::BL, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall:isVoid (texternalsym:iPTR):$func)
- // Emits: (BLr9:isVoid (texternalsym:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_4(N, ARM::BLr9, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall:isVoid GPR:i32:$func)
- // Emits: (BLX:isVoid GPR:i32:$func)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_4(N, ARM::BLX, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall:isVoid GPR:i32:$func)
- // Emits: (BLXr9:isVoid GPR:i32:$func)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_4(N, ARM::BLXr9, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall:isVoid GPR:i32:$dst)
- // Emits: (tBLXr:isVoid GPR:i32:$dst)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_4(N, ARM::tBLXr, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall:isVoid GPR:i32:$dst)
- // Emits: (tBLXr_r9:isVoid GPR:i32:$dst)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_4(N, ARM::tBLXr_r9, 1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_CALL_NOLINK(SDNode *N) {
-
- // Pattern: (ARMcall_nolink:isVoid GPR:i32:$func)
- // Emits: (BX:isVoid GPR:i32:$func)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_4(N, ARM::BX, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall_nolink:isVoid GPR:i32:$func)
- // Emits: (BXr9:isVoid GPR:i32:$func)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_4(N, ARM::BXr9, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall_nolink:isVoid tGPR:i32:$func)
- // Emits: (tBX:isVoid tGPR:i32:$func)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_4(N, ARM::tBX, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall_nolink:isVoid tGPR:i32:$func)
- // Emits: (tBXr9:isVoid tGPR:i32:$func)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_4(N, ARM::tBXr9, 1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_5(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(N1);
- Ops0.push_back(Tmp1);
- Ops0.push_back(Tmp2);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_ARMISD_CALL_PRED(SDNode *N) {
-
- // Pattern: (ARMcall_pred:isVoid (tglobaladdr:iPTR):$func)
- // Emits: (BL_pred:isVoid (tglobaladdr:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_5(N, ARM::BL_pred, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMcall_pred:isVoid (tglobaladdr:iPTR):$func)
- // Emits: (BLr9_pred:isVoid (tglobaladdr:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_5(N, ARM::BLr9_pred, 1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_6(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_7(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_8(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 6);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_9(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 5);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-SDNode *Select_ARMISD_CMP(SDNode *N) {
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Emits: (CMPrs:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_8(N, ARM::CMPrs, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2CMPrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_9(N, ARM::t2CMPrs, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (CMPri:isVoid GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_6(N, ARM::CMPri);
- return Result;
- }
- }
-
- // Pattern: (ARMcmp:isVoid tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_255>>:$rhs)
- // Emits: (tCMPi8:isVoid tGPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm0_255(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_6(N, ARM::tCMPi8);
- return Result;
- }
- }
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2CMPri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_6(N, ARM::t2CMPri);
- return Result;
- }
- }
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$a, GPR:i32:$b)
- // Emits: (CMPrr:isVoid GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_7(N, ARM::CMPrr);
- return Result;
- }
- }
-
- // Pattern: (ARMcmp:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tCMPr:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_7(N, ARM::tCMPr);
- return Result;
- }
- }
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2CMPrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_7(N, ARM::t2CMPrr);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_CMPFP(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (arm_cmpfp:isVoid DPR:f64:$a, DPR:f64:$b)
- // Emits: (VCMPED:isVoid DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_7(N, ARM::VCMPED);
- return Result;
- }
-
- // Pattern: (arm_cmpfp:isVoid SPR:f32:$a, SPR:f32:$b)
- // Emits: (VCMPES:isVoid SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_7(N, ARM::VCMPES);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_10(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, N0, Tmp1, Tmp2);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-SDNode *Select_ARMISD_CMPFPw0(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (arm_cmpfp0:isVoid DPR:f64:$a)
- // Emits: (VCMPEZD:isVoid DPR:f64:$a)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_10(N, ARM::VCMPEZD);
- return Result;
- }
-
- // Pattern: (arm_cmpfp0:isVoid SPR:f32:$a)
- // Emits: (VCMPEZS:isVoid SPR:f32:$a)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_10(N, ARM::VCMPEZS);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_11(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, Tmp3, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_12(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N01, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_13(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 6);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_14(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp3, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_15(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N11, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_16(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 6);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_17(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 5);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_18(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, CPTmpN01_0, CPTmpN01_1, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 5);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_19(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_t2_so_imm_neg_XFORM(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_20(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_so_imm_neg_XFORM(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_21(SDNode *N, unsigned Opc0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1, SDValue &CPTmpN00_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N01, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 6);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_22(SDNode *N, unsigned Opc0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 6);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_23(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, Tmp3, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_24(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N01, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_25(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 6);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_26(SDNode *N, unsigned Opc0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 5);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_27(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 5);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_28(SDNode *N, unsigned Opc0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N01, CPTmpN00_0, CPTmpN00_1, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 5);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-SDNode *Select_ARMISD_CMPZ(SDNode *N) {
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$a, so_reg:i32:$b), 0:i32)
- // Emits: (TSTrs:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- if (SelectShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_13(N, ARM::TSTrs, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$a, so_reg:i32:$b), 0:i32)
- // Emits: (TEQrs:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- if (SelectShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_13(N, ARM::TEQrs, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$a, (sub:i32 0:i32, so_reg:i32:$b))
- // Emits: (CMNzrs:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 23 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- if (SelectShifterOperandReg(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_16(N, ARM::CMNzrs, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (and:i32 so_reg:i32:$b, GPR:i32:$a), 0:i32)
- // Emits: (TSTrs:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue CPTmpN00_0;
- SDValue CPTmpN00_1;
- SDValue CPTmpN00_2;
- if (SelectShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_21(N, ARM::TSTrs, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (xor:i32 so_reg:i32:$b, GPR:i32:$a), 0:i32)
- // Emits: (TEQrs:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue CPTmpN00_0;
- SDValue CPTmpN00_1;
- SDValue CPTmpN00_2;
- if (SelectShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_21(N, ARM::TEQrs, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, so_reg:i32:$b), GPR:i32:$a)
- // Emits: (CMNzrs:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- if (SelectShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2)) {
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_25(N, ARM::CMNzrs, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, (sub:i32 0:i32, t2_so_reg:i32:$rhs))
- // Emits: (t2CMNzrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 20 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- if (SelectT2ShifterOperandReg(N, N11, CPTmpN11_0, CPTmpN11_1) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_17(N, ARM::t2CMNzrs, CPTmpN11_0, CPTmpN11_1);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs), 0:i32)
- // Emits: (t2TSTrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 20 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- if (SelectT2ShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_18(N, ARM::t2TSTrs, CPTmpN01_0, CPTmpN01_1);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs), 0:i32)
- // Emits: (t2TEQrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 20 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- if (SelectT2ShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_18(N, ARM::t2TEQrs, CPTmpN01_0, CPTmpN01_1);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, t2_so_reg:i32:$rhs), GPR:i32:$lhs)
- // Emits: (t2CMNzrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 20 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- if (SelectT2ShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1)) {
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_27(N, ARM::t2CMNzrs, CPTmpN01_0, CPTmpN01_1);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (and:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs), 0:i32)
- // Emits: (t2TSTrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 20 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue CPTmpN00_0;
- SDValue CPTmpN00_1;
- if (SelectT2ShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_28(N, ARM::t2TSTrs, CPTmpN00_0, CPTmpN00_1);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (xor:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs), 0:i32)
- // Emits: (t2TEQrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 20 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue CPTmpN00_0;
- SDValue CPTmpN00_1;
- if (SelectT2ShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_28(N, ARM::t2TEQrs, CPTmpN00_0, CPTmpN00_1);
- return Result;
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b), 0:i32)
- // Emits: (TSTri:isVoid GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_11(N, ARM::TSTri);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b), 0:i32)
- // Emits: (TEQri:isVoid GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_11(N, ARM::TEQri);
- return Result;
- }
- }
- }
- }
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Emits: (CMPzrs:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_8(N, ARM::CMPzrs, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$a, (sub:i32 0:i32, (imm:i32)<<P:Predicate_so_imm>>:$b))
- // Emits: (CMNzri:isVoid GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N11.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_14(N, ARM::CMNzri);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, (sub:i32 0:i32, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs))
- // Emits: (t2CMNzri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N11.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_14(N, ARM::t2CMNzri);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), 0:i32)
- // Emits: (t2TSTri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_11(N, ARM::t2TSTri);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), 0:i32)
- // Emits: (t2TEQri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_11(N, ARM::t2TEQri);
- return Result;
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (ARMcmpZ:isVoid so_reg:i32:$b, GPR:i32:$a)
- // Emits: (CMPzrs:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- SDValue CPTmpN0_2;
- if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_22(N, ARM::CMPzrs, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, (imm:i32)<<P:Predicate_so_imm>>:$b), GPR:i32:$a)
- // Emits: (CMNzri:isVoid GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_23(N, ARM::CMNzri);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), GPR:i32:$lhs)
- // Emits: (t2CMNzri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_23(N, ARM::t2CMNzri);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2CMPzrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_9(N, ARM::t2CMPzrs, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid t2_so_reg:i32:$rhs, GPR:i32:$lhs)
- // Emits: (t2CMPzrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_26(N, ARM::t2CMPzrs, CPTmpN0_0, CPTmpN0_1);
- return Result;
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$a, GPR:i32:$b), 0:i32)
- // Emits: (TSTrr:isVoid GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_12(N, ARM::TSTrr);
- return Result;
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$a, GPR:i32:$b), 0:i32)
- // Emits: (TEQrr:isVoid GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_12(N, ARM::TEQrr);
- return Result;
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$a, (sub:i32 0:i32, GPR:i32:$b))
- // Emits: (CMNzrr:isVoid GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 11 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_15(N, ARM::CMNzrr);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (ARMcmpZ:isVoid tGPR:i32:$lhs, (sub:i32 0:i32, tGPR:i32:$rhs))
- // Emits: (tCMNz:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 11 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_15(N, ARM::tCMNz);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (and:i32 tGPR:i32:$lhs, tGPR:i32:$rhs), 0:i32)
- // Emits: (tTST:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_12(N, ARM::tTST);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, (sub:i32 0:i32, GPR:i32:$rhs))
- // Emits: (t2CMNzrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 11 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_15(N, ARM::t2CMNzrr);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$lhs, GPR:i32:$rhs), 0:i32)
- // Emits: (t2TSTrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_12(N, ARM::t2TSTrr);
- return Result;
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$lhs, GPR:i32:$rhs), 0:i32)
- // Emits: (t2TEQrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_12(N, ARM::t2TEQrr);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, GPR:i32:$b), GPR:i32:$a)
- // Emits: (CMNzrr:isVoid GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 11 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_24(N, ARM::CMNzrr);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, tGPR:i32:$rhs), tGPR:i32:$lhs)
- // Emits: (tCMNz:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 11 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_24(N, ARM::tCMNz);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, GPR:i32:$rhs), GPR:i32:$lhs)
- // Emits: (t2CMNzrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 11 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_24(N, ARM::t2CMNzrr);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (CMPzri:isVoid GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_6(N, ARM::CMPzri);
- return Result;
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_255>>:$rhs)
- // Emits: (tCMPzi8:isVoid tGPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm0_255(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_6(N, ARM::tCMPzi8);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2CMPzri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_t2_so_imm(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_6(N, ARM::t2CMPzri);
- return Result;
- }
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$src, (imm:i32)<<P:Predicate_t2_so_imm_neg>><<X:t2_so_imm_neg_XFORM>>:$imm)
- // Emits: (t2CMNzri:isVoid GPR:i32:$src, (t2_so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_neg>>:$imm))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_t2_so_imm_neg(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_19(N, ARM::t2CMNzri);
- return Result;
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$src, (imm:i32)<<P:Predicate_so_imm_neg>><<X:so_imm_neg_XFORM>>:$imm)
- // Emits: (CMNzri:isVoid GPR:i32:$src, (so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_so_imm_neg>>:$imm))
- // Pattern complexity = 7 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm_neg(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_20(N, ARM::CMNzri);
- return Result;
- }
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$a, GPR:i32:$b)
- // Emits: (CMPzrr:isVoid GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_7(N, ARM::CMPzrr);
- return Result;
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tCMPzr:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_7(N, ARM::tCMPzr);
- return Result;
- }
- }
-
- // Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2CMPzrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_7(N, ARM::t2CMPzrr);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_29(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, N1);
-}
-SDNode *Select_ARMISD_EH_SJLJ_SETJMP_i32(SDNode *N) {
-
- // Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src, GPR:i32:$val)
- // Emits: (Int_eh_sjlj_setjmp:isVoid GPR:i32:$src, GPR:i32:$val)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_29(N, ARM::Int_eh_sjlj_setjmp);
- return Result;
- }
- }
-
- // Pattern: (ARMeh_sjlj_setjmp:i32 tGPR:i32:$src, tGPR:i32:$val)
- // Emits: (tInt_eh_sjlj_setjmp:isVoid tGPR:i32:$src, tGPR:i32:$val)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_29(N, ARM::tInt_eh_sjlj_setjmp);
- return Result;
- }
- }
-
- // Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src, tGPR:i32:$val)
- // Emits: (t2Int_eh_sjlj_setjmp:isVoid GPR:i32:$src, tGPR:i32:$val)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_29(N, ARM::t2Int_eh_sjlj_setjmp);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_30(SDNode *N, unsigned Opc0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp1 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N->getOperand(0);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Tmp0, Tmp1, InFlag);
- InFlag = SDValue(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-SDNode *Select_ARMISD_FMSTAT(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDNode *Result = Emit_30(N, ARM::FMSTAT);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_31(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_32(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp0, N0, Tmp2), 0);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp6(CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Tmp3, Tmp4, Tmp5), 0);
- SDValue Tmp7 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc3, VT3, Tmp6, Tmp7);
-}
-SDNode *Select_ARMISD_FTOSI_f32(SDNode *N) {
-
- // Pattern: (arm_ftosi:f32 DPR:f64:$a)
- // Emits: (VTOSIZD:f32 DPR:f64:$a)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasVFP2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_31(N, ARM::VTOSIZD, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (arm_ftosi:f32 SPR:f32:$a)
- // Emits: (VTOSIZS:f32 SPR:f32:$a)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_31(N, ARM::VTOSIZS, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (arm_ftosi:f32 SPR:f32:$a)
- // Emits: (EXTRACT_SUBREG:f32 (VCVTf2sd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
- // Pattern complexity = 3 cost = 4 size = 0
- if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VCVTf2sd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_FTOUI_f32(SDNode *N) {
-
- // Pattern: (arm_ftoui:f32 DPR:f64:$a)
- // Emits: (VTOUIZD:f32 DPR:f64:$a)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasVFP2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_31(N, ARM::VTOUIZD, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (arm_ftoui:f32 SPR:f32:$a)
- // Emits: (VTOUIZS:f32 SPR:f32:$a)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_31(N, ARM::VTOUIZS, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (arm_ftoui:f32 SPR:f32:$a)
- // Emits: (EXTRACT_SUBREG:f32 (VCVTf2ud_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
- // Pattern complexity = 3 cost = 4 size = 0
- if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VCVTf2ud_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_33(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
-}
-DISABLE_INLINE SDNode *Emit_34(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, N1, Chain);
-}
-SDNode *Select_ARMISD_MEMBARRIER(SDNode *N) {
-
- // Pattern: (ARMMemBarrierV7:isVoid)
- // Emits: (Int_MemBarrierV7:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV7Ops())) {
- SDNode *Result = Emit_33(N, ARM::Int_MemBarrierV7);
- return Result;
- }
-
- // Pattern: (ARMMemBarrierV6:isVoid GPR:i32:$zero)
- // Emits: (Int_MemBarrierV6:isVoid GPR:i32:$zero)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_34(N, ARM::Int_MemBarrierV6);
- return Result;
- }
- }
-
- // Pattern: (ARMMemBarrierV7:isVoid)
- // Emits: (t2Int_MemBarrierV7:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_33(N, ARM::t2Int_MemBarrierV7);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_35(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_36(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_37(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, N010, Tmp1, Chain0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ARMISD_PIC_ADD_i32(SDNode *N) {
-
- // Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
- // Emits: (tLDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
- // Pattern complexity = 16 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_37(N, ARM::tLDRpci_pic, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
- // Emits: (t2LDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
- // Pattern complexity = 16 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_37(N, ARM::t2LDRpci_pic, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (ARMpic_add:i32 GPR:i32:$a, (imm:i32):$cp)
- // Emits: (PICADD:i32 GPR:i32:$a, (imm:i32):$cp)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::PICADD, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (ARMpic_add:i32 GPR:i32:$lhs, (imm:i32):$cp)
- // Emits: (tPICADD:i32 GPR:i32:$lhs, (imm:i32):$cp)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_36(N, ARM::tPICADD, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_RBIT_i32(SDNode *N) {
-
- // Pattern: (ARMrbit:i32 GPR:i32:$src)
- // Emits: (RBIT:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
- SDNode *Result = Emit_31(N, ARM::RBIT, MVT::i32);
- return Result;
- }
-
- // Pattern: (ARMrbit:i32 GPR:i32:$src)
- // Emits: (t2RBIT:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_31(N, ARM::t2RBIT, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_38(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SDValue Tmp0 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp1 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- SDValue Ops0[] = { Tmp0, Tmp1, Chain, InFlag };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, HasInFlag ? 4 : 3);
-}
-DISABLE_INLINE SDNode *Emit_39(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- SDValue Ops0[] = { Chain, InFlag };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, HasInFlag ? 2 : 1);
-}
-SDNode *Select_ARMISD_RET_FLAG(SDNode *N) {
-
- // Pattern: (ARMretflag:isVoid)
- // Emits: (BX_RET:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDNode *Result = Emit_38(N, ARM::BX_RET);
- return Result;
- }
-
- // Pattern: (ARMretflag:isVoid)
- // Emits: (tBX_RET:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb())) {
- SDNode *Result = Emit_39(N, ARM::tBX_RET);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_40(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N->getOperand(1);
- SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, InFlag };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-SDNode *Select_ARMISD_RRX_i32(SDNode *N) {
-
- // Pattern: (ARMrrx:i32 GPR:i32:$src)
- // Emits: (MOVrx:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDNode *Result = Emit_40(N, ARM::MOVrx, MVT::i32);
- return Result;
- }
-
- // Pattern: (ARMrrx:i32 GPR:i32:$src)
- // Emits: (t2MOVrx:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_40(N, ARM::t2MOVrx, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_SITOF_f32(SDNode *N) {
-
- // Pattern: (arm_sitof:f32 SPR:f32:$a)
- // Emits: (VSITOS:f32 SPR:f32:$a)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_31(N, ARM::VSITOS, MVT::f32);
- return Result;
- }
-
- // Pattern: (arm_sitof:f32 SPR:f32:$a)
- // Emits: (EXTRACT_SUBREG:f32 (VCVTs2fd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2i32), SPR:f32:$a, 1:i32)), 1:i32)
- // Pattern complexity = 3 cost = 4 size = 0
- if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VCVTs2fd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2i32, MVT::f64, MVT::f64, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_SITOF_f64(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDNode *Result = Emit_31(N, ARM::VSITOD, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_41(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1, Tmp2);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_42(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ARMISD_SRA_FLAG_i32(SDNode *N) {
-
- // Pattern: (ARMsra_flag:i32 GPR:i32:$src)
- // Emits: (MOVsra_flag:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDNode *Result = Emit_41(N, ARM::MOVsra_flag, MVT::i32);
- return Result;
- }
-
- // Pattern: (ARMsra_flag:i32 GPR:i32:$src)
- // Emits: (t2MOVsra_flag:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_42(N, ARM::t2MOVsra_flag, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_SRL_FLAG_i32(SDNode *N) {
-
- // Pattern: (ARMsrl_flag:i32 GPR:i32:$src)
- // Emits: (MOVsrl_flag:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDNode *Result = Emit_41(N, ARM::MOVsrl_flag, MVT::i32);
- return Result;
- }
-
- // Pattern: (ARMsrl_flag:i32 GPR:i32:$src)
- // Emits: (t2MOVsrl_flag:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_42(N, ARM::t2MOVsrl_flag, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_SYNCBARRIER(SDNode *N) {
-
- // Pattern: (ARMSyncBarrierV7:isVoid)
- // Emits: (Int_SyncBarrierV7:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV7Ops())) {
- SDNode *Result = Emit_33(N, ARM::Int_SyncBarrierV7);
- return Result;
- }
-
- // Pattern: (ARMSyncBarrierV6:isVoid GPR:i32:$zero)
- // Emits: (Int_SyncBarrierV6:isVoid GPR:i32:$zero)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_34(N, ARM::Int_SyncBarrierV6);
- return Result;
- }
- }
-
- // Pattern: (ARMSyncBarrierV7:isVoid)
- // Emits: (t2Int_SyncBarrierV7:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_33(N, ARM::t2Int_SyncBarrierV7);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_43(SDNode *N, unsigned Opc0) {
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32);
-}
-SDNode *Select_ARMISD_THREAD_POINTER_i32(SDNode *N) {
-
- // Pattern: (ARMthread_pointer:i32)
- // Emits: (TPsoft:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDNode *Result = Emit_43(N, ARM::TPsoft);
- return Result;
- }
-
- // Pattern: (ARMthread_pointer:i32)
- // Emits: (tTPsoft:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb())) {
- SDNode *Result = Emit_43(N, ARM::tTPsoft);
- return Result;
- }
-
- // Pattern: (ARMthread_pointer:i32)
- // Emits: (t2TPsoft:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_43(N, ARM::t2TPsoft);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_UITOF_f32(SDNode *N) {
-
- // Pattern: (arm_uitof:f32 SPR:f32:$a)
- // Emits: (VUITOS:f32 SPR:f32:$a)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_31(N, ARM::VUITOS, MVT::f32);
- return Result;
- }
-
- // Pattern: (arm_uitof:f32 SPR:f32:$a)
- // Emits: (EXTRACT_SUBREG:f32 (VCVTu2fd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2i32), SPR:f32:$a, 1:i32)), 1:i32)
- // Pattern complexity = 3 cost = 4 size = 0
- if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VCVTu2fd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2i32, MVT::f64, MVT::f64, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_UITOF_f64(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDNode *Result = Emit_31(N, ARM::VUITOD, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_44(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ARMISD_VCEQ_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_44(N, ARM::VCEQv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCEQ_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_44(N, ARM::VCEQv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCEQ_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_44(N, ARM::VCEQv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCEQ_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_44(N, ARM::VCEQv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCEQ_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (NEONvceq:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VCEQv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_44(N, ARM::VCEQv2i32, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (NEONvceq:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VCEQfd:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_44(N, ARM::VCEQfd, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCEQ_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (NEONvceq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VCEQv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_44(N, ARM::VCEQv4i32, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (NEONvceq:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VCEQfq:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_44(N, ARM::VCEQfq, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGE_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_44(N, ARM::VCGEsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGE_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_44(N, ARM::VCGEsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGE_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_44(N, ARM::VCGEsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGE_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_44(N, ARM::VCGEsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGE_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (NEONvcge:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VCGEsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_44(N, ARM::VCGEsv2i32, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (NEONvcge:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VCGEfd:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_44(N, ARM::VCGEfd, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGE_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (NEONvcge:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VCGEsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_44(N, ARM::VCGEsv4i32, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (NEONvcge:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VCGEfq:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_44(N, ARM::VCGEfq, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGEU_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_44(N, ARM::VCGEuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGEU_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_44(N, ARM::VCGEuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGEU_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_44(N, ARM::VCGEuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGEU_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_44(N, ARM::VCGEuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGEU_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_44(N, ARM::VCGEuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGEU_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_44(N, ARM::VCGEuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGT_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_44(N, ARM::VCGTsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGT_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_44(N, ARM::VCGTsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGT_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_44(N, ARM::VCGTsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGT_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_44(N, ARM::VCGTsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGT_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (NEONvcgt:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VCGTsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_44(N, ARM::VCGTsv2i32, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (NEONvcgt:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VCGTfd:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_44(N, ARM::VCGTfd, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGT_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (NEONvcgt:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VCGTsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_44(N, ARM::VCGTsv4i32, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (NEONvcgt:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VCGTfq:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_44(N, ARM::VCGTfq, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGTU_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_44(N, ARM::VCGTuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGTU_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_44(N, ARM::VCGTuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGTU_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_44(N, ARM::VCGTuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGTU_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_44(N, ARM::VCGTuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGTU_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_44(N, ARM::VCGTuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VCGTU_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_44(N, ARM::VCGTuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUP_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_31(N, ARM::VDUP8d, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUP_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_31(N, ARM::VDUP8q, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUP_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_31(N, ARM::VDUP16d, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUP_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_31(N, ARM::VDUP16q, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUP_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_31(N, ARM::VDUP32d, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUP_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_31(N, ARM::VDUP32q, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_45(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, Tmp1, Tmp2);
-}
-SDNode *Select_ARMISD_VDUP_v2f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (NEONvdup:v2f32 (bitconvert:f32 GPR:i32:$src))
- // Emits: (VDUPfd:v2f32 GPR:i32:$src)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N0.getValueType() == MVT::f32 &&
- N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_45(N, ARM::VDUPfd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (NEONvdup:v2f32 SPR:f32:$src)
- // Emits: (VDUPfdf:v2f32 SPR:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_31(N, ARM::VDUPfdf, MVT::v2f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUP_v4f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (NEONvdup:v4f32 (bitconvert:f32 GPR:i32:$src))
- // Emits: (VDUPfq:v4f32 GPR:i32:$src)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N0.getValueType() == MVT::f32 &&
- N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_45(N, ARM::VDUPfq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (NEONvdup:v4f32 SPR:f32:$src)
- // Emits: (VDUPfqf:v4f32 SPR:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_31(N, ARM::VDUPfqf, MVT::v4f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUPLANE_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_35(N, ARM::VDUPLN8d, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_46(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_DSubReg_i8_reg(Tmp1.getNode());
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
- SDValue Tmp4 = Transform_SubReg_i8_lane(Tmp1.getNode());
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp3, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 4);
-}
-SDNode *Select_ARMISD_VDUPLANE_v16i8(SDNode *N) {
-
- // Pattern: (NEONvduplane:v16i8 DPR:v8i8:$src, (imm:i32):$lane)
- // Emits: (VDUPLN8q:v16i8 DPR:v8i8:$src, (imm:i32):$lane)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_35(N, ARM::VDUPLN8q, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (NEONvduplane:v16i8 QPR:v16i8:$src, (imm:i32):$lane)
- // Emits: (VDUPLN8q:v16i8 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 6 cost = 2 size = 0
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_46(N, TargetOpcode::EXTRACT_SUBREG, ARM::VDUPLN8q, MVT::v8i8, MVT::v16i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUPLANE_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_35(N, ARM::VDUPLN16d, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_47(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_DSubReg_i16_reg(Tmp1.getNode());
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
- SDValue Tmp4 = Transform_SubReg_i16_lane(Tmp1.getNode());
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp3, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 4);
-}
-SDNode *Select_ARMISD_VDUPLANE_v8i16(SDNode *N) {
-
- // Pattern: (NEONvduplane:v8i16 DPR:v4i16:$src, (imm:i32):$lane)
- // Emits: (VDUPLN16q:v8i16 DPR:v4i16:$src, (imm:i32):$lane)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_35(N, ARM::VDUPLN16q, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (NEONvduplane:v8i16 QPR:v8i16:$src, (imm:i32):$lane)
- // Emits: (VDUPLN16q:v8i16 (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 6 cost = 2 size = 0
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_47(N, TargetOpcode::EXTRACT_SUBREG, ARM::VDUPLN16q, MVT::v4i16, MVT::v8i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUPLANE_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_35(N, ARM::VDUPLN32d, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_48(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_DSubReg_i32_reg(Tmp1.getNode());
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
- SDValue Tmp4 = Transform_SubReg_i32_lane(Tmp1.getNode());
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp3, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 4);
-}
-SDNode *Select_ARMISD_VDUPLANE_v4i32(SDNode *N) {
-
- // Pattern: (NEONvduplane:v4i32 DPR:v2i32:$src, (imm:i32):$lane)
- // Emits: (VDUPLN32q:v4i32 DPR:v2i32:$src, (imm:i32):$lane)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_35(N, ARM::VDUPLN32q, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (NEONvduplane:v4i32 QPR:v4i32:$src, (imm:i32):$lane)
- // Emits: (VDUPLN32q:v4i32 (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 6 cost = 2 size = 0
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_48(N, TargetOpcode::EXTRACT_SUBREG, ARM::VDUPLN32q, MVT::v2i32, MVT::v4i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_49(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_DSubReg_f64_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp3), 0);
- SDValue Tmp5 = Transform_DSubReg_f64_other_reg(Tmp2.getNode());
- return CurDAG->SelectNodeTo(N, Opc1, VT1, N0, Tmp4, Tmp5);
-}
-SDNode *Select_ARMISD_VDUPLANE_v2i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_49(N, TargetOpcode::EXTRACT_SUBREG, TargetOpcode::INSERT_SUBREG, MVT::i64, MVT::v2i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUPLANE_v2f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_35(N, ARM::VDUPLNfd, MVT::v2f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUPLANE_v4f32(SDNode *N) {
-
- // Pattern: (NEONvduplane:v4f32 DPR:v2f32:$src, (imm:i32):$lane)
- // Emits: (VDUPLNfq:v4f32 DPR:v2f32:$src, (imm:i32):$lane)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_35(N, ARM::VDUPLNfq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (NEONvduplane:v4f32 QPR:v4f32:$src, (imm:i32):$lane)
- // Emits: (VDUPLNfq:v4f32 (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 6 cost = 2 size = 0
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_48(N, TargetOpcode::EXTRACT_SUBREG, ARM::VDUPLNfq, MVT::v2f32, MVT::v4f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VDUPLANE_v2f64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_49(N, TargetOpcode::EXTRACT_SUBREG, TargetOpcode::INSERT_SUBREG, MVT::f64, MVT::v2f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_50(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-SDNode *Select_ARMISD_VEXT_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VEXTd8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VEXT_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VEXTq8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VEXT_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VEXTd16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VEXT_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VEXTq16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VEXT_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VEXTd32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VEXT_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VEXTq32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VEXT_v2f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VEXTdf, MVT::v2f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VEXT_v4f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VEXTqf, MVT::v4f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VGETLANEs_i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (NEONvgetlanes:i32 DPR:v8i8:$src, (imm:i32):$lane)
- // Emits: (VGETLNs8:i32 DPR:v8i8:$src, (imm:i32):$lane)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_35(N, ARM::VGETLNs8, MVT::i32);
- return Result;
- }
-
- // Pattern: (NEONvgetlanes:i32 DPR:v4i16:$src, (imm:i32):$lane)
- // Emits: (VGETLNs16:i32 DPR:v4i16:$src, (imm:i32):$lane)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_35(N, ARM::VGETLNs16, MVT::i32);
- return Result;
- }
- }
- }
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (NEONvgetlanes:i32 QPR:v16i8:$src, (imm:i32):$lane)
- // Emits: (VGETLNs8:i32 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 6 cost = 2 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_46(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNs8, MVT::v8i8, MVT::i32);
- return Result;
- }
-
- // Pattern: (NEONvgetlanes:i32 QPR:v8i16:$src, (imm:i32):$lane)
- // Emits: (VGETLNs16:i32 (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 6 cost = 2 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_47(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNs16, MVT::v4i16, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VGETLANEu_i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (NEONvgetlaneu:i32 DPR:v8i8:$src, (imm:i32):$lane)
- // Emits: (VGETLNu8:i32 DPR:v8i8:$src, (imm:i32):$lane)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_35(N, ARM::VGETLNu8, MVT::i32);
- return Result;
- }
-
- // Pattern: (NEONvgetlaneu:i32 DPR:v4i16:$src, (imm:i32):$lane)
- // Emits: (VGETLNu16:i32 DPR:v4i16:$src, (imm:i32):$lane)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_35(N, ARM::VGETLNu16, MVT::i32);
- return Result;
- }
- }
- }
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (NEONvgetlaneu:i32 QPR:v16i8:$src, (imm:i32):$lane)
- // Emits: (VGETLNu8:i32 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 6 cost = 2 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_46(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNu8, MVT::v8i8, MVT::i32);
- return Result;
- }
-
- // Pattern: (NEONvgetlaneu:i32 QPR:v8i16:$src, (imm:i32):$lane)
- // Emits: (VGETLNu16:i32 (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 6 cost = 2 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_47(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNu16, MVT::v4i16, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VMOVDRR_f64(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDNode *Result = Emit_44(N, ARM::VMOVDRR, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQRSHRNs_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_35(N, ARM::VQRSHRNsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQRSHRNs_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_35(N, ARM::VQRSHRNsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQRSHRNs_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_35(N, ARM::VQRSHRNsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQRSHRNsu_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_35(N, ARM::VQRSHRUNv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQRSHRNsu_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_35(N, ARM::VQRSHRUNv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQRSHRNsu_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_35(N, ARM::VQRSHRUNv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQRSHRNu_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_35(N, ARM::VQRSHRNuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQRSHRNu_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_35(N, ARM::VQRSHRNuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQRSHRNu_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_35(N, ARM::VQRSHRNuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLs_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsiv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLs_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsiv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLs_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsiv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLs_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsiv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLs_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsiv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLs_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsiv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLs_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsiv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLs_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsiv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLsu_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLsu_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLsu_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLsu_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLsu_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLsu_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLsu_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsuv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLsu_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLsuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLu_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLuiv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLu_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLuiv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLu_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLuiv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLu_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLuiv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLu_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLuiv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLu_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLuiv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLu_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLuiv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHLu_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VQSHLuiv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHRNs_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_35(N, ARM::VQSHRNsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHRNs_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_35(N, ARM::VQSHRNsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHRNs_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_35(N, ARM::VQSHRNsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHRNsu_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_35(N, ARM::VQSHRUNv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHRNsu_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_35(N, ARM::VQSHRUNv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHRNsu_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_35(N, ARM::VQSHRUNv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHRNu_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_35(N, ARM::VQSHRNuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHRNu_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_35(N, ARM::VQSHRNuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VQSHRNu_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_35(N, ARM::VQSHRNuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV16_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV16d8, MVT::v8i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV16_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV16q8, MVT::v16i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV32_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV32d8, MVT::v8i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV32_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV32q8, MVT::v16i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV32_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV32d16, MVT::v4i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV32_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV32q16, MVT::v8i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV64_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV64d8, MVT::v8i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV64_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV64q8, MVT::v16i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV64_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV64d16, MVT::v4i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV64_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV64q16, MVT::v8i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV64_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV64d32, MVT::v2i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV64_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV64q32, MVT::v4i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV64_v2f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV64df, MVT::v2f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VREV64_v4f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VREV64qf, MVT::v4f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRN_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_35(N, ARM::VRSHRNv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRN_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_35(N, ARM::VRSHRNv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRN_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_35(N, ARM::VRSHRNv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRs_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRs_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRs_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRs_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRs_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRs_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRs_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRsv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRs_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRu_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRu_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRu_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRu_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRu_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRu_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRu_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRuv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VRSHRu_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VRSHRuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHL_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHLiv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHL_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHLiv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHL_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHLiv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHL_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHLiv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHL_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHLiv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHL_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHLiv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHL_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHLiv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHL_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHLiv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHLLi_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_35(N, ARM::VSHLLi8, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHLLi_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_35(N, ARM::VSHLLi16, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHLLi_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_35(N, ARM::VSHLLi32, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHLLs_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_35(N, ARM::VSHLLsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHLLs_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_35(N, ARM::VSHLLsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHLLs_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_35(N, ARM::VSHLLsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHLLu_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_35(N, ARM::VSHLLuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHLLu_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_35(N, ARM::VSHLLuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHLLu_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_35(N, ARM::VSHLLuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRN_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_35(N, ARM::VSHRNv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRN_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_35(N, ARM::VSHRNv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRN_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_35(N, ARM::VSHRNv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRs_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRs_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRs_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRs_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRs_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRs_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRs_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRsv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRs_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRu_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRu_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRu_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRu_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRu_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRu_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRu_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRuv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSHRu_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::VSHRuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSLI_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSLIv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSLI_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSLIv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSLI_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSLIv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSLI_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSLIv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSLI_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSLIv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSLI_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSLIv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSLI_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSLIv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSLI_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSLIv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSRI_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSRIv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSRI_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSRIv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSRI_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSRIv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSRI_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSRIv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSRI_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSRIv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSRI_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSRIv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSRI_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSRIv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VSRI_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSRIv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VTST_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_44(N, ARM::VTSTv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VTST_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_44(N, ARM::VTSTv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VTST_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_44(N, ARM::VTSTv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VTST_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_44(N, ARM::VTSTv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VTST_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_44(N, ARM::VTSTv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_VTST_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_44(N, ARM::VTSTv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_Wrapper_i32(SDNode *N) {
-
- // Pattern: (ARMWrapper:i32 (tglobaladdr:i32):$dst)
- // Emits: (t2LEApcrel:i32 (tglobaladdr:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!Subtarget->useMovt())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_31(N, ARM::t2LEApcrel, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (ARMWrapper:i32 (tconstpool:i32):$dst)
- // Emits: (t2LEApcrel:i32 (tconstpool:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_31(N, ARM::t2LEApcrel, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (ARMWrapper:i32 (tglobaladdr:i32):$dst)
- // Emits: (t2MOVi32imm:i32 (tglobaladdr:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (Subtarget->useMovt())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_31(N, ARM::t2MOVi32imm, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (ARMWrapper:i32 (tglobaladdr:i32):$dst)
- // Emits: (LEApcrel:i32 (tglobaladdr:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!Subtarget->useMovt())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_31(N, ARM::LEApcrel, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (ARMWrapper:i32 (tconstpool:i32):$dst)
- // Emits: (LEApcrel:i32 (tconstpool:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_31(N, ARM::LEApcrel, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (ARMWrapper:i32 (tglobaladdr:i32):$dst)
- // Emits: (MOVi32imm:i32 (tglobaladdr:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->useMovt())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_31(N, ARM::MOVi32imm, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (ARMWrapper:i32 (tglobaladdr:i32):$dst)
- // Emits: (tLEApcrel:i32 (tglobaladdr:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_31(N, ARM::tLEApcrel, MVT::i32);
- return Result;
- }
-
- // Pattern: (ARMWrapper:i32 (tconstpool:i32):$dst)
- // Emits: (tLEApcrel:i32 (tconstpool:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_31(N, ARM::tLEApcrel, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_WrapperJT_i32(SDNode *N) {
-
- // Pattern: (ARMWrapperJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
- // Emits: (t2LEApcrelJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
- // Pattern complexity = 9 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::t2LEApcrelJT, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (ARMWrapperJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
- // Emits: (LEApcrelJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
- // Pattern complexity = 9 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::LEApcrelJT, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (ARMWrapperJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
- // Emits: (tLEApcrelJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
- // Pattern complexity = 9 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_35(N, ARM::tLEApcrelJT, MVT::i32);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ARMISD_tCALL(SDNode *N) {
-
- // Pattern: (ARMtcall:isVoid (tglobaladdr:iPTR):$func)
- // Emits: (tBL:isVoid (tglobaladdr:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_4(N, ARM::tBL, 1);
- return Result;
- }
- }
- if ((Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (ARMtcall:isVoid (tglobaladdr:iPTR):$func)
- // Emits: (tBLr9:isVoid (tglobaladdr:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_4(N, ARM::tBLr9, 1);
- return Result;
- }
-
- // Pattern: (ARMtcall:isVoid (texternalsym:iPTR):$func)
- // Emits: (tBLr9:isVoid (texternalsym:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_4(N, ARM::tBLr9, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMtcall:isVoid (texternalsym:iPTR):$func)
- // Emits: (tBL:isVoid (texternalsym:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_4(N, ARM::tBL, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMtcall:isVoid GPR:i32:$func)
- // Emits: (tBLXr:isVoid GPR:i32:$func)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_4(N, ARM::tBLXr, 1);
- return Result;
- }
- }
-
- // Pattern: (ARMtcall:isVoid GPR:i32:$func)
- // Emits: (tBLXr_r9:isVoid GPR:i32:$func)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_4(N, ARM::tBLXr_r9, 1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_51(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N10, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_52(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N100, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_53(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N10, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_54(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N100, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_55(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_56(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_57(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 7);
-}
-DISABLE_INLINE SDNode *Emit_58(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N01, N1, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_59(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N01, N1, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_60(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N100, N110, N0, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_61(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N100, N110, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_62(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N100, N110, N0, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_63(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N100, N1010, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_64(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N100, N1010, N0, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_65(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, N0, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_66(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, N0, N1, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_67(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_imm_neg_XFORM(Tmp2.getNode());
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, N0, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_68(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_69(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_imm_neg_XFORM(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_70(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_t2_so_imm_neg_XFORM(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_71(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_t2_so_imm2part_1(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Ops0, 5), 0);
- SDValue Tmp7 = Transform_t2_so_imm2part_2(Tmp1.getNode());
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp6, Tmp7, Tmp8, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-DISABLE_INLINE SDNode *Emit_72(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_t2_so_neg_imm2part_1(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Ops0, 5), 0);
- SDValue Tmp7 = Transform_t2_so_neg_imm2part_2(Tmp1.getNode());
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp6, Tmp7, Tmp8, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-DISABLE_INLINE SDNode *Emit_73(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_so_imm_neg_XFORM(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_74(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_so_imm2part_1(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Ops0, 5), 0);
- SDValue Tmp7 = Transform_so_imm2part_2(Tmp1.getNode());
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp6, Tmp7, Tmp8, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-DISABLE_INLINE SDNode *Emit_75(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_so_neg_imm2part_1(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Ops0, 5), 0);
- SDValue Tmp7 = Transform_so_neg_imm2part_2(Tmp1.getNode());
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp6, Tmp7, Tmp8, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-DISABLE_INLINE SDNode *Emit_76(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1000, N1100, N0, Tmp11, Tmp12 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_77(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N10, N11, N0, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_78(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1000, N110, N0, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_79(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N10, N110, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_80(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N100, N1100, N0, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_81(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N100, N11, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_82(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N10100 = N1010.getNode()->getOperand(0);
- SDValue N10101 = N1010.getNode()->getOperand(1);
- SDValue N1011 = N101.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N100, N10100, N0, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_83(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N100, N101, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_84(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N00, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_85(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N000, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_86(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N00, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_87(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N000, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_88(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 7);
-}
-DISABLE_INLINE SDNode *Emit_89(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N10, N11, N0, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_90(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N010, N1, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_91(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N110, N100, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_92(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N010, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_93(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N010, N000, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_94(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N110, N100, N0, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_95(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N010, N1, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_96(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N010, N000, N1, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_97(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N101, N1000, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_98(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N0010, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_99(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N001, N0000, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_100(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N101, N1000, N0, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_101(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N0010, N1, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_102(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N001, N0000, N1, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_103(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_104(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1100, N1000, N0, Tmp11, Tmp12 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_105(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0000, N0100, N1, Tmp11, Tmp12 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_106(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0100, N0000, N1, Tmp11, Tmp12 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_107(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1100, N100, N0, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_108(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0000, N010, N1, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_109(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0100, N000, N1, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_110(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N11, N100, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_111(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N010, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_112(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N01, N000, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_113(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N110, N1000, N0, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_114(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N0100, N1, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_115(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N010, N0000, N1, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_116(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N110, N10, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_117(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N01, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_118(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N010, N00, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_119(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N10000 = N1000.getNode()->getOperand(0);
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N101, N10000, N0, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_120(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N00100 = N0010.getNode()->getOperand(0);
- SDValue N00101 = N0010.getNode()->getOperand(1);
- SDValue N0011 = N001.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N00100, N1, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_121(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N001, N00000, N1, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_122(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N101, N100, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_123(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N001, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_124(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N001, N000, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-SDNode *Select_ISD_ADD_i32(SDNode *N) {
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp6) {
- int64_t CN7 = Tmp6->getSExtValue();
- if (CN7 == INT64_C(16) &&
- N1001.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i32) {
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)))
- // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 38 cost = 1 size = 0
- {
- SDNode *Result = Emit_76(N, ARM::SMLABB, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32)))
- // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 38 cost = 1 size = 0
- SDNode *Result = Emit_104(N, ARM::SMLABB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6) {
- int64_t CN7 = Tmp6->getSExtValue();
- if (CN7 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N0001.getValueType() == MVT::i32 &&
- N001.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), GPR:i32:$acc)
- // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 38 cost = 1 size = 0
- {
- SDNode *Result = Emit_105(N, ARM::SMLABB, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32)), GPR:i32:$acc)
- // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 38 cost = 1 size = 0
- SDNode *Result = Emit_106(N, ARM::SMLABB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
-
- // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32))
- // Emits: (UXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 34 cost = 1 size = 0
- if (CheckAndMask(N10, Tmp0, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N101.getNode()) &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_54(N, ARM::UXTABrr_rot, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 65535:i32))
- // Emits: (UXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 34 cost = 1 size = 0
- if (CheckAndMask(N10, Tmp0, INT64_C(65535)) &&
- N10.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N101.getNode()) &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_54(N, ARM::UXTAHrr_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
-
- // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32))
- // Emits: (t2UXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 34 cost = 1 size = 0
- if (CheckAndMask(N10, Tmp0, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N101.getNode()) &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_54(N, ARM::t2UXTABrr_rot, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 65535:i32))
- // Emits: (t2UXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 34 cost = 1 size = 0
- if (CheckAndMask(N10, Tmp0, INT64_C(65535)) &&
- N10.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N101.getNode()) &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_54(N, ARM::t2UXTAHrr_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
-
- // Pattern: (add:i32 (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32), GPR:i32:$LHS)
- // Emits: (UXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 34 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N001.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_87(N, ARM::UXTABrr_rot, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i32 (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 65535:i32), GPR:i32:$LHS)
- // Emits: (UXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 34 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(65535)) &&
- N00.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N001.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_87(N, ARM::UXTAHrr_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
-
- // Pattern: (add:i32 (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32), GPR:i32:$LHS)
- // Emits: (t2UXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 34 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N001.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_87(N, ARM::t2UXTABrr_rot, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i32 (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 65535:i32), GPR:i32:$LHS)
- // Emits: (t2UXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 34 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(65535)) &&
- N00.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N001.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_87(N, ARM::t2UXTAHrr_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 GPR:i32:$b, 16:i32)))
- // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 30 cost = 1 size = 0
- if (N100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16) &&
- N1001.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_78(N, ARM::SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)))
- // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 30 cost = 1 size = 0
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16) &&
- N101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_80(N, ARM::SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), 16:i32))
- // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 30 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SRA) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- if (N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16) &&
- N10101.getValueType() == MVT::i32 &&
- N1011.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_82(N, ARM::SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32)))
- // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 30 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16) &&
- N101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_107(N, ARM::SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
- // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 30 cost = 1 size = 0
- if (N000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N0001.getValueType() == MVT::i32 &&
- N001.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_108(N, ARM::SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32)), GPR:i32:$acc)
- // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 30 cost = 1 size = 0
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_109(N, ARM::SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 GPR:i32:$a, 16:i32)))
- // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 30 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16) &&
- N1001.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_113(N, ARM::SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), GPR:i32:$acc)
- // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 30 cost = 1 size = 0
- {
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_114(N, ARM::SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
- // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 30 cost = 1 size = 0
- if (N000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N0001.getValueType() == MVT::i32 &&
- N001.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_115(N, ARM::SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), GPR:i32:$a), 16:i32))
- // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 30 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SRA) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16) &&
- N10001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_119(N, ARM::SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::MUL) {
- SDValue N000 = N00.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), 16:i32), GPR:i32:$acc)
- // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 30 cost = 1 size = 0
- {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::SRA) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- if (N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N00101.getValueType() == MVT::i32 &&
- N0011.getValueType() == MVT::i32 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_120(N, ARM::SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (sra:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), GPR:i32:$a), 16:i32), GPR:i32:$acc)
- // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 30 cost = 1 size = 0
- if (N000.getNode()->getOpcode() == ISD::SRA) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- if (N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N00001.getValueType() == MVT::i32 &&
- N0001.getValueType() == MVT::i32 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_121(N, ARM::SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
-
- // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 GPR:i32:$RHS, 255:i32))
- // Emits: (UXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 27 cost = 1 size = 0
- if (CheckAndMask(N10, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_53(N, ARM::UXTABrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 GPR:i32:$RHS, 65535:i32))
- // Emits: (UXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 27 cost = 1 size = 0
- if (CheckAndMask(N10, Tmp0, INT64_C(65535))) {
- SDNode *Result = Emit_53(N, ARM::UXTAHrr, MVT::i32);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
-
- // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 GPR:i32:$RHS, 255:i32))
- // Emits: (t2UXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 27 cost = 1 size = 0
- if (CheckAndMask(N10, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_53(N, ARM::t2UXTABrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$LHS, (and:i32 GPR:i32:$RHS, 65535:i32))
- // Emits: (t2UXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 27 cost = 1 size = 0
- if (CheckAndMask(N10, Tmp0, INT64_C(65535))) {
- SDNode *Result = Emit_53(N, ARM::t2UXTAHrr, MVT::i32);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
-
- // Pattern: (add:i32 (and:i32 GPR:i32:$RHS, 255:i32), GPR:i32:$LHS)
- // Emits: (UXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 27 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_86(N, ARM::UXTABrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 (and:i32 GPR:i32:$RHS, 65535:i32), GPR:i32:$LHS)
- // Emits: (UXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 27 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDNode *Result = Emit_86(N, ARM::UXTAHrr, MVT::i32);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
-
- // Pattern: (add:i32 (and:i32 GPR:i32:$RHS, 255:i32), GPR:i32:$LHS)
- // Emits: (t2UXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 27 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_86(N, ARM::t2UXTABrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 (and:i32 GPR:i32:$RHS, 65535:i32), GPR:i32:$LHS)
- // Emits: (t2UXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 27 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDNode *Result = Emit_86(N, ARM::t2UXTAHrr, MVT::i32);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32)))
- // Emits: (SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N101.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_62(N, ARM::SMLATT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32))
- // Emits: (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SRA) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N1011.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_64(N, ARM::SMLAWT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32)))
- // Emits: (t2SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N101.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_62(N, ARM::t2SMLATT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32))
- // Emits: (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SRA) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N1011.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_64(N, ARM::t2SMLAWT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32)))
- // Emits: (SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N101.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_94(N, ARM::SMLATT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
- // Emits: (SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- {
- SDNode *Result = Emit_95(N, ARM::SMLATT, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
- // Emits: (SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- SDNode *Result = Emit_96(N, ARM::SMLATT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32))
- // Emits: (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SRA) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N1001.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_100(N, ARM::SMLAWT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::MUL) {
- SDValue N000 = N00.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32), GPR:i32:$acc)
- // Emits: (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::SRA) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N0011.getValueType() == MVT::i32 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_101(N, ARM::SMLAWT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32), GPR:i32:$acc)
- // Emits: (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- if (N000.getNode()->getOpcode() == ISD::SRA) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N0001.getValueType() == MVT::i32 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_102(N, ARM::SMLAWT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32)))
- // Emits: (t2SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N101.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_94(N, ARM::t2SMLATT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
- // Emits: (t2SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- {
- SDNode *Result = Emit_95(N, ARM::t2SMLATT, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
- // Emits: (t2SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- SDNode *Result = Emit_96(N, ARM::t2SMLATT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32))
- // Emits: (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SRA) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N1001.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_100(N, ARM::t2SMLAWT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::MUL) {
- SDValue N000 = N00.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32), GPR:i32:$acc)
- // Emits: (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::SRA) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N0011.getValueType() == MVT::i32 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_101(N, ARM::t2SMLAWT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32), GPR:i32:$acc)
- // Emits: (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 22 cost = 1 size = 0
- if (N000.getNode()->getOpcode() == ISD::SRA) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N0001.getValueType() == MVT::i32 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_102(N, ARM::t2SMLAWT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32)))
- // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (cast<VTSDNode>(N101.getNode())->getVT() == MVT::i16) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_61(N, ARM::SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other)))
- // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (cast<VTSDNode>(N111.getNode())->getVT() == MVT::i16 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_61(N, ARM::SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32))
- // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- if (cast<VTSDNode>(N1011.getNode())->getVT() == MVT::i16) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_63(N, ARM::SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32)))
- // Emits: (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (cast<VTSDNode>(N101.getNode())->getVT() == MVT::i16) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_61(N, ARM::t2SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other)))
- // Emits: (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (cast<VTSDNode>(N111.getNode())->getVT() == MVT::i16 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_61(N, ARM::t2SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32))
- // Emits: (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- if (cast<VTSDNode>(N1011.getNode())->getVT() == MVT::i16) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_63(N, ARM::t2SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other)))
- // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (cast<VTSDNode>(N111.getNode())->getVT() == MVT::i16 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_91(N, ARM::SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
- // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_92(N, ARM::SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other)), GPR:i32:$acc)
- // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_93(N, ARM::SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32)))
- // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (cast<VTSDNode>(N101.getNode())->getVT() == MVT::i16) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_91(N, ARM::SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other)), GPR:i32:$acc)
- // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_92(N, ARM::SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
- // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_93(N, ARM::SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32))
- // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- if (cast<VTSDNode>(N1001.getNode())->getVT() == MVT::i16) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_97(N, ARM::SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::MUL) {
- SDValue N000 = N00.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32), GPR:i32:$acc)
- // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- if (cast<VTSDNode>(N0011.getNode())->getVT() == MVT::i16) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_98(N, ARM::SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32), GPR:i32:$acc)
- // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N000.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- if (cast<VTSDNode>(N0001.getNode())->getVT() == MVT::i16) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_99(N, ARM::SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other)))
- // Emits: (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (cast<VTSDNode>(N111.getNode())->getVT() == MVT::i16 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_91(N, ARM::t2SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
- // Emits: (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_92(N, ARM::t2SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other)), GPR:i32:$acc)
- // Emits: (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_93(N, ARM::t2SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32)))
- // Emits: (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (cast<VTSDNode>(N101.getNode())->getVT() == MVT::i16) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_91(N, ARM::t2SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other)), GPR:i32:$acc)
- // Emits: (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_92(N, ARM::t2SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
- // Emits: (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_93(N, ARM::t2SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32))
- // Emits: (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- if (cast<VTSDNode>(N1001.getNode())->getVT() == MVT::i16) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_97(N, ARM::t2SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::MUL) {
- SDValue N000 = N00.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32), GPR:i32:$acc)
- // Emits: (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- if (cast<VTSDNode>(N0011.getNode())->getVT() == MVT::i16) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_98(N, ARM::t2SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32), GPR:i32:$acc)
- // Emits: (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 17 cost = 1 size = 0
- if (N000.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- if (cast<VTSDNode>(N0001.getNode())->getVT() == MVT::i16) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_99(N, ARM::t2SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$a, so_reg:i32:$b)
- // Emits: (ADDrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
- SDNode *Result = Emit_57(N, ARM::ADDrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, (sra:i32 GPR:i32:$b, 16:i32)))
- // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 15 cost = 1 size = 0
- if (Predicate_sext_16_node(N10.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_79(N, ARM::SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$b))
- // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (Predicate_sext_16_node(N11.getNode()) &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_81(N, ARM::SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b), 16:i32))
- // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (Predicate_sext_16_node(N101.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_83(N, ARM::SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 so_reg:i32:$b, GPR:i32:$a)
- // Emits: (ADDrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- SDValue CPTmpN0_2;
- if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDNode *Result = Emit_88(N, ARM::ADDrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$a))
- // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (Predicate_sext_16_node(N11.getNode()) &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_110(N, ARM::SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
- // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 15 cost = 1 size = 0
- if (Predicate_sext_16_node(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_111(N, ARM::SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$a), GPR:i32:$acc)
- // Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (Predicate_sext_16_node(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_112(N, ARM::SMLABT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$b, (sra:i32 GPR:i32:$a, 16:i32)))
- // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (Predicate_sext_16_node(N10.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N111.getValueType() == MVT::i32) {
- SDNode *Result = Emit_116(N, ARM::SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$b), GPR:i32:$acc)
- // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (Predicate_sext_16_node(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_117(N, ARM::SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$b, (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
- // Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 15 cost = 1 size = 0
- if (Predicate_sext_16_node(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_118(N, ARM::SMLATB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$b, GPR:i32:$a), 16:i32))
- // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (Predicate_sext_16_node(N100.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_122(N, ARM::SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::MUL) {
- SDValue N000 = N00.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b), 16:i32), GPR:i32:$acc)
- // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (Predicate_sext_16_node(N001.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_123(N, ARM::SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$b, GPR:i32:$a), 16:i32), GPR:i32:$acc)
- // Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 15 cost = 1 size = 0
- if (Predicate_sext_16_node(N000.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_124(N, ARM::SMLAWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N101.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
-
- // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other))
- // Emits: (SXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i8 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_52(N, ARM::SXTABrr_rot, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other))
- // Emits: (SXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_52(N, ARM::SXTAHrr_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N101.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
-
- // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other))
- // Emits: (t2SXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i8 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_52(N, ARM::t2SXTABrr_rot, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other))
- // Emits: (t2SXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_52(N, ARM::t2SXTAHrr_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N001.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
-
- // Pattern: (add:i32 (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other), GPR:i32:$LHS)
- // Emits: (SXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i8) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_85(N, ARM::SXTABrr_rot, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (add:i32 (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other), GPR:i32:$LHS)
- // Emits: (SXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_85(N, ARM::SXTAHrr_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N001.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
-
- // Pattern: (add:i32 (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other), GPR:i32:$LHS)
- // Emits: (t2SXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i8) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_85(N, ARM::t2SXTABrr_rot, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (add:i32 (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other), GPR:i32:$LHS)
- // Emits: (t2SXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
- // Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- if (N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_85(N, ARM::t2SXTAHrr_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other)))
- // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (cast<VTSDNode>(N101.getNode())->getVT() == MVT::i16) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (cast<VTSDNode>(N111.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_60(N, ARM::SMLABB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2ADDrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_68(N, ARM::t2ADDrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other)))
- // Emits: (t2SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (cast<VTSDNode>(N101.getNode())->getVT() == MVT::i16) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (cast<VTSDNode>(N111.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_60(N, ARM::t2SMLABB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other)), GPR:i32:$acc)
- // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_90(N, ARM::SMLABB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
- // Emits: (t2ADDrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDNode *Result = Emit_103(N, ARM::t2ADDrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
- return Result;
- }
- }
-
- // Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other)), GPR:i32:$acc)
- // Emits: (t2SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_90(N, ARM::t2SMLABB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_imm0_255_neg>><<X:imm_neg_XFORM>>:$imm)
- // Emits: (t2SUBri:i32 GPR:i32:$src, (imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_imm0_255_neg>>:$imm))
- // Pattern complexity = 8 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm0_255_neg(N1.getNode())) {
- SDNode *Result = Emit_69(N, ARM::t2SUBri, MVT::i32);
- return Result;
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:i32 GPR:i32:$acc, (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b))
- // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 8 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (Predicate_sext_16_node(N10.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (Predicate_sext_16_node(N11.getNode())) {
- SDNode *Result = Emit_77(N, ARM::SMLABB, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b), GPR:i32:$acc)
- // Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
- // Pattern complexity = 8 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (Predicate_sext_16_node(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (Predicate_sext_16_node(N01.getNode())) {
- SDNode *Result = Emit_59(N, ARM::SMLABB, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (ADDri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N1.getNode())) {
- SDNode *Result = Emit_55(N, ARM::ADDri, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (add:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7>>:$rhs)
- // Emits: (tADDi3:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm0_7(N1.getNode())) {
- SDNode *Result = Emit_65(N, ARM::tADDi3, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm8_255>>:$rhs)
- // Emits: (tADDi8:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm8_255(N1.getNode())) {
- SDNode *Result = Emit_65(N, ARM::tADDi8, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7_neg>><<X:imm_neg_XFORM>>:$rhs)
- // Emits: (tSUBi3:i32 tGPR:i32:$lhs, (imm_neg_XFORM:i32 (imm:i32):$rhs))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm0_7_neg(N1.getNode())) {
- SDNode *Result = Emit_67(N, ARM::tSUBi3, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm8_255_neg>><<X:imm_neg_XFORM>>:$rhs)
- // Emits: (tSUBi8:i32 tGPR:i32:$lhs, (imm_neg_XFORM:i32 (imm:i32):$rhs))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm8_255_neg(N1.getNode())) {
- SDNode *Result = Emit_67(N, ARM::tSUBi8, MVT::i32);
- return Result;
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (add:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2ADDri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_t2_so_imm(N1.getNode())) {
- SDNode *Result = Emit_55(N, ARM::t2ADDri, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_4095>>:$rhs)
- // Emits: (t2ADDri12:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm0_4095(N1.getNode())) {
- SDNode *Result = Emit_55(N, ARM::t2ADDri12, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_t2_so_imm_neg>><<X:t2_so_imm_neg_XFORM>>:$imm)
- // Emits: (t2SUBri:i32 GPR:i32:$src, (t2_so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_neg>>:$imm))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_t2_so_imm_neg(N1.getNode())) {
- SDNode *Result = Emit_70(N, ARM::t2SUBri, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_imm0_4095_neg>><<X:imm_neg_XFORM>>:$imm)
- // Emits: (t2SUBri12:i32 GPR:i32:$src, (imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_imm0_4095_neg>>:$imm))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm0_4095_neg(N1.getNode())) {
- SDNode *Result = Emit_69(N, ARM::t2SUBri12, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_so_imm_neg>><<X:so_imm_neg_XFORM>>:$imm)
- // Emits: (SUBri:i32 GPR:i32:$src, (so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_so_imm_neg>>:$imm))
- // Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm_neg(N1.getNode())) {
- SDNode *Result = Emit_73(N, ARM::SUBri, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (add:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_t2_so_imm2part>>:$RHS)
- // Emits: (t2ADDri:i32 (t2ADDri:i32 GPR:i32:$LHS, (t2_so_imm2part_1:i32 (imm:i32):$RHS)), (t2_so_imm2part_2:i32 (imm:i32):$RHS))
- // Pattern complexity = 7 cost = 2 size = 0
- if (Predicate_t2_so_imm2part(N1.getNode())) {
- SDNode *Result = Emit_71(N, ARM::t2ADDri, ARM::t2ADDri, MVT::i32, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_t2_so_neg_imm2part>>:$RHS)
- // Emits: (t2SUBri:i32 (t2SUBri:i32 GPR:i32:$LHS, (t2_so_neg_imm2part_1:i32 (imm:i32):$RHS)), (t2_so_neg_imm2part_2:i32 (imm:i32):$RHS))
- // Pattern complexity = 7 cost = 2 size = 0
- if (Predicate_t2_so_neg_imm2part(N1.getNode())) {
- SDNode *Result = Emit_72(N, ARM::t2SUBri, ARM::t2SUBri, MVT::i32, MVT::i32);
- return Result;
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (add:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_so_imm2part>>:$RHS)
- // Emits: (ADDri:i32 (ADDri:i32 GPR:i32:$LHS, (so_imm2part_1:i32 (imm:i32):$RHS)), (so_imm2part_2:i32 (imm:i32):$RHS))
- // Pattern complexity = 7 cost = 2 size = 0
- if (Predicate_so_imm2part(N1.getNode())) {
- SDNode *Result = Emit_74(N, ARM::ADDri, ARM::ADDri, MVT::i32, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_so_neg_imm2part>>:$RHS)
- // Emits: (SUBri:i32 (SUBri:i32 GPR:i32:$LHS, (so_neg_imm2part_1:i32 (imm:i32):$RHS)), (so_neg_imm2part_2:i32 (imm:i32):$RHS))
- // Pattern complexity = 7 cost = 2 size = 0
- if (Predicate_so_neg_imm2part(N1.getNode())) {
- SDNode *Result = Emit_75(N, ARM::SUBri, ARM::SUBri, MVT::i32, MVT::i32);
- return Result;
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
-
- // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 GPR:i32:$RHS, i8:Other))
- // Emits: (SXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_51(N, ARM::SXTABrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 GPR:i32:$RHS, i16:Other))
- // Emits: (SXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_51(N, ARM::SXTAHrr, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i32 (mul:i32 GPR:i32:$a, GPR:i32:$b), GPR:i32:$c)
- // Emits: (MLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_58(N, ARM::MLA, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (add:i32 (mulhs:i32 GPR:i32:$a, GPR:i32:$b), GPR:i32:$c)
- // Emits: (SMMLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::MULHS) {
- SDNode *Result = Emit_59(N, ARM::SMMLA, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
-
- // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 GPR:i32:$RHS, i8:Other))
- // Emits: (t2SXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_51(N, ARM::t2SXTABrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 GPR:i32:$RHS, i16:Other))
- // Emits: (t2SXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_51(N, ARM::t2SXTAHrr, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i32 (mul:i32 GPR:i32:$a, GPR:i32:$b), GPR:i32:$c)
- // Emits: (t2MLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_59(N, ARM::t2MLA, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 (mulhs:i32 GPR:i32:$a, GPR:i32:$b), GPR:i32:$c)
- // Emits: (t2SMMLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::MULHS) {
- SDNode *Result = Emit_59(N, ARM::t2SMMLA, MVT::i32);
- return Result;
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
-
- // Pattern: (add:i32 (sext_inreg:i32 GPR:i32:$RHS, i8:Other), GPR:i32:$LHS)
- // Emits: (SXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_84(N, ARM::SXTABrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 (sext_inreg:i32 GPR:i32:$RHS, i16:Other), GPR:i32:$LHS)
- // Emits: (SXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_84(N, ARM::SXTAHrr, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$c, (mul:i32 GPR:i32:$a, GPR:i32:$b))
- // Emits: (MLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_89(N, ARM::MLA, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$c, (mulhs:i32 GPR:i32:$a, GPR:i32:$b))
- // Emits: (SMMLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MULHS) {
- SDNode *Result = Emit_77(N, ARM::SMMLA, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
-
- // Pattern: (add:i32 (sext_inreg:i32 GPR:i32:$RHS, i8:Other), GPR:i32:$LHS)
- // Emits: (t2SXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_84(N, ARM::t2SXTABrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 (sext_inreg:i32 GPR:i32:$RHS, i16:Other), GPR:i32:$LHS)
- // Emits: (t2SXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
- // Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_84(N, ARM::t2SXTAHrr, MVT::i32);
- return Result;
- }
- }
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:i32 GPR:i32:$c, (mul:i32 GPR:i32:$a, GPR:i32:$b))
- // Emits: (t2MLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_77(N, ARM::t2MLA, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$c, (mulhs:i32 GPR:i32:$a, GPR:i32:$b))
- // Emits: (t2SMMLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::MULHS) {
- SDNode *Result = Emit_77(N, ARM::t2SMMLA, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (add:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (ADDrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDNode *Result = Emit_56(N, ARM::ADDrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tADDrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDNode *Result = Emit_66(N, ARM::tADDrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2ADDrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_56(N, ARM::t2ADDrr, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_125(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N10, N11, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_126(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N10, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_127(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N00, N01, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_128(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N00, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-SDNode *Select_ISD_ADD_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:v8i8 DPR:v8i8:$src1, (NEONvshrs:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (add:v8i8 DPR:v8i8:$src1, (NEONvshru:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (add:v8i8 DPR:v8i8:$src1, (NEONvrshrs:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (add:v8i8 DPR:v8i8:$src1, (NEONvrshru:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAuv8i8, MVT::v8i8);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v8i8 (NEONvshrs:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM), DPR:v8i8:$src1)
- // Emits: (VSRAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (add:v8i8 (NEONvshru:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM), DPR:v8i8:$src1)
- // Emits: (VSRAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (add:v8i8 (NEONvrshrs:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM), DPR:v8i8:$src1)
- // Emits: (VRSRAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (add:v8i8 (NEONvrshru:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM), DPR:v8i8:$src1)
- // Emits: (VRSRAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (add:v8i8 DPR:v8i8:$src1, (mul:v8i8 DPR:v8i8:$src2, DPR:v8i8:$src3))
- // Emits: (VMLAv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_125(N, ARM::VMLAv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (add:v8i8 (mul:v8i8 DPR:v8i8:$src2, DPR:v8i8:$src3), DPR:v8i8:$src1)
- // Emits: (VMLAv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_127(N, ARM::VMLAv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (add:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VADDv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VADDv8i8, MVT::v8i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ADD_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:v16i8 QPR:v16i8:$src1, (NEONvshrs:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (add:v16i8 QPR:v16i8:$src1, (NEONvshru:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (add:v16i8 QPR:v16i8:$src1, (NEONvrshrs:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (add:v16i8 QPR:v16i8:$src1, (NEONvrshru:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAuv16i8, MVT::v16i8);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v16i8 (NEONvshrs:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM), QPR:v16i8:$src1)
- // Emits: (VSRAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (add:v16i8 (NEONvshru:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM), QPR:v16i8:$src1)
- // Emits: (VSRAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (add:v16i8 (NEONvrshrs:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM), QPR:v16i8:$src1)
- // Emits: (VRSRAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (add:v16i8 (NEONvrshru:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM), QPR:v16i8:$src1)
- // Emits: (VRSRAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (add:v16i8 QPR:v16i8:$src1, (mul:v16i8 QPR:v16i8:$src2, QPR:v16i8:$src3))
- // Emits: (VMLAv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_125(N, ARM::VMLAv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (add:v16i8 (mul:v16i8 QPR:v16i8:$src2, QPR:v16i8:$src3), QPR:v16i8:$src1)
- // Emits: (VMLAv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_127(N, ARM::VMLAv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (add:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VADDv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VADDv16i8, MVT::v16i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_129(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N111)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N10, N110, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_130(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N11, N100, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_131(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N011)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N00, N010, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_132(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N01, N000, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-SDNode *Select_ISD_ADD_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (add:v4i16 DPR:v4i16:$src1, (mul:v4i16 DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane)))
- // Emits: (VMLAslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_129(N, ARM::VMLAslv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v4i16 DPR:v4i16:$src1, (mul:v4i16 (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane), DPR:v4i16:$src2))
- // Emits: (VMLAslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_130(N, ARM::VMLAslv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:v4i16 (mul:v4i16 DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane)), DPR:v4i16:$src1)
- // Emits: (VMLAslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N010.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_131(N, ARM::VMLAslv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:v4i16 (mul:v4i16 (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane), DPR:v4i16:$src2), DPR:v4i16:$src1)
- // Emits: (VMLAslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_132(N, ARM::VMLAslv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
- }
- {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:v4i16 DPR:v4i16:$src1, (NEONvshrs:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (add:v4i16 DPR:v4i16:$src1, (NEONvshru:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (add:v4i16 DPR:v4i16:$src1, (NEONvrshrs:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (add:v4i16 DPR:v4i16:$src1, (NEONvrshru:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAuv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v4i16 (NEONvshrs:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM), DPR:v4i16:$src1)
- // Emits: (VSRAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (add:v4i16 (NEONvshru:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM), DPR:v4i16:$src1)
- // Emits: (VSRAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (add:v4i16 (NEONvrshrs:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM), DPR:v4i16:$src1)
- // Emits: (VRSRAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (add:v4i16 (NEONvrshru:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM), DPR:v4i16:$src1)
- // Emits: (VRSRAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (add:v4i16 DPR:v4i16:$src1, (mul:v4i16 DPR:v4i16:$src2, DPR:v4i16:$src3))
- // Emits: (VMLAv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_125(N, ARM::VMLAv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (add:v4i16 (mul:v4i16 DPR:v4i16:$src2, DPR:v4i16:$src3), DPR:v4i16:$src1)
- // Emits: (VMLAv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_127(N, ARM::VMLAv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (add:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VADDv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VADDv4i16, MVT::v4i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_133(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N111)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = Transform_DSubReg_i16_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N110, Tmp4), 0);
- SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp3.getNode());
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N0, N10, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
-}
-DISABLE_INLINE SDNode *Emit_134(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = Transform_DSubReg_i16_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N100, Tmp4), 0);
- SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp3.getNode());
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N0, N11, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
-}
-DISABLE_INLINE SDNode *Emit_135(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N011)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = Transform_DSubReg_i16_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N010, Tmp4), 0);
- SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp3.getNode());
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N1, N00, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
-}
-DISABLE_INLINE SDNode *Emit_136(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = Transform_DSubReg_i16_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N000, Tmp4), 0);
- SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp3.getNode());
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N1, N01, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
-}
-SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane)))
- // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_129(N, ARM::VMLAslv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2))
- // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_130(N, ARM::VMLAslv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:v8i16 (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane)), QPR:v8i16:$src1)
- // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N010.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_131(N, ARM::VMLAslv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:v8i16 (mul:v8i16 (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2), QPR:v8i16:$src1)
- // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_132(N, ARM::VMLAslv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane)))
- // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_133(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2))
- // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_134(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:v8i16 (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane)), QPR:v8i16:$src1)
- // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N010.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_135(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:v8i16 (mul:v8i16 (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2), QPR:v8i16:$src1)
- // Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_136(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:v8i16 QPR:v8i16:$src1, (NEONvshrs:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (add:v8i16 QPR:v8i16:$src1, (NEONvshru:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (add:v8i16 QPR:v8i16:$src1, (NEONvrshrs:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (add:v8i16 QPR:v8i16:$src1, (NEONvrshru:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAuv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v8i16 (NEONvshrs:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM), QPR:v8i16:$src1)
- // Emits: (VSRAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (add:v8i16 (NEONvshru:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM), QPR:v8i16:$src1)
- // Emits: (VSRAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (add:v8i16 (NEONvrshrs:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM), QPR:v8i16:$src1)
- // Emits: (VRSRAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (add:v8i16 (NEONvrshru:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM), QPR:v8i16:$src1)
- // Emits: (VRSRAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, QPR:v8i16:$src3))
- // Emits: (VMLAv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_125(N, ARM::VMLAv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (add:v8i16 (mul:v8i16 QPR:v8i16:$src2, QPR:v8i16:$src3), QPR:v8i16:$src1)
- // Emits: (VMLAv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_127(N, ARM::VMLAv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (add:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VADDv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VADDv8i16, MVT::v8i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ADD_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (add:v2i32 DPR:v2i32:$src1, (mul:v2i32 DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)))
- // Emits: (VMLAslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_129(N, ARM::VMLAslv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v2i32 DPR:v2i32:$src1, (mul:v2i32 (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), DPR:v2i32:$src2))
- // Emits: (VMLAslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_130(N, ARM::VMLAslv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:v2i32 (mul:v2i32 DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)), DPR:v2i32:$src1)
- // Emits: (VMLAslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N010.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_131(N, ARM::VMLAslv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:v2i32 (mul:v2i32 (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), DPR:v2i32:$src2), DPR:v2i32:$src1)
- // Emits: (VMLAslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_132(N, ARM::VMLAslv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
- }
- {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:v2i32 DPR:v2i32:$src1, (NEONvshrs:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (add:v2i32 DPR:v2i32:$src1, (NEONvshru:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (add:v2i32 DPR:v2i32:$src1, (NEONvrshrs:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (add:v2i32 DPR:v2i32:$src1, (NEONvrshru:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAuv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v2i32 (NEONvshrs:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM), DPR:v2i32:$src1)
- // Emits: (VSRAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (add:v2i32 (NEONvshru:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM), DPR:v2i32:$src1)
- // Emits: (VSRAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (add:v2i32 (NEONvrshrs:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM), DPR:v2i32:$src1)
- // Emits: (VRSRAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (add:v2i32 (NEONvrshru:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM), DPR:v2i32:$src1)
- // Emits: (VRSRAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (add:v2i32 DPR:v2i32:$src1, (mul:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src3))
- // Emits: (VMLAv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_125(N, ARM::VMLAv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (add:v2i32 (mul:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src3), DPR:v2i32:$src1)
- // Emits: (VMLAv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_127(N, ARM::VMLAv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (add:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VADDv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VADDv2i32, MVT::v2i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_137(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N111)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = Transform_DSubReg_i32_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N110, Tmp4), 0);
- SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp3.getNode());
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N0, N10, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
-}
-DISABLE_INLINE SDNode *Emit_138(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = Transform_DSubReg_i32_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N100, Tmp4), 0);
- SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp3.getNode());
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N0, N11, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
-}
-DISABLE_INLINE SDNode *Emit_139(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N011)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = Transform_DSubReg_i32_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N010, Tmp4), 0);
- SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp3.getNode());
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N1, N00, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
-}
-DISABLE_INLINE SDNode *Emit_140(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = Transform_DSubReg_i32_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N000, Tmp4), 0);
- SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp3.getNode());
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N1, N01, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
-}
-SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)))
- // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_129(N, ARM::VMLAslv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2))
- // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_130(N, ARM::VMLAslv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:v4i32 (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)), QPR:v4i32:$src1)
- // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N010.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_131(N, ARM::VMLAslv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:v4i32 (mul:v4i32 (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2), QPR:v4i32:$src1)
- // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_132(N, ARM::VMLAslv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane)))
- // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_137(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2))
- // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_138(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:v4i32 (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane)), QPR:v4i32:$src1)
- // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N010.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_139(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:v4i32 (mul:v4i32 (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2), QPR:v4i32:$src1)
- // Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_140(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:v4i32 QPR:v4i32:$src1, (NEONvshrs:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (add:v4i32 QPR:v4i32:$src1, (NEONvshru:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (add:v4i32 QPR:v4i32:$src1, (NEONvrshrs:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (add:v4i32 QPR:v4i32:$src1, (NEONvrshru:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAuv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v4i32 (NEONvshrs:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM), QPR:v4i32:$src1)
- // Emits: (VSRAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (add:v4i32 (NEONvshru:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM), QPR:v4i32:$src1)
- // Emits: (VSRAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (add:v4i32 (NEONvrshrs:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM), QPR:v4i32:$src1)
- // Emits: (VRSRAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (add:v4i32 (NEONvrshru:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM), QPR:v4i32:$src1)
- // Emits: (VRSRAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src3))
- // Emits: (VMLAv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_125(N, ARM::VMLAv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (add:v4i32 (mul:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src3), QPR:v4i32:$src1)
- // Emits: (VMLAv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_127(N, ARM::VMLAv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (add:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VADDv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VADDv4i32, MVT::v4i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ADD_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:v1i64 DPR:v1i64:$src1, (NEONvshrs:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAsv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (add:v1i64 DPR:v1i64:$src1, (NEONvshru:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAuv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (add:v1i64 DPR:v1i64:$src1, (NEONvrshrs:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAsv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (add:v1i64 DPR:v1i64:$src1, (NEONvrshru:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAuv1i64, MVT::v1i64);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v1i64 (NEONvshrs:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM), DPR:v1i64:$src1)
- // Emits: (VSRAsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAsv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (add:v1i64 (NEONvshru:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM), DPR:v1i64:$src1)
- // Emits: (VSRAuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAuv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (add:v1i64 (NEONvrshrs:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM), DPR:v1i64:$src1)
- // Emits: (VRSRAsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAsv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (add:v1i64 (NEONvrshru:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM), DPR:v1i64:$src1)
- // Emits: (VRSRAuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAuv1i64, MVT::v1i64);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VADDv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VADDv1i64, MVT::v1i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ADD_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:v2i64 QPR:v2i64:$src1, (NEONvshrs:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (add:v2i64 QPR:v2i64:$src1, (NEONvshru:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM))
- // Emits: (VSRAuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VSRAuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (add:v2i64 QPR:v2i64:$src1, (NEONvrshrs:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (add:v2i64 QPR:v2i64:$src1, (NEONvrshru:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM))
- // Emits: (VRSRAuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, ARM::VRSRAuv2i64, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v2i64 (NEONvshrs:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM), QPR:v2i64:$src1)
- // Emits: (VSRAsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (add:v2i64 (NEONvshru:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM), QPR:v2i64:$src1)
- // Emits: (VSRAuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VSRAuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (add:v2i64 (NEONvrshrs:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM), QPR:v2i64:$src1)
- // Emits: (VRSRAsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (add:v2i64 (NEONvrshru:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM), QPR:v2i64:$src1)
- // Emits: (VRSRAuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, ARM::VRSRAuv2i64, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (add:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VADDv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VADDv2i64, MVT::v2i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_141(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_142(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_143(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 6);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_144(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_145(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, N0, Tmp2, Tmp3, Tmp4 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_146(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, N0, N1, Tmp3, Tmp4 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_147(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_imm_neg_XFORM(Tmp2.getNode());
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, N0, Tmp3, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_148(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 6);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_149(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_ADDC_i32(SDNode *N) {
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (addc:i32 GPR:i32:$a, so_reg:i32:$b)
- // Emits: (ADDSrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
- SDNode *Result = Emit_143(N, ARM::ADDSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (addc:i32 so_reg:i32:$b, GPR:i32:$a)
- // Emits: (ADDSrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- SDValue CPTmpN0_2;
- if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDNode *Result = Emit_148(N, ARM::ADDSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (addc:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2ADDSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_144(N, ARM::t2ADDSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (addc:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
- // Emits: (t2ADDSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDNode *Result = Emit_149(N, ARM::t2ADDSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
- return Result;
- }
- }
-
- // Pattern: (addc:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (ADDSri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N1.getNode())) {
- SDNode *Result = Emit_141(N, ARM::ADDSri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (addc:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2ADDSri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N1.getNode())) {
- SDNode *Result = Emit_141(N, ARM::t2ADDSri, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (addc:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7>>:$rhs)
- // Emits: (tADDi3:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7>>:$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm0_7(N1.getNode())) {
- SDNode *Result = Emit_145(N, ARM::tADDi3, MVT::i32);
- return Result;
- }
-
- // Pattern: (addc:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm8_255>>:$rhs)
- // Emits: (tADDi8:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm8_255>>:$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm8_255(N1.getNode())) {
- SDNode *Result = Emit_145(N, ARM::tADDi8, MVT::i32);
- return Result;
- }
-
- // Pattern: (addc:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7_neg>><<X:imm_neg_XFORM>>:$rhs)
- // Emits: (tSUBi3:i32 tGPR:i32:$lhs, (imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_imm0_7_neg>>:$rhs))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm0_7_neg(N1.getNode())) {
- SDNode *Result = Emit_147(N, ARM::tSUBi3, MVT::i32);
- return Result;
- }
-
- // Pattern: (addc:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm8_255_neg>><<X:imm_neg_XFORM>>:$rhs)
- // Emits: (tSUBi8:i32 tGPR:i32:$lhs, (imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_imm8_255_neg>>:$rhs))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm8_255_neg(N1.getNode())) {
- SDNode *Result = Emit_147(N, ARM::tSUBi8, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (addc:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (ADDSrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDNode *Result = Emit_142(N, ARM::ADDSrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (addc:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2ADDSrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_142(N, ARM::t2ADDSrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (addc:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tADDrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDNode *Result = Emit_146(N, ARM::tADDrr, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_150(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 6);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_151(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { N0, N1, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 6);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_152(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 8);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_153(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_154(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, N1, InFlag);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_155(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_156(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { Tmp0, N0, N1, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 6);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_157(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 7);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_158(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 4);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_159(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 8);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_160(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_161(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 7);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_162(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 4);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_ADDE_i32(SDNode *N) {
-
- // Pattern: (adde:i32 GPR:i32:$a, so_reg:i32:$b)
- // Emits: (ADCrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
- SDNode *Result = Emit_152(N, ARM::ADCrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 GPR:i32:$a, so_reg:i32:$b)
- // Emits: (ADCSSrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
- SDNode *Result = Emit_155(N, ARM::ADCSSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 so_reg:i32:$b, GPR:i32:$a)
- // Emits: (ADCrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- SDValue CPTmpN0_2;
- if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDNode *Result = Emit_159(N, ARM::ADCrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 so_reg:i32:$b, GPR:i32:$a)
- // Emits: (ADCSSrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- SDValue CPTmpN0_2;
- if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDNode *Result = Emit_160(N, ARM::ADCSSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2ADCrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_157(N, ARM::t2ADCrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2ADCSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_158(N, ARM::t2ADCSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
- // Emits: (t2ADCrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDNode *Result = Emit_161(N, ARM::t2ADCrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
- // Emits: (t2ADCSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDNode *Result = Emit_162(N, ARM::t2ADCSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (ADCri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N1.getNode())) {
- SDNode *Result = Emit_150(N, ARM::ADCri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (ADCSSri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N1.getNode())) {
- SDNode *Result = Emit_153(N, ARM::ADCSSri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2ADCri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N1.getNode())) {
- SDNode *Result = Emit_150(N, ARM::t2ADCri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2ADCSri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N1.getNode())) {
- SDNode *Result = Emit_153(N, ARM::t2ADCSri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (ADCrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
- SDNode *Result = Emit_151(N, ARM::ADCrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (adde:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (ADCSSrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
- SDNode *Result = Emit_154(N, ARM::ADCSSrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (adde:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tADC:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDNode *Result = Emit_156(N, ARM::tADC, MVT::i32);
- return Result;
- }
-
- // Pattern: (adde:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2ADCrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
- SDNode *Result = Emit_151(N, ARM::t2ADCrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (adde:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2ADCSrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
- SDNode *Result = Emit_154(N, ARM::t2ADCSrr, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_163(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_164(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_165(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N10)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_166(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N10, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_167(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10_0, SDValue &CPTmpN10_1, SDValue &CPTmpN10_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, CPTmpN10_0, CPTmpN10_1, CPTmpN10_2, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 7);
-}
-DISABLE_INLINE SDNode *Emit_168(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, N0, N10, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_169(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10_0, SDValue &CPTmpN10_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, CPTmpN10_0, CPTmpN10_1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_170(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0x18ULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_171(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0x8ULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_172(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_t2_so_imm_not_XFORM(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_173(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_so_imm_not_XFORM(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_174(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_175(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N00)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_176(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_177(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N00, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_178(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1, SDValue &CPTmpN00_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 7);
-}
-DISABLE_INLINE SDNode *Emit_179(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, N1, N00, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_180(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN00_0, CPTmpN00_1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-SDNode *Select_ISD_AND_i32(SDNode *N) {
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0 &&
- CheckAndMask(N0, Tmp0, INT64_C(16711935))) {
-
- // Pattern: (and:i32 (shl:i32 GPR:i32:$Src, 8:i32), 16711935:i32)
- // Emits: (t2UXTB16r_rot:i32 GPR:i32:$Src, 24:i32)
- // Pattern complexity = 32 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_170(N, ARM::t2UXTB16r_rot, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i32 (srl:i32 GPR:i32:$Src, 8:i32), 16711935:i32)
- // Emits: (t2UXTB16r_rot:i32 GPR:i32:$Src, 8:i32)
- // Pattern complexity = 32 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_171(N, ARM::t2UXTB16r_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- if (CheckAndMask(N0, Tmp0, INT64_C(16711935))) {
-
- // Pattern: (and:i32 (shl:i32 GPR:i32:$Src, 8:i32), 16711935:i32)
- // Emits: (UXTB16r_rot:i32 GPR:i32:$Src, 24:i32)
- // Pattern complexity = 32 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_170(N, ARM::UXTB16r_rot, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i32 (srl:i32 GPR:i32:$Src, 8:i32), 16711935:i32)
- // Emits: (UXTB16r_rot:i32 GPR:i32:$Src, 8:i32)
- // Pattern complexity = 32 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_171(N, ARM::UXTB16r_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32)
- // Emits: (UXTBr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
- // Pattern complexity = 31 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(255)) &&
- N0.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N01.getNode()) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_164(N, ARM::UXTBr_rot, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 65535:i32)
- // Emits: (UXTHr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
- // Pattern complexity = 31 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(65535)) &&
- N0.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N01.getNode()) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_164(N, ARM::UXTHr_rot, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 16711935:i32)
- // Emits: (UXTB16r_rot:i32 GPR:i32:$src, (imm:i32):$rot)
- // Pattern complexity = 31 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(16711935)) &&
- N0.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N01.getNode()) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_164(N, ARM::UXTB16r_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
-
- // Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32)
- // Emits: (t2UXTBr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
- // Pattern complexity = 31 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(255)) &&
- N0.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N01.getNode()) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_164(N, ARM::t2UXTBr_rot, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 65535:i32)
- // Emits: (t2UXTHr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
- // Pattern complexity = 31 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(65535)) &&
- N0.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N01.getNode()) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_164(N, ARM::t2UXTHr_rot, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 16711935:i32)
- // Emits: (t2UXTB16r_rot:i32 GPR:i32:$src, (imm:i32):$rot)
- // Pattern complexity = 31 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(16711935)) &&
- N0.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N01.getNode()) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_164(N, ARM::t2UXTB16r_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
-
- // Pattern: (and:i32 GPR:i32:$src, 255:i32)
- // Emits: (UXTBr:i32 GPR:i32:$src)
- // Pattern complexity = 24 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_163(N, ARM::UXTBr, MVT::i32);
- return Result;
- }
-
- // Pattern: (and:i32 GPR:i32:$src, 65535:i32)
- // Emits: (UXTHr:i32 GPR:i32:$src)
- // Pattern complexity = 24 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(65535))) {
- SDNode *Result = Emit_163(N, ARM::UXTHr, MVT::i32);
- return Result;
- }
-
- // Pattern: (and:i32 GPR:i32:$src, 16711935:i32)
- // Emits: (UXTB16r:i32 GPR:i32:$src)
- // Pattern complexity = 24 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(16711935))) {
- SDNode *Result = Emit_163(N, ARM::UXTB16r, MVT::i32);
- return Result;
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
-
- // Pattern: (and:i32 GPR:i32:$src, 255:i32)
- // Emits: (t2UXTBr:i32 GPR:i32:$src)
- // Pattern complexity = 24 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_163(N, ARM::t2UXTBr, MVT::i32);
- return Result;
- }
-
- // Pattern: (and:i32 GPR:i32:$src, 65535:i32)
- // Emits: (t2UXTHr:i32 GPR:i32:$src)
- // Pattern complexity = 24 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(65535))) {
- SDNode *Result = Emit_163(N, ARM::t2UXTHr, MVT::i32);
- return Result;
- }
-
- // Pattern: (and:i32 GPR:i32:$src, 16711935:i32)
- // Emits: (t2UXTB16r:i32 GPR:i32:$src)
- // Pattern complexity = 24 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(16711935))) {
- SDNode *Result = Emit_163(N, ARM::t2UXTB16r, MVT::i32);
- return Result;
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:i32 GPR:i32:$a, (xor:i32 so_reg:i32:$b, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (BICrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 22 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue CPTmpN10_0;
- SDValue CPTmpN10_1;
- SDValue CPTmpN10_2;
- if (SelectShifterOperandReg(N, N10, CPTmpN10_0, CPTmpN10_1, CPTmpN10_2)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_167(N, ARM::BICrs, MVT::i32, CPTmpN10_0, CPTmpN10_1, CPTmpN10_2);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i32 (xor:i32 so_reg:i32:$b, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$a)
- // Emits: (BICrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 22 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue CPTmpN00_0;
- SDValue CPTmpN00_1;
- SDValue CPTmpN00_2;
- if (SelectShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_178(N, ARM::BICrs, MVT::i32, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:i32 GPR:i32:$lhs, (xor:i32 t2_so_reg:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (t2BICrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 19 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue CPTmpN10_0;
- SDValue CPTmpN10_1;
- if (SelectT2ShifterOperandReg(N, N10, CPTmpN10_0, CPTmpN10_1)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_169(N, ARM::t2BICrs, MVT::i32, CPTmpN10_0, CPTmpN10_1);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i32 (xor:i32 t2_so_reg:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
- // Emits: (t2BICrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 19 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue CPTmpN00_0;
- SDValue CPTmpN00_1;
- if (SelectT2ShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_180(N, ARM::t2BICrs, MVT::i32, CPTmpN00_0, CPTmpN00_1);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:i32 GPR:i32:$a, so_reg:i32:$b)
- // Emits: (ANDrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
- SDNode *Result = Emit_57(N, ARM::ANDrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (and:i32 so_reg:i32:$b, GPR:i32:$a)
- // Emits: (ANDrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- SDValue CPTmpN0_2;
- if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDNode *Result = Emit_88(N, ARM::ANDrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
- }
-
- // Pattern: (and:i32 GPR:i32:$a, (xor:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (BICri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 14 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N10.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_165(N, ARM::BICri, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i32 GPR:i32:$lhs, (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (t2BICri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 14 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N10.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_165(N, ARM::t2BICri, MVT::i32);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:i32 GPR:i32:$a, (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_so_imm>>:$b))
- // Emits: (BICri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 14 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N10.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N11.getNode())) {
- SDNode *Result = Emit_174(N, ARM::BICri, MVT::i32);
- return Result;
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (and:i32 (xor:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$a)
- // Emits: (BICri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if (Predicate_so_imm(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_175(N, ARM::BICri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (and:i32 (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_so_imm>>:$b), GPR:i32:$a)
- // Emits: (BICri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if (Predicate_immAllOnes(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N01.getNode())) {
- SDNode *Result = Emit_176(N, ARM::BICri, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:i32 GPR:i32:$lhs, (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs))
- // Emits: (t2BICri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 14 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N10.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N11.getNode())) {
- SDNode *Result = Emit_174(N, ARM::t2BICri, MVT::i32);
- return Result;
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (and:i32 (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
- // Emits: (t2BICri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 14 cost = 1 size = 0
- if (Predicate_t2_so_imm(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_175(N, ARM::t2BICri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (and:i32 (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), GPR:i32:$lhs)
- // Emits: (t2BICri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 14 cost = 1 size = 0
- if (Predicate_immAllOnes(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N01.getNode())) {
- SDNode *Result = Emit_176(N, ARM::t2BICri, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2ANDrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_68(N, ARM::t2ANDrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (and:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
- // Emits: (t2ANDrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDNode *Result = Emit_103(N, ARM::t2ANDrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
- return Result;
- }
- }
-
- // Pattern: (and:i32 GPR:i32:$a, (xor:i32 GPR:i32:$b, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (BICrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 10 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_166(N, ARM::BICrr, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i32 tGPR:i32:$lhs, (xor:i32 tGPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (tBIC:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 10 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_168(N, ARM::tBIC, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i32 GPR:i32:$lhs, (xor:i32 GPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (t2BICrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 10 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_166(N, ARM::t2BICrr, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i32 (xor:i32 GPR:i32:$b, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$a)
- // Emits: (BICrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 10 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_177(N, ARM::BICrr, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i32 (xor:i32 tGPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), tGPR:i32:$lhs)
- // Emits: (tBIC:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 10 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_179(N, ARM::tBIC, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i32 (xor:i32 GPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
- // Emits: (t2BICrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 10 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_177(N, ARM::t2BICrr, MVT::i32);
- return Result;
- }
- }
- }
- if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
-
- // Pattern: (and:i32 tGPR:i32:$src, 255:i32)
- // Emits: (tUXTB:i32 tGPR:i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_163(N, ARM::tUXTB, MVT::i32);
- return Result;
- }
-
- // Pattern: (and:i32 tGPR:i32:$src, 65535:i32)
- // Emits: (tUXTH:i32 tGPR:i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CheckAndMask(N0, Tmp0, INT64_C(65535))) {
- SDNode *Result = Emit_163(N, ARM::tUXTH, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (ANDri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N1.getNode())) {
- SDNode *Result = Emit_55(N, ARM::ANDri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (and:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_bf_inv_mask_imm>>:$imm)
- // Emits: (BFC:i32 GPR:i32:$src, (imm:i32):$imm)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_bf_inv_mask_imm(N1.getNode())) {
- SDNode *Result = Emit_35(N, ARM::BFC, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (and:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2ANDri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_t2_so_imm(N1.getNode())) {
- SDNode *Result = Emit_55(N, ARM::t2ANDri, MVT::i32);
- return Result;
- }
-
- // Pattern: (and:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_bf_inv_mask_imm>>:$imm)
- // Emits: (t2BFC:i32 GPR:i32:$src, (imm:i32):$imm)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_bf_inv_mask_imm(N1.getNode())) {
- SDNode *Result = Emit_35(N, ARM::t2BFC, MVT::i32);
- return Result;
- }
-
- // Pattern: (and:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_t2_so_imm_not>><<X:t2_so_imm_not_XFORM>>:$imm)
- // Emits: (t2BICri:i32 GPR:i32:$src, (t2_so_imm_not_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_not>>:$imm))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_t2_so_imm_not(N1.getNode())) {
- SDNode *Result = Emit_172(N, ARM::t2BICri, MVT::i32);
- return Result;
- }
- }
- }
- if ((!Subtarget->isThumb())) {
-
- // Pattern: (and:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_so_imm_not>><<X:so_imm_not_XFORM>>:$imm)
- // Emits: (BICri:i32 GPR:i32:$src, (so_imm_not_XFORM:i32 (imm:i32)<<P:Predicate_so_imm_not>>:$imm))
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm_not(N1.getNode())) {
- SDNode *Result = Emit_173(N, ARM::BICri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (and:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (ANDrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_56(N, ARM::ANDrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (and:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tAND:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDNode *Result = Emit_66(N, ARM::tAND, MVT::i32);
- return Result;
- }
-
- // Pattern: (and:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2ANDrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_56(N, ARM::t2ANDrr, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_181(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N11, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_182(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N01, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ISD_AND_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v2i32 DPR:v2i32:$src1, (xor:v2i32 DPR:v2i32:$src2, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>))
- // Emits: (VBICd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N11.getNode())) {
- SDNode *Result = Emit_51(N, ARM::VBICd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (and:v2i32 DPR:v2i32:$src1, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src2))
- // Emits: (VBICd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N10.getNode())) {
- SDNode *Result = Emit_181(N, ARM::VBICd, MVT::v2i32);
- return Result;
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (and:v2i32 (xor:v2i32 DPR:v2i32:$src2, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src1)
- // Emits: (VBICd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N01.getNode())) {
- SDNode *Result = Emit_84(N, ARM::VBICd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src2), DPR:v2i32:$src1)
- // Emits: (VBICd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N00.getNode())) {
- SDNode *Result = Emit_182(N, ARM::VBICd, MVT::v2i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VANDd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VANDd, MVT::v2i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_AND_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v4i32 QPR:v4i32:$src1, (xor:v4i32 QPR:v4i32:$src2, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>))
- // Emits: (VBICq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N11.getNode())) {
- SDNode *Result = Emit_51(N, ARM::VBICq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (and:v4i32 QPR:v4i32:$src1, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src2))
- // Emits: (VBICq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N10.getNode())) {
- SDNode *Result = Emit_181(N, ARM::VBICq, MVT::v4i32);
- return Result;
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (and:v4i32 (xor:v4i32 QPR:v4i32:$src2, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src1)
- // Emits: (VBICq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N01.getNode())) {
- SDNode *Result = Emit_84(N, ARM::VBICq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src2), QPR:v4i32:$src1)
- // Emits: (VBICq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N00.getNode())) {
- SDNode *Result = Emit_182(N, ARM::VBICq, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VANDq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VANDq, MVT::v4i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_183(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { N1, N2, N3, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 4);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_cmp_swap:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)<<P:Predicate_atomic_cmp_swap_8>>
- // Emits: (ATOMIC_CMP_SWAP_I8:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_cmp_swap_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_183(N, ARM::ATOMIC_CMP_SWAP_I8, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_cmp_swap:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)<<P:Predicate_atomic_cmp_swap_16>>
- // Emits: (ATOMIC_CMP_SWAP_I16:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_cmp_swap_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_183(N, ARM::ATOMIC_CMP_SWAP_I16, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_cmp_swap:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)<<P:Predicate_atomic_cmp_swap_32>>
- // Emits: (ATOMIC_CMP_SWAP_I32:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_cmp_swap_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_183(N, ARM::ATOMIC_CMP_SWAP_I32, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_184(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, N1, N2, Chain);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_load_add:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_add_8>>
- // Emits: (ATOMIC_LOAD_ADD_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_add_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_ADD_I8, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_add:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_add_16>>
- // Emits: (ATOMIC_LOAD_ADD_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_add_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_ADD_I16, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_add:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_add_32>>
- // Emits: (ATOMIC_LOAD_ADD_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_add_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_ADD_I32, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_load_and:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_and_8>>
- // Emits: (ATOMIC_LOAD_AND_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_and_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_AND_I8, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_and:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_and_16>>
- // Emits: (ATOMIC_LOAD_AND_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_and_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_AND_I16, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_and:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_and_32>>
- // Emits: (ATOMIC_LOAD_AND_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_and_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_AND_I32, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_load_nand:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_nand_8>>
- // Emits: (ATOMIC_LOAD_NAND_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_nand_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_NAND_I8, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_nand:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_nand_16>>
- // Emits: (ATOMIC_LOAD_NAND_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_nand_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_NAND_I16, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_nand:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_nand_32>>
- // Emits: (ATOMIC_LOAD_NAND_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_nand_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_NAND_I32, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_load_or:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_or_8>>
- // Emits: (ATOMIC_LOAD_OR_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_or_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_OR_I8, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_or:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_or_16>>
- // Emits: (ATOMIC_LOAD_OR_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_or_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_OR_I16, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_or:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_or_32>>
- // Emits: (ATOMIC_LOAD_OR_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_or_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_OR_I32, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_load_sub:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_sub_8>>
- // Emits: (ATOMIC_LOAD_SUB_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_sub_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_SUB_I8, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_sub:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_sub_16>>
- // Emits: (ATOMIC_LOAD_SUB_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_sub_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_SUB_I16, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_sub:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_sub_32>>
- // Emits: (ATOMIC_LOAD_SUB_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_sub_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_SUB_I32, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_load_xor:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_xor_8>>
- // Emits: (ATOMIC_LOAD_XOR_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_xor_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_XOR_I8, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_xor:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_xor_16>>
- // Emits: (ATOMIC_LOAD_XOR_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_xor_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_XOR_I16, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_xor:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_xor_32>>
- // Emits: (ATOMIC_LOAD_XOR_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_xor_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_XOR_I32, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_SWAP_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_swap:i32 GPR:i32:$ptr, GPR:i32:$new)<<P:Predicate_atomic_swap_8>>
- // Emits: (ATOMIC_SWAP_I8:i32 GPR:i32:$ptr, GPR:i32:$new)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_swap_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_SWAP_I8, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_swap:i32 GPR:i32:$ptr, GPR:i32:$new)<<P:Predicate_atomic_swap_16>>
- // Emits: (ATOMIC_SWAP_I16:i32 GPR:i32:$ptr, GPR:i32:$new)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_swap_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_SWAP_I16, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (atomic_swap:i32 GPR:i32:$ptr, GPR:i32:$new)<<P:Predicate_atomic_swap_32>>
- // Emits: (ATOMIC_SWAP_I32:i32 GPR:i32:$ptr, GPR:i32:$new)
- // Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_swap_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, ARM::ATOMIC_SWAP_I32, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_i32(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_31(N, ARM::VMOVRS, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_f32(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_31(N, ARM::VMOVSR, MVT::f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_185(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- ReplaceUses(SDValue(N, 0), N0);
- return NULL;
-}
-SDNode *Select_ISD_BIT_CONVERT_f64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:f64 DPR:v1i64:$src)
- // Emits: DPR:f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:f64 DPR:v2i32:$src)
- // Emits: DPR:f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:f64 DPR:v4i16:$src)
- // Emits: DPR:f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:f64 DPR:v8i8:$src)
- // Emits: DPR:f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:f64 DPR:v2f32:$src)
- // Emits: DPR:f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v8i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v8i8 DPR:v1i64:$src)
- // Emits: DPR:v8i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i8 DPR:v2i32:$src)
- // Emits: DPR:v8i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i8 DPR:v4i16:$src)
- // Emits: DPR:v8i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i8 DPR:f64:$src)
- // Emits: DPR:v8i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i8 DPR:v2f32:$src)
- // Emits: DPR:v8i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v16i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v16i8 QPR:v2i64:$src)
- // Emits: QPR:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v16i8 QPR:v4i32:$src)
- // Emits: QPR:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v16i8 QPR:v8i16:$src)
- // Emits: QPR:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v16i8 QPR:v2f64:$src)
- // Emits: QPR:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v16i8 QPR:v4f32:$src)
- // Emits: QPR:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v4i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v4i16 DPR:v1i64:$src)
- // Emits: DPR:v4i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i16 DPR:v2i32:$src)
- // Emits: DPR:v4i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i16 DPR:v8i8:$src)
- // Emits: DPR:v4i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i16 DPR:f64:$src)
- // Emits: DPR:v4i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i16 DPR:v2f32:$src)
- // Emits: DPR:v4i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v8i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v8i16 QPR:v2i64:$src)
- // Emits: QPR:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i16 QPR:v4i32:$src)
- // Emits: QPR:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i16 QPR:v16i8:$src)
- // Emits: QPR:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i16 QPR:v2f64:$src)
- // Emits: QPR:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i16 QPR:v4f32:$src)
- // Emits: QPR:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v2i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v2i32 DPR:v1i64:$src)
- // Emits: DPR:v2i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i32 DPR:v4i16:$src)
- // Emits: DPR:v2i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i32 DPR:v8i8:$src)
- // Emits: DPR:v2i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i32 DPR:f64:$src)
- // Emits: DPR:v2i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i32 DPR:v2f32:$src)
- // Emits: DPR:v2i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v4i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v4i32 QPR:v2i64:$src)
- // Emits: QPR:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i32 QPR:v8i16:$src)
- // Emits: QPR:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i32 QPR:v16i8:$src)
- // Emits: QPR:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i32 QPR:v2f64:$src)
- // Emits: QPR:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i32 QPR:v4f32:$src)
- // Emits: QPR:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v1i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v1i64 DPR:v2i32:$src)
- // Emits: DPR:v1i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v1i64 DPR:v4i16:$src)
- // Emits: DPR:v1i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v1i64 DPR:v8i8:$src)
- // Emits: DPR:v1i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v1i64 DPR:f64:$src)
- // Emits: DPR:v1i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v1i64 DPR:v2f32:$src)
- // Emits: DPR:v1i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v2i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v2i64 QPR:v4i32:$src)
- // Emits: QPR:v2i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i64 QPR:v8i16:$src)
- // Emits: QPR:v2i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i64 QPR:v16i8:$src)
- // Emits: QPR:v2i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i64 QPR:v2f64:$src)
- // Emits: QPR:v2i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i64 QPR:v4f32:$src)
- // Emits: QPR:v2i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v2f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v2f32 DPR:f64:$src)
- // Emits: DPR:v2f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f32 DPR:v1i64:$src)
- // Emits: DPR:v2f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f32 DPR:v2i32:$src)
- // Emits: DPR:v2f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f32 DPR:v4i16:$src)
- // Emits: DPR:v2f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f32 DPR:v8i8:$src)
- // Emits: DPR:v2f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v4f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v4f32 QPR:v2i64:$src)
- // Emits: QPR:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4f32 QPR:v4i32:$src)
- // Emits: QPR:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4f32 QPR:v8i16:$src)
- // Emits: QPR:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4f32 QPR:v16i8:$src)
- // Emits: QPR:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4f32 QPR:v2f64:$src)
- // Emits: QPR:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v2f64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v2f64 QPR:v2i64:$src)
- // Emits: QPR:v2f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f64 QPR:v4i32:$src)
- // Emits: QPR:v2f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f64 QPR:v8i16:$src)
- // Emits: QPR:v2f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f64 QPR:v16i8:$src)
- // Emits: QPR:v2f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f64 QPR:v4f32:$src)
- // Emits: QPR:v2f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_185(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BR(SDNode *N) {
-
- // Pattern: (br:isVoid (bb:Other):$target)
- // Emits: (B:isVoid (bb:Other):$target)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
- SDNode *Result = Emit_34(N, ARM::B);
- return Result;
- }
- }
-
- // Pattern: (br:isVoid (bb:Other):$target)
- // Emits: (tB:isVoid (bb:Other):$target)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
- SDNode *Result = Emit_34(N, ARM::tB);
- return Result;
- }
- }
-
- // Pattern: (br:isVoid (bb:Other):$target)
- // Emits: (t2B:isVoid (bb:Other):$target)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
- SDNode *Result = Emit_34(N, ARM::t2B);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BRIND(SDNode *N) {
-
- // Pattern: (brind:isVoid GPR:i32:$dst)
- // Emits: (BRIND:isVoid GPR:i32:$dst)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_34(N, ARM::BRIND);
- return Result;
- }
- }
-
- // Pattern: (brind:isVoid GPR:i32:$dst)
- // Emits: (tBRIND:isVoid GPR:i32:$dst)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_34(N, ARM::tBRIND);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BSWAP_i32(SDNode *N) {
-
- // Pattern: (bswap:i32 GPR:i32:$src)
- // Emits: (REV:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDNode *Result = Emit_31(N, ARM::REV, MVT::i32);
- return Result;
- }
-
- // Pattern: (bswap:i32 tGPR:i32:$src)
- // Emits: (tREV:i32 tGPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDNode *Result = Emit_31(N, ARM::tREV, MVT::i32);
- return Result;
- }
-
- // Pattern: (bswap:i32 GPR:i32:$src)
- // Emits: (t2REV:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_31(N, ARM::t2REV, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_186(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VMOV_get_imm8(SDValue(N, 0).getNode());
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, Tmp2, Tmp3);
-}
-SDNode *Select_ISD_BUILD_VECTOR_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm8(N)) {
- SDNode *Result = Emit_186(N, ARM::VMOVv8i8, MVT::v8i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm8(N)) {
- SDNode *Result = Emit_186(N, ARM::VMOVv16i8, MVT::v16i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_187(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VMOV_get_imm16(SDValue(N, 0).getNode());
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, Tmp2, Tmp3);
-}
-SDNode *Select_ISD_BUILD_VECTOR_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm16(N)) {
- SDNode *Result = Emit_187(N, ARM::VMOVv4i16, MVT::v4i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm16(N)) {
- SDNode *Result = Emit_187(N, ARM::VMOVv8i16, MVT::v8i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_188(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VMOV_get_imm32(SDValue(N, 0).getNode());
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, Tmp2, Tmp3);
-}
-SDNode *Select_ISD_BUILD_VECTOR_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm32(N)) {
- SDNode *Result = Emit_188(N, ARM::VMOVv2i32, MVT::v2i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm32(N)) {
- SDNode *Result = Emit_188(N, ARM::VMOVv4i32, MVT::v4i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_189(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VMOV_get_imm64(SDValue(N, 0).getNode());
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, Tmp2, Tmp3);
-}
-SDNode *Select_ISD_BUILD_VECTOR_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm64(N)) {
- SDNode *Result = Emit_189(N, ARM::VMOVv1i64, MVT::v1i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm64(N)) {
- SDNode *Result = Emit_189(N, ARM::VMOVv2i64, MVT::v2i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_190(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- SDValue Ops0[] = { N1, N2, Tmp2, Tmp3, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 6 : 5);
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_191(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- SDValue Ops0[] = { Tmp0, Tmp1, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_ISD_CALLSEQ_END(SDNode *N) {
-
- // Pattern: (ARMcallseq_end:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
- // Emits: (ADJCALLSTACKUP:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
- // Pattern complexity = 9 cost = 1 size = 0
- {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_190(N, ARM::ADJCALLSTACKUP);
- return Result;
- }
- }
- }
-
- // Pattern: (ARMcallseq_end:isVoid (imm:i32):$amt1, (imm:i32):$amt2)
- // Emits: (tADJCALLSTACKUP:isVoid (imm:i32):$amt1, (imm:i32):$amt2)
- // Pattern complexity = 9 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_191(N, ARM::tADJCALLSTACKUP);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_192(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, Tmp1, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 4);
- Chain = SDValue(ResNode, 0);
- SDValue InFlag(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_193(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Tmp0, Chain);
- Chain = SDValue(ResNode, 0);
- SDValue InFlag(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_ISD_CALLSEQ_START(SDNode *N) {
-
- // Pattern: (ARMcallseq_start:isVoid (timm:i32):$amt)
- // Emits: (ADJCALLSTACKDOWN:isVoid (timm:i32):$amt)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_192(N, ARM::ADJCALLSTACKDOWN);
- return Result;
- }
- }
-
- // Pattern: (ARMcallseq_start:isVoid (imm:i32):$amt)
- // Emits: (tADJCALLSTACKDOWN:isVoid (imm:i32):$amt)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_193(N, ARM::tADJCALLSTACKDOWN);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_CTLZ_i32(SDNode *N) {
-
- // Pattern: (ctlz:i32 GPR:i32:$src)
- // Emits: (CLZ:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TOps())) {
- SDNode *Result = Emit_31(N, ARM::CLZ, MVT::i32);
- return Result;
- }
-
- // Pattern: (ctlz:i32 GPR:i32:$src)
- // Emits: (t2CLZ:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_31(N, ARM::t2CLZ, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_194(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_195(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0, Tmp1, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_196(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- SDValue Tmp1 = Transform_so_imm_not_XFORM(Tmp0.getNode());
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_197(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_198(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp1 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_thumb_immshifted_val(Tmp2.getNode());
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp1, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Ops0, 4), 0);
- SDValue Tmp7 = Transform_thumb_immshifted_shamt(Tmp2.getNode());
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp0, Tmp6, Tmp7, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-DISABLE_INLINE SDNode *Emit_199(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp1 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_imm_comp_XFORM(Tmp2.getNode());
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp1, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Ops0, 4), 0);
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp0, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 4);
-}
-DISABLE_INLINE SDNode *Emit_200(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- SDValue Tmp1 = Transform_t2_so_imm_not_XFORM(Tmp0.getNode());
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ISD_Constant_i32(SDNode *N) {
-
- // Pattern: (imm:i32)<<P:Predicate_t2_so_imm>>:$src
- // Emits: (t2MOVi:i32 (imm:i32):$src)
- // Pattern complexity = 5 cost = 1 size = 0
- if ((Subtarget->isThumb2()) &&
- Predicate_t2_so_imm(N)) {
- SDNode *Result = Emit_194(N, ARM::t2MOVi, MVT::i32);
- return Result;
- }
-
- // Pattern: (imm:i32)<<P:Predicate_so_imm>>:$src
- // Emits: (MOVi:i32 (imm:i32):$src)
- // Pattern complexity = 4 cost = 1 size = 0
- if ((!Subtarget->isThumb()) &&
- Predicate_so_imm(N)) {
- SDNode *Result = Emit_194(N, ARM::MOVi, MVT::i32);
- return Result;
- }
-
- // Pattern: (imm:i32)<<P:Predicate_imm0_65535>>:$src
- // Emits: (MOVi16:i32 (imm:i32):$src)
- // Pattern complexity = 4 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops()) &&
- Predicate_imm0_65535(N)) {
- SDNode *Result = Emit_195(N, ARM::MOVi16, MVT::i32);
- return Result;
- }
-
- // Pattern: (imm:i32)<<P:Predicate_so_imm_not>><<X:so_imm_not_XFORM>>:$imm
- // Emits: (MVNi:i32 (so_imm_not_XFORM:i32 (imm:i32):$imm))
- // Pattern complexity = 4 cost = 1 size = 0
- if ((!Subtarget->isThumb()) &&
- Predicate_so_imm_not(N)) {
- SDNode *Result = Emit_196(N, ARM::MVNi, MVT::i32);
- return Result;
- }
-
- // Pattern: (imm:i32)<<P:Predicate_so_imm2part>>:$src
- // Emits: (MOVi2pieces:i32 (imm:i32):$src)
- // Pattern complexity = 4 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!Subtarget->hasV6T2Ops()) &&
- Predicate_so_imm2part(N)) {
- SDNode *Result = Emit_195(N, ARM::MOVi2pieces, MVT::i32);
- return Result;
- }
-
- // Pattern: (imm:i32)<<P:Predicate_imm0_255>>:$src
- // Emits: (tMOVi8:i32 (imm:i32):$src)
- // Pattern complexity = 4 cost = 1 size = 0
- if ((Subtarget->isThumb1Only()) &&
- Predicate_imm0_255(N)) {
- SDNode *Result = Emit_197(N, ARM::tMOVi8, MVT::i32);
- return Result;
- }
- if ((Subtarget->isThumb2())) {
-
- // Pattern: (imm:i32)<<P:Predicate_imm0_65535>>:$src
- // Emits: (t2MOVi16:i32 (imm:i32):$src)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_imm0_65535(N)) {
- SDNode *Result = Emit_195(N, ARM::t2MOVi16, MVT::i32);
- return Result;
- }
-
- // Pattern: (imm:i32)<<P:Predicate_t2_so_imm_not>><<X:t2_so_imm_not_XFORM>>:$src
- // Emits: (t2MVNi:i32 (t2_so_imm_not_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_not>>:$src))
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_t2_so_imm_not(N)) {
- SDNode *Result = Emit_200(N, ARM::t2MVNi, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb1Only())) {
-
- // Pattern: (imm:i32)<<P:Predicate_thumb_immshifted>>:$src
- // Emits: (tLSLri:i32 (tMOVi8:i32 (thumb_immshifted_val:i32 (imm:i32):$src)), (thumb_immshifted_shamt:i32 (imm:i32):$src))
- // Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_thumb_immshifted(N)) {
- SDNode *Result = Emit_198(N, ARM::tMOVi8, ARM::tLSLri, MVT::i32, MVT::i32);
- return Result;
- }
-
- // Pattern: (imm:i32)<<P:Predicate_imm0_255_comp>>:$src
- // Emits: (tMVN:i32 (tMOVi8:i32 (imm_comp_XFORM:i32 (imm:i32):$src)))
- // Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_imm0_255_comp(N)) {
- SDNode *Result = Emit_199(N, ARM::tMOVi8, ARM::tMVN, MVT::i32, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (imm:i32):$src
- // Emits: (MOVi32imm:i32 (imm:i32):$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
- SDNode *Result = Emit_195(N, ARM::MOVi32imm, MVT::i32);
- return Result;
- }
-
- // Pattern: (imm:i32):$src
- // Emits: (t2MOVi32imm:i32 (imm:i32):$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_195(N, ARM::t2MOVi32imm, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_201(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstantFP(*cast<ConstantFPSDNode>(N)->getConstantFPValue(), cast<ConstantFPSDNode>(N)->getValueType(0));
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0, Tmp1, Tmp2);
-}
-SDNode *Select_ISD_ConstantFP_f32(SDNode *N) {
- if ((Subtarget->hasVFP3()) &&
- Predicate_vfp_f32imm(N)) {
- SDNode *Result = Emit_201(N, ARM::FCONSTS, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ConstantFP_f64(SDNode *N) {
- if ((Subtarget->hasVFP3()) &&
- Predicate_vfp_f64imm(N)) {
- SDNode *Result = Emit_201(N, ARM::FCONSTD, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(SDNode *N) {
-
- // Pattern: (extractelt:i32 DPR:v2i32:$src, (imm:iPTR):$lane)
- // Emits: (VGETLNi32:i32 DPR:v2i32:$src, (imm:i32):$lane)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_35(N, ARM::VGETLNi32, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (extractelt:i32 QPR:v4i32:$src, (imm:iPTR):$lane)
- // Emits: (VGETLNi32:i32 (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 6 cost = 2 size = 0
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_48(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNi32, MVT::v2i32, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_202(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = Transform_SSubReg_f32_reg(Tmp3.getNode());
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, Tmp4);
-}
-DISABLE_INLINE SDNode *Emit_203(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = Transform_SSubReg_f32_reg(Tmp3.getNode());
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, Tmp4);
-}
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (extractelt:f32 DPR:v2f32:$src1, (imm:iPTR):$src2)
- // Emits: (EXTRACT_SUBREG:f32 (COPY_TO_REGCLASS:v2f32 DPR:v2f32:$src1, DPR_VFP2:f64), (SSubReg_f32_reg:i32 (imm:i32):$src2))
- // Pattern complexity = 6 cost = 2 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_202(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f32);
- return Result;
- }
-
- // Pattern: (extractelt:f32 QPR:v4f32:$src1, (imm:iPTR):$src2)
- // Emits: (EXTRACT_SUBREG:f32 (COPY_TO_REGCLASS:v4f32 QPR:v4f32:$src1, QPR_VFP2:v16i8), (SSubReg_f32_reg:i32 (imm:i32):$src2))
- // Pattern complexity = 6 cost = 2 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_203(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::v4f32, MVT::f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_204(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_DSubReg_f64_reg(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
-}
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_204(N, TargetOpcode::EXTRACT_SUBREG, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FABS_f32(SDNode *N) {
-
- // Pattern: (fabs:f32 SPR:f32:$a)
- // Emits: (VABSS:f32 SPR:f32:$a)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_31(N, ARM::VABSS, MVT::f32);
- return Result;
- }
-
- // Pattern: (fabs:f32 SPR:f32:$a)
- // Emits: (EXTRACT_SUBREG:f32 (VABSfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
- // Pattern complexity = 3 cost = 4 size = 0
- if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VABSfd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FABS_f64(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDNode *Result = Emit_31(N, ARM::VABSD, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_205(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N000, N001, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_206(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, unsigned Opc4, unsigned Opc5, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3, MVT::SimpleValueType VT4, MVT::SimpleValueType VT5) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp0, N0, Tmp2), 0);
- SDValue Tmp4(CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2), 0);
- SDValue Tmp6 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp7(CurDAG->getMachineNode(Opc3, N->getDebugLoc(), VT3, Tmp4, N1, Tmp6), 0);
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops4[] = { Tmp3, Tmp7, Tmp8, Tmp9 };
- SDValue Tmp10(CurDAG->getMachineNode(Opc4, N->getDebugLoc(), VT4, Ops4, 4), 0);
- SDValue Tmp11 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc5, VT5, Tmp10, Tmp11);
-}
-DISABLE_INLINE SDNode *Emit_207(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N100, N101, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-SDNode *Select_ISD_FADD_f32(SDNode *N) {
- if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:f32 (fneg:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b)), SPR:f32:$dstin)
- // Emits: (VMLSS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FNEG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_205(N, ARM::VMLSS, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (fadd:f32 SPR:f32:$dstin, (fneg:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b)))
- // Emits: (VMLSS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 9 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FNEG) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_207(N, ARM::VMLSS, MVT::f32);
- return Result;
- }
- }
- }
-
- // Pattern: (fadd:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b), SPR:f32:$dstin)
- // Emits: (VMLAS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_127(N, ARM::VMLAS, MVT::f32);
- return Result;
- }
-
- // Pattern: (fadd:f32 SPR:f32:$dstin, (fmul:f32 SPR:f32:$a, SPR:f32:$b))
- // Emits: (VMLAS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_125(N, ARM::VMLAS, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (fadd:f32 SPR:f32:$a, SPR:f32:$b)
- // Emits: (VADDS:f32 SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VADDS, MVT::f32);
- return Result;
- }
-
- // Pattern: (fadd:f32 SPR:f32:$a, SPR:f32:$b)
- // Emits: (EXTRACT_SUBREG:f32 (VADDfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32), (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$b, 1:i32)), 1:i32)
- // Pattern complexity = 3 cost = 6 size = 0
- if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_206(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VADDfd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FADD_f64(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:f64 (fneg:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b)), DPR:f64:$dstin)
- // Emits: (VMLSD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FNEG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_205(N, ARM::VMLSD, MVT::f64);
- return Result;
- }
- }
-
- // Pattern: (fadd:f64 DPR:f64:$dstin, (fneg:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b)))
- // Emits: (VMLSD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 9 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FNEG) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_207(N, ARM::VMLSD, MVT::f64);
- return Result;
- }
- }
- }
-
- // Pattern: (fadd:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b), DPR:f64:$dstin)
- // Emits: (VMLAD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_127(N, ARM::VMLAD, MVT::f64);
- return Result;
- }
-
- // Pattern: (fadd:f64 DPR:f64:$dstin, (fmul:f64 DPR:f64:$a, DPR:f64:$b))
- // Emits: (VMLAD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_125(N, ARM::VMLAD, MVT::f64);
- return Result;
- }
- }
-
- // Pattern: (fadd:f64 DPR:f64:$a, DPR:f64:$b)
- // Emits: (VADDD:f64 DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VADDD, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FADD_v2f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (fadd:v2f32 DPR:v2f32:$src1, (fmul:v2f32 DPR:v2f32:$src2, (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)))
- // Emits: (VMLAslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_129(N, ARM::VMLAslfd, MVT::v2f32);
- return Result;
- }
- }
- }
-
- // Pattern: (fadd:v2f32 DPR:v2f32:$src1, (fmul:v2f32 (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), DPR:v2f32:$src2))
- // Emits: (VMLAslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_130(N, ARM::VMLAslfd, MVT::v2f32);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (fadd:v2f32 (fmul:v2f32 DPR:v2f32:$src2, (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)), DPR:v2f32:$src1)
- // Emits: (VMLAslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N010.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_131(N, ARM::VMLAslfd, MVT::v2f32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:v2f32 (fmul:v2f32 (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), DPR:v2f32:$src2), DPR:v2f32:$src1)
- // Emits: (VMLAslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_132(N, ARM::VMLAslfd, MVT::v2f32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:v2f32 DPR:v2f32:$src1, (fmul:v2f32 DPR:v2f32:$src2, DPR:v2f32:$src3))
- // Emits: (VMLAfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR:v2f32:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_125(N, ARM::VMLAfd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (fadd:v2f32 (fmul:v2f32 DPR:v2f32:$src2, DPR:v2f32:$src3), DPR:v2f32:$src1)
- // Emits: (VMLAfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR:v2f32:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_127(N, ARM::VMLAfd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (fadd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VADDfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VADDfd, MVT::v2f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)))
- // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_129(N, ARM::VMLAslfq, MVT::v4f32);
- return Result;
- }
- }
- }
-
- // Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2))
- // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_130(N, ARM::VMLAslfq, MVT::v4f32);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (fadd:v4f32 (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)), QPR:v4f32:$src1)
- // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N010.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_131(N, ARM::VMLAslfq, MVT::v4f32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:v4f32 (fmul:v4f32 (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2), QPR:v4f32:$src1)
- // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_132(N, ARM::VMLAslfq, MVT::v4f32);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane)))
- // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_137(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
- return Result;
- }
- }
- }
-
- // Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2))
- // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_138(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (fadd:v4f32 (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane)), QPR:v4f32:$src1)
- // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N010.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_139(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:v4f32 (fmul:v4f32 (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2), QPR:v4f32:$src1)
- // Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_140(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, QPR:v4f32:$src3))
- // Emits: (VMLAfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, QPR:v4f32:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_125(N, ARM::VMLAfq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (fadd:v4f32 (fmul:v4f32 QPR:v4f32:$src2, QPR:v4f32:$src3), QPR:v4f32:$src1)
- // Emits: (VMLAfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, QPR:v4f32:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_127(N, ARM::VMLAfq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (fadd:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VADDfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VADDfq, MVT::v4f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FDIV_f32(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDNode *Result = Emit_44(N, ARM::VDIVS, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FDIV_f64(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDNode *Result = Emit_44(N, ARM::VDIVD, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_208(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_209(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N10, N0, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ISD_FMUL_f32(SDNode *N) {
- if ((!HonorSignDependentRoundingFPMath())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:f32 (fneg:f32 SPR:f32:$a), SPR:f32:$b)
- // Emits: (VNMULS:f32 SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FNEG) {
- SDNode *Result = Emit_208(N, ARM::VNMULS, MVT::f32);
- return Result;
- }
-
- // Pattern: (fmul:f32 SPR:f32:$b, (fneg:f32 SPR:f32:$a))
- // Emits: (VNMULS:f32 SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FNEG) {
- SDNode *Result = Emit_209(N, ARM::VNMULS, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (fmul:f32 SPR:f32:$a, SPR:f32:$b)
- // Emits: (VMULS:f32 SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_44(N, ARM::VMULS, MVT::f32);
- return Result;
- }
-
- // Pattern: (fmul:f32 SPR:f32:$a, SPR:f32:$b)
- // Emits: (EXTRACT_SUBREG:f32 (VMULfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32), (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$b, 1:i32)), 1:i32)
- // Pattern complexity = 3 cost = 6 size = 0
- if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_206(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VMULfd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FMUL_f64(SDNode *N) {
- if ((!HonorSignDependentRoundingFPMath())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:f64 (fneg:f64 DPR:f64:$a), DPR:f64:$b)
- // Emits: (VNMULD:f64 DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FNEG) {
- SDNode *Result = Emit_208(N, ARM::VNMULD, MVT::f64);
- return Result;
- }
-
- // Pattern: (fmul:f64 DPR:f64:$b, (fneg:f64 DPR:f64:$a))
- // Emits: (VNMULD:f64 DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FNEG) {
- SDNode *Result = Emit_209(N, ARM::VNMULD, MVT::f64);
- return Result;
- }
- }
-
- // Pattern: (fmul:f64 DPR:f64:$a, DPR:f64:$b)
- // Emits: (VMULD:f64 DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasVFP2())) {
- SDNode *Result = Emit_44(N, ARM::VMULD, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FMUL_v2f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:v2f32 DPR:v2f32:$src1, (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src2, (imm:i32):$lane))
- // Emits: (VMULslfd:v2f32 DPR:v2f32:$src1, DPR_VFP2:v2f32:$src2, (imm:i32):$lane)
- // Pattern complexity = 9 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_126(N, ARM::VMULslfd, MVT::v2f32);
- return Result;
- }
- }
- }
-
- // Pattern: (fmul:v2f32 (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src2, (imm:i32):$lane), DPR:v2f32:$src1)
- // Emits: (VMULslfd:v2f32 DPR:v2f32:$src1, DPR_VFP2:v2f32:$src2, (imm:i32):$lane)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_128(N, ARM::VMULslfd, MVT::v2f32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fmul:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VMULfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VMULfd, MVT::v2f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_210(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_DSubReg_i32_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N10, Tmp3), 0);
- SDValue Tmp5 = Transform_SubReg_i32_lane(Tmp2.getNode());
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N0, Tmp4, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-DISABLE_INLINE SDNode *Emit_211(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_DSubReg_i32_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp3), 0);
- SDValue Tmp5 = Transform_SubReg_i32_lane(Tmp2.getNode());
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N1, Tmp4, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-SDNode *Select_ISD_FMUL_v4f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:v4f32 QPR:v4f32:$src1, (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src2, (imm:i32):$lane))
- // Emits: (VMULslfq:v4f32 QPR:v4f32:$src1, DPR_VFP2:v2f32:$src2, (imm:i32):$lane)
- // Pattern complexity = 9 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_126(N, ARM::VMULslfq, MVT::v4f32);
- return Result;
- }
- }
- }
-
- // Pattern: (fmul:v4f32 (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src2, (imm:i32):$lane), QPR:v4f32:$src1)
- // Emits: (VMULslfq:v4f32 QPR:v4f32:$src1, DPR_VFP2:v2f32:$src2, (imm:i32):$lane)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_128(N, ARM::VMULslfq, MVT::v4f32);
- return Result;
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:v4f32 QPR:v4f32:$src1, (NEONvduplane:v4f32 QPR:v4f32:$src2, (imm:i32):$lane))
- // Emits: (VMULslfq:v4f32 QPR:v4f32:$src1, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 9 cost = 2 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_210(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
- return Result;
- }
- }
- }
-
- // Pattern: (fmul:v4f32 (NEONvduplane:v4f32 QPR:v4f32:$src2, (imm:i32):$lane), QPR:v4f32:$src1)
- // Emits: (VMULslfq:v4f32 QPR:v4f32:$src1, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 9 cost = 2 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_211(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fmul:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VMULfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_44(N, ARM::VMULfq, MVT::v4f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_212(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N01, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ISD_FNEG_f32(SDNode *N) {
-
- // Pattern: (fneg:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b))
- // Emits: (VNMULS:f32 SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->hasVFP2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_212(N, ARM::VNMULS, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (fneg:f32 SPR:f32:$a)
- // Emits: (VNEGS:f32 SPR:f32:$a)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_31(N, ARM::VNEGS, MVT::f32);
- return Result;
- }
-
- // Pattern: (fneg:f32 SPR:f32:$a)
- // Emits: (EXTRACT_SUBREG:f32 (VNEGf32d_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
- // Pattern complexity = 3 cost = 4 size = 0
- if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VNEGf32d_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FNEG_f64(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
-
- // Pattern: (fneg:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b))
- // Emits: (VNMULD:f64 DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_212(N, ARM::VNMULD, MVT::f64);
- return Result;
- }
- }
-
- // Pattern: (fneg:f64 DPR:f64:$a)
- // Emits: (VNEGD:f64 DPR:f64:$a)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_31(N, ARM::VNEGD, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FNEG_v2f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VNEGf32d, MVT::v2f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FNEG_v4f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_31(N, ARM::VNEGf32q, MVT::v4f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_EXTEND_f64(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_31(N, ARM::VCVTDS, MVT::f64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_ROUND_f32(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_31(N, ARM::VCVTSD, MVT::f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_TO_SINT_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_31(N, ARM::VCVTf2sd, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_TO_SINT_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_31(N, ARM::VCVTf2sq, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_TO_UINT_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_31(N, ARM::VCVTf2ud, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_TO_UINT_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_31(N, ARM::VCVTf2uq, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSQRT_f32(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDNode *Result = Emit_31(N, ARM::VSQRTS, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSQRT_f64(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDNode *Result = Emit_31(N, ARM::VSQRTD, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
+// The main instruction selector code.
+SDNode *SelectCode(SDNode *N) {
+ // Opcodes are emitted as 2 bytes, TARGET_OPCODE handles this.
+ #define TARGET_OPCODE(X) X & 255, unsigned(X) >> 8
+ static const unsigned char MatcherTable[] = {
+ OPC_SwitchOpcode , 94|128,83, ISD::OR,
+ OPC_Scope, 27|128,59,
+ OPC_MoveChild, 0,
+ OPC_Scope, 80|128,8,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 12|128,1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 102|128,3,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 95,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 95,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 95,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 95,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 95,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 44|128,1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 69,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 69,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 45|128,1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 70,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 70,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 99,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 75|128,10,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 56|128,5,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 114,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 86|128,1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 92,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 92,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 87|128,1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 93,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 93,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 88|128,1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 94,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 94,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 0,
+ 66|128,7,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 102|128,3,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 95,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 95,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 95,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 95,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 95,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 44|128,1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 69,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 69,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 45|128,1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 70,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 70,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 99,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 75|128,10,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 56|128,5,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 114,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 86|128,1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 92,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 92,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 87|128,1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 93,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 93,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 88|128,1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 94,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 94,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 0,
+ 66|128,7,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 102|128,3,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 95,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 95,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 95,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 95,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 95,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 44|128,1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 69,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 69,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 45|128,1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 70,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 70,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 99,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 75|128,10,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 56|128,5,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 114,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 114,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 86|128,1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 92,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 92,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 87|128,1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 93,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 93,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 88|128,1,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 94,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 94,
+ OPC_CheckAndImm, 0|128,0|128,0|128,120|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV16), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 0,
+ 20|128,1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,127|128,15,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 63, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 0,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PKHTB), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2PKHTB), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 0,
+ 63, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PKHTB), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2PKHTB), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 0,
+ 0,
+ 110|128,1,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_Scope, 26|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 73, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 0,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,127|128,15,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PKHTB), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2PKHTB), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 73, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,127|128,15,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2PKHTB), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PKHTB), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 0,
+ 75,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,127|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PKHBT), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2PKHBT), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 0,
+ 0,
+ 79,
+ OPC_CheckAndImm, 0|128,0|128,124|128,127|128,15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PKHBT), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2PKHBT), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 0,
+ 50,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORNrs), 0,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 115|128,14,
+ OPC_MoveChild, 0,
+ OPC_Scope, 48,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORNrs), 0,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 41,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,127|128,15,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PKHBT), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 46,
+ OPC_CheckAndImm, 0|128,0|128,124|128,127|128,15,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 16,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PKHTB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 41,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,127|128,15,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2PKHBT), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 81,
+ OPC_CheckAndImm, 0|128,0|128,124|128,127|128,15,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_Scope, 36,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 16,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2PKHTB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 31,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2PKHBT), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 46,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,127|128,15,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 16,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2PKHTB), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 41,
+ OPC_CheckAndImm, 0|128,0|128,124|128,127|128,15,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PKHBT), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 46,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 0|128,0|128,124|128,127|128,15,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 16,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PKHTB), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 72,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 0,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PKHBT), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2PKHBT), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 0,
+ 72,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 0,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2PKHBT), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PKHBT), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 36|128,10,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_Scope, 9|128,4,
+ OPC_RecordChild0,
+ OPC_Scope, 98|128,2,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_Scope, 103,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 58,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 1, 0, 2, 3, 4,
+ 20, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 34,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 80,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 35,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 1, 0, 2, 3, 4,
+ 35,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 79,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 34,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 0, 1, 2, 3, 4,
+ 34,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 80,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 35,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 0, 1, 2, 3, 4,
+ 35,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 0,
+ 32|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 76,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_Scope, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 1, 2, 0, 3, 4,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 76,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_Scope, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 1, 2, 0, 3, 4,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 0,
+ 0,
+ 34|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 77,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_Scope, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 0, 2, 1, 3, 4,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 0, 2, 1, 3, 4,
+ 0,
+ 77,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_Scope, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 0, 2, 1, 3, 4,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLd), 0,
+ 1, MVT::v2i32, 5, 0, 2, 1, 3, 4,
+ 0,
+ 0,
+ 75|128,3,
+ OPC_RecordChild0,
+ OPC_Scope, 36|128,2,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_Scope, 41,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 1, 0, 2, 3, 4,
+ 80,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 35,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 1, 0, 2, 3, 4,
+ 35,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 79,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 34,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 34,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 80,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_Scope, 35,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 35,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 0,
+ 32|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 76,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_Scope, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 1, 2, 0, 3, 4,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 76,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_Scope, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 1, 2, 0, 3, 4,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 0,
+ 0,
+ 34|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 77,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_Scope, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 0, 2, 1, 3, 4,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 0, 2, 1, 3, 4,
+ 0,
+ 77,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_Scope, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 0, 2, 1, 3, 4,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBSLq), 0,
+ 1, MVT::v4i32, 5, 0, 2, 1, 3, 4,
+ 0,
+ 0,
+ 0,
+ 40,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVTi16), 0,
+ 1, MVT::i32, 4, 0, 3, 4, 5,
+ 0,
+ 32,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ORRrs), 0,
+ 1, MVT::i32, 7, 0, 2, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 0,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MOVTi16), 0,
+ 1, MVT::i32, 4, 0, 3, 4, 5,
+ 17|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 54,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORNri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 31,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ORRrs), 0,
+ 1, MVT::i32, 7, 1, 2, 3, 4, 5, 6, 7,
+ 54,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORNri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 0,
+ 110,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 51,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORNri), 0,
+ 1, MVT::i32, 5, 1, 2, 3, 4, 5,
+ 51,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORNri), 0,
+ 1, MVT::i32, 5, 1, 2, 3, 4, 5,
+ 0,
+ 109,
+ OPC_RecordChild0,
+ OPC_Scope, 59,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 25,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORRrs), 0,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORRrs), 0,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 0,
+ 45,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORNrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 46,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORNrr), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 92,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 53,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 19, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VORNd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 19, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VORNq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 30,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VORNd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 0,
+ 70,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 31,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VORNd), 0,
+ 1, MVT::v2i32, 4, 1, 0, 2, 3,
+ 31,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VORNd), 0,
+ 1, MVT::v2i32, 4, 1, 0, 2, 3,
+ 0,
+ 35,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VORNq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 70,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 31,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VORNq), 0,
+ 1, MVT::v4i32, 4, 1, 0, 2, 3,
+ 31,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VORNq), 0,
+ 1, MVT::v4i32, 4, 1, 0, 2, 3,
+ 0,
+ 61,
+ OPC_CheckOrImm, 0|128,0|128,124|128,127|128,15,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 24,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitInteger, MVT::i32, 127|128,127|128,3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVTi16), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 127|128,127|128,3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MOVTi16), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 93|128,2,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 94|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 30,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ORRri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 30,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORRri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 33,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORNri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ 59,
+ OPC_CheckPredicate, 7,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 2, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::ORRri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 3, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ORRri), 0,
+ 1, MVT::i32, 5, 7, 9, 10, 11, 12,
+ 59,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 4, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::t2ORRri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 5, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORRri), 0,
+ 1, MVT::i32, 5, 7, 9, 10, 11, 12,
+ 0,
+ 76,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ORRrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tORR), 0,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ORRrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 21,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VORRd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 21,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VORRq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 44|128,71, ISD::ADD,
+ OPC_Scope, 94,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_Scope, 12,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABB), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 12,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABB), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 0,
+ 94,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_Scope, 12,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 12,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABB), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 59|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_Scope, 44,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTABrr_rot), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 45,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTAHrr_rot), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 44,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTABrr_rot), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 45,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTAHrr_rot), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 0,
+ 62|128,1,
+ OPC_MoveChild, 0,
+ OPC_Scope, 45,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTABrr_rot), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 46,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTAHrr_rot), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 45,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTABrr_rot), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 46,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTAHrr_rot), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 81|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 10|128,1, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_Scope, 57,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABT), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 73,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_Scope, 12,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATB), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 12,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABT), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 0,
+ 0,
+ 61, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 0|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_Scope, 58,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABT), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 58,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABT), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 66,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATB), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 0|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_Scope, 58,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 58,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATB), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 66,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 0|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 58,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 58,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 115,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_Scope, 26,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTABrr), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 27,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTAHrr), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTABrr), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 27,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTAHrr), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 118,
+ OPC_MoveChild, 0,
+ OPC_Scope, 27,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTABrr), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 28,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTAHrr), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 27,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTABrr), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 28,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTAHrr), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 48|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 94, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATT), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 20,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLATT), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 20,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATT), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 0,
+ 73, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWT), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 20,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLAWT), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 0,
+ 70,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_Scope, 12,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATT), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 12,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATT), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 54,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWT), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 104,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 46,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWT), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 46,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWT), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 54,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLATT), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 70,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_Scope, 12,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLATT), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 12,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLATT), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 54,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLAWT), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 104,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 46,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLAWT), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 46,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLAWT), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 116|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 35|128,1, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 67, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABT), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 20,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLABT), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 88, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATB), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 20,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLATB), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 20,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABT), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 0,
+ 0,
+ 71, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 20,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLAWB), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 0,
+ 100,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 44, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABT), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 44, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABT), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 52,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATB), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 100,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 44, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 44, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATB), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 52,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 100,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 44,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 44,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 52,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLABT), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 100,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 44, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLABT), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 44, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLABT), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 52,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLATB), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 100,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 44, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLATB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 44, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLATB), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 52,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLAWB), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 100,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 44,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLAWB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 44,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLAWB), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 126|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADDrs), 0,
+ 1, MVT::i32, 7, 0, 2, 3, 4, 5, 6, 7,
+ 10|128,1,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 88, ISD::MUL,
+ OPC_Scope, 42,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABT), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 42,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATB), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 42, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 31,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADDrs), 0,
+ 1, MVT::i32, 7, 1, 2, 3, 4, 5, 6, 7,
+ 46,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABT), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 0,
+ 94,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 43,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABT), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 43,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABT), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 47,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATB), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 94,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 43,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 43,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLATB), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 47,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 89,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_Scope, 38,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 38,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 13|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_Scope, 28,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTABrr_rot), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 28,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTAHrr_rot), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 28,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTABrr_rot), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 28,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTAHrr_rot), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 0,
+ 16|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_Scope, 29,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTABrr_rot), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 29,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTAHrr_rot), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 29,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTABrr_rot), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 29,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTAHrr_rot), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 18|128,2,
+ OPC_RecordChild0,
+ OPC_Scope, 49,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABB), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 30,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADDrs), 0,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 60|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 45,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLABB), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 6|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 62,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 23, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv4i16), 0,
+ 1, MVT::v4i16, 6, 0, 1, 2, 4, 5, 6,
+ 23, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv8i16), 0,
+ 1, MVT::v8i16, 6, 0, 1, 2, 4, 5, 6,
+ 0,
+ 62,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 23, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv2i32), 0,
+ 1, MVT::v2i32, 6, 0, 1, 2, 4, 5, 6,
+ 23, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv4i32), 0,
+ 1, MVT::v4i32, 6, 0, 1, 2, 4, 5, 6,
+ 0,
+ 0,
+ 0,
+ 0,
+ 50,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 31,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADDrs), 0,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 50,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMLABB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 46,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv4i16), 0,
+ 1, MVT::v4i16, 6, 0, 3, 1, 4, 5, 6,
+ 92,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 42,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv4i16), 0,
+ 1, MVT::v4i16, 6, 3, 0, 1, 4, 5, 6,
+ 42,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv4i16), 0,
+ 1, MVT::v4i16, 6, 3, 2, 0, 4, 5, 6,
+ 0,
+ 46,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv2i32), 0,
+ 1, MVT::v2i32, 6, 0, 3, 1, 4, 5, 6,
+ 92,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 42,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv2i32), 0,
+ 1, MVT::v2i32, 6, 3, 0, 1, 4, 5, 6,
+ 42,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv2i32), 0,
+ 1, MVT::v2i32, 6, 3, 2, 0, 4, 5, 6,
+ 0,
+ 46,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv8i16), 0,
+ 1, MVT::v8i16, 6, 0, 3, 1, 4, 5, 6,
+ 92,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 42,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv8i16), 0,
+ 1, MVT::v8i16, 6, 3, 0, 1, 4, 5, 6,
+ 42,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv8i16), 0,
+ 1, MVT::v8i16, 6, 3, 2, 0, 4, 5, 6,
+ 0,
+ 46,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv4i32), 0,
+ 1, MVT::v4i32, 6, 0, 3, 1, 4, 5, 6,
+ 92,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 42,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv4i32), 0,
+ 1, MVT::v4i32, 6, 3, 0, 1, 4, 5, 6,
+ 42,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv4i32), 0,
+ 1, MVT::v4i32, 6, 3, 2, 0, 4, 5, 6,
+ 0,
+ 47|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 110,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 50,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 6, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 2, 5,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 7, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv8i16), 0,
+ 1, MVT::v8i16, 6, 0, 1, 6, 8, 9, 10,
+ 50,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 8, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 2, 5,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 9, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv4i32), 0,
+ 1, MVT::v4i32, 6, 0, 1, 6, 8, 9, 10,
+ 0,
+ 56,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 6, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 1, 5,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 7, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv8i16), 0,
+ 1, MVT::v8i16, 6, 0, 3, 6, 8, 9, 10,
+ 0,
+ 122,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 57,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 6, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 1, 5,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 7, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv8i16), 0,
+ 1, MVT::v8i16, 6, 3, 0, 6, 8, 9, 10,
+ 57,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 6, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 0, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 7, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv8i16), 0,
+ 1, MVT::v8i16, 6, 3, 2, 6, 8, 9, 10,
+ 0,
+ 61,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 8, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 1, 5,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 9, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv4i32), 0,
+ 1, MVT::v4i32, 6, 0, 3, 6, 8, 9, 10,
+ 122,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 57,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 8, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 1, 5,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 9, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv4i32), 0,
+ 1, MVT::v4i32, 6, 3, 0, 6, 8, 9, 10,
+ 57,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 8, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 0, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 9, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslv4i32), 0,
+ 1, MVT::v4i32, 6, 3, 2, 6, 8, 9, 10,
+ 0,
+ 57|128,6,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 74|128,1, ARMISD::VSHRs,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv8i8), 0,
+ 1, MVT::v8i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv1i64), 0,
+ 1, MVT::v1i64, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv16i8), 0,
+ 1, MVT::v16i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 3, 4, 5,
+ 0,
+ 74|128,1, ARMISD::VSHRu,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv8i8), 0,
+ 1, MVT::v8i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv1i64), 0,
+ 1, MVT::v1i64, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv16i8), 0,
+ 1, MVT::v16i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 3, 4, 5,
+ 0,
+ 74|128,1, ARMISD::VRSHRs,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv8i8), 0,
+ 1, MVT::v8i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv1i64), 0,
+ 1, MVT::v1i64, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv16i8), 0,
+ 1, MVT::v16i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 3, 4, 5,
+ 0,
+ 74|128,1, ARMISD::VRSHRu,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv8i8), 0,
+ 1, MVT::v8i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv1i64), 0,
+ 1, MVT::v1i64, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv16i8), 0,
+ 1, MVT::v16i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 3, 4, 5,
+ 0,
+ 0,
+ 60|128,6,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 75|128,1, ARMISD::VSHRs,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 22, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv8i8), 0,
+ 1, MVT::v8i8, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv4i16), 0,
+ 1, MVT::v4i16, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv2i32), 0,
+ 1, MVT::v2i32, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv1i64), 0,
+ 1, MVT::v1i64, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv16i8), 0,
+ 1, MVT::v16i8, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv8i16), 0,
+ 1, MVT::v8i16, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv4i32), 0,
+ 1, MVT::v4i32, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAsv2i64), 0,
+ 1, MVT::v2i64, 5, 2, 0, 3, 4, 5,
+ 0,
+ 75|128,1, ARMISD::VSHRu,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 22, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv8i8), 0,
+ 1, MVT::v8i8, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv4i16), 0,
+ 1, MVT::v4i16, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv2i32), 0,
+ 1, MVT::v2i32, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv1i64), 0,
+ 1, MVT::v1i64, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv16i8), 0,
+ 1, MVT::v16i8, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv8i16), 0,
+ 1, MVT::v8i16, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv4i32), 0,
+ 1, MVT::v4i32, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRAuv2i64), 0,
+ 1, MVT::v2i64, 5, 2, 0, 3, 4, 5,
+ 0,
+ 75|128,1, ARMISD::VRSHRs,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 22, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv8i8), 0,
+ 1, MVT::v8i8, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv4i16), 0,
+ 1, MVT::v4i16, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv2i32), 0,
+ 1, MVT::v2i32, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv1i64), 0,
+ 1, MVT::v1i64, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv16i8), 0,
+ 1, MVT::v16i8, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv8i16), 0,
+ 1, MVT::v8i16, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv4i32), 0,
+ 1, MVT::v4i32, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAsv2i64), 0,
+ 1, MVT::v2i64, 5, 2, 0, 3, 4, 5,
+ 0,
+ 75|128,1, ARMISD::VRSHRu,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 22, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv8i8), 0,
+ 1, MVT::v8i8, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv4i16), 0,
+ 1, MVT::v4i16, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv2i32), 0,
+ 1, MVT::v2i32, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv1i64), 0,
+ 1, MVT::v1i64, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv16i8), 0,
+ 1, MVT::v16i8, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv8i16), 0,
+ 1, MVT::v8i16, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv4i32), 0,
+ 1, MVT::v4i32, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSRAuv2i64), 0,
+ 1, MVT::v2i64, 5, 2, 0, 3, 4, 5,
+ 0,
+ 0,
+ 82,
+ OPC_RecordChild0,
+ OPC_Scope, 39,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABB), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 38,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 10, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SUBri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ 0,
+ 40,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLABB), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 127|128,4,
+ OPC_RecordChild0,
+ OPC_Scope, 60|128,4,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 30,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADDri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 33,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 11, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SUBri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ 30,
+ OPC_CheckPredicate, 13,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tADDi3), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 30,
+ OPC_CheckPredicate, 14,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tADDi8), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 33,
+ OPC_CheckPredicate, 15,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 10, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSUBi3), 0,
+ 1, MVT::i32, 5, 2, 0, 4, 5, 6,
+ 33,
+ OPC_CheckPredicate, 16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 10, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSUBi8), 0,
+ 1, MVT::i32, 5, 2, 0, 4, 5, 6,
+ 30,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADDri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 30,
+ OPC_CheckPredicate, 17,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADDri12), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 33,
+ OPC_CheckPredicate, 18,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 12, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SUBri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ 33,
+ OPC_CheckPredicate, 19,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 10, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SUBri12), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ 59,
+ OPC_CheckPredicate, 7,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 2, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::ADDri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 3, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADDri), 0,
+ 1, MVT::i32, 5, 7, 9, 10, 11, 12,
+ 59,
+ OPC_CheckPredicate, 20,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 13, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::SUBri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 14, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SUBri), 0,
+ 1, MVT::i32, 5, 7, 9, 10, 11, 12,
+ 59,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 4, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::t2ADDri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 5, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADDri), 0,
+ 1, MVT::i32, 5, 7, 9, 10, 11, 12,
+ 59,
+ OPC_CheckPredicate, 21,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 15, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::t2SUBri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 16, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SUBri), 0,
+ 1, MVT::i32, 5, 7, 9, 10, 11, 12,
+ 0,
+ 61,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_Scope, 25,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTABrr), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 25,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTAHrr), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 64,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 30, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MLA), 0,
+ 1, MVT::i32, 6, 0, 1, 2, 3, 4, 5,
+ 26, ISD::MULHS,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMMLA), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 62,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_Scope, 25,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTABrr), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 25,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTAHrr), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 60,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 26, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MLA), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 26, ISD::MULHS,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMMLA), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 14|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAv8i8), 0,
+ 1, MVT::v8i8, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAv16i8), 0,
+ 1, MVT::v16i8, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 63,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_Scope, 26,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTABrr), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 26,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTAHrr), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 63,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 29, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MLA), 0,
+ 1, MVT::i32, 6, 1, 2, 0, 3, 4, 5,
+ 25, ISD::MULHS,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMMLA), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 63,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_Scope, 26,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTABrr), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 26,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTAHrr), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 59,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 25, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MLA), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 25, ISD::MULHS,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMMLA), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 14|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAv8i8), 0,
+ 1, MVT::v8i8, 5, 2, 0, 1, 3, 4,
+ 20, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAv4i16), 0,
+ 1, MVT::v4i16, 5, 2, 0, 1, 3, 4,
+ 20, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAv2i32), 0,
+ 1, MVT::v2i32, 5, 2, 0, 1, 3, 4,
+ 20, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAv16i8), 0,
+ 1, MVT::v16i8, 5, 2, 0, 1, 3, 4,
+ 20, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAv8i16), 0,
+ 1, MVT::v8i16, 5, 2, 0, 1, 3, 4,
+ 20, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAv4i32), 0,
+ 1, MVT::v4i32, 5, 2, 0, 1, 3, 4,
+ 0,
+ 120|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 74, MVT::i32,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADDrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tADDrr), 0,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADDrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 19, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 19, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 19, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 19, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 19, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 19, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 19, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 19, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 80|128,11, ISD::MUL,
+ OPC_Scope, 50|128,4,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 65|128,3, ISD::SRA,
+ OPC_Scope, 116,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_Scope, 57,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_Scope, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULBB), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULBB), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 30,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULBT), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 70,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_Scope, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULTB), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULBT), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 55,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULTB), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 73|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 93, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULTT), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMULTT), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULTT), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMULTT), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 91, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULTB), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMULTB), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULBT), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMULBT), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 0,
+ 0,
+ 104, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULBT), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMULBT), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULTB), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMULTB), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 0,
+ 40,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULBT), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 55,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_Scope, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULTB), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULBT), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 40,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULTB), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 66,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULBB), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMULBB), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 0|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 59,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 3, 4, 5,
+ 0,
+ 59,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 0,
+ 0,
+ 1|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 60,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslv4i16), 0,
+ 1, MVT::v4i16, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslv8i16), 0,
+ 1, MVT::v8i16, 5, 2, 0, 3, 4, 5,
+ 0,
+ 60,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslv2i32), 0,
+ 1, MVT::v2i32, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslv4i32), 0,
+ 1, MVT::v4i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 0,
+ 106,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 48,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 6, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 1, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 7, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 5, 7, 8, 9,
+ 48,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 8, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 1, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 9, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 5, 7, 8, 9,
+ 0,
+ 107,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 49,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 6, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 0, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 7, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslv8i16), 0,
+ 1, MVT::v8i16, 5, 2, 5, 7, 8, 9,
+ 49,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 8, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 0, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 9, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslv4i32), 0,
+ 1, MVT::v4i32, 5, 2, 5, 7, 8, 9,
+ 0,
+ 111|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 32,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULBB), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 73|128,1,
+ OPC_RecordChild1,
+ OPC_SwitchType , 70, MVT::i32,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MUL), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tMUL), 0,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MUL), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 19, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 19, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 19, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 19, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 19, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 19, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 0,
+ 120|128,16, ISD::AND,
+ OPC_Scope, 3|128,1,
+ OPC_CheckAndImm, 127|128,1|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 59, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 24,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTB16r_rot), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 24,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTB16r_rot), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 59, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTB16r_rot), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTB16r_rot), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 42,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTBr_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 43,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTHr_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 44,
+ OPC_CheckAndImm, 127|128,1|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTB16r_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 42,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTBr_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 43,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTHr_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 44,
+ OPC_CheckAndImm, 127|128,1|128,124|128,7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTB16r_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 24,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTBr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 25,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTHr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 26,
+ OPC_CheckAndImm, 127|128,1|128,124|128,7,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::UXTB16r), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 24,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTBr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 25,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTHr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 26,
+ OPC_CheckAndImm, 127|128,1|128,124|128,7,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2UXTB16r), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 51,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BICrs), 0,
+ 1, MVT::i32, 7, 0, 2, 3, 4, 5, 6, 7,
+ 51,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BICrs), 0,
+ 1, MVT::i32, 7, 1, 2, 3, 4, 5, 6, 7,
+ 50,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2BICrs), 0,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 50,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2BICrs), 0,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 98|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ANDrs), 0,
+ 1, MVT::i32, 7, 0, 2, 3, 4, 5, 6, 7,
+ 103,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 45,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BICri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 45,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2BICri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 0,
+ 31,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ANDrs), 0,
+ 1, MVT::i32, 7, 1, 2, 3, 4, 5, 6, 7,
+ 54,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BICri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 0,
+ 110,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 51,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BICri), 0,
+ 1, MVT::i32, 5, 1, 2, 3, 4, 5,
+ 51,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BICri), 0,
+ 1, MVT::i32, 5, 1, 2, 3, 4, 5,
+ 0,
+ 55,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2BICri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 110,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 51,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2BICri), 0,
+ 1, MVT::i32, 5, 1, 2, 3, 4, 5,
+ 51,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2BICri), 0,
+ 1, MVT::i32, 5, 1, 2, 3, 4, 5,
+ 0,
+ 32|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 59,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 25,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ANDrs), 0,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ANDrs), 0,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 0,
+ 96,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BICrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBIC), 0,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2BICrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 0,
+ 97,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BICrr), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBIC), 0,
+ 1, MVT::i32, 5, 2, 1, 0, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2BICrr), 0,
+ 1, MVT::i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 92,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 53,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 19, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBICd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 19, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBICq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 30,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBICd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 0,
+ 70,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 31,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBICd), 0,
+ 1, MVT::v2i32, 4, 1, 0, 2, 3,
+ 31,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBICd), 0,
+ 1, MVT::v2i32, 4, 1, 0, 2, 3,
+ 0,
+ 35,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBICq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 70,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 31,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBICq), 0,
+ 1, MVT::v4i32, 4, 1, 0, 2, 3,
+ 31,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VBICq), 0,
+ 1, MVT::v4i32, 4, 1, 0, 2, 3,
+ 0,
+ 24,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tUXTB), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 25,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tUXTH), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 61|128,2,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 62|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 30,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ANDri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 26,
+ OPC_CheckPredicate, 22,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BFC), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 33,
+ OPC_CheckPredicate, 23,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 17, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BICri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ 30,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ANDri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 26,
+ OPC_CheckPredicate, 22,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2BFC), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 33,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2BICri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ 0,
+ 76,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ANDrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tAND), 0,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ANDrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 21,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VANDd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 21,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VANDq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 112|128,3, ISD::SIGN_EXTEND_INREG,
+ OPC_Scope, 85|128,2,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 80|128,1, ISD::OR,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 100, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REVSH), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREVSH), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REVSH), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 100, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckAndImm, 0|128,126|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REVSH), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREVSH), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REVSH), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 0,
+ 124, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_Scope, 26,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTBr_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 26,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTHr_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 26,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTBr_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 26,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTHr_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 0,
+ 0,
+ 21|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_Scope, 23,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTBr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 23,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTHr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 23,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSXTB), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 23,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSXTH), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 23,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTBr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 23,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTHr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 0,
+ 117|128,4, ISD::SRA,
+ OPC_Scope, 126|128,2,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 55,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULWB), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 55,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULWB), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 66,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULWT), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMULWT), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 66,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULWT), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMULWT), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 64,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULWB), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMULWB), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 64,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULWB), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMULWB), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 0,
+ 30,
+ OPC_RecordNode,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVs), 0,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 79,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_Scope, 35,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULWB), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 35,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 10,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 16,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULWB), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 2|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 70,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 24,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ASRri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 30,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tASRri), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 54,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tASRrr), 0,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ASRrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 0,
+ 0,
+ 17|128,1, ARMISD::BR_JT,
+ OPC_RecordNode,
+ OPC_Scope, 89,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 47, ISD::LOAD,
+ OPC_CheckPredicate, 25,
+ OPC_CheckPredicate, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BR_JTm), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 5, 6, 7, 3, 8,
+ 34, ISD::ADD,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BR_JTadd), 0|OPFL_Chain,
+ 0, 4, 1, 2, 3, 5,
+ 0,
+ 51,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_Scope, 16,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BR_JTr), 0|OPFL_Chain,
+ 0, 3, 1, 2, 4,
+ 16,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBR_JTr), 0|OPFL_Chain,
+ 0, 3, 1, 2, 4,
+ 0,
+ 0,
+ 94|128,20, ISD::LOAD,
+ OPC_CheckPredicate, 25,
+ OPC_Scope, 34,
+ OPC_CheckPredicate, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDR), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 74,
+ OPC_CheckPredicate, 27,
+ OPC_Scope, 34,
+ OPC_CheckPredicate, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 34,
+ OPC_CheckPredicate, 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 10|128,1,
+ OPC_CheckPredicate, 30,
+ OPC_Scope, 34,
+ OPC_CheckPredicate, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRSH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 63,
+ OPC_CheckPredicate, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 25,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRSB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 25,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRSB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 34,
+ OPC_CheckPredicate, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRSH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 35,
+ OPC_CheckPredicate, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDR), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 76,
+ OPC_CheckPredicate, 27,
+ OPC_Scope, 35,
+ OPC_CheckPredicate, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/5, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 76,
+ OPC_CheckPredicate, 30,
+ OPC_Scope, 35,
+ OPC_CheckPredicate, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/5, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRSH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/5, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRSB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 37,
+ OPC_CheckPredicate, 27,
+ OPC_CheckPredicate, 33,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 112,
+ OPC_CheckPredicate, 34,
+ OPC_Scope, 35,
+ OPC_CheckPredicate, 35,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 36,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 37,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/5, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 35,
+ OPC_CheckPredicate, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/6, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDR), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 112,
+ OPC_CheckPredicate, 27,
+ OPC_Scope, 35,
+ OPC_CheckPredicate, 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/8, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 33,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 112,
+ OPC_CheckPredicate, 34,
+ OPC_Scope, 35,
+ OPC_CheckPredicate, 35,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 36,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 37,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/8, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 35,
+ OPC_CheckPredicate, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 76,
+ OPC_CheckPredicate, 27,
+ OPC_Scope, 35,
+ OPC_CheckPredicate, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 76,
+ OPC_CheckPredicate, 30,
+ OPC_Scope, 35,
+ OPC_CheckPredicate, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSHs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSBs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 37,
+ OPC_CheckPredicate, 27,
+ OPC_CheckPredicate, 33,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 112,
+ OPC_CheckPredicate, 34,
+ OPC_Scope, 35,
+ OPC_CheckPredicate, 35,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 36,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 37,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 32|128,2,
+ OPC_CheckPredicate, 30,
+ OPC_Scope, 54,
+ OPC_CheckPredicate, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tSXTB), 0|OPFL_MemRefs,
+ 1, MVT::i32, 3, 7, 8, 9,
+ OPC_CompleteMatch, 1, 10,
+
+ 54,
+ OPC_CheckPredicate, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/8, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tLDRH), 0|OPFL_Chain,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tSXTH), 0|OPFL_MemRefs,
+ 1, MVT::i32, 3, 7, 8, 9,
+ OPC_CompleteMatch, 1, 10,
+
+ 86,
+ OPC_CheckPredicate, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain,
+ 1, MVT::i32, 5, 2, 3, 4, 7, 8,
+ OPC_EmitInteger, MVT::i32, 24,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tLSLri), 0,
+ 1, MVT::i32, 5, 6, 9, 10, 11, 12,
+ OPC_EmitInteger, MVT::i32, 24,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tASRri), 0|OPFL_MemRefs,
+ 1, MVT::i32, 5, 5, 13, 14, 15, 16,
+ OPC_CompleteMatch, 1, 17,
+
+ 86,
+ OPC_CheckPredicate, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tLDRH), 0|OPFL_Chain,
+ 1, MVT::i32, 5, 2, 3, 4, 7, 8,
+ OPC_EmitInteger, MVT::i32, 16,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tLSLri), 0,
+ 1, MVT::i32, 5, 6, 9, 10, 11, 12,
+ OPC_EmitInteger, MVT::i32, 16,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tASRri), 0|OPFL_MemRefs,
+ 1, MVT::i32, 5, 5, 13, 14, 15, 16,
+ OPC_CompleteMatch, 1, 17,
+
+ 0,
+ 74,
+ OPC_CheckPredicate, 34,
+ OPC_Scope, 34,
+ OPC_CheckPredicate, 36,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 34,
+ OPC_CheckPredicate, 37,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 90,
+ OPC_CheckPredicate, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 25,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/10, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRspi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 52,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 0,
+ 0|128,1,
+ OPC_CheckPredicate, 27,
+ OPC_Scope, 61,
+ OPC_CheckPredicate, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 61,
+ OPC_CheckPredicate, 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 0,
+ 0|128,1,
+ OPC_CheckPredicate, 30,
+ OPC_Scope, 61,
+ OPC_CheckPredicate, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSHi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSHi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 61,
+ OPC_CheckPredicate, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSBi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 0,
+ 63,
+ OPC_CheckPredicate, 27,
+ OPC_CheckPredicate, 33,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 62|128,1,
+ OPC_CheckPredicate, 34,
+ OPC_Scope, 61,
+ OPC_CheckPredicate, 35,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 61,
+ OPC_CheckPredicate, 36,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 61,
+ OPC_CheckPredicate, 37,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 0,
+ 25|128,1,
+ OPC_CheckPredicate, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_Scope, 86,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_SwitchType , 25, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/13, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLDRD), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 4, 2, 3, 4, 5,
+ 25, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/13, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLDRS), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 4, 2, 3, 4, 5,
+ 25, MVT::v2f64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/14, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLDRQ), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 4, 2, 3, 4, 5,
+ 0,
+ 59,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 21,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 21,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 0,
+ 82,
+ OPC_CheckPredicate, 27,
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 38,
+ OPC_CheckPredicate, 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 82,
+ OPC_CheckPredicate, 30,
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSHpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 38,
+ OPC_CheckPredicate, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSBpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 40,
+ OPC_CheckPredicate, 27,
+ OPC_CheckPredicate, 33,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 121,
+ OPC_CheckPredicate, 34,
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 35,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 38,
+ OPC_CheckPredicate, 36,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 38,
+ OPC_CheckPredicate, 37,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 0,
+ 44|128,10, ISD::STORE,
+ OPC_Scope, 81|128,3,
+ OPC_CheckPredicate, 38,
+ OPC_Scope, 35,
+ OPC_CheckPredicate, 39,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICSTR), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 76,
+ OPC_CheckPredicate, 40,
+ OPC_Scope, 35,
+ OPC_CheckPredicate, 41,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICSTRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 35,
+ OPC_CheckPredicate, 42,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICSTRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 0,
+ 36,
+ OPC_CheckPredicate, 39,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STR), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 78,
+ OPC_CheckPredicate, 40,
+ OPC_Scope, 36,
+ OPC_CheckPredicate, 41,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/5, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 36,
+ OPC_CheckPredicate, 42,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 0,
+ 36,
+ OPC_CheckPredicate, 39,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/6, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSTR), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 78,
+ OPC_CheckPredicate, 40,
+ OPC_Scope, 36,
+ OPC_CheckPredicate, 42,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSTRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 36,
+ OPC_CheckPredicate, 41,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/8, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSTRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 0,
+ 36,
+ OPC_CheckPredicate, 39,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRs), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 78,
+ OPC_CheckPredicate, 40,
+ OPC_Scope, 36,
+ OPC_CheckPredicate, 42,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRBs), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 36,
+ OPC_CheckPredicate, 41,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRHs), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 86,
+ OPC_CheckPredicate, 43,
+ OPC_Scope, 40,
+ OPC_CheckPredicate, 44,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/15, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STR_PRE), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 45,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/15, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STR_POST), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
+ 0,
+ 48|128,1,
+ OPC_CheckPredicate, 46,
+ OPC_Scope, 42,
+ OPC_CheckPredicate, 47,
+ OPC_CheckPredicate, 48,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/16, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRH_PRE), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
+ 42,
+ OPC_CheckPredicate, 49,
+ OPC_CheckPredicate, 50,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/16, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRH_POST), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
+ 42,
+ OPC_CheckPredicate, 47,
+ OPC_CheckPredicate, 51,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/15, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRB_PRE), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
+ 42,
+ OPC_CheckPredicate, 49,
+ OPC_CheckPredicate, 52,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/15, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRB_POST), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
+ 0,
+ 73|128,2,
+ OPC_CheckPredicate, 38,
+ OPC_Scope, 91,
+ OPC_CheckPredicate, 39,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_Scope, 25,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/10, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSTRspi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 52,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 0,
+ 0,
+ 2|128,1,
+ OPC_CheckPredicate, 40,
+ OPC_Scope, 62,
+ OPC_CheckPredicate, 42,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRBi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 0,
+ 62,
+ OPC_CheckPredicate, 41,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRHi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRHi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 0,
+ 0,
+ 100,
+ OPC_CheckPredicate, 39,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 30,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/13, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSTRD), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 30,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/13, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSTRS), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 30,
+ OPC_CheckChild1Type, MVT::v2f64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/14, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSTRQ), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 0,
+ 0,
+ 84,
+ OPC_CheckPredicate, 43,
+ OPC_Scope, 39,
+ OPC_CheckPredicate, 44,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/17, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STR_PRE), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ 39,
+ OPC_CheckPredicate, 45,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/17, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STR_POST), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ 0,
+ 44|128,1,
+ OPC_CheckPredicate, 46,
+ OPC_Scope, 41,
+ OPC_CheckPredicate, 47,
+ OPC_CheckPredicate, 48,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/17, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRH_PRE), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ 41,
+ OPC_CheckPredicate, 49,
+ OPC_CheckPredicate, 50,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/17, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRH_POST), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ 41,
+ OPC_CheckPredicate, 47,
+ OPC_CheckPredicate, 51,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/17, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRB_PRE), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ 41,
+ OPC_CheckPredicate, 49,
+ OPC_CheckPredicate, 52,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/17, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRB_POST), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ 0,
+ 0,
+ 71|128,10, ARMISD::CMPZ,
+ OPC_Scope, 74,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 33, ISD::AND,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::TSTrs), 0|OPFL_FlagOutput,
+ 0, 6, 0, 2, 3, 4, 5, 6,
+ 33, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::TEQrs), 0|OPFL_FlagOutput,
+ 0, 6, 0, 2, 3, 4, 5, 6,
+ 0,
+ 37,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMNzrs), 0|OPFL_FlagOutput,
+ 0, 6, 0, 2, 3, 4, 5, 6,
+ 109,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 33, ISD::AND,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::TSTrs), 0|OPFL_FlagOutput,
+ 0, 6, 1, 2, 3, 4, 5, 6,
+ 33, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::TEQrs), 0|OPFL_FlagOutput,
+ 0, 6, 1, 2, 3, 4, 5, 6,
+ 33, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMNzrs), 0|OPFL_FlagOutput,
+ 0, 6, 1, 2, 3, 4, 5, 6,
+ 0,
+ 36,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMNzrs), 0|OPFL_FlagOutput,
+ 0, 5, 0, 2, 3, 4, 5,
+ 104|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 95, ISD::AND,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 54,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 20,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2TSTrs), 0|OPFL_FlagOutput,
+ 0, 5, 0, 2, 3, 4, 5,
+ 20,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2TSTrs), 0|OPFL_FlagOutput,
+ 0, 5, 1, 2, 3, 4, 5,
+ 0,
+ 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::TSTri), 0|OPFL_FlagOutput,
+ 0, 4, 0, 2, 3, 4,
+ 0,
+ 95, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 54,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 20,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2TEQrs), 0|OPFL_FlagOutput,
+ 0, 5, 0, 2, 3, 4, 5,
+ 20,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2TEQrs), 0|OPFL_FlagOutput,
+ 0, 5, 1, 2, 3, 4, 5,
+ 0,
+ 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::TEQri), 0|OPFL_FlagOutput,
+ 0, 4, 0, 2, 3, 4,
+ 0,
+ 32, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMNzrs), 0|OPFL_FlagOutput,
+ 0, 5, 1, 2, 3, 4, 5,
+ 0,
+ 97,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_Scope, 24,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMPzrs), 0|OPFL_FlagOutput,
+ 0, 6, 0, 2, 3, 4, 5, 6,
+ 66,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMNzri), 0|OPFL_FlagOutput,
+ 0, 4, 0, 2, 3, 4,
+ 24,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMNzri), 0|OPFL_FlagOutput,
+ 0, 4, 0, 2, 3, 4,
+ 0,
+ 0,
+ 82,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 37, ISD::AND,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2TSTri), 0|OPFL_FlagOutput,
+ 0, 4, 0, 2, 3, 4,
+ 37, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2TEQri), 0|OPFL_FlagOutput,
+ 0, 4, 0, 2, 3, 4,
+ 0,
+ 27,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMPzrs), 0|OPFL_FlagOutput,
+ 0, 6, 1, 2, 3, 4, 5, 6,
+ 72,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMNzri), 0|OPFL_FlagOutput,
+ 0, 4, 1, 2, 3, 4,
+ 27,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMNzri), 0|OPFL_FlagOutput,
+ 0, 4, 1, 2, 3, 4,
+ 0,
+ 50,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 20,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMPzrs), 0|OPFL_FlagOutput,
+ 0, 5, 0, 2, 3, 4, 5,
+ 20,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMPzrs), 0|OPFL_FlagOutput,
+ 0, 5, 1, 2, 3, 4, 5,
+ 0,
+ 64,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 28, ISD::AND,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::TSTrr), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 28, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::TEQrr), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 0,
+ 54,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMNzrr), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 18,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tCMNz), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 0,
+ 32,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tTST), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 32,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMNzrr), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 7|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 28, ISD::AND,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2TSTrr), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 28, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2TEQrr), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 69, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMNzrr), 0|OPFL_FlagOutput,
+ 0, 4, 1, 0, 2, 3,
+ 18,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tCMNz), 0|OPFL_FlagOutput,
+ 0, 4, 1, 0, 2, 3,
+ 18,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMNzrr), 0|OPFL_FlagOutput,
+ 0, 4, 1, 0, 2, 3,
+ 0,
+ 0,
+ 69|128,1,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_RecordChild1,
+ OPC_Scope, 4|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMPzri), 0|OPFL_FlagOutput,
+ 0, 4, 0, 2, 3, 4,
+ 26,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 11, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMNzri), 0|OPFL_FlagOutput,
+ 0, 4, 0, 3, 4, 5,
+ 23,
+ OPC_CheckPredicate, 53,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tCMPzi8), 0|OPFL_FlagOutput,
+ 0, 4, 0, 2, 3, 4,
+ 23,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMPzri), 0|OPFL_FlagOutput,
+ 0, 4, 0, 2, 3, 4,
+ 26,
+ OPC_CheckPredicate, 18,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 12, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMNzri), 0|OPFL_FlagOutput,
+ 0, 4, 0, 3, 4, 5,
+ 0,
+ 18,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMPzrr), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 18,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tCMPzr), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 18,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMPzrr), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 45|128,2, ISD::INTRINSIC_W_CHAIN,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_SwitchType , 27, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLD1d8), 0|OPFL_Chain,
+ 1, MVT::v8i8, 6, 2, 3, 4, 5, 6, 7,
+ 27, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLD1d16), 0|OPFL_Chain,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 27, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLD1d32), 0|OPFL_Chain,
+ 1, MVT::v2i32, 6, 2, 3, 4, 5, 6, 7,
+ 27, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLD1df), 0|OPFL_Chain,
+ 1, MVT::v2f32, 6, 2, 3, 4, 5, 6, 7,
+ 27, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLD1d64), 0|OPFL_Chain,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 27, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLD1q8), 0|OPFL_Chain,
+ 1, MVT::v16i8, 6, 2, 3, 4, 5, 6, 7,
+ 27, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLD1q16), 0|OPFL_Chain,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 27, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLD1q32), 0|OPFL_Chain,
+ 1, MVT::v4i32, 6, 2, 3, 4, 5, 6, 7,
+ 27, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLD1qf), 0|OPFL_Chain,
+ 1, MVT::v4f32, 6, 2, 3, 4, 5, 6, 7,
+ 27, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLD1q64), 0|OPFL_Chain,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 56|128,2, ISD::INTRINSIC_VOID,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 105,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_RecordChild3,
+ OPC_Scope, 29,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VST1d8), 0|OPFL_Chain,
+ 0, 7, 3, 4, 5, 6, 2, 7, 8,
+ 29,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VST1d16), 0|OPFL_Chain,
+ 0, 7, 3, 4, 5, 6, 2, 7, 8,
+ 29,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VST1d32), 0|OPFL_Chain,
+ 0, 7, 3, 4, 5, 6, 2, 7, 8,
+ 29,
+ OPC_CheckChild3Type, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VST1df), 0|OPFL_Chain,
+ 0, 7, 3, 4, 5, 6, 2, 7, 8,
+ 29,
+ OPC_CheckChild3Type, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VST1d64), 0|OPFL_Chain,
+ 0, 7, 3, 4, 5, 6, 2, 7, 8,
+ 29,
+ OPC_CheckChild3Type, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VST1q8), 0|OPFL_Chain,
+ 0, 7, 3, 4, 5, 6, 2, 7, 8,
+ 29,
+ OPC_CheckChild3Type, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VST1q16), 0|OPFL_Chain,
+ 0, 7, 3, 4, 5, 6, 2, 7, 8,
+ 29,
+ OPC_CheckChild3Type, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VST1q32), 0|OPFL_Chain,
+ 0, 7, 3, 4, 5, 6, 2, 7, 8,
+ 29,
+ OPC_CheckChild3Type, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VST1qf), 0|OPFL_Chain,
+ 0, 7, 3, 4, 5, 6, 2, 7, 8,
+ 29,
+ OPC_CheckChild3Type, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/18, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VST1q64), 0|OPFL_Chain,
+ 0, 7, 3, 4, 5, 6, 2, 7, 8,
+ 0,
+ 5|128,7, ISD::XOR,
+ OPC_Scope, 55|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 69,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 27,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MVNs), 0,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MVNs), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 61,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_Scope, 26,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::EORrs), 0,
+ 1, MVT::i32, 7, 0, 2, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::EORrs), 0,
+ 1, MVT::i32, 7, 1, 2, 3, 4, 5, 6, 7,
+ 0,
+ 47,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MVNi), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 48,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MVNi), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 56|128,2,
+ OPC_RecordChild0,
+ OPC_Scope, 59,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 25,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2EORrs), 0,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2EORrs), 0,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 0,
+ 83,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MVNr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MVNr), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 22,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tMVN), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 0,
+ 69,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 30,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::EORri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 30,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2EORri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 0,
+ 94,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 45, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 54,
+ OPC_MoveParent,
+ OPC_SwitchType , 18, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMVNd), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 18, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMVNq), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 41, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_SwitchType , 16, MVT::v2i32,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMVNd), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 16, MVT::v4i32,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMVNq), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 0,
+ 0,
+ 96,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 46, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 54,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 18, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMVNd), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 18, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMVNq), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 42, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 16, MVT::v2i32,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMVNd), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 16, MVT::v4i32,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMVNq), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 0,
+ 124|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 126,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 59,
+ OPC_CheckPredicate, 7,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 2, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::EORri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 3, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::EORri), 0,
+ 1, MVT::i32, 5, 7, 9, 10, 11, 12,
+ 59,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 4, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::t2EORri), 0,
+ 1, MVT::i32, 5, 0, 3, 4, 5, 6,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 5, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2EORri), 0,
+ 1, MVT::i32, 5, 7, 9, 10, 11, 12,
+ 0,
+ 76,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::EORrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tEOR), 0,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2EORrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 21,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VEORd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 21,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VEORq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 39|128,4, ISD::ADDE,
+ OPC_Scope, 35,
+ OPC_CheckPredicate, 55,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 7, 0, 2, 3, 4, 5, 6, 7,
+ 23,
+ OPC_CheckPredicate, 56,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCSSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 35,
+ OPC_CheckPredicate, 55,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 7, 1, 2, 3, 4, 5, 6, 7,
+ 23,
+ OPC_CheckPredicate, 56,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCSSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 34,
+ OPC_CheckPredicate, 55,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 34,
+ OPC_CheckPredicate, 56,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 34,
+ OPC_CheckPredicate, 55,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 34,
+ OPC_CheckPredicate, 56,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 39,
+ OPC_CheckPredicate, 55,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 27,
+ OPC_CheckPredicate, 56,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCSSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 39,
+ OPC_CheckPredicate, 55,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 39,
+ OPC_CheckPredicate, 56,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 30,
+ OPC_CheckPredicate, 55,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 56,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCSSrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 1,
+ 30,
+ OPC_CheckPredicate, 55,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckPredicate, 56,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCSrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 28,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tADC), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 0,
+ 8|128,4, ISD::SUBE,
+ OPC_Scope, 35,
+ OPC_CheckPredicate, 57,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 7, 0, 2, 3, 4, 5, 6, 7,
+ 23,
+ OPC_CheckPredicate, 58,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCSSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 81,
+ OPC_CheckPredicate, 57,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 43,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_Scope, 23,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 7, 1, 2, 3, 4, 5, 6, 7,
+ 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSCSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 27,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 0,
+ 34,
+ OPC_CheckPredicate, 58,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 39,
+ OPC_CheckPredicate, 57,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 27,
+ OPC_CheckPredicate, 58,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCSSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 91,
+ OPC_CheckPredicate, 57,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_Scope, 48,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 0,
+ OPC_Scope, 21,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 1, 2, 3, 4, 5,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSCSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 1, 2,
+ 0,
+ 35,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 0,
+ 39,
+ OPC_CheckPredicate, 58,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 30,
+ OPC_CheckPredicate, 57,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 18,
+ OPC_CheckPredicate, 58,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCSSrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 1,
+ 30,
+ OPC_CheckPredicate, 57,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckPredicate, 58,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCSrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 28,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSBC), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 0,
+ 118, ARMISD::PIC_ADD,
+ OPC_Scope, 67,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 25,
+ OPC_CheckPredicate, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 16,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRpci_pic), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 3,
+ 16,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRpci_pic), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 3,
+ 0,
+ 47,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 21,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICADD), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 13,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tPICADD), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 50|128,12, ISD::SUB,
+ OPC_Scope, 113|128,4,
+ OPC_RecordChild0,
+ OPC_Scope, 117,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 58,
+ OPC_CheckPatternPredicate, 5,
+ OPC_Scope, 26,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SUBrs), 0,
+ 1, MVT::i32, 7, 0, 2, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSBrs), 0,
+ 1, MVT::i32, 7, 1, 2, 3, 4, 5, 6, 7,
+ 0,
+ 52,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 25,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SUBrs), 0,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 21,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2RSBrs), 0,
+ 1, MVT::i32, 5, 1, 2, 3, 4, 5,
+ 0,
+ 0,
+ 118|128,3,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::MUL,
+ OPC_Scope, 6|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 62,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 23, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslv4i16), 0,
+ 1, MVT::v4i16, 6, 0, 1, 2, 4, 5, 6,
+ 23, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslv8i16), 0,
+ 1, MVT::v8i16, 6, 0, 1, 2, 4, 5, 6,
+ 0,
+ 62,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 23, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslv2i32), 0,
+ 1, MVT::v2i32, 6, 0, 1, 2, 4, 5, 6,
+ 23, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslv4i32), 0,
+ 1, MVT::v4i32, 6, 0, 1, 2, 4, 5, 6,
+ 0,
+ 0,
+ 7|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 63,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 23, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslv4i16), 0,
+ 1, MVT::v4i16, 6, 0, 3, 1, 4, 5, 6,
+ 23, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslv8i16), 0,
+ 1, MVT::v8i16, 6, 0, 3, 1, 4, 5, 6,
+ 0,
+ 63,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 23, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslv2i32), 0,
+ 1, MVT::v2i32, 6, 0, 3, 1, 4, 5, 6,
+ 23, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslv4i32), 0,
+ 1, MVT::v4i32, 6, 0, 3, 1, 4, 5, 6,
+ 0,
+ 0,
+ 110,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 50,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 6, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 2, 5,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 7, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslv8i16), 0,
+ 1, MVT::v8i16, 6, 0, 1, 6, 8, 9, 10,
+ 50,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 8, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 2, 5,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 9, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslv4i32), 0,
+ 1, MVT::v4i32, 6, 0, 1, 6, 8, 9, 10,
+ 0,
+ 111,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 51,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 6, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 1, 5,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 7, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslv8i16), 0,
+ 1, MVT::v8i16, 6, 0, 3, 6, 8, 9, 10,
+ 51,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 8, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 1, 5,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 9, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslv4i32), 0,
+ 1, MVT::v4i32, 6, 0, 3, 6, 8, 9, 10,
+ 0,
+ 0,
+ 0,
+ 30,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tRSB), 0,
+ 1, MVT::i32, 4, 1, 0, 2, 3,
+ 49|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 35,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SUBri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 35,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSBri), 0,
+ 1, MVT::i32, 5, 1, 2, 3, 4, 5,
+ 69,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 30,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SUBri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 30,
+ OPC_CheckPredicate, 17,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SUBri12), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 0,
+ 31,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2RSBri), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 120|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 126, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 59,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 18, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGs8d), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 18, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGs16d), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 18, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGs32d), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 18, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGs8q), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 18, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGs16q), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 18, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGs32q), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 114, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 60,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 16, MVT::v8i8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGs8d), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 16, MVT::v4i16,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGs16d), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 16, MVT::v2i32,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGs32d), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 16, MVT::v16i8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGs8q), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 16, MVT::v8i16,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGs16q), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 16, MVT::v4i32,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGs32q), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 0,
+ 111|128,3,
+ OPC_RecordChild0,
+ OPC_Scope, 113|128,1,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 55|128,1, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 44, MVT::i32,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MLS), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 20,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MLS), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 20, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSv8i8), 0,
+ 1, MVT::v8i8, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSv16i8), 0,
+ 1, MVT::v16i8, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 49, ISD::MULHS,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMMLS), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 20,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMMLS), 0,
+ 1, MVT::i32, 5, 1, 2, 0, 3, 4,
+ 0,
+ 0,
+ 119|128,1,
+ OPC_RecordChild1,
+ OPC_SwitchType , 74, MVT::i32,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SUBrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSUBrr), 0,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SUBrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 19, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 19, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 19, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 19, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 19, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 19, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 19, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 19, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 0,
+ 114|128,2, ISD::ADDC,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 104,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 50,
+ OPC_CheckPatternPredicate, 5,
+ OPC_Scope, 22,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADDSrs), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 22,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADDSrs), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 0,
+ 48,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 21,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADDSrs), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 21,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADDSrs), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 1, 2, 3, 4, 5,
+ 0,
+ 0,
+ 62|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 26,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADDSri), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 30,
+ OPC_CheckPredicate, 13,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tADDi3), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 30,
+ OPC_CheckPredicate, 14,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tADDi8), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 33,
+ OPC_CheckPredicate, 15,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 10, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSUBi3), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 2, 0, 4, 5, 6,
+ 33,
+ OPC_CheckPredicate, 16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 10, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSUBi8), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 2, 0, 4, 5, 6,
+ 26,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADDSri), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 0,
+ 68,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADDSrr), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tADDrr), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADDSrr), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 46|128,2, ISD::SUBC,
+ OPC_RecordChild0,
+ OPC_Scope, 7|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 100,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 50,
+ OPC_CheckPatternPredicate, 5,
+ OPC_Scope, 22,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SUBSrs), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 22,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSBSrs), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 0,
+ 44,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 21,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SUBSrs), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 17,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2RSBSrs), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 0,
+ 30,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SUBSri), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 0,
+ 31,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSBSri), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 31,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SUBSri), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 27,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2RSBSri), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 69,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SUBSrr), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSUBrr), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SUBSrr), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 61|128,1, ARMISD::CMP,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_RecordChild1,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMPrs), 0|OPFL_FlagOutput,
+ 0, 6, 0, 2, 3, 4, 5, 6,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMPrs), 0|OPFL_FlagOutput,
+ 0, 5, 0, 2, 3, 4, 5,
+ 78,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMPri), 0|OPFL_FlagOutput,
+ 0, 4, 0, 2, 3, 4,
+ 23,
+ OPC_CheckPredicate, 53,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tCMPi8), 0|OPFL_FlagOutput,
+ 0, 4, 0, 2, 3, 4,
+ 23,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMPri), 0|OPFL_FlagOutput,
+ 0, 4, 0, 2, 3, 4,
+ 0,
+ 18,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CMPrr), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 18,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tCMPr), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 18,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMPrr), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 0,
+ 15|128,114, ISD::INTRINSIC_WO_CHAIN,
+ OPC_MoveChild, 0,
+ OPC_Scope, 41|128,5,
+ OPC_CheckInteger, 68,
+ OPC_MoveParent,
+ OPC_Scope, 47|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 42,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 3, 4, 5,
+ 42,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 3, 4, 5,
+ 42,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 3, 4, 5,
+ 42,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 0,
+ 21|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 70,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 28, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv4i16), 0,
+ 1, MVT::v4i16, 5, 2, 0, 3, 4, 5,
+ 28, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv8i16), 0,
+ 1, MVT::v8i16, 5, 2, 0, 3, 4, 5,
+ 0,
+ 70,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 28, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv2i32), 0,
+ 1, MVT::v2i32, 5, 2, 0, 3, 4, 5,
+ 28, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv4i32), 0,
+ 1, MVT::v4i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 0,
+ 119,
+ OPC_RecordChild1,
+ OPC_Scope, 57,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 6, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 1, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 7, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 5, 7, 8, 9,
+ 57,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 8, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 1, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 9, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 5, 7, 8, 9,
+ 0,
+ 115,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 53,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 6, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 0, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 7, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv8i16), 0,
+ 1, MVT::v8i16, 5, 2, 5, 7, 8, 9,
+ 53,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 8, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 0, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 9, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv4i32), 0,
+ 1, MVT::v4i32, 5, 2, 5, 7, 8, 9,
+ 0,
+ 111,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 41|128,5,
+ OPC_CheckInteger, 74,
+ OPC_MoveParent,
+ OPC_Scope, 47|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 42,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 3, 4, 5,
+ 42,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 3, 4, 5,
+ 42,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 3, 4, 5,
+ 42,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 0,
+ 21|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 70,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 28, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv4i16), 0,
+ 1, MVT::v4i16, 5, 2, 0, 3, 4, 5,
+ 28, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv8i16), 0,
+ 1, MVT::v8i16, 5, 2, 0, 3, 4, 5,
+ 0,
+ 70,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 28, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv2i32), 0,
+ 1, MVT::v2i32, 5, 2, 0, 3, 4, 5,
+ 28, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv4i32), 0,
+ 1, MVT::v4i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 0,
+ 119,
+ OPC_RecordChild1,
+ OPC_Scope, 57,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 6, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 1, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 7, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 5, 7, 8, 9,
+ 57,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 8, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 1, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 9, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 5, 7, 8, 9,
+ 0,
+ 115,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 53,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 6, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 0, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 7, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv8i16), 0,
+ 1, MVT::v8i16, 5, 2, 5, 7, 8, 9,
+ 53,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 8, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 0, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 9, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv4i32), 0,
+ 1, MVT::v4i32, 5, 2, 5, 7, 8, 9,
+ 0,
+ 111,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 10|128,2,
+ OPC_CheckInteger, 51,
+ OPC_MoveParent,
+ OPC_Scope, 89,
+ OPC_RecordChild1,
+ OPC_Scope, 42,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLslsv4i16), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 42,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLslsv2i32), 0,
+ 1, MVT::v2i64, 5, 0, 1, 3, 4, 5,
+ 0,
+ 85,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 38,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLslsv4i16), 0,
+ 1, MVT::v4i32, 5, 2, 0, 3, 4, 5,
+ 38,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLslsv2i32), 0,
+ 1, MVT::v2i64, 5, 2, 0, 3, 4, 5,
+ 0,
+ 84,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 10|128,2,
+ OPC_CheckInteger, 52,
+ OPC_MoveParent,
+ OPC_Scope, 89,
+ OPC_RecordChild1,
+ OPC_Scope, 42,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLsluv4i16), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 42,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLsluv2i32), 0,
+ 1, MVT::v2i64, 5, 0, 1, 3, 4, 5,
+ 0,
+ 85,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 38,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLsluv4i16), 0,
+ 1, MVT::v4i32, 5, 2, 0, 3, 4, 5,
+ 38,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLsluv2i32), 0,
+ 1, MVT::v2i64, 5, 2, 0, 3, 4, 5,
+ 0,
+ 84,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 111|128,1,
+ OPC_CheckInteger, 69,
+ OPC_MoveParent,
+ OPC_Scope, 89,
+ OPC_RecordChild1,
+ OPC_Scope, 42,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULLslv4i16), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 42,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULLslv2i32), 0,
+ 1, MVT::v2i64, 5, 0, 1, 3, 4, 5,
+ 0,
+ 85,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 38,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULLslv4i16), 0,
+ 1, MVT::v4i32, 5, 2, 0, 3, 4, 5,
+ 38,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULLslv2i32), 0,
+ 1, MVT::v2i64, 5, 2, 0, 3, 4, 5,
+ 0,
+ 57,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULLv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULLv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 116|128,2,
+ OPC_CheckInteger, 43,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 75,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALslsv4i16), 0,
+ 1, MVT::v4i32, 6, 0, 1, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALsv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALslsv2i32), 0,
+ 1, MVT::v2i64, 6, 0, 1, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALsv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALslsv4i16), 0,
+ 1, MVT::v4i32, 6, 1, 0, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALsv4i32), 0,
+ 1, MVT::v4i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALslsv2i32), 0,
+ 1, MVT::v2i64, 6, 1, 0, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALsv2i64), 0,
+ 1, MVT::v2i64, 5, 1, 0, 2, 3, 4,
+ 0,
+ 30,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALsv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALsv8i16), 0,
+ 1, MVT::v8i16, 5, 1, 0, 2, 3, 4,
+ 0,
+ 116|128,2,
+ OPC_CheckInteger, 44,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 75,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALsluv4i16), 0,
+ 1, MVT::v4i32, 6, 0, 1, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALuv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALsluv2i32), 0,
+ 1, MVT::v2i64, 6, 0, 1, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALuv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALsluv4i16), 0,
+ 1, MVT::v4i32, 6, 1, 0, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALuv4i32), 0,
+ 1, MVT::v4i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALsluv2i32), 0,
+ 1, MVT::v2i64, 6, 1, 0, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALuv2i64), 0,
+ 1, MVT::v2i64, 5, 1, 0, 2, 3, 4,
+ 0,
+ 30,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALuv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLALuv8i16), 0,
+ 1, MVT::v8i16, 5, 1, 0, 2, 3, 4,
+ 0,
+ 54|128,2,
+ OPC_CheckInteger, 66,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 75,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLALslv4i16), 0,
+ 1, MVT::v4i32, 6, 0, 1, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLALv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLALslv2i32), 0,
+ 1, MVT::v2i64, 6, 0, 1, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLALv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLALslv4i16), 0,
+ 1, MVT::v4i32, 6, 1, 0, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLALv4i32), 0,
+ 1, MVT::v4i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLALslv2i32), 0,
+ 1, MVT::v2i64, 6, 1, 0, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLALv2i64), 0,
+ 1, MVT::v2i64, 5, 1, 0, 2, 3, 4,
+ 0,
+ 0,
+ 116|128,2,
+ OPC_CheckInteger, 45,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 75,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLslsv4i16), 0,
+ 1, MVT::v4i32, 6, 0, 1, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLsv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLslsv2i32), 0,
+ 1, MVT::v2i64, 6, 0, 1, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLsv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLslsv4i16), 0,
+ 1, MVT::v4i32, 6, 1, 0, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLsv4i32), 0,
+ 1, MVT::v4i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLslsv2i32), 0,
+ 1, MVT::v2i64, 6, 1, 0, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLsv2i64), 0,
+ 1, MVT::v2i64, 5, 1, 0, 2, 3, 4,
+ 0,
+ 30,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLsv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLsv8i16), 0,
+ 1, MVT::v8i16, 5, 1, 0, 2, 3, 4,
+ 0,
+ 116|128,2,
+ OPC_CheckInteger, 46,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 75,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLsluv4i16), 0,
+ 1, MVT::v4i32, 6, 0, 1, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLuv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLsluv2i32), 0,
+ 1, MVT::v2i64, 6, 0, 1, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLuv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLsluv4i16), 0,
+ 1, MVT::v4i32, 6, 1, 0, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLuv4i32), 0,
+ 1, MVT::v4i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLsluv2i32), 0,
+ 1, MVT::v2i64, 6, 1, 0, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLuv2i64), 0,
+ 1, MVT::v2i64, 5, 1, 0, 2, 3, 4,
+ 0,
+ 30,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLuv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSLuv8i16), 0,
+ 1, MVT::v8i16, 5, 1, 0, 2, 3, 4,
+ 0,
+ 54|128,2,
+ OPC_CheckInteger, 67,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 75,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLSLslv4i16), 0,
+ 1, MVT::v4i32, 6, 0, 1, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLSLv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLSLslv2i32), 0,
+ 1, MVT::v2i64, 6, 0, 1, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLSLv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLSLslv4i16), 0,
+ 1, MVT::v4i32, 6, 1, 0, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLSLv4i32), 0,
+ 1, MVT::v4i32, 5, 1, 0, 2, 3, 4,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_Scope, 41,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLSLslv2i32), 0,
+ 1, MVT::v2i64, 6, 1, 0, 2, 4, 5, 6,
+ 25,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMLSLv2i64), 0,
+ 1, MVT::v2i64, 5, 1, 0, 2, 3, 4,
+ 0,
+ 0,
+ 70,
+ OPC_CheckInteger, 24,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 31,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTf2xsd), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTf2xsq), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 0,
+ 70,
+ OPC_CheckInteger, 25,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 31,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTf2xud), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTf2xuq), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 0,
+ 70,
+ OPC_CheckInteger, 26,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 31,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTxs2fd), 0,
+ 1, MVT::v2f32, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTxs2fq), 0,
+ 1, MVT::v4f32, 4, 0, 2, 3, 4,
+ 0,
+ 70,
+ OPC_CheckInteger, 27,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 31,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTxu2fd), 0,
+ 1, MVT::v2f32, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTxu2fq), 0,
+ 1, MVT::v4f32, 4, 0, 2, 3, 4,
+ 0,
+ 87,
+ OPC_CheckInteger, 17,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDLsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDLsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDLsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 0,
+ 87,
+ OPC_CheckInteger, 18,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDLuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDLuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDLuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 19,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv8i16), 0,
+ 1, MVT::v8i16, 4, 1, 0, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv4i32), 0,
+ 1, MVT::v4i32, 4, 1, 0, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv2i64), 0,
+ 1, MVT::v2i64, 4, 1, 0, 2, 3,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 20,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv8i16), 0,
+ 1, MVT::v8i16, 4, 1, 0, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv4i32), 0,
+ 1, MVT::v4i32, 4, 1, 0, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv2i64), 0,
+ 1, MVT::v2i64, 4, 1, 0, 2, 3,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 28,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 29,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 91,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 92,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v1i64,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 65,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v1i64,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 87,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDHNv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDHNv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDHNv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 0,
+ 87,
+ OPC_CheckInteger, 88,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRADDHNv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRADDHNv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRADDHNv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 0,
+ 60,
+ OPC_CheckInteger, 53,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULpd), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULpq), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 0,
+ 30,
+ OPC_CheckInteger, 50,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLp), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 87,
+ OPC_CheckInteger, 113,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBLsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBLsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBLsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 0,
+ 87,
+ OPC_CheckInteger, 114,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBLuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBLuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBLuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 0,
+ 87,
+ OPC_CheckInteger, 115,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBWsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBWsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBWsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 87,
+ OPC_CheckInteger, 116,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBWuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBWuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBWuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 30,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 31,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 86,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v1i64,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 87,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v1i64,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 87,
+ OPC_CheckInteger, 112,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBHNv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBHNv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBHNv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 0,
+ 87,
+ OPC_CheckInteger, 98,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSUBHNv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSUBHNv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSUBHNv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 0,
+ 24,
+ OPC_CheckInteger, 12,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VACGEd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckInteger, 13,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VACGEq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckInteger, 14,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VACGTd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckInteger, 15,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VACGTq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 94|128,1,
+ OPC_CheckInteger, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDfd), 0,
+ 1, MVT::v2f32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDfq), 0,
+ 1, MVT::v4f32, 4, 0, 1, 2, 3,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 10,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 0,
+ 87,
+ OPC_CheckInteger, 7,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDLsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDLsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDLsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 0,
+ 87,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDLuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDLuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDLuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 0,
+ 64|128,1,
+ OPC_CheckInteger, 5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 30,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAsv8i8), 0,
+ 1, MVT::v8i8, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAsv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAsv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAsv16i8), 0,
+ 1, MVT::v16i8, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAsv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAsv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 64|128,1,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 30,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAuv8i8), 0,
+ 1, MVT::v8i8, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAuv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAuv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAuv16i8), 0,
+ 1, MVT::v16i8, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAuv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAuv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 99,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 30,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABALsv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABALsv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABALsv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
+ 0,
+ 99,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 30,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABALuv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABALuv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 2, 3, 4,
+ 30,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_RecordChild3,
+ OPC_CheckChild3Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABALuv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 39,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXfd), 0,
+ 1, MVT::v2f32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXfq), 0,
+ 1, MVT::v4f32, 4, 0, 1, 2, 3,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 40,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 41,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINfd), 0,
+ 1, MVT::v2f32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINfq), 0,
+ 1, MVT::v4f32, 4, 0, 1, 2, 3,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 42,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 0,
+ 114,
+ OPC_CheckInteger, 56,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDi8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDi16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDi32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDf), 0,
+ 1, MVT::v2f32, 4, 0, 1, 2, 3,
+ 0,
+ 16|128,1,
+ OPC_CheckInteger, 57,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLsv8i8), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLsv4i16), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLsv2i32), 0,
+ 1, MVT::v1i64, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLsv16i8), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLsv8i16), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLsv4i32), 0,
+ 1, MVT::v2i64, 3, 0, 1, 2,
+ 0,
+ 16|128,1,
+ OPC_CheckInteger, 58,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLuv8i8), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLuv4i16), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLuv2i32), 0,
+ 1, MVT::v1i64, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLuv16i8), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLuv8i16), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLuv4i32), 0,
+ 1, MVT::v2i64, 3, 0, 1, 2,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 54,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALsv8i8), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALsv4i16), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALsv2i32), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALsv16i8), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALsv8i16), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALsv4i32), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 40|128,1,
+ OPC_CheckInteger, 55,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALuv8i8), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALuv4i16), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALuv2i32), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALuv16i8), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALuv8i16), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALuv4i32), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 114,
+ OPC_CheckInteger, 59,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXs8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXs16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXs32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXf), 0,
+ 1, MVT::v2f32, 4, 0, 1, 2, 3,
+ 0,
+ 87,
+ OPC_CheckInteger, 60,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXu8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXu16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXu32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 0,
+ 114,
+ OPC_CheckInteger, 61,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINs8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINs16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINs32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINf), 0,
+ 1, MVT::v2f32, 4, 0, 1, 2, 3,
+ 0,
+ 87,
+ OPC_CheckInteger, 62,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINu8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINu16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINu32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 0,
+ 98,
+ OPC_CheckInteger, 89,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRECPEd), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRECPEq), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRECPEfd), 0,
+ 1, MVT::v2f32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRECPEfq), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 0,
+ 60,
+ OPC_CheckInteger, 90,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRECPSfd), 0,
+ 1, MVT::v2f32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRECPSfq), 0,
+ 1, MVT::v4f32, 4, 0, 1, 2, 3,
+ 0,
+ 98,
+ OPC_CheckInteger, 96,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSQRTEd), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSQRTEq), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSQRTEfd), 0,
+ 1, MVT::v2f32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSQRTEfq), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 0,
+ 60,
+ OPC_CheckInteger, 97,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSQRTSfd), 0,
+ 1, MVT::v2f32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSQRTSfq), 0,
+ 1, MVT::v4f32, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 103,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v1i64,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 104,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v1i64,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 94,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v1i64,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 95,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v1i64,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 83,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v1i64,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 85,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v1i64,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 78,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v1i64,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 94|128,1,
+ OPC_CheckInteger, 79,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v1i64,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 0,
+ 62|128,1,
+ OPC_CheckInteger, 11,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSv8i8), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSv4i16), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSv2i32), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSv16i8), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSv8i16), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSv4i32), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSfd), 0,
+ 1, MVT::v2f32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSfq), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 0,
+ 16|128,1,
+ OPC_CheckInteger, 63,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQABSv8i8), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQABSv4i16), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQABSv2i32), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQABSv16i8), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQABSv8i16), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQABSv4i32), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 16|128,1,
+ OPC_CheckInteger, 73,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQNEGv8i8), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQNEGv4i16), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQNEGv2i32), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQNEGv16i8), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQNEGv8i16), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQNEGv4i32), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 16|128,1,
+ OPC_CheckInteger, 21,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLSv8i8), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLSv4i16), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLSv2i32), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLSv16i8), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLSv8i16), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLSv4i32), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 16|128,1,
+ OPC_CheckInteger, 22,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLZv8i8), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLZv4i16), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLZv2i32), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLZv16i8), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLZv8i16), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLZv4i32), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 52,
+ OPC_CheckInteger, 23,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCNTd), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCNTq), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 0,
+ 75,
+ OPC_CheckInteger, 49,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVNv8i8), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVNv4i16), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVNv2i32), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 0,
+ 75,
+ OPC_CheckInteger, 70,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNsv8i8), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNsv4i16), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNsv2i32), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 0,
+ 75,
+ OPC_CheckInteger, 72,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNuv8i8), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNuv4i16), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNuv2i32), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 0,
+ 75,
+ OPC_CheckInteger, 71,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNsuv8i8), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNsuv4i16), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNsuv2i32), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 0,
+ 75,
+ OPC_CheckInteger, 47,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVLsv8i16), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVLsv4i32), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVLsv2i64), 0,
+ 1, MVT::v2i64, 3, 0, 1, 2,
+ 0,
+ 75,
+ OPC_CheckInteger, 48,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 22,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVLuv8i16), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVLuv4i32), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVLuv2i64), 0,
+ 1, MVT::v2i64, 3, 0, 1, 2,
+ 0,
+ 24,
+ OPC_CheckInteger, 117,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTBL1), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 26,
+ OPC_CheckInteger, 118,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTBL2), 0,
+ 1, MVT::v8i8, 5, 0, 1, 2, 3, 4,
+ 28,
+ OPC_CheckInteger, 119,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTBL3), 0,
+ 1, MVT::v8i8, 6, 0, 1, 2, 3, 4, 5,
+ 30,
+ OPC_CheckInteger, 120,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTBL4), 0,
+ 1, MVT::v8i8, 7, 0, 1, 2, 3, 4, 5, 6,
+ 26,
+ OPC_CheckInteger, 121,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTBX1), 0,
+ 1, MVT::v8i8, 5, 0, 1, 2, 3, 4,
+ 28,
+ OPC_CheckInteger, 122,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTBX2), 0,
+ 1, MVT::v8i8, 6, 0, 1, 2, 3, 4, 5,
+ 30,
+ OPC_CheckInteger, 123,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTBX3), 0,
+ 1, MVT::v8i8, 7, 0, 1, 2, 3, 4, 5, 6,
+ 32,
+ OPC_CheckInteger, 124,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_RecordChild6,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTBX4), 0,
+ 1, MVT::v8i8, 8, 0, 1, 2, 3, 4, 5, 6, 7,
+ 0,
+ 37|128,1, ISD::SHL,
+ OPC_Scope, 30,
+ OPC_RecordNode,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVs), 0,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 2|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 70,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 24,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LSLri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 30,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLSLri), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 54,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLSLrr), 0,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LSLrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 0,
+ 0,
+ 37|128,1, ISD::SRL,
+ OPC_Scope, 30,
+ OPC_RecordNode,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVs), 0,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 2|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 70,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 24,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LSRri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 30,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLSRri), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 54,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLSRrr), 0,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LSRrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 0,
+ 0,
+ 2|128,1, ISD::ROTR,
+ OPC_Scope, 30,
+ OPC_RecordNode,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVs), 0,
+ 1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
+ 96,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 24,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2RORri), 0,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 54,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 23,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tROR), 0,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
+ 23,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2RORrr), 0,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 0,
+ 0,
+ 69|128,8, ISD::FADD,
+ OPC_Scope, 118,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_Scope, 68,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 23, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslfd), 0,
+ 1, MVT::v2f32, 6, 0, 1, 2, 4, 5, 6,
+ 23, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslfq), 0,
+ 1, MVT::v4f32, 6, 0, 1, 2, 4, 5, 6,
+ 0,
+ 41,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslfd), 0,
+ 1, MVT::v2f32, 6, 0, 3, 1, 4, 5, 6,
+ 0,
+ 92,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_Scope, 42,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslfd), 0,
+ 1, MVT::v2f32, 6, 3, 0, 1, 4, 5, 6,
+ 42,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslfd), 0,
+ 1, MVT::v2f32, 6, 3, 2, 0, 4, 5, 6,
+ 0,
+ 46,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslfq), 0,
+ 1, MVT::v4f32, 6, 0, 3, 1, 4, 5, 6,
+ 92,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_Scope, 42,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslfq), 0,
+ 1, MVT::v4f32, 6, 3, 0, 1, 4, 5, 6,
+ 42,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslfq), 0,
+ 1, MVT::v4f32, 6, 3, 2, 0, 4, 5, 6,
+ 0,
+ 121,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_Scope, 56,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 8, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2f32, 2, 2, 5,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 9, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslfq), 0,
+ 1, MVT::v4f32, 6, 0, 1, 6, 8, 9, 10,
+ 56,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 8, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2f32, 2, 1, 5,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 9, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslfq), 0,
+ 1, MVT::v4f32, 6, 0, 3, 6, 8, 9, 10,
+ 0,
+ 53|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 118, ISD::FMUL,
+ OPC_Scope, 57,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 8, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2f32, 2, 1, 5,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 9, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslfq), 0,
+ 1, MVT::v4f32, 6, 3, 0, 6, 8, 9, 10,
+ 57,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 8, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2f32, 2, 0, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 9, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAslfq), 0,
+ 1, MVT::v4f32, 6, 3, 2, 6, 8, 9, 10,
+ 0,
+ 55, ISD::FNEG,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSD), 0,
+ 1, MVT::f64, 5, 2, 0, 1, 3, 4,
+ 20, MVT::f32,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSS), 0,
+ 1, MVT::f32, 5, 2, 0, 1, 3, 4,
+ 0,
+ 0,
+ 59,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::FNEG,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSD), 0,
+ 1, MVT::f64, 5, 0, 1, 2, 3, 4,
+ 20, MVT::f32,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSS), 0,
+ 1, MVT::f32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 54,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAD), 0,
+ 1, MVT::f64, 5, 2, 0, 1, 3, 4,
+ 20, MVT::f32,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAS), 0,
+ 1, MVT::f32, 5, 2, 0, 1, 3, 4,
+ 0,
+ 98,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAfd), 0,
+ 1, MVT::v2f32, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAfq), 0,
+ 1, MVT::v4f32, 5, 0, 1, 2, 3, 4,
+ 20, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAD), 0,
+ 1, MVT::f64, 5, 0, 1, 2, 3, 4,
+ 20, MVT::f32,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAS), 0,
+ 1, MVT::f32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 54,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAfd), 0,
+ 1, MVT::v2f32, 5, 2, 0, 1, 3, 4,
+ 20, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLAfq), 0,
+ 1, MVT::v4f32, 5, 2, 0, 1, 3, 4,
+ 0,
+ 35|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 19, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDD), 0,
+ 1, MVT::f64, 4, 0, 1, 2, 3,
+ 94, MVT::f32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDS), 0,
+ 1, MVT::f32, 4, 0, 1, 2, 3,
+ 71,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 2, 0, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 5, 1, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VADDfd_sfp), 0,
+ 1, MVT::f64, 4, 4, 7, 8, 9,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 10, 11,
+ 0,
+ 19, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDfd), 0,
+ 1, MVT::v2f32, 4, 0, 1, 2, 3,
+ 19, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDfq), 0,
+ 1, MVT::v4f32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 4|128,5, ISD::FSUB,
+ OPC_Scope, 3|128,2,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_Scope, 68,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 23, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslfd), 0,
+ 1, MVT::v2f32, 6, 0, 1, 2, 4, 5, 6,
+ 23, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslfq), 0,
+ 1, MVT::v4f32, 6, 0, 1, 2, 4, 5, 6,
+ 0,
+ 68,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 23, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslfd), 0,
+ 1, MVT::v2f32, 6, 0, 3, 1, 4, 5, 6,
+ 23, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslfq), 0,
+ 1, MVT::v4f32, 6, 0, 3, 1, 4, 5, 6,
+ 0,
+ 56,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 8, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2f32, 2, 2, 5,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 9, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslfq), 0,
+ 1, MVT::v4f32, 6, 0, 1, 6, 8, 9, 10,
+ 56,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 8, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2f32, 2, 1, 5,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 9, 7,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSslfq), 0,
+ 1, MVT::v4f32, 6, 0, 3, 6, 8, 9, 10,
+ 0,
+ 113,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 55, ISD::FNEG,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNMLAD), 0,
+ 1, MVT::f64, 5, 2, 0, 1, 3, 4,
+ 20, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNMLAS), 0,
+ 1, MVT::f32, 5, 2, 0, 1, 3, 4,
+ 0,
+ 50, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNMLSD), 0,
+ 1, MVT::f64, 5, 2, 0, 1, 3, 4,
+ 20, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNMLSS), 0,
+ 1, MVT::f32, 5, 2, 0, 1, 3, 4,
+ 0,
+ 0,
+ 9|128,2,
+ OPC_RecordChild0,
+ OPC_Scope, 97,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::f64,
+ OPC_CheckPatternPredicate, 12,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSD), 0,
+ 1, MVT::f64, 5, 0, 1, 2, 3, 4,
+ 20, MVT::f32,
+ OPC_CheckPatternPredicate, 12,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSS), 0,
+ 1, MVT::f32, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSfd), 0,
+ 1, MVT::v2f32, 5, 0, 1, 2, 3, 4,
+ 20, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMLSfq), 0,
+ 1, MVT::v4f32, 5, 0, 1, 2, 3, 4,
+ 0,
+ 34|128,1,
+ OPC_RecordChild1,
+ OPC_SwitchType , 19, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBD), 0,
+ 1, MVT::f64, 4, 0, 1, 2, 3,
+ 94, MVT::f32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBS), 0,
+ 1, MVT::f32, 4, 0, 1, 2, 3,
+ 71,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 2, 0, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 5, 1, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VSUBfd_sfp), 0,
+ 1, MVT::f64, 4, 4, 7, 8, 9,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 10, 11,
+ 0,
+ 19, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBfd), 0,
+ 1, MVT::v2f32, 4, 0, 1, 2, 3,
+ 19, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBfq), 0,
+ 1, MVT::v4f32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 0,
+ 61, ISD::CALLSEQ_END,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 26, ISD::TargetConstant,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::TargetConstant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADJCALLSTACKUP), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 4, 1, 2, 3, 4,
+ 24, ISD::Constant,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tADJCALLSTACKUP), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 2, 3, 4,
+ 0,
+ 82, ARMISD::WrapperJT,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 21,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LEApcrelJT), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 21,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLEApcrelJT), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 21,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LEApcrelJT), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 0,
+ 34, ARMISD::BR2_JT,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_RecordChild4,
+ OPC_MoveChild, 4,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2BR_JT), 0|OPFL_Chain,
+ 0, 4, 1, 2, 3, 5,
+ 3|128,4, ISD::FMUL,
+ OPC_Scope, 65,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslfd), 0,
+ 1, MVT::v2f32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslfq), 0,
+ 1, MVT::v4f32, 5, 0, 1, 3, 4, 5,
+ 0,
+ 65,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 22, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslfd), 0,
+ 1, MVT::v2f32, 5, 2, 0, 3, 4, 5,
+ 22, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslfq), 0,
+ 1, MVT::v4f32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 54,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 8, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2f32, 2, 1, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 9, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslfq), 0,
+ 1, MVT::v4f32, 5, 0, 5, 7, 8, 9,
+ 105,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 50, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 8, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2f32, 2, 0, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 9, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULslfq), 0,
+ 1, MVT::v4f32, 5, 2, 5, 7, 8, 9,
+ 47, ISD::FNEG,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 19, MVT::f64,
+ OPC_CheckPatternPredicate, 13,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNMULD), 0,
+ 1, MVT::f64, 4, 0, 1, 2, 3,
+ 19, MVT::f32,
+ OPC_CheckPatternPredicate, 13,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNMULS), 0,
+ 1, MVT::f32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 90|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 50,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::FNEG,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_SwitchType , 19, MVT::f64,
+ OPC_CheckPatternPredicate, 13,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNMULD), 0,
+ 1, MVT::f64, 4, 1, 0, 2, 3,
+ 19, MVT::f32,
+ OPC_CheckPatternPredicate, 13,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNMULS), 0,
+ 1, MVT::f32, 4, 1, 0, 2, 3,
+ 0,
+ 34|128,1,
+ OPC_RecordChild1,
+ OPC_SwitchType , 19, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULD), 0,
+ 1, MVT::f64, 4, 0, 1, 2, 3,
+ 94, MVT::f32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULS), 0,
+ 1, MVT::f32, 4, 0, 1, 2, 3,
+ 71,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 2, 0, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 5, 1, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VMULfd_sfp), 0,
+ 1, MVT::f64, 4, 4, 7, 8, 9,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 10, 11,
+ 0,
+ 19, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULfd), 0,
+ 1, MVT::v2f32, 4, 0, 1, 2, 3,
+ 19, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULfq), 0,
+ 1, MVT::v4f32, 4, 0, 1, 2, 3,
+ 0,
+ 0,
+ 0,
+ 44, ISD::CALLSEQ_START,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 19, ISD::TargetConstant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADJCALLSTACKDOWN), 0|OPFL_Chain|OPFL_FlagOutput,
+ 0, 3, 1, 2, 3,
+ 15, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tADJCALLSTACKDOWN), 0|OPFL_Chain|OPFL_FlagOutput,
+ 0, 1, 2,
+ 0,
+ 53|128,1, ARMISD::CALL,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_Scope, 118,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 55, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 15,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BLr9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 16,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBLXi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 17,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBLXi_r9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 55, ISD::TargetExternalSymbol,
+ OPC_MoveParent,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 15,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BLr9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 16,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBLXi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 17,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBLXi_r9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 0,
+ 56,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 18,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BLX), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 19,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BLXr9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 16,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBLXr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 17,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBLXr_r9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 0,
+ 52, ARMISD::CALL_PRED,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BL_pred), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 3, 1, 2, 3,
+ 20,
+ OPC_CheckPatternPredicate, 15,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BLr9_pred), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 3, 1, 2, 3,
+ 0,
+ 43|128,1, ARMISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 100, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 20,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LEApcrel), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 21,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVi32imm), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLEApcrel), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 22,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LEApcrel), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 23,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MOVi32imm), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 62, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LEApcrel), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLEApcrel), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LEApcrel), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 0,
+ 103, ARMISD::tCALL,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_Scope, 66,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 29, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 24,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 25,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBLr9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 29, ISD::TargetExternalSymbol,
+ OPC_MoveParent,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 24,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 25,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBLr9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 0,
+ 30,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 16,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBLXr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 17,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBLXr_r9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 0,
+ 65|128,1, ISD::FNEG,
+ OPC_Scope, 51,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 19, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNMULD), 0,
+ 1, MVT::f64, 4, 0, 1, 2, 3,
+ 19, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNMULS), 0,
+ 1, MVT::f32, 4, 0, 1, 2, 3,
+ 0,
+ 9|128,1,
+ OPC_RecordChild0,
+ OPC_SwitchType , 18, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGD), 0,
+ 1, MVT::f64, 3, 0, 1, 2,
+ 72, MVT::f32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGS), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 50,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 1, 0, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VNEGfd_sfp), 0,
+ 1, MVT::f64, 3, 3, 4, 5,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 6, 7,
+ 0,
+ 18, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGfd), 0,
+ 1, MVT::v2f32, 3, 0, 1, 2,
+ 18, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VNEGf32q), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 0,
+ 0,
+ 65|128,1, ARMISD::VSHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLiv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLiv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLiv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 21, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLiv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 2, 3, 4,
+ 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLiv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 2, 3, 4,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLiv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 2, 3, 4,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLiv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 21, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLiv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 2, 3, 4,
+ 0,
+ 65|128,1, ARMISD::VSHRs,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 21, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRsv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 2, 3, 4,
+ 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 2, 3, 4,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 2, 3, 4,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 21, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 2, 3, 4,
+ 0,
+ 65|128,1, ARMISD::VSHRu,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 21, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRuv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 2, 3, 4,
+ 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 2, 3, 4,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 2, 3, 4,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 21, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 2, 3, 4,
+ 0,
+ 99, ARMISD::VSHLLs,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLLsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLLsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLLsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 2, 3, 4,
+ 0,
+ 99, ARMISD::VSHLLu,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLLuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLLuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLLuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 2, 3, 4,
+ 0,
+ 99, ARMISD::VSHLLi,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLLi8), 0,
+ 1, MVT::v8i16, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLLi16), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLLi32), 0,
+ 1, MVT::v2i64, 4, 0, 2, 3, 4,
+ 0,
+ 99, ARMISD::VSHRN,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRNv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRNv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHRNv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 0,
+ 65|128,1, ARMISD::VRSHRs,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 21, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRsv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 2, 3, 4,
+ 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 2, 3, 4,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 2, 3, 4,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 21, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 2, 3, 4,
+ 0,
+ 65|128,1, ARMISD::VRSHRu,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 21, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRuv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 2, 3, 4,
+ 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 2, 3, 4,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 2, 3, 4,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 21, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 2, 3, 4,
+ 0,
+ 99, ARMISD::VRSHRN,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRNv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRNv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHRNv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 0,
+ 65|128,1, ARMISD::VQSHLs,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsiv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsiv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsiv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 21, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsiv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 2, 3, 4,
+ 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsiv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 2, 3, 4,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsiv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 2, 3, 4,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsiv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 21, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsiv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 2, 3, 4,
+ 0,
+ 65|128,1, ARMISD::VQSHLu,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuiv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuiv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuiv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 21, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuiv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 2, 3, 4,
+ 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuiv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 2, 3, 4,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuiv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 2, 3, 4,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuiv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 21, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuiv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 2, 3, 4,
+ 0,
+ 65|128,1, ARMISD::VQSHLsu,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 21, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsuv1i64), 0,
+ 1, MVT::v1i64, 4, 0, 2, 3, 4,
+ 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 2, 3, 4,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 2, 3, 4,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 21, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 2, 3, 4,
+ 0,
+ 99, ARMISD::VQSHRNs,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHRNsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHRNsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHRNsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 0,
+ 99, ARMISD::VQSHRNu,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHRNuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHRNuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHRNuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 0,
+ 99, ARMISD::VQSHRNsu,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHRUNv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHRUNv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHRUNv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 0,
+ 99, ARMISD::VQRSHRNs,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHRNsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHRNsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHRNsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 0,
+ 99, ARMISD::VQRSHRNu,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHRNuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHRNuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHRNuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 0,
+ 99, ARMISD::VQRSHRNsu,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHRUNv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHRUNv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 31,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHRUNv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 0,
+ 74|128,1, ARMISD::VSLI,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSLIv8i8), 0,
+ 1, MVT::v8i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSLIv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSLIv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSLIv1i64), 0,
+ 1, MVT::v1i64, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSLIv16i8), 0,
+ 1, MVT::v16i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSLIv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSLIv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSLIv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 3, 4, 5,
+ 0,
+ 74|128,1, ARMISD::VSRI,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRIv8i8), 0,
+ 1, MVT::v8i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRIv4i16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRIv2i32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRIv1i64), 0,
+ 1, MVT::v1i64, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRIv16i8), 0,
+ 1, MVT::v16i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRIv8i16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRIv4i32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSRIv2i64), 0,
+ 1, MVT::v2i64, 5, 0, 1, 3, 4, 5,
+ 0,
+ 25|128,1, ARMISD::VGETLANEs,
+ OPC_RecordChild0,
+ OPC_Scope, 29,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VGETLNs8), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 29,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VGETLNs16), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 44,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 18, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v8i8, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 19, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VGETLNs8), 0,
+ 1, MVT::i32, 4, 4, 6, 7, 8,
+ 44,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 6, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 7, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VGETLNs16), 0,
+ 1, MVT::i32, 4, 4, 6, 7, 8,
+ 0,
+ 25|128,1, ARMISD::VGETLANEu,
+ OPC_RecordChild0,
+ OPC_Scope, 29,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VGETLNu8), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 29,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VGETLNu16), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 44,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 18, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v8i8, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 19, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VGETLNu8), 0,
+ 1, MVT::i32, 4, 4, 6, 7, 8,
+ 44,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 6, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 7, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VGETLNu16), 0,
+ 1, MVT::i32, 4, 4, 6, 7, 8,
+ 0,
+ 53|128,1, ISD::EXTRACT_VECTOR_ELT,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VGETLNi32), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 24,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 20, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 0, 3,
+ 46,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 8, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 9, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VGETLNi32), 0,
+ 1, MVT::i32, 4, 4, 6, 7, 8,
+ 36,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::v2f32, 2, 0, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 21, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 3, 5,
+ 36,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_EmitInteger, MVT::i32, ARM::QPR_VFP2RegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::v4f32, 2, 0, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 21, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 3, 5,
+ 0,
+ 95|128,2, ISD::INSERT_VECTOR_ELT,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 58,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSETLNi8), 0,
+ 1, MVT::v8i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSETLNi16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 3, 4, 5,
+ 0,
+ 107,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSETLNi32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 3, 4, 5,
+ 15, MVT::v2f64,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 20, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v2f64, 3, 0, 1, 4,
+ 27, MVT::v2f32,
+ OPC_EmitInteger, MVT::i32, ARM::DPR_VFP2RegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::v2f32, 2, 0, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 21, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v2f32, 3, 4, 1, 6,
+ 27, MVT::v4f32,
+ OPC_EmitInteger, MVT::i32, ARM::QPR_VFP2RegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::v4f32, 2, 0, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 21, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v4f32, 3, 4, 1, 6,
+ 0,
+ 118,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 52, MVT::v16i8,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 18, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v8i8, 2, 0, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 19, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VSETLNi8), 0,
+ 1, MVT::f64, 5, 5, 1, 7, 8, 9,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 18, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v16i8, 3, 0, 10, 12,
+ 52, MVT::v8i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 6, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 0, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 7, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VSETLNi16), 0,
+ 1, MVT::f64, 5, 5, 1, 7, 8, 9,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 6, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v8i16, 3, 0, 10, 12,
+ 0,
+ 60,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 8, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 0, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 9, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VSETLNi32), 0,
+ 1, MVT::f64, 5, 5, 1, 7, 8, 9,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 8, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v4i32, 3, 0, 10, 12,
+ 0,
+ 102|128,1, ARMISD::VDUP,
+ OPC_Scope, 52,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::f32,
+ OPC_MoveParent,
+ OPC_SwitchType , 18, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPfd), 0,
+ 1, MVT::v2f32, 3, 0, 1, 2,
+ 18, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPfq), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 0,
+ 45|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 124,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_SwitchType , 18, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUP8d), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 18, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUP16d), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 18, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUP32d), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 18, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUP8q), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 18, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUP16q), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 18, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUP32q), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 44,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_SwitchType , 18, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPfdf), 0,
+ 1, MVT::v2f32, 3, 0, 1, 2,
+ 18, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPfqf), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 0,
+ 0,
+ 0,
+ 115|128,3, ARMISD::VDUPLANE,
+ OPC_RecordChild0,
+ OPC_Scope, 56,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPLN8d), 0,
+ 1, MVT::v8i8, 4, 0, 2, 3, 4,
+ 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPLN8q), 0,
+ 1, MVT::v16i8, 4, 0, 2, 3, 4,
+ 0,
+ 56,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPLN16d), 0,
+ 1, MVT::v4i16, 4, 0, 2, 3, 4,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPLN16q), 0,
+ 1, MVT::v8i16, 4, 0, 2, 3, 4,
+ 0,
+ 56,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPLN32d), 0,
+ 1, MVT::v2i32, 4, 0, 2, 3, 4,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPLN32q), 0,
+ 1, MVT::v4i32, 4, 0, 2, 3, 4,
+ 0,
+ 56,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPLNfd), 0,
+ 1, MVT::v2f32, 4, 0, 2, 3, 4,
+ 21, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPLNfq), 0,
+ 1, MVT::v4f32, 4, 0, 2, 3, 4,
+ 0,
+ 46,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 18, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v8i8, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 19, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPLN8q), 0,
+ 1, MVT::v16i8, 4, 4, 6, 7, 8,
+ 46,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 6, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v4i16, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 7, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPLN16q), 0,
+ 1, MVT::v8i16, 4, 4, 6, 7, 8,
+ 46,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 8, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2i32, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 9, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPLN32q), 0,
+ 1, MVT::v4i32, 4, 4, 6, 7, 8,
+ 46,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 8, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::v2f32, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 9, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDUPLNfq), 0,
+ 1, MVT::v4f32, 4, 4, 6, 7, 8,
+ 39,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 20, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i64, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 22, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v2i64, 3, 0, 4, 6,
+ 39,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 20, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 22, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v2f64, 3, 0, 4, 6,
+ 0,
+ 74|128,1, ARMISD::VEXT,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VEXTd8), 0,
+ 1, MVT::v8i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VEXTd16), 0,
+ 1, MVT::v4i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VEXTd32), 0,
+ 1, MVT::v2i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VEXTdf), 0,
+ 1, MVT::v2f32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VEXTq8), 0,
+ 1, MVT::v16i8, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VEXTq16), 0,
+ 1, MVT::v8i16, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VEXTq32), 0,
+ 1, MVT::v4i32, 5, 0, 1, 3, 4, 5,
+ 22, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VEXTqf), 0,
+ 1, MVT::v4f32, 5, 0, 1, 3, 4, 5,
+ 0,
+ 2|128,3, ISD::Constant,
+ OPC_RecordNode,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 4,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MOVi), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 28,
+ OPC_CheckPredicate, 5,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVi), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 24,
+ OPC_CheckPredicate, 61,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVi16), 0,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 31,
+ OPC_CheckPredicate, 23,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 17, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MVNi), 0,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 24,
+ OPC_CheckPredicate, 7,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 26,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVi2pieces), 0,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 28,
+ OPC_CheckPredicate, 53,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tMOVi8), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 24,
+ OPC_CheckPredicate, 61,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MOVi16), 0,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 31,
+ OPC_CheckPredicate, 6,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 1, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MVNi), 0,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 57,
+ OPC_CheckPredicate, 62,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 23, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tMOVi8), 0,
+ 1, MVT::i32, 4, 2, 4, 5, 6,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 24, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLSLri), 0,
+ 1, MVT::i32, 5, 1, 7, 9, 10, 11,
+ 51,
+ OPC_CheckPredicate, 63,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 25, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tMOVi8), 0,
+ 1, MVT::i32, 4, 2, 4, 5, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tMVN), 0,
+ 1, MVT::i32, 4, 1, 7, 8, 9,
+ 46,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVi32imm), 0,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 20,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MOVi32imm), 0,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 0,
+ 53, ISD::ConstantFP,
+ OPC_RecordNode,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 64,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 27,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::FCONSTD), 0,
+ 1, MVT::f64, 3, 1, 2, 3,
+ 24,
+ OPC_CheckPredicate, 65,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 27,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::FCONSTS), 0,
+ 1, MVT::f32, 3, 1, 2, 3,
+ 0,
+ 79|128,1, ISD::BUILD_VECTOR,
+ OPC_RecordNode,
+ OPC_Scope, 50,
+ OPC_CheckPredicate, 66,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitNodeXForm, 26, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVv8i8), 0,
+ 1, MVT::v8i8, 3, 1, 2, 3,
+ 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitNodeXForm, 26, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVv16i8), 0,
+ 1, MVT::v16i8, 3, 1, 2, 3,
+ 0,
+ 50,
+ OPC_CheckPredicate, 67,
+ OPC_SwitchType , 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitNodeXForm, 27, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVv4i16), 0,
+ 1, MVT::v4i16, 3, 1, 2, 3,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitNodeXForm, 27, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVv8i16), 0,
+ 1, MVT::v8i16, 3, 1, 2, 3,
+ 0,
+ 50,
+ OPC_CheckPredicate, 68,
+ OPC_SwitchType , 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitNodeXForm, 28, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVv2i32), 0,
+ 1, MVT::v2i32, 3, 1, 2, 3,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitNodeXForm, 28, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVv4i32), 0,
+ 1, MVT::v4i32, 3, 1, 2, 3,
+ 0,
+ 50,
+ OPC_CheckPredicate, 69,
+ OPC_SwitchType , 21, MVT::v1i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitNodeXForm, 29, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVv1i64), 0,
+ 1, MVT::v1i64, 3, 1, 2, 3,
+ 21, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitNodeXForm, 29, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVv2i64), 0,
+ 1, MVT::v2i64, 3, 1, 2, 3,
+ 0,
+ 0,
+ 71, ISD::ATOMIC_LOAD_ADD,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 70,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_ADD_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 71,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_ADD_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 72,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_ADD_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 0,
+ 71, ISD::ATOMIC_LOAD_SUB,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 73,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_SUB_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 74,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_SUB_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 75,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_SUB_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 0,
+ 71, ISD::ATOMIC_LOAD_AND,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 76,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_AND_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 77,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_AND_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 78,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_AND_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 0,
+ 71, ISD::ATOMIC_LOAD_OR,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 79,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_OR_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 80,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_OR_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 81,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_OR_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 0,
+ 71, ISD::ATOMIC_LOAD_XOR,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 82,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_XOR_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 83,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_XOR_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 84,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_XOR_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 0,
+ 71, ISD::ATOMIC_LOAD_NAND,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 85,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_NAND_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 86,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_NAND_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 87,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_NAND_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 0,
+ 71, ISD::ATOMIC_SWAP,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 88,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_SWAP_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 89,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_SWAP_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 22,
+ OPC_CheckPredicate, 90,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_SWAP_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 1, 2,
+ 0,
+ 77, ISD::ATOMIC_CMP_SWAP,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 91,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_CMP_SWAP_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 24,
+ OPC_CheckPredicate, 92,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_CMP_SWAP_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 24,
+ OPC_CheckPredicate, 93,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_CMP_SWAP_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 0,
+ 25|128,3, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_Scope, 29,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_SwitchType , 3, MVT::v1i64,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v8i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::f64,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_SwitchType , 3, MVT::v1i64,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v8i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::f64,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_SwitchType , 3, MVT::v1i64,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::f64,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_SwitchType , 3, MVT::v1i64,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v8i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_SwitchType , 3, MVT::v1i64,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2i32,
+ OPC_CompleteMatch, 1, 0,
-SDNode *Select_ISD_FSUB_f32(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fsub:f32 (fneg:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b)), SPR:f32:$dstin)
- // Emits: (VNMLAS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FNEG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_205(N, ARM::VNMLAS, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (fsub:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b), SPR:f32:$dstin)
- // Emits: (VNMLSS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_127(N, ARM::VNMLSS, MVT::f32);
- return Result;
- }
- }
+ 3, MVT::v4i16,
+ OPC_CompleteMatch, 1, 0,
- // Pattern: (fsub:f32 SPR:f32:$dstin, (fmul:f32 SPR:f32:$a, SPR:f32:$b))
- // Emits: (VMLSS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->useNEONForSinglePrecisionFP())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_125(N, ARM::VMLSS, MVT::f32);
- return Result;
- }
- }
+ 3, MVT::v8i8,
+ OPC_CompleteMatch, 1, 0,
- // Pattern: (fsub:f32 SPR:f32:$a, SPR:f32:$b)
- // Emits: (VSUBS:f32 SPR:f32:$a, SPR:f32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_44(N, ARM::VSUBS, MVT::f32);
- return Result;
- }
+ 3, MVT::f64,
+ OPC_CompleteMatch, 1, 0,
- // Pattern: (fsub:f32 SPR:f32:$a, SPR:f32:$b)
- // Emits: (EXTRACT_SUBREG:f32 (VSUBfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32), (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$b, 1:i32)), 1:i32)
- // Pattern complexity = 3 cost = 6 size = 0
- if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_206(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VSUBfd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
- return Result;
- }
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::v1i64,
+ OPC_SwitchType , 3, MVT::v2i32,
+ OPC_CompleteMatch, 1, 0,
- CannotYetSelect(N);
- return NULL;
-}
+ 3, MVT::v4i16,
+ OPC_CompleteMatch, 1, 0,
-SDNode *Select_ISD_FSUB_f64(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fsub:f64 (fneg:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b)), DPR:f64:$dstin)
- // Emits: (VNMLAD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FNEG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_205(N, ARM::VNMLAD, MVT::f64);
- return Result;
- }
- }
-
- // Pattern: (fsub:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b), DPR:f64:$dstin)
- // Emits: (VNMLSD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_127(N, ARM::VNMLSD, MVT::f64);
- return Result;
- }
- }
+ 3, MVT::v8i8,
+ OPC_CompleteMatch, 1, 0,
- // Pattern: (fsub:f64 DPR:f64:$dstin, (fmul:f64 DPR:f64:$a, DPR:f64:$b))
- // Emits: (VMLSD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->useNEONForSinglePrecisionFP())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_125(N, ARM::VMLSD, MVT::f64);
- return Result;
- }
- }
+ 3, MVT::f64,
+ OPC_CompleteMatch, 1, 0,
- // Pattern: (fsub:f64 DPR:f64:$a, DPR:f64:$b)
- // Emits: (VSUBD:f64 DPR:f64:$a, DPR:f64:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasVFP2())) {
- SDNode *Result = Emit_44(N, ARM::VSUBD, MVT::f64);
- return Result;
- }
+ 3, MVT::v2f32,
+ OPC_CompleteMatch, 1, 0,
- CannotYetSelect(N);
- return NULL;
-}
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_SwitchType , 3, MVT::v2i64,
+ OPC_CompleteMatch, 1, 0,
-SDNode *Select_ISD_FSUB_v2f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (fsub:v2f32 DPR:v2f32:$src1, (fmul:v2f32 DPR:v2f32:$src2, (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)))
- // Emits: (VMLSslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_129(N, ARM::VMLSslfd, MVT::v2f32);
- return Result;
- }
- }
- }
-
- // Pattern: (fsub:v2f32 DPR:v2f32:$src1, (fmul:v2f32 (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), DPR:v2f32:$src2))
- // Emits: (VMLSslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_130(N, ARM::VMLSslfd, MVT::v2f32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fsub:v2f32 DPR:v2f32:$src1, (fmul:v2f32 DPR:v2f32:$src2, DPR:v2f32:$src3))
- // Emits: (VMLSfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR:v2f32:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- SDNode *Result = Emit_125(N, ARM::VMLSfd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (fsub:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VSUBfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VSUBfd, MVT::v2f32);
- return Result;
- }
+ 3, MVT::v8i16,
+ OPC_CompleteMatch, 1, 0,
- CannotYetSelect(N);
- return NULL;
-}
+ 3, MVT::v16i8,
+ OPC_CompleteMatch, 1, 0,
-SDNode *Select_ISD_FSUB_v4f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)))
- // Emits: (VMLSslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_129(N, ARM::VMLSslfq, MVT::v4f32);
- return Result;
- }
- }
- }
-
- // Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2))
- // Emits: (VMLSslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_130(N, ARM::VMLSslfq, MVT::v4f32);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane)))
- // Emits: (VMLSslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_137(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
- return Result;
- }
- }
- }
-
- // Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2))
- // Emits: (VMLSslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_138(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasNEON())) {
-
- // Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, QPR:v4f32:$src3))
- // Emits: (VMLSfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, QPR:v4f32:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_125(N, ARM::VMLSfq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (fsub:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VSUBfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VSUBfq, MVT::v4f32);
- return Result;
- }
+ 3, MVT::v4f32,
+ OPC_CompleteMatch, 1, 0,
- CannotYetSelect(N);
- return NULL;
-}
+ 3, MVT::v2f64,
+ OPC_CompleteMatch, 1, 0,
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_50(N, ARM::VSETLNi8, MVT::v8i8);
- return Result;
- }
- }
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_SwitchType , 3, MVT::v2i64,
+ OPC_CompleteMatch, 1, 0,
- CannotYetSelect(N);
- return NULL;
-}
+ 3, MVT::v4i32,
+ OPC_CompleteMatch, 1, 0,
-DISABLE_INLINE SDNode *Emit_213(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_DSubReg_i8_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp3), 0);
- SDValue Tmp6 = Transform_SubReg_i8_lane(Tmp2.getNode());
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp4, N1, Tmp6, Tmp7, Tmp8 };
- SDValue Tmp9(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Ops1, 5), 0);
- SDValue Tmp10 = Transform_DSubReg_i8_reg(Tmp2.getNode());
- return CurDAG->SelectNodeTo(N, Opc2, VT2, N0, Tmp9, Tmp10);
-}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v16i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_213(N, TargetOpcode::EXTRACT_SUBREG, ARM::VSETLNi8, TargetOpcode::INSERT_SUBREG, MVT::v8i8, MVT::f64, MVT::v16i8);
- return Result;
- }
+ 3, MVT::v16i8,
+ OPC_CompleteMatch, 1, 0,
- CannotYetSelect(N);
- return NULL;
-}
+ 3, MVT::v4f32,
+ OPC_CompleteMatch, 1, 0,
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_50(N, ARM::VSETLNi16, MVT::v4i16);
- return Result;
- }
- }
+ 3, MVT::v2f64,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_SwitchType , 3, MVT::v2i64,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v8i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2f64,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_SwitchType , 3, MVT::v2i64,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v8i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v16i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_SwitchType , 3, MVT::v2i64,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v8i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v16i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2f64,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_SwitchType , 3, MVT::v4i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v8i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v16i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2f64,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 22,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVRS), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVSR), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 0,
+ 36, ARMISD::RET_FLAG,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BX_RET), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 2, 1, 2,
+ 11,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBX_RET), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 0,
+ 0,
+ 32, ISD::BRIND,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BRIND), 0|OPFL_Chain,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBRIND), 0|OPFL_Chain,
+ 0, 1, 1,
+ 0,
+ 59, ARMISD::CALL_NOLINK,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BX), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 15,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BXr9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 28,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBX), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 29,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBXr9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 48, ISD::BR,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BasicBlock,
+ OPC_MoveParent,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::B), 0|OPFL_Chain,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tB), 0|OPFL_Chain,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2B), 0|OPFL_Chain,
+ 0, 1, 1,
+ 0,
+ 52, ARMISD::RRX,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVrx), 0|OPFL_FlagInput,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MOVrx), 0|OPFL_FlagInput,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 35, ARMISD::SRL_FLAG,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVsrl_flag), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MOVsrl_flag), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 35, ARMISD::SRA_FLAG,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVsra_flag), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 10,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MOVsra_flag), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 46, ISD::MULHS,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMMUL), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 19,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SMMUL), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 0,
+ 43, ISD::CTLZ,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 30,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::CLZ), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CLZ), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 43, ARMISD::RBIT,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RBIT), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2RBIT), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 62, ISD::BSWAP,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::REV), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tREV), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2REV), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
+ 43, ARMISD::MEMBARRIER,
+ OPC_RecordNode,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 31,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::Int_MemBarrierV7), 0|OPFL_Chain,
+ 0, 0,
+ 15,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::Int_MemBarrierV6), 0|OPFL_Chain,
+ 0, 1, 1,
+ 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2Int_MemBarrierV7), 0|OPFL_Chain,
+ 0, 0,
+ 0,
+ 43, ARMISD::SYNCBARRIER,
+ OPC_RecordNode,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 31,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::Int_SyncBarrierV7), 0|OPFL_Chain,
+ 0, 0,
+ 15,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::Int_SyncBarrierV6), 0|OPFL_Chain,
+ 0, 1, 1,
+ 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2Int_SyncBarrierV7), 0|OPFL_Chain,
+ 0, 0,
+ 0,
+ 34, ARMISD::THREAD_POINTER,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 9,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::TPsoft), 0,
+ 1, MVT::i32, 0,
+ 9,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tTPsoft), 0,
+ 1, MVT::i32, 0,
+ 9,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2TPsoft), 0,
+ 1, MVT::i32, 0,
+ 0,
+ 46, ARMISD::EH_SJLJ_SETJMP,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::Int_eh_sjlj_setjmp), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tInt_eh_sjlj_setjmp), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2Int_eh_sjlj_setjmp), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 47, ARMISD::CMPFP,
+ OPC_RecordChild0,
+ OPC_Scope, 21,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCMPED), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 21,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCMPES), 0|OPFL_FlagOutput,
+ 0, 4, 0, 1, 2, 3,
+ 0,
+ 46, ISD::FDIV,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 19, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDIVD), 0,
+ 1, MVT::f64, 4, 0, 1, 2, 3,
+ 19, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VDIVS), 0,
+ 1, MVT::f32, 4, 0, 1, 2, 3,
+ 0,
+ 97, ISD::FABS,
+ OPC_RecordChild0,
+ OPC_SwitchType , 18, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSD), 0,
+ 1, MVT::f64, 3, 0, 1, 2,
+ 72, MVT::f32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSS), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 50,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 1, 0, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VABSfd_sfp), 0,
+ 1, MVT::f64, 3, 3, 4, 5,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 6, 7,
+ 0,
+ 0,
+ 43, ARMISD::CMPFPw0,
+ OPC_RecordChild0,
+ OPC_Scope, 19,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCMPEZD), 0|OPFL_FlagOutput,
+ 0, 3, 0, 1, 2,
+ 19,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCMPEZS), 0|OPFL_FlagOutput,
+ 0, 3, 0, 1, 2,
+ 0,
+ 23, ISD::FP_EXTEND,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTDS), 0,
+ 1, MVT::f64, 3, 0, 1, 2,
+ 23, ISD::FP_ROUND,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTSD), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 43, ISD::FSQRT,
+ OPC_RecordChild0,
+ OPC_SwitchType , 18, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSQRTD), 0,
+ 1, MVT::f64, 3, 0, 1, 2,
+ 18, MVT::f32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSQRTS), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 0,
+ 21, ARMISD::VMOVDRR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVDRR), 0,
+ 1, MVT::f64, 4, 0, 1, 2, 3,
+ 97, ARMISD::SITOF,
+ OPC_RecordChild0,
+ OPC_SwitchType , 18, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSITOD), 0,
+ 1, MVT::f64, 3, 0, 1, 2,
+ 72, MVT::f32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSITOS), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 50,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2i32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 1, 0, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VCVTs2fd_sfp), 0,
+ 1, MVT::f64, 3, 3, 4, 5,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 6, 7,
+ 0,
+ 0,
+ 97, ARMISD::UITOF,
+ OPC_RecordChild0,
+ OPC_SwitchType , 18, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VUITOD), 0,
+ 1, MVT::f64, 3, 0, 1, 2,
+ 72, MVT::f32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VUITOS), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 50,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2i32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 1, 0, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VCVTu2fd_sfp), 0,
+ 1, MVT::f64, 3, 3, 4, 5,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 6, 7,
+ 0,
+ 0,
+ 99, ARMISD::FTOSI,
+ OPC_RecordChild0,
+ OPC_Scope, 20,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTOSIZD), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 74,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTOSIZS), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 50,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 1, 0, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VCVTf2sd_sfp), 0,
+ 1, MVT::f64, 3, 3, 4, 5,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 6, 7,
+ 0,
+ 0,
+ 99, ARMISD::FTOUI,
+ OPC_RecordChild0,
+ OPC_Scope, 20,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTOUIZD), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 74,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTOUIZS), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 50,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 1, 0, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VCVTf2ud_sfp), 0,
+ 1, MVT::f64, 3, 3, 4, 5,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 6, 7,
+ 0,
+ 0,
+ 17, ARMISD::FMSTAT,
+ OPC_CaptureFlagInput,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::FMSTAT), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 2, 0, 1,
+ 75|128,1, ARMISD::VCEQ,
+ OPC_RecordChild0,
+ OPC_Scope, 24,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQfd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQfq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 75|128,1, ARMISD::VCGE,
+ OPC_RecordChild0,
+ OPC_Scope, 24,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEfd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEfq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 25|128,1, ARMISD::VCGEU,
+ OPC_RecordChild0,
+ OPC_Scope, 24,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 75|128,1, ARMISD::VCGT,
+ OPC_RecordChild0,
+ OPC_Scope, 24,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTfd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTfq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 25|128,1, ARMISD::VCGTU,
+ OPC_RecordChild0,
+ OPC_Scope, 24,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTuv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTuv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTuv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTuv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 25|128,1, ARMISD::VTST,
+ OPC_RecordChild0,
+ OPC_Scope, 24,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTSTv8i8), 0,
+ 1, MVT::v8i8, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTSTv4i16), 0,
+ 1, MVT::v4i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTSTv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTSTv16i8), 0,
+ 1, MVT::v16i8, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTSTv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTSTv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
+ 49, ISD::FP_TO_SINT,
+ OPC_RecordChild0,
+ OPC_Scope, 22,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTf2sd), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTf2sq), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 49, ISD::FP_TO_UINT,
+ OPC_RecordChild0,
+ OPC_Scope, 22,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTf2ud), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTf2uq), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 0,
+ 49, ISD::SINT_TO_FP,
+ OPC_RecordChild0,
+ OPC_Scope, 22,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTs2fd), 0,
+ 1, MVT::v2f32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTs2fq), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 0,
+ 49, ISD::UINT_TO_FP,
+ OPC_RecordChild0,
+ OPC_Scope, 22,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTu2fd), 0,
+ 1, MVT::v2f32, 3, 0, 1, 2,
+ 22,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTu2fq), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 0,
+ 35|128,1, ARMISD::VREV64,
+ OPC_RecordChild0,
+ OPC_SwitchType , 18, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV64d8), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 18, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV64d16), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 18, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV64d32), 0,
+ 1, MVT::v2i32, 3, 0, 1, 2,
+ 18, MVT::v2f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV64df), 0,
+ 1, MVT::v2f32, 3, 0, 1, 2,
+ 18, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV64q8), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 18, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV64q16), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 18, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV64q32), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 18, MVT::v4f32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV64qf), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 0,
+ 83, ARMISD::VREV32,
+ OPC_RecordChild0,
+ OPC_SwitchType , 18, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV32d8), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 18, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV32d16), 0,
+ 1, MVT::v4i16, 3, 0, 1, 2,
+ 18, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV32q8), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 18, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV32q16), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 0,
+ 43, ARMISD::VREV16,
+ OPC_RecordChild0,
+ OPC_SwitchType , 18, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV16d8), 0,
+ 1, MVT::v8i8, 3, 0, 1, 2,
+ 18, MVT::v16i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VREV16q8), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 0,
+ 67|128,2, ISD::SCALAR_TO_VECTOR,
+ OPC_RecordChild0,
+ OPC_Scope, 48,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_SwitchType , 20, MVT::v2f32,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v2f32, 3, 1, 0, 2,
+ 20, MVT::v4f32,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v4f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v4f32, 3, 1, 0, 2,
+ 0,
+ 24,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_CheckType, MVT::v2f64,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f64, 0,
+ OPC_EmitInteger, MVT::i32, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v2f64, 3, 1, 0, 2,
+ 116|128,1,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_SwitchType , 28, MVT::v8i8,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v8i8, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSETLNi8), 0,
+ 1, MVT::v8i8, 5, 1, 0, 2, 3, 4,
+ 28, MVT::v4i16,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v4i16, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSETLNi16), 0,
+ 1, MVT::v4i16, 5, 1, 0, 2, 3, 4,
+ 28, MVT::v2i32,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2i32, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSETLNi32), 0,
+ 1, MVT::v2i32, 5, 1, 0, 2, 3, 4,
+ 48, MVT::v16i8,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v16i8, 0,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v8i8, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VSETLNi8), 0,
+ 1, MVT::f64, 5, 2, 0, 3, 4, 5,
+ OPC_EmitInteger, MVT::i32, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v16i8, 3, 1, 6, 7,
+ 48, MVT::v8i16,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v8i16, 0,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v4i16, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VSETLNi16), 0,
+ 1, MVT::f64, 5, 2, 0, 3, 4, 5,
+ OPC_EmitInteger, MVT::i32, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v8i16, 3, 1, 6, 7,
+ 48, MVT::v4i32,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v4i32, 0,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2i32, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VSETLNi32), 0,
+ 1, MVT::f64, 5, 2, 0, 3, 4, 5,
+ OPC_EmitInteger, MVT::i32, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v4i32, 3, 1, 6, 7,
+ 0,
+ 0,
+ 73, ARMISD::FMAX,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 2, 0, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 5, 1, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VMAXfd_sfp), 0,
+ 1, MVT::f64, 4, 4, 7, 8, 9,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 10, 11,
+ 73, ARMISD::FMIN,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 2, 0, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::f64, 3, 5, 1, 6,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::VMINfd_sfp), 0,
+ 1, MVT::f64, 4, 4, 7, 8, 9,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 10, 11,
+ 0,
+ 0
+ }; // Total Array size is 63661 bytes
+
+ #undef TARGET_OPCODE
+ return SelectCodeCommon(N, MatcherTable,sizeof(MatcherTable));
+}
+
+bool CheckPatternPredicate(unsigned PredNo) const {
+ switch (PredNo) {
+ default: assert(0 && "Invalid predicate in table?");
+ case 0: return (!Subtarget->isThumb()) && (Subtarget->hasV6Ops());
+ case 1: return (Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops());
+ case 2: return (Subtarget->isThumb2());
+ case 3: return (Subtarget->hasNEON());
+ case 4: return (!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops());
+ case 5: return (!Subtarget->isThumb());
+ case 6: return (Subtarget->isThumb1Only());
+ case 7: return (!Subtarget->isThumb()) && (Subtarget->hasV5TEOps());
+ case 8: return (Subtarget->hasVFP2());
+ case 9: return (Subtarget->isThumb());
+ case 10: return (Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP());
+ case 11: return (Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP());
+ case 12: return (!Subtarget->useNEONForSinglePrecisionFP());
+ case 13: return (!HonorSignDependentRoundingFPMath());
+ case 14: return (!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin());
+ case 15: return (!Subtarget->isThumb()) && (Subtarget->isTargetDarwin());
+ case 16: return (Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin());
+ case 17: return (Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin());
+ case 18: return (!Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin());
+ case 19: return (!Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin());
+ case 20: return (!Subtarget->isThumb()) && (!Subtarget->useMovt());
+ case 21: return (!Subtarget->isThumb()) && (Subtarget->useMovt());
+ case 22: return (Subtarget->isThumb2()) && (!Subtarget->useMovt());
+ case 23: return (Subtarget->isThumb2()) && (Subtarget->useMovt());
+ case 24: return (Subtarget->isThumb()) && (!Subtarget->isTargetDarwin());
+ case 25: return (Subtarget->isThumb()) && (Subtarget->isTargetDarwin());
+ case 26: return (!Subtarget->isThumb()) && (!Subtarget->hasV6T2Ops());
+ case 27: return (Subtarget->hasVFP3());
+ case 28: return (Subtarget->isThumb1Only()) && (!Subtarget->isTargetDarwin());
+ case 29: return (Subtarget->isThumb1Only()) && (Subtarget->isTargetDarwin());
+ case 30: return (!Subtarget->isThumb()) && (Subtarget->hasV5TOps());
+ case 31: return (!Subtarget->isThumb()) && (Subtarget->hasV7Ops());
+ }
+}
+
+bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {
+ switch (PredNo) {
+ default: assert(0 && "Invalid predicate in table?");
+ case 0: { // Predicate_imm16_31
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
-DISABLE_INLINE SDNode *Emit_214(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_DSubReg_i16_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp3), 0);
- SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp2.getNode());
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp4, N1, Tmp6, Tmp7, Tmp8 };
- SDValue Tmp9(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Ops1, 5), 0);
- SDValue Tmp10 = Transform_DSubReg_i16_reg(Tmp2.getNode());
- return CurDAG->SelectNodeTo(N, Opc2, VT2, N0, Tmp9, Tmp10);
-}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v8i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_214(N, TargetOpcode::EXTRACT_SUBREG, ARM::VSETLNi16, TargetOpcode::INSERT_SUBREG, MVT::v4i16, MVT::f64, MVT::v8i16);
- return Result;
}
+ case 1: { // Predicate_imm1_15
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_50(N, ARM::VSETLNi32, MVT::v2i32);
- return Result;
- }
}
+ case 2: { // Predicate_immAllOnesV_bc
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return ISD::isBuildVectorAllOnes(N);
-DISABLE_INLINE SDNode *Emit_215(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_DSubReg_i32_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp3), 0);
- SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp2.getNode());
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp4, N1, Tmp6, Tmp7, Tmp8 };
- SDValue Tmp9(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Ops1, 5), 0);
- SDValue Tmp10 = Transform_DSubReg_i32_reg(Tmp2.getNode());
- return CurDAG->SelectNodeTo(N, Opc2, VT2, N0, Tmp9, Tmp10);
-}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_215(N, TargetOpcode::EXTRACT_SUBREG, ARM::VSETLNi32, TargetOpcode::INSERT_SUBREG, MVT::v2i32, MVT::f64, MVT::v4i32);
- return Result;
}
+ case 3: { // Predicate_lo16AllZero
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ // Returns true if all low 16-bits are 0.
+ return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
-DISABLE_INLINE SDNode *Emit_216(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp1 = CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue Tmp5 = Transform_SSubReg_f32_reg(Tmp4.getNode());
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, N1, Tmp5);
-}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_216(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
- return Result;
}
+ case 4: { // Predicate_t2_so_imm
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
-DISABLE_INLINE SDNode *Emit_217(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp1 = CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue Tmp5 = Transform_SSubReg_f32_reg(Tmp4.getNode());
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, N1, Tmp5);
-}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v4f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_217(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
- return Result;
}
+ case 5: { // Predicate_so_imm
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_218(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_DSubReg_f64_reg(Tmp2.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp3);
-}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_218(N, TargetOpcode::INSERT_SUBREG, MVT::v2f64);
- return Result;
+ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
+
}
+ case 6: { // Predicate_t2_so_imm_not
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
-DISABLE_INLINE SDNode *Emit_219(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, N3, Tmp4, Tmp5, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
-}
-SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(105)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3)) {
- SDValue N3 = N->getOperand(3);
- if (N2.getValueType() == MVT::i32) {
-
- // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, DPR:v8i8:$src)
- // Emits: (VST1d8:isVoid addrmode6:i32:$addr, DPR:v8i8:$src)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_219(N, ARM::VST1d8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, DPR:v4i16:$src)
- // Emits: (VST1d16:isVoid addrmode6:i32:$addr, DPR:v4i16:$src)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_219(N, ARM::VST1d16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, DPR:v2i32:$src)
- // Emits: (VST1d32:isVoid addrmode6:i32:$addr, DPR:v2i32:$src)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_219(N, ARM::VST1d32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, DPR:v2f32:$src)
- // Emits: (VST1df:isVoid addrmode6:i32:$addr, DPR:v2f32:$src)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N3.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_219(N, ARM::VST1df, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, DPR:v1i64:$src)
- // Emits: (VST1d64:isVoid addrmode6:i32:$addr, DPR:v1i64:$src)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N3.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_219(N, ARM::VST1d64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, QPR:v16i8:$src)
- // Emits: (VST1q8:isVoid addrmode6:i32:$addr, QPR:v16i8:$src)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N3.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_219(N, ARM::VST1q8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, QPR:v8i16:$src)
- // Emits: (VST1q16:isVoid addrmode6:i32:$addr, QPR:v8i16:$src)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N3.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_219(N, ARM::VST1q16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, QPR:v4i32:$src)
- // Emits: (VST1q32:isVoid addrmode6:i32:$addr, QPR:v4i32:$src)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N3.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_219(N, ARM::VST1q32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, QPR:v4f32:$src)
- // Emits: (VST1qf:isVoid addrmode6:i32:$addr, QPR:v4f32:$src)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N3.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_219(N, ARM::VST1qf, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, QPR:v2i64:$src)
- // Emits: (VST1q64:isVoid addrmode6:i32:$addr, QPR:v2i64:$src)
- // Pattern complexity = 23 cost = 1 size = 0
- if (N3.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_219(N, ARM::VST1q64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
- }
- }
- }
- }
}
+ case 7: { // Predicate_so_imm2part
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_220(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N2, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_221(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N2, N3, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_222(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, Tmp3, Tmp4);
-}
-DISABLE_INLINE SDNode *Emit_223(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N2, N3, N4, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_224(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N2, N3, N4, N5, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 7);
-}
-DISABLE_INLINE SDNode *Emit_225(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- SDValue N6 = N->getOperand(6);
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N2, N3, N4, N5, N6, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 8);
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i8 28:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VHADDsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(28)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VHADDsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 29:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VHADDuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(29)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VHADDuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 91:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VRHADDsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(91)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VRHADDsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 92:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VRHADDuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(92)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VRHADDuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 64:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VQADDsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(64)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VQADDsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 65:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VQADDuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(65)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VQADDuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 16:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VADDHNv8i8:v8i8 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VADDHNv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 88:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VRADDHNv8i8:v8i8 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(88)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VRADDHNv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 53:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VMULpd:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(53)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VMULpd, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 30:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VHSUBsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(30)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VHSUBsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 31:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VHSUBuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(31)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VHSUBuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 86:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VQSUBsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(86)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VQSUBsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 87:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VQSUBuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(87)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VQSUBuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 112:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VSUBHNv8i8:v8i8 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(112)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VSUBHNv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 98:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VRSUBHNv8i8:v8i8 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(98)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VRSUBHNv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 9:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VABDsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(9)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VABDsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 10:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VABDuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(10)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VABDuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 5:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Emits: (VABAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(5)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8 &&
- N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_221(N, ARM::VABAsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 6:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Emits: (VABAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(6)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8 &&
- N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_221(N, ARM::VABAuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 39:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VMAXsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(39)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VMAXsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 40:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VMAXuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(40)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VMAXuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 41:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VMINsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(41)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VMINsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 42:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VMINuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(42)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VMINuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 56:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VPADDi8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(56)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VPADDi8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 59:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VPMAXs8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(59)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VPMAXs8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 60:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VPMAXu8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(60)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VPMAXu8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 61:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VPMINs8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(61)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VPMINs8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 62:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VPMINu8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(62)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VPMINu8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 103:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VSHLsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(103)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VSHLsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 104:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VSHLuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(104)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VSHLuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 94:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VRSHLsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(94)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VRSHLsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 95:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VRSHLuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(95)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VRSHLuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 83:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VQSHLsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(83)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VQSHLsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 85:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VQSHLuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(85)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VQSHLuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 78:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VQRSHLsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(78)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 79:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VQRSHLuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(79)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 11:iPTR, DPR:v8i8:$src)
- // Emits: (VABSv8i8:v8i8 DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(11)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_222(N, ARM::VABSv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 63:iPTR, DPR:v8i8:$src)
- // Emits: (VQABSv8i8:v8i8 DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(63)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_222(N, ARM::VQABSv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 73:iPTR, DPR:v8i8:$src)
- // Emits: (VQNEGv8i8:v8i8 DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(73)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_222(N, ARM::VQNEGv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 21:iPTR, DPR:v8i8:$src)
- // Emits: (VCLSv8i8:v8i8 DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(21)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_222(N, ARM::VCLSv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 22:iPTR, DPR:v8i8:$src)
- // Emits: (VCLZv8i8:v8i8 DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(22)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_222(N, ARM::VCLZv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 23:iPTR, DPR:v8i8:$src)
- // Emits: (VCNTd:v8i8 DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(23)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_222(N, ARM::VCNTd, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 49:iPTR, QPR:v8i16:$src)
- // Emits: (VMOVNv8i8:v8i8 QPR:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(49)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_222(N, ARM::VMOVNv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 70:iPTR, QPR:v8i16:$src)
- // Emits: (VQMOVNsv8i8:v8i8 QPR:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(70)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_222(N, ARM::VQMOVNsv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 72:iPTR, QPR:v8i16:$src)
- // Emits: (VQMOVNuv8i8:v8i8 QPR:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(72)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_222(N, ARM::VQMOVNuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 71:iPTR, QPR:v8i16:$src)
- // Emits: (VQMOVNsuv8i8:v8i8 QPR:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(71)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_222(N, ARM::VQMOVNsuv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 117:iPTR, DPR:v8i8:$tbl1, DPR:v8i8:$src)
- // Emits: (VTBL1:v8i8 DPR:v8i8:$tbl1, DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(117)) {
- SDNode *Result = Emit_220(N, ARM::VTBL1, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 118:iPTR, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$src)
- // Emits: (VTBL2:v8i8 DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(118)) {
- SDNode *Result = Emit_221(N, ARM::VTBL2, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 119:iPTR, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$src)
- // Emits: (VTBL3:v8i8 DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(119)) {
- SDNode *Result = Emit_223(N, ARM::VTBL3, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 120:iPTR, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$tbl4, DPR:v8i8:$src)
- // Emits: (VTBL4:v8i8 DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$tbl4, DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(120)) {
- SDNode *Result = Emit_224(N, ARM::VTBL4, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 121:iPTR, DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$src)
- // Emits: (VTBX1:v8i8 DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(121)) {
- SDNode *Result = Emit_221(N, ARM::VTBX1, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 122:iPTR, DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$src)
- // Emits: (VTBX2:v8i8 DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(122)) {
- SDNode *Result = Emit_223(N, ARM::VTBX2, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 123:iPTR, DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$src)
- // Emits: (VTBX3:v8i8 DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(123)) {
- SDNode *Result = Emit_224(N, ARM::VTBX3, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 124:iPTR, DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$tbl4, DPR:v8i8:$src)
- // Emits: (VTBX4:v8i8 DPR:v8i8:$orig, DPR:v8i8:$tbl1, DPR:v8i8:$tbl2, DPR:v8i8:$tbl3, DPR:v8i8:$tbl4, DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(124)) {
- SDNode *Result = Emit_225(N, ARM::VTBX4, MVT::v8i8);
- return Result;
- }
- }
+ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
+
}
+ case 8: { // Predicate_t2_so_imm2part
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v16i8 28:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VHADDsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(28)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VHADDsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 29:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VHADDuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(29)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VHADDuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 91:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VRHADDsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(91)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VRHADDsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 92:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VRHADDuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(92)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VRHADDuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 64:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VQADDsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(64)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VQADDsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 65:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VQADDuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(65)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VQADDuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 53:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VMULpq:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(53)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VMULpq, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 30:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VHSUBsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(30)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VHSUBsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 31:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VHSUBuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(31)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VHSUBuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 86:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VQSUBsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(86)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VQSUBsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 87:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VQSUBuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(87)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VQSUBuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 9:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VABDsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(9)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VABDsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 10:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VABDuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(10)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VABDuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 5:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
- // Emits: (VABAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(5)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8 &&
- N3.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_221(N, ARM::VABAsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 6:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
- // Emits: (VABAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(6)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8 &&
- N3.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_221(N, ARM::VABAuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 39:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VMAXsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(39)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VMAXsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 40:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VMAXuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(40)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VMAXuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 41:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VMINsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(41)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VMINsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 42:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VMINuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(42)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VMINuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 103:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VSHLsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(103)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VSHLsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 104:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VSHLuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(104)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VSHLuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 94:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VRSHLsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(94)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VRSHLsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 95:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VRSHLuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(95)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VRSHLuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 83:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VQSHLsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(83)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VQSHLsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 85:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VQSHLuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(85)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VQSHLuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 78:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VQRSHLsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(78)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLsv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 79:iPTR, QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VQRSHLuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(79)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v16i8 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLuv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 11:iPTR, QPR:v16i8:$src)
- // Emits: (VABSv16i8:v16i8 QPR:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(11)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_222(N, ARM::VABSv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 63:iPTR, QPR:v16i8:$src)
- // Emits: (VQABSv16i8:v16i8 QPR:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(63)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_222(N, ARM::VQABSv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 73:iPTR, QPR:v16i8:$src)
- // Emits: (VQNEGv16i8:v16i8 QPR:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(73)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_222(N, ARM::VQNEGv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 21:iPTR, QPR:v16i8:$src)
- // Emits: (VCLSv16i8:v16i8 QPR:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(21)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_222(N, ARM::VCLSv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 22:iPTR, QPR:v16i8:$src)
- // Emits: (VCLZv16i8:v16i8 QPR:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(22)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_222(N, ARM::VCLZv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 23:iPTR, QPR:v16i8:$src)
- // Emits: (VCNTq:v16i8 QPR:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(23)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_222(N, ARM::VCNTq, MVT::v16i8);
- return Result;
- }
- }
- }
+ return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
+
}
+ case 9: { // Predicate_rot_imm
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
+ int32_t v = (int32_t)N->getZExtValue();
+ return v == 8 || v == 16 || v == 24;
-DISABLE_INLINE SDNode *Emit_226(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N21)->getZExtValue()), MVT::i32);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N20, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_227(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N2, N10, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i16 68:iPTR, DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
- // Emits: (VQDMULHslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16 &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_226(N, ARM::VQDMULHslv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 74:iPTR, DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
- // Emits: (VQRDMULHslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16 &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_226(N, ARM::VQRDMULHslv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 68:iPTR, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
- // Emits: (VQDMULHslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N10.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_227(N, ARM::VQDMULHslv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 74:iPTR, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
- // Emits: (VQRDMULHslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N10.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_227(N, ARM::VQRDMULHslv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 28:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VHADDsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(28)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VHADDsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 29:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VHADDuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(29)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VHADDuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 91:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VRHADDsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(91)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VRHADDsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 92:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VRHADDuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(92)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VRHADDuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 64:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VQADDsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(64)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VQADDsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 65:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VQADDuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(65)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VQADDuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 16:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VADDHNv4i16:v4i16 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VADDHNv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 88:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VRADDHNv4i16:v4i16 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(88)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VRADDHNv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 68:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VQDMULHv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VQDMULHv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 74:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VQRDMULHv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VQRDMULHv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 30:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VHSUBsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(30)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VHSUBsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 31:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VHSUBuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(31)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VHSUBuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 86:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VQSUBsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(86)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VQSUBsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 87:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VQSUBuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(87)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VQSUBuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 112:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VSUBHNv4i16:v4i16 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(112)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VSUBHNv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 98:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VRSUBHNv4i16:v4i16 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(98)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VRSUBHNv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 9:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VABDsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(9)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VABDsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 10:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VABDuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(10)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VABDuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 5:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Emits: (VABAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(5)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_221(N, ARM::VABAsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 6:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Emits: (VABAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(6)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_221(N, ARM::VABAuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 39:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VMAXsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(39)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VMAXsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 40:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VMAXuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(40)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VMAXuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 41:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VMINsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(41)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VMINsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 42:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VMINuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(42)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VMINuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 56:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VPADDi16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(56)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VPADDi16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 57:iPTR, DPR:v8i8:$src)
- // Emits: (VPADDLsv8i8:v4i16 DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(57)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_222(N, ARM::VPADDLsv8i8, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 58:iPTR, DPR:v8i8:$src)
- // Emits: (VPADDLuv8i8:v4i16 DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(58)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_222(N, ARM::VPADDLuv8i8, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 54:iPTR, DPR:v4i16:$src1, DPR:v8i8:$src2)
- // Emits: (VPADALsv8i8:v4i16 DPR:v4i16:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(54)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VPADALsv8i8, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 55:iPTR, DPR:v4i16:$src1, DPR:v8i8:$src2)
- // Emits: (VPADALuv8i8:v4i16 DPR:v4i16:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(55)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VPADALuv8i8, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 59:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VPMAXs16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(59)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VPMAXs16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 60:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VPMAXu16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(60)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VPMAXu16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 61:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VPMINs16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(61)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VPMINs16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 62:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VPMINu16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(62)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VPMINu16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 103:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VSHLsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(103)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VSHLsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 104:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VSHLuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(104)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VSHLuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 94:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VRSHLsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(94)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VRSHLsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 95:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VRSHLuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(95)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VRSHLuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 83:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VQSHLsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(83)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VQSHLsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 85:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VQSHLuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(85)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VQSHLuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 78:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VQRSHLsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(78)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 79:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VQRSHLuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(79)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 11:iPTR, DPR:v4i16:$src)
- // Emits: (VABSv4i16:v4i16 DPR:v4i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(11)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_222(N, ARM::VABSv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 63:iPTR, DPR:v4i16:$src)
- // Emits: (VQABSv4i16:v4i16 DPR:v4i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(63)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_222(N, ARM::VQABSv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 73:iPTR, DPR:v4i16:$src)
- // Emits: (VQNEGv4i16:v4i16 DPR:v4i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(73)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_222(N, ARM::VQNEGv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 21:iPTR, DPR:v4i16:$src)
- // Emits: (VCLSv4i16:v4i16 DPR:v4i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(21)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_222(N, ARM::VCLSv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 22:iPTR, DPR:v4i16:$src)
- // Emits: (VCLZv4i16:v4i16 DPR:v4i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(22)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_222(N, ARM::VCLZv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 49:iPTR, QPR:v4i32:$src)
- // Emits: (VMOVNv4i16:v4i16 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(49)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VMOVNv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 70:iPTR, QPR:v4i32:$src)
- // Emits: (VQMOVNsv4i16:v4i16 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(70)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VQMOVNsv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 72:iPTR, QPR:v4i32:$src)
- // Emits: (VQMOVNuv4i16:v4i16 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(72)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VQMOVNuv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 71:iPTR, QPR:v4i32:$src)
- // Emits: (VQMOVNsuv4i16:v4i16 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(71)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VQMOVNsuv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
}
+ case 10: { // Predicate_sext_16_node
+ SDNode *N = Node;
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
+ return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
-DISABLE_INLINE SDNode *Emit_228(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N21)->getZExtValue()), MVT::i32);
- SDValue Tmp5 = Transform_DSubReg_i16_reg(Tmp4.getNode());
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N20, Tmp5), 0);
- SDValue Tmp7 = Transform_SubReg_i16_lane(Tmp4.getNode());
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N1, Tmp6, Tmp7, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-DISABLE_INLINE SDNode *Emit_229(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N2, N1, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_230(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N2, N1, N3, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_231(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- SDValue Tmp5 = Transform_DSubReg_i16_reg(Tmp4.getNode());
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N10, Tmp5), 0);
- SDValue Tmp7 = Transform_SubReg_i16_lane(Tmp4.getNode());
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N2, Tmp6, Tmp7, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 68:iPTR, QPR:v8i16:$src1, (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
- // Emits: (VQDMULHslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16 &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_226(N, ARM::VQDMULHslv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 74:iPTR, QPR:v8i16:$src1, (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
- // Emits: (VQRDMULHslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16 &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_226(N, ARM::VQRDMULHslv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 68:iPTR, (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
- // Emits: (VQDMULHslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N10.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_227(N, ARM::VQDMULHslv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 74:iPTR, (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
- // Emits: (VQRDMULHslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N10.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_227(N, ARM::VQRDMULHslv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 68:iPTR, QPR:v8i16:$src1, (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane))
- // Emits: (VQDMULHslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 14 cost = 2 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16 &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_228(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQDMULHslv8i16, MVT::v4i16, MVT::v8i16);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 74:iPTR, QPR:v8i16:$src1, (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane))
- // Emits: (VQRDMULHslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 14 cost = 2 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16 &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_228(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQRDMULHslv8i16, MVT::v4i16, MVT::v8i16);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 68:iPTR, (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
- // Emits: (VQDMULHslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 14 cost = 2 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N10.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_231(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQDMULHslv8i16, MVT::v4i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 74:iPTR, (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
- // Emits: (VQRDMULHslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 14 cost = 2 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N10.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_231(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQRDMULHslv8i16, MVT::v4i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 17:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VADDLsv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(17)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VADDLsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 18:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VADDLuv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(18)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VADDLuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 19:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2)
- // Emits: (VADDWsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(19)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VADDWsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 20:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2)
- // Emits: (VADDWuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(20)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VADDWuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 28:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VHADDsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(28)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VHADDsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 29:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VHADDuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(29)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VHADDuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 91:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VRHADDsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(91)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VRHADDsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 92:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VRHADDuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(92)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VRHADDuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 64:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VQADDsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(64)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VQADDsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 65:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VQADDuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(65)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VQADDuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 68:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VQDMULHv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VQDMULHv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 74:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VQRDMULHv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VQRDMULHv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 51:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VMULLsv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(51)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VMULLsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 52:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VMULLuv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(52)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VMULLuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 50:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VMULLp:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(50)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VMULLp, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 43:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Emits: (VMLALsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(43)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i8 &&
- N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_221(N, ARM::VMLALsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 44:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Emits: (VMLALuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(44)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i8 &&
- N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_221(N, ARM::VMLALuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 45:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Emits: (VMLSLsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(45)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i8 &&
- N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_221(N, ARM::VMLSLsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 46:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Emits: (VMLSLuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(46)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i8 &&
- N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_221(N, ARM::VMLSLuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 113:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VSUBLsv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(113)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VSUBLsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 114:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VSUBLuv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(114)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VSUBLuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 115:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2)
- // Emits: (VSUBWsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(115)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VSUBWsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 116:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2)
- // Emits: (VSUBWuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(116)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VSUBWuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 30:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VHSUBsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(30)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VHSUBsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 31:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VHSUBuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(31)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VHSUBuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 86:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VQSUBsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(86)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VQSUBsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 87:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VQSUBuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(87)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VQSUBuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 9:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VABDsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(9)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VABDsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 10:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VABDuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(10)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VABDuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 7:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VABDLsv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(7)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VABDLsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 8:iPTR, DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VABDLuv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_220(N, ARM::VABDLuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 5:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
- // Emits: (VABAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(5)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16 &&
- N3.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_221(N, ARM::VABAsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 6:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
- // Emits: (VABAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(6)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16 &&
- N3.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_221(N, ARM::VABAuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 3:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Emits: (VABALsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(3)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i8 &&
- N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_221(N, ARM::VABALsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 4:iPTR, QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Emits: (VABALuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(4)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i8 &&
- N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_221(N, ARM::VABALuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 39:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VMAXsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(39)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VMAXsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 40:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VMAXuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(40)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VMAXuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 41:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VMINsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(41)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VMINsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 42:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VMINuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(42)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VMINuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 57:iPTR, QPR:v16i8:$src)
- // Emits: (VPADDLsv16i8:v8i16 QPR:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(57)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_222(N, ARM::VPADDLsv16i8, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 58:iPTR, QPR:v16i8:$src)
- // Emits: (VPADDLuv16i8:v8i16 QPR:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(58)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_222(N, ARM::VPADDLuv16i8, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 54:iPTR, QPR:v8i16:$src1, QPR:v16i8:$src2)
- // Emits: (VPADALsv16i8:v8i16 QPR:v8i16:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(54)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VPADALsv16i8, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 55:iPTR, QPR:v8i16:$src1, QPR:v16i8:$src2)
- // Emits: (VPADALuv16i8:v8i16 QPR:v8i16:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(55)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_220(N, ARM::VPADALuv16i8, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 103:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VSHLsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(103)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VSHLsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 104:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VSHLuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(104)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VSHLuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 94:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VRSHLsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(94)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VRSHLsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 95:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VRSHLuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(95)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VRSHLuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 83:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VQSHLsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(83)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VQSHLsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 85:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VQSHLuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(85)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VQSHLuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 78:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VQRSHLsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(78)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 79:iPTR, QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VQRSHLuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(79)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i16 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 11:iPTR, QPR:v8i16:$src)
- // Emits: (VABSv8i16:v8i16 QPR:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(11)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_222(N, ARM::VABSv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 63:iPTR, QPR:v8i16:$src)
- // Emits: (VQABSv8i16:v8i16 QPR:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(63)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_222(N, ARM::VQABSv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 73:iPTR, QPR:v8i16:$src)
- // Emits: (VQNEGv8i16:v8i16 QPR:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(73)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_222(N, ARM::VQNEGv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 21:iPTR, QPR:v8i16:$src)
- // Emits: (VCLSv8i16:v8i16 QPR:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(21)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_222(N, ARM::VCLSv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 22:iPTR, QPR:v8i16:$src)
- // Emits: (VCLZv8i16:v8i16 QPR:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(22)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_222(N, ARM::VCLZv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 47:iPTR, DPR:v8i8:$src)
- // Emits: (VMOVLsv8i16:v8i16 DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(47)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_222(N, ARM::VMOVLsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 48:iPTR, DPR:v8i8:$src)
- // Emits: (VMOVLuv8i16:v8i16 DPR:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(48)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_222(N, ARM::VMOVLuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 19:iPTR, DPR:v8i8:$src2, QPR:v8i16:$src1)
- // Emits: (VADDWsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(19)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_229(N, ARM::VADDWsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 20:iPTR, DPR:v8i8:$src2, QPR:v8i16:$src1)
- // Emits: (VADDWuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(20)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_229(N, ARM::VADDWuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 43:iPTR, DPR:v8i8:$src2, QPR:v8i16:$src1, DPR:v8i8:$src3)
- // Emits: (VMLALsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(43)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i16 &&
- N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_230(N, ARM::VMLALsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 44:iPTR, DPR:v8i8:$src2, QPR:v8i16:$src1, DPR:v8i8:$src3)
- // Emits: (VMLALuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(44)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i16 &&
- N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_230(N, ARM::VMLALuv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 45:iPTR, DPR:v8i8:$src2, QPR:v8i16:$src1, DPR:v8i8:$src3)
- // Emits: (VMLSLsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(45)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i16 &&
- N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_230(N, ARM::VMLSLsv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 46:iPTR, DPR:v8i8:$src2, QPR:v8i16:$src1, DPR:v8i8:$src3)
- // Emits: (VMLSLuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(46)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v8i8 &&
- N2.getValueType() == MVT::v8i16 &&
- N3.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_230(N, ARM::VMLSLuv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
}
+ case 11: { // Predicate_imm0_255_neg
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
+ return (uint32_t)(-N->getZExtValue()) < 255;
-DISABLE_INLINE SDNode *Emit_232(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i32 68:iPTR, DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
- // Emits: (VQDMULHslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32 &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_226(N, ARM::VQDMULHslv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 74:iPTR, DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
- // Emits: (VQRDMULHslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32 &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_226(N, ARM::VQRDMULHslv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 68:iPTR, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
- // Emits: (VQDMULHslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N10.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_227(N, ARM::VQDMULHslv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 74:iPTR, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
- // Emits: (VQRDMULHslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N10.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_227(N, ARM::VQRDMULHslv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 24:iPTR, DPR:v2f32:$src, (imm:i32):$SIMM)
- // Emits: (VCVTf2xsd:v2i32 DPR:v2f32:$src, (imm:i32):$SIMM)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(24)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_232(N, ARM::VCVTf2xsd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 25:iPTR, DPR:v2f32:$src, (imm:i32):$SIMM)
- // Emits: (VCVTf2xud:v2i32 DPR:v2f32:$src, (imm:i32):$SIMM)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(25)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_232(N, ARM::VCVTf2xud, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 28:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VHADDsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(28)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VHADDsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 29:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VHADDuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(29)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VHADDuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 91:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VRHADDsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(91)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VRHADDsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 92:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VRHADDuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(92)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VRHADDuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 64:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VQADDsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(64)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VQADDsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 65:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VQADDuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(65)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VQADDuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 16:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VADDHNv2i32:v2i32 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VADDHNv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 88:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VRADDHNv2i32:v2i32 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(88)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VRADDHNv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 68:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VQDMULHv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VQDMULHv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 74:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VQRDMULHv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VQRDMULHv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 30:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VHSUBsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(30)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VHSUBsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 31:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VHSUBuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(31)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VHSUBuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 86:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VQSUBsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(86)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VQSUBsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 87:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VQSUBuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(87)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VQSUBuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 112:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VSUBHNv2i32:v2i32 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(112)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VSUBHNv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 98:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VRSUBHNv2i32:v2i32 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(98)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VRSUBHNv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 12:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VACGEd:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_220(N, ARM::VACGEd, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 14:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VACGTd:v2i32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_220(N, ARM::VACGTd, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 9:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VABDsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(9)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VABDsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 10:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VABDuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(10)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VABDuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 5:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Emits: (VABAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(5)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_221(N, ARM::VABAsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 6:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Emits: (VABAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(6)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_221(N, ARM::VABAuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 39:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VMAXsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(39)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VMAXsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 40:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VMAXuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(40)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VMAXuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 41:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VMINsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(41)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VMINsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 42:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VMINuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(42)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VMINuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 56:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VPADDi32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(56)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VPADDi32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 57:iPTR, DPR:v4i16:$src)
- // Emits: (VPADDLsv4i16:v2i32 DPR:v4i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(57)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_222(N, ARM::VPADDLsv4i16, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 58:iPTR, DPR:v4i16:$src)
- // Emits: (VPADDLuv4i16:v2i32 DPR:v4i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(58)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_222(N, ARM::VPADDLuv4i16, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 54:iPTR, DPR:v2i32:$src1, DPR:v4i16:$src2)
- // Emits: (VPADALsv4i16:v2i32 DPR:v2i32:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(54)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VPADALsv4i16, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 55:iPTR, DPR:v2i32:$src1, DPR:v4i16:$src2)
- // Emits: (VPADALuv4i16:v2i32 DPR:v2i32:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(55)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VPADALuv4i16, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 59:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VPMAXs32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(59)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VPMAXs32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 60:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VPMAXu32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(60)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VPMAXu32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 61:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VPMINs32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(61)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VPMINs32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 62:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VPMINu32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(62)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VPMINu32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 89:iPTR, DPR:v2i32:$src)
- // Emits: (VRECPEd:v2i32 DPR:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(89)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_222(N, ARM::VRECPEd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 96:iPTR, DPR:v2i32:$src)
- // Emits: (VRSQRTEd:v2i32 DPR:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(96)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_222(N, ARM::VRSQRTEd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 103:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VSHLsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(103)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VSHLsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 104:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VSHLuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(104)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VSHLuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 94:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VRSHLsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(94)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VRSHLsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 95:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VRSHLuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(95)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VRSHLuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 83:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VQSHLsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(83)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VQSHLsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 85:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VQSHLuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(85)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VQSHLuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 78:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VQRSHLsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(78)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 79:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VQRSHLuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(79)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 11:iPTR, DPR:v2i32:$src)
- // Emits: (VABSv2i32:v2i32 DPR:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(11)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_222(N, ARM::VABSv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 63:iPTR, DPR:v2i32:$src)
- // Emits: (VQABSv2i32:v2i32 DPR:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(63)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_222(N, ARM::VQABSv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 73:iPTR, DPR:v2i32:$src)
- // Emits: (VQNEGv2i32:v2i32 DPR:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(73)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_222(N, ARM::VQNEGv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 21:iPTR, DPR:v2i32:$src)
- // Emits: (VCLSv2i32:v2i32 DPR:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(21)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_222(N, ARM::VCLSv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 22:iPTR, DPR:v2i32:$src)
- // Emits: (VCLZv2i32:v2i32 DPR:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(22)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_222(N, ARM::VCLZv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 49:iPTR, QPR:v2i64:$src)
- // Emits: (VMOVNv2i32:v2i32 QPR:v2i64:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(49)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_222(N, ARM::VMOVNv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 70:iPTR, QPR:v2i64:$src)
- // Emits: (VQMOVNsv2i32:v2i32 QPR:v2i64:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(70)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_222(N, ARM::VQMOVNsv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 72:iPTR, QPR:v2i64:$src)
- // Emits: (VQMOVNuv2i32:v2i32 QPR:v2i64:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(72)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_222(N, ARM::VQMOVNuv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 71:iPTR, QPR:v2i64:$src)
- // Emits: (VQMOVNsuv2i32:v2i32 QPR:v2i64:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(71)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_222(N, ARM::VQMOVNsuv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
}
+ case 12: { // Predicate_so_imm_neg
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_233(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N31)->getZExtValue()), MVT::i32);
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N2, N30, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_234(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N21)->getZExtValue()), MVT::i32);
- SDValue Tmp5 = Transform_DSubReg_i32_reg(Tmp4.getNode());
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N20, Tmp5), 0);
- SDValue Tmp7 = Transform_SubReg_i32_lane(Tmp4.getNode());
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N1, Tmp6, Tmp7, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-DISABLE_INLINE SDNode *Emit_235(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N31)->getZExtValue()), MVT::i32);
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N2, N1, N30, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_236(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- SDValue Tmp5 = Transform_DSubReg_i32_reg(Tmp4.getNode());
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N10, Tmp5), 0);
- SDValue Tmp7 = Transform_SubReg_i32_lane(Tmp4.getNode());
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N2, Tmp6, Tmp7, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 68:iPTR, QPR:v4i32:$src1, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
- // Emits: (VQDMULHslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32 &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_226(N, ARM::VQDMULHslv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 74:iPTR, QPR:v4i32:$src1, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
- // Emits: (VQRDMULHslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32 &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_226(N, ARM::VQRDMULHslv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 51:iPTR, DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
- // Emits: (VMULLslsv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(51)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16 &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_226(N, ARM::VMULLslsv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 52:iPTR, DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
- // Emits: (VMULLsluv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(52)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16 &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_226(N, ARM::VMULLsluv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 69:iPTR, DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
- // Emits: (VQDMULLslv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(69)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16 &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_226(N, ARM::VQDMULLslv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 43:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
- // Emits: (VMLALslsv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(43)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16 &&
- N30.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_233(N, ARM::VMLALslsv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 44:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
- // Emits: (VMLALsluv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(44)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16 &&
- N30.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_233(N, ARM::VMLALsluv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 66:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
- // Emits: (VQDMLALslv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(66)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16 &&
- N30.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_233(N, ARM::VQDMLALslv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 45:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
- // Emits: (VMLSLslsv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(45)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16 &&
- N30.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_233(N, ARM::VMLSLslsv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 46:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
- // Emits: (VMLSLsluv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(46)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16 &&
- N30.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_233(N, ARM::VMLSLsluv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 67:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
- // Emits: (VQDMLSLslv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(67)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16 &&
- N30.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_233(N, ARM::VQDMLSLslv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 68:iPTR, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
- // Emits: (VQDMULHslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N10.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_227(N, ARM::VQDMULHslv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 74:iPTR, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
- // Emits: (VQRDMULHslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N10.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_227(N, ARM::VQRDMULHslv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 51:iPTR, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
- // Emits: (VMULLslsv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(51)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N10.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_227(N, ARM::VMULLslsv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 52:iPTR, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
- // Emits: (VMULLsluv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(52)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N10.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_227(N, ARM::VMULLsluv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 69:iPTR, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
- // Emits: (VQDMULLslv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(69)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N10.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_227(N, ARM::VQDMULLslv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 43:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
- // Emits: (VMLALslsv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(43)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i16 &&
- N30.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_235(N, ARM::VMLALslsv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 44:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
- // Emits: (VMLALsluv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(44)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i16 &&
- N30.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_235(N, ARM::VMLALsluv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 66:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
- // Emits: (VQDMLALslv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(66)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i16 &&
- N30.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_235(N, ARM::VQDMLALslv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 45:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
- // Emits: (VMLSLslsv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(45)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i16 &&
- N30.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_235(N, ARM::VMLSLslsv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 46:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
- // Emits: (VMLSLsluv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(46)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i16 &&
- N30.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_235(N, ARM::VMLSLsluv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 67:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane))
- // Emits: (VQDMLSLslv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(67)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i16 &&
- N30.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_235(N, ARM::VQDMLSLslv4i16, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 68:iPTR, QPR:v4i32:$src1, (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane))
- // Emits: (VQDMULHslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 14 cost = 2 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32 &&
- N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_234(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQDMULHslv4i32, MVT::v2i32, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 74:iPTR, QPR:v4i32:$src1, (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane))
- // Emits: (VQRDMULHslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 14 cost = 2 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32 &&
- N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_234(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQRDMULHslv4i32, MVT::v2i32, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 68:iPTR, (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
- // Emits: (VQDMULHslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 14 cost = 2 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N10.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_236(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQDMULHslv4i32, MVT::v2i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 74:iPTR, (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
- // Emits: (VQRDMULHslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 14 cost = 2 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N10.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_236(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQRDMULHslv4i32, MVT::v2i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 24:iPTR, QPR:v4f32:$src, (imm:i32):$SIMM)
- // Emits: (VCVTf2xsq:v4i32 QPR:v4f32:$src, (imm:i32):$SIMM)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(24)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_232(N, ARM::VCVTf2xsq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 25:iPTR, QPR:v4f32:$src, (imm:i32):$SIMM)
- // Emits: (VCVTf2xuq:v4i32 QPR:v4f32:$src, (imm:i32):$SIMM)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(25)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_232(N, ARM::VCVTf2xuq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 17:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VADDLsv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(17)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VADDLsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 18:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VADDLuv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(18)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VADDLuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 19:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2)
- // Emits: (VADDWsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(19)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VADDWsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 20:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2)
- // Emits: (VADDWuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(20)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VADDWuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 28:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VHADDsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(28)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VHADDsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 29:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VHADDuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(29)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VHADDuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 91:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VRHADDsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(91)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VRHADDsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 92:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VRHADDuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(92)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VRHADDuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 64:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VQADDsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(64)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VQADDsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 65:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VQADDuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(65)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VQADDuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 68:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VQDMULHv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(68)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VQDMULHv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 74:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VQRDMULHv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(74)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VQRDMULHv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 51:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VMULLsv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(51)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VMULLsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 52:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VMULLuv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(52)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VMULLuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 69:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VQDMULLv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(69)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VQDMULLv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 43:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Emits: (VMLALsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(43)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_221(N, ARM::VMLALsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 44:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Emits: (VMLALuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(44)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_221(N, ARM::VMLALuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 66:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Emits: (VQDMLALv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(66)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_221(N, ARM::VQDMLALv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 45:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Emits: (VMLSLsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(45)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_221(N, ARM::VMLSLsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 46:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Emits: (VMLSLuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(46)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_221(N, ARM::VMLSLuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 67:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Emits: (VQDMLSLv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(67)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_221(N, ARM::VQDMLSLv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 113:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VSUBLsv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(113)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VSUBLsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 114:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VSUBLuv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(114)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VSUBLuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 115:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2)
- // Emits: (VSUBWsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(115)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VSUBWsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 116:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2)
- // Emits: (VSUBWuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(116)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VSUBWuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 30:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VHSUBsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(30)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VHSUBsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 31:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VHSUBuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(31)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VHSUBuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 86:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VQSUBsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(86)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VQSUBsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 87:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VQSUBuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(87)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VQSUBuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 13:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VACGEq:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_220(N, ARM::VACGEq, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 15:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VACGTq:v4i32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_220(N, ARM::VACGTq, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 9:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VABDsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(9)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VABDsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 10:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VABDuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(10)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VABDuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 7:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VABDLsv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(7)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VABDLsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 8:iPTR, DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VABDLuv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_220(N, ARM::VABDLuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 5:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Emits: (VABAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(5)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_221(N, ARM::VABAsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 6:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Emits: (VABAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(6)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_221(N, ARM::VABAuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 3:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Emits: (VABALsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(3)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_221(N, ARM::VABALsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 4:iPTR, QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Emits: (VABALuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(4)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i16 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_221(N, ARM::VABALuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 39:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VMAXsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(39)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VMAXsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 40:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VMAXuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(40)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VMAXuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 41:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VMINsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(41)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VMINsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 42:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VMINuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(42)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VMINuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 57:iPTR, QPR:v8i16:$src)
- // Emits: (VPADDLsv8i16:v4i32 QPR:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(57)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_222(N, ARM::VPADDLsv8i16, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 58:iPTR, QPR:v8i16:$src)
- // Emits: (VPADDLuv8i16:v4i32 QPR:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(58)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_222(N, ARM::VPADDLuv8i16, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 54:iPTR, QPR:v4i32:$src1, QPR:v8i16:$src2)
- // Emits: (VPADALsv8i16:v4i32 QPR:v4i32:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(54)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VPADALsv8i16, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 55:iPTR, QPR:v4i32:$src1, QPR:v8i16:$src2)
- // Emits: (VPADALuv8i16:v4i32 QPR:v4i32:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(55)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_220(N, ARM::VPADALuv8i16, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 89:iPTR, QPR:v4i32:$src)
- // Emits: (VRECPEq:v4i32 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(89)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VRECPEq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 96:iPTR, QPR:v4i32:$src)
- // Emits: (VRSQRTEq:v4i32 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(96)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VRSQRTEq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 103:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VSHLsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(103)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VSHLsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 104:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VSHLuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(104)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VSHLuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 94:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VRSHLsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(94)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VRSHLsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 95:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VRSHLuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(95)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VRSHLuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 83:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VQSHLsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(83)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VQSHLsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 85:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VQSHLuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(85)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VQSHLuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 78:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VQRSHLsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(78)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 79:iPTR, QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VQRSHLuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(79)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i32 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 11:iPTR, QPR:v4i32:$src)
- // Emits: (VABSv4i32:v4i32 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(11)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VABSv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 63:iPTR, QPR:v4i32:$src)
- // Emits: (VQABSv4i32:v4i32 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(63)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VQABSv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 73:iPTR, QPR:v4i32:$src)
- // Emits: (VQNEGv4i32:v4i32 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(73)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VQNEGv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 21:iPTR, QPR:v4i32:$src)
- // Emits: (VCLSv4i32:v4i32 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(21)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VCLSv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 22:iPTR, QPR:v4i32:$src)
- // Emits: (VCLZv4i32:v4i32 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(22)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VCLZv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 47:iPTR, DPR:v4i16:$src)
- // Emits: (VMOVLsv4i32:v4i32 DPR:v4i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(47)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_222(N, ARM::VMOVLsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 48:iPTR, DPR:v4i16:$src)
- // Emits: (VMOVLuv4i32:v4i32 DPR:v4i16:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(48)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_222(N, ARM::VMOVLuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 19:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1)
- // Emits: (VADDWsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(19)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_229(N, ARM::VADDWsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 20:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1)
- // Emits: (VADDWuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(20)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_229(N, ARM::VADDWuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 43:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, DPR:v4i16:$src3)
- // Emits: (VMLALsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(43)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_230(N, ARM::VMLALsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 44:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, DPR:v4i16:$src3)
- // Emits: (VMLALuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(44)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_230(N, ARM::VMLALuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 66:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, DPR:v4i16:$src3)
- // Emits: (VQDMLALv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(66)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_230(N, ARM::VQDMLALv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 45:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, DPR:v4i16:$src3)
- // Emits: (VMLSLsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(45)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_230(N, ARM::VMLSLsv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 46:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, DPR:v4i16:$src3)
- // Emits: (VMLSLuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(46)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_230(N, ARM::VMLSLuv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 67:iPTR, DPR:v4i16:$src2, QPR:v4i32:$src1, DPR:v4i16:$src3)
- // Emits: (VQDMLSLv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(67)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v4i16 &&
- N2.getValueType() == MVT::v4i32 &&
- N3.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_230(N, ARM::VQDMLSLv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
+ return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
+
}
+ case 13: { // Predicate_imm0_7
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
+ return (uint32_t)N->getZExtValue() < 8;
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v1i64 64:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VQADDsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(64)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_220(N, ARM::VQADDsv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 65:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VQADDuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(65)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_220(N, ARM::VQADDuv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 86:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VQSUBsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(86)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_220(N, ARM::VQSUBsv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 87:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VQSUBuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(87)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_220(N, ARM::VQSUBuv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 57:iPTR, DPR:v2i32:$src)
- // Emits: (VPADDLsv2i32:v1i64 DPR:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(57)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_222(N, ARM::VPADDLsv2i32, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 58:iPTR, DPR:v2i32:$src)
- // Emits: (VPADDLuv2i32:v1i64 DPR:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(58)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_222(N, ARM::VPADDLuv2i32, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 54:iPTR, DPR:v1i64:$src1, DPR:v2i32:$src2)
- // Emits: (VPADALsv2i32:v1i64 DPR:v1i64:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(54)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VPADALsv2i32, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 55:iPTR, DPR:v1i64:$src1, DPR:v2i32:$src2)
- // Emits: (VPADALuv2i32:v1i64 DPR:v1i64:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(55)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VPADALuv2i32, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 103:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VSHLsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(103)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_220(N, ARM::VSHLsv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 104:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VSHLuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(104)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_220(N, ARM::VSHLuv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 94:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VRSHLsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(94)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_220(N, ARM::VRSHLsv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 95:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VRSHLuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(95)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_220(N, ARM::VRSHLuv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 83:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VQSHLsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(83)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_220(N, ARM::VQSHLsv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 85:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VQSHLuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(85)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_220(N, ARM::VQSHLuv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 78:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VQRSHLsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(78)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLsv1i64, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 79:iPTR, DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Emits: (VQRSHLuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(79)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v1i64 &&
- N2.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLuv1i64, MVT::v1i64);
- return Result;
- }
- }
- }
}
+ case 14: { // Predicate_imm8_255
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
+ return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i64 51:iPTR, DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
- // Emits: (VMULLslsv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(51)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32 &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_226(N, ARM::VMULLslsv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 52:iPTR, DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
- // Emits: (VMULLsluv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(52)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32 &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_226(N, ARM::VMULLsluv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 69:iPTR, DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
- // Emits: (VQDMULLslv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(69)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- if (N21.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32 &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_226(N, ARM::VQDMULLslv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 43:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
- // Emits: (VMLALslsv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(43)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32 &&
- N30.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_233(N, ARM::VMLALslsv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 44:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
- // Emits: (VMLALsluv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(44)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32 &&
- N30.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_233(N, ARM::VMLALsluv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 66:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
- // Emits: (VQDMLALslv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(66)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32 &&
- N30.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_233(N, ARM::VQDMLALslv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 45:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
- // Emits: (VMLSLslsv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(45)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32 &&
- N30.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_233(N, ARM::VMLSLslsv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 46:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
- // Emits: (VMLSLsluv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(46)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32 &&
- N30.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_233(N, ARM::VMLSLsluv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 67:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
- // Emits: (VQDMLSLslv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(67)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32 &&
- N30.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_233(N, ARM::VQDMLSLslv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 51:iPTR, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
- // Emits: (VMULLslsv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(51)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N10.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_227(N, ARM::VMULLslsv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 52:iPTR, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
- // Emits: (VMULLsluv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(52)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N10.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_227(N, ARM::VMULLsluv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 69:iPTR, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
- // Emits: (VQDMULLslv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(69)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N10.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_227(N, ARM::VQDMULLslv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 43:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
- // Emits: (VMLALslsv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(43)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64 &&
- N3.getValueType() == MVT::v2i32 &&
- N30.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_235(N, ARM::VMLALslsv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 44:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
- // Emits: (VMLALsluv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(44)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64 &&
- N3.getValueType() == MVT::v2i32 &&
- N30.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_235(N, ARM::VMLALsluv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 66:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
- // Emits: (VQDMLALslv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(66)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64 &&
- N3.getValueType() == MVT::v2i32 &&
- N30.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_235(N, ARM::VQDMLALslv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 45:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
- // Emits: (VMLSLslsv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(45)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64 &&
- N3.getValueType() == MVT::v2i32 &&
- N30.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_235(N, ARM::VMLSLslsv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 46:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
- // Emits: (VMLSLsluv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(46)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64 &&
- N3.getValueType() == MVT::v2i32 &&
- N30.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_235(N, ARM::VMLSLsluv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 67:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane))
- // Emits: (VQDMLSLslv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 14 cost = 1 size = 0
- if (CN1 == INT64_C(67)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- if (N31.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64 &&
- N3.getValueType() == MVT::v2i32 &&
- N30.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_235(N, ARM::VQDMLSLslv2i32, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 17:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VADDLsv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(17)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VADDLsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 18:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VADDLuv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(18)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VADDLuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 19:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2)
- // Emits: (VADDWsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(19)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VADDWsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 20:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2)
- // Emits: (VADDWuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(20)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VADDWuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 64:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VQADDsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(64)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VQADDsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 65:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VQADDuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(65)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VQADDuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 51:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VMULLsv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(51)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VMULLsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 52:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VMULLuv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(52)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VMULLuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 69:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VQDMULLv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(69)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VQDMULLv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 43:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Emits: (VMLALsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(43)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_221(N, ARM::VMLALsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 44:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Emits: (VMLALuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(44)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_221(N, ARM::VMLALuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 66:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Emits: (VQDMLALv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(66)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_221(N, ARM::VQDMLALv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 45:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Emits: (VMLSLsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(45)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_221(N, ARM::VMLSLsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 46:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Emits: (VMLSLuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(46)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_221(N, ARM::VMLSLuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 67:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Emits: (VQDMLSLv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(67)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_221(N, ARM::VQDMLSLv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 113:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VSUBLsv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(113)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VSUBLsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 114:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VSUBLuv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(114)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VSUBLuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 115:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2)
- // Emits: (VSUBWsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(115)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VSUBWsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 116:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2)
- // Emits: (VSUBWuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(116)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VSUBWuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 86:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VQSUBsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(86)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VQSUBsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 87:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VQSUBuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(87)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VQSUBuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 7:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VABDLsv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(7)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VABDLsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 8:iPTR, DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VABDLuv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_220(N, ARM::VABDLuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 3:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Emits: (VABALsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(3)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_221(N, ARM::VABALsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 4:iPTR, QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Emits: (VABALuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(4)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i32 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_221(N, ARM::VABALuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 57:iPTR, QPR:v4i32:$src)
- // Emits: (VPADDLsv4i32:v2i64 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(57)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VPADDLsv4i32, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 58:iPTR, QPR:v4i32:$src)
- // Emits: (VPADDLuv4i32:v2i64 QPR:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(58)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_222(N, ARM::VPADDLuv4i32, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 54:iPTR, QPR:v2i64:$src1, QPR:v4i32:$src2)
- // Emits: (VPADALsv4i32:v2i64 QPR:v2i64:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(54)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VPADALsv4i32, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 55:iPTR, QPR:v2i64:$src1, QPR:v4i32:$src2)
- // Emits: (VPADALuv4i32:v2i64 QPR:v2i64:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(55)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_220(N, ARM::VPADALuv4i32, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 103:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VSHLsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(103)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VSHLsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 104:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VSHLuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(104)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VSHLuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 94:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VRSHLsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(94)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VRSHLsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 95:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VRSHLuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(95)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VRSHLuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 83:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VQSHLsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(83)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VQSHLsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 85:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VQSHLuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(85)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VQSHLuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 78:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VQRSHLsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(78)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 79:iPTR, QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Emits: (VQRSHLuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(79)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i64 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_220(N, ARM::VQRSHLuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 47:iPTR, DPR:v2i32:$src)
- // Emits: (VMOVLsv2i64:v2i64 DPR:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(47)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_222(N, ARM::VMOVLsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 48:iPTR, DPR:v2i32:$src)
- // Emits: (VMOVLuv2i64:v2i64 DPR:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(48)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_222(N, ARM::VMOVLuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 19:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1)
- // Emits: (VADDWsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(19)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_229(N, ARM::VADDWsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 20:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1)
- // Emits: (VADDWuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(20)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_229(N, ARM::VADDWuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 43:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, DPR:v2i32:$src3)
- // Emits: (VMLALsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(43)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_230(N, ARM::VMLALsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 44:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, DPR:v2i32:$src3)
- // Emits: (VMLALuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(44)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_230(N, ARM::VMLALuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 66:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, DPR:v2i32:$src3)
- // Emits: (VQDMLALv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(66)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_230(N, ARM::VQDMLALv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 45:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, DPR:v2i32:$src3)
- // Emits: (VMLSLsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(45)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_230(N, ARM::VMLSLsv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 46:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, DPR:v2i32:$src3)
- // Emits: (VMLSLuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(46)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_230(N, ARM::VMLSLuv2i64, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 67:iPTR, DPR:v2i32:$src2, QPR:v2i64:$src1, DPR:v2i32:$src3)
- // Emits: (VQDMLSLv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(67)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N1.getValueType() == MVT::v2i32 &&
- N2.getValueType() == MVT::v2i64 &&
- N3.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_230(N, ARM::VQDMLSLv2i64, MVT::v2i64);
- return Result;
- }
- }
- }
}
+ case 15: { // Predicate_imm0_7_neg
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
+ return (uint32_t)-N->getZExtValue() < 8;
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2f32 26:iPTR, DPR:v2i32:$src, (imm:i32):$SIMM)
- // Emits: (VCVTxs2fd:v2f32 DPR:v2i32:$src, (imm:i32):$SIMM)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(26)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_232(N, ARM::VCVTxs2fd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f32 27:iPTR, DPR:v2i32:$src, (imm:i32):$SIMM)
- // Emits: (VCVTxu2fd:v2f32 DPR:v2i32:$src, (imm:i32):$SIMM)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(27)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_232(N, ARM::VCVTxu2fd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f32 9:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VABDfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(9)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2f32 &&
- N2.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_220(N, ARM::VABDfd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f32 39:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VMAXfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(39)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2f32 &&
- N2.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_220(N, ARM::VMAXfd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f32 41:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VMINfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(41)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2f32 &&
- N2.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_220(N, ARM::VMINfd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f32 56:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VPADDf:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(56)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2f32 &&
- N2.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_220(N, ARM::VPADDf, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f32 59:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VPMAXf:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(59)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2f32 &&
- N2.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_220(N, ARM::VPMAXf, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f32 61:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VPMINf:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(61)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2f32 &&
- N2.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_220(N, ARM::VPMINf, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f32 89:iPTR, DPR:v2f32:$src)
- // Emits: (VRECPEfd:v2f32 DPR:v2f32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(89)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_222(N, ARM::VRECPEfd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f32 90:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VRECPSfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(90)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2f32 &&
- N2.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_220(N, ARM::VRECPSfd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f32 96:iPTR, DPR:v2f32:$src)
- // Emits: (VRSQRTEfd:v2f32 DPR:v2f32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(96)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_222(N, ARM::VRSQRTEfd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f32 97:iPTR, DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Emits: (VRSQRTSfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(97)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v2f32 &&
- N2.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_220(N, ARM::VRSQRTSfd, MVT::v2f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f32 11:iPTR, DPR:v2f32:$src)
- // Emits: (VABSfd:v2f32 DPR:v2f32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(11)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_222(N, ARM::VABSfd, MVT::v2f32);
- return Result;
- }
- }
- }
}
+ case 16: { // Predicate_imm8_255_neg
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
+ unsigned Val = -N->getZExtValue();
+ return Val >= 8 && Val < 256;
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 26:iPTR, QPR:v4i32:$src, (imm:i32):$SIMM)
- // Emits: (VCVTxs2fq:v4f32 QPR:v4i32:$src, (imm:i32):$SIMM)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(26)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_232(N, ARM::VCVTxs2fq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 27:iPTR, QPR:v4i32:$src, (imm:i32):$SIMM)
- // Emits: (VCVTxu2fq:v4f32 QPR:v4i32:$src, (imm:i32):$SIMM)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(27)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_232(N, ARM::VCVTxu2fq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 9:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VABDfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(9)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4f32 &&
- N2.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_220(N, ARM::VABDfq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 39:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VMAXfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(39)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4f32 &&
- N2.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_220(N, ARM::VMAXfq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 41:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VMINfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(41)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4f32 &&
- N2.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_220(N, ARM::VMINfq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 89:iPTR, QPR:v4f32:$src)
- // Emits: (VRECPEfq:v4f32 QPR:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(89)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_222(N, ARM::VRECPEfq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 90:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VRECPSfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(90)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4f32 &&
- N2.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_220(N, ARM::VRECPSfq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 96:iPTR, QPR:v4f32:$src)
- // Emits: (VRSQRTEfq:v4f32 QPR:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(96)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_222(N, ARM::VRSQRTEfq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 97:iPTR, QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Emits: (VRSQRTSfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(97)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1.getValueType() == MVT::v4f32 &&
- N2.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_220(N, ARM::VRSQRTSfq, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 11:iPTR, QPR:v4f32:$src)
- // Emits: (VABSfq:v4f32 QPR:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(11)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_222(N, ARM::VABSfq, MVT::v4f32);
- return Result;
- }
- }
- }
}
+ case 17: { // Predicate_imm0_4095
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
+ return (uint32_t)N->getZExtValue() < 4096;
-DISABLE_INLINE SDNode *Emit_237(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, Tmp3, Tmp4, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
-}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_237(N, ARM::VLD1d8, MVT::v8i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
- }
- }
}
+ case 18: { // Predicate_t2_so_imm_neg
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
+ return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_237(N, ARM::VLD1q8, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
- }
- }
}
+ case 19: { // Predicate_imm0_4095_neg
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
+ return (uint32_t)(-N->getZExtValue()) < 4096;
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_237(N, ARM::VLD1d16, MVT::v4i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
- }
- }
}
+ case 20: { // Predicate_so_neg_imm2part
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_237(N, ARM::VLD1q16, MVT::v8i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
- }
- }
+ return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
+
}
+ case 21: { // Predicate_t2_so_neg_imm2part
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_237(N, ARM::VLD1d32, MVT::v2i32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
- }
- }
+ return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
+
}
+ case 22: { // Predicate_bf_inv_mask_imm
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_237(N, ARM::VLD1q32, MVT::v4i32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
- }
- }
+ uint32_t v = (uint32_t)N->getZExtValue();
+ if (v == 0xffffffff)
+ return 0;
+ // there can be 1's on either or both "outsides", all the "inside"
+ // bits must be 0's
+ unsigned int lsb = 0, msb = 31;
+ while (v & (1 << msb)) --msb;
+ while (v & (1 << lsb)) ++lsb;
+ for (unsigned int i = lsb; i <= msb; ++i) {
+ if (v & (1 << i))
+ return 0;
}
+ return 1;
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_237(N, ARM::VLD1d64, MVT::v1i64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
- }
- }
}
+ case 23: { // Predicate_so_imm_not
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_237(N, ARM::VLD1q64, MVT::v2i64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
- }
- }
+ return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
+
}
+ case 24: { // Predicate_imm1_31
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
+ return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_237(N, ARM::VLD1df, MVT::v2f32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
- }
- }
}
+ case 25: { // Predicate_unindexedload
+ SDNode *N = Node;
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_237(N, ARM::VLD1qf, MVT::v4f32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3);
- return Result;
- }
- }
- }
}
+ case 26: { // Predicate_load
+ SDNode *N = Node;
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_238(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, Tmp1, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 5);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_239(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp1, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_240(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { N10, Tmp1, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 4);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_241(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp1, Tmp2, Chain };
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
- Chain = SDValue(Tmp3.getNode(), 1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
- MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
- SDNode *ResNode = CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp3, Tmp4, Tmp5);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
- ReplaceUses(SDValue(N, 1), Chain);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_242(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp1 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp3, Tmp4, Chain };
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
- Chain = SDValue(Tmp5.getNode(), 1);
- SDValue Tmp6 = CurDAG->getTargetConstant(0x18ULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp1, Tmp5, Tmp6, Tmp7, Tmp8 };
- SDValue Tmp9(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Ops1, 5), 0);
- SDValue Tmp10 = CurDAG->getTargetConstant(0x18ULL, MVT::i32);
- SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
- MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
- MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops2[] = { Tmp0, Tmp9, Tmp10, Tmp11, Tmp12 };
- SDNode *ResNode = CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Ops2, 5);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
- ReplaceUses(SDValue(N, 1), Chain);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_243(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp1 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp3, Tmp4, Chain };
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
- Chain = SDValue(Tmp5.getNode(), 1);
- SDValue Tmp6 = CurDAG->getTargetConstant(0x10ULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp1, Tmp5, Tmp6, Tmp7, Tmp8 };
- SDValue Tmp9(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Ops1, 5), 0);
- SDValue Tmp10 = CurDAG->getTargetConstant(0x10ULL, MVT::i32);
- SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
- MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
- MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops2[] = { Tmp0, Tmp9, Tmp10, Tmp11, Tmp12 };
- SDNode *ResNode = CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Ops2, 5);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
- ReplaceUses(SDValue(N, 1), Chain);
- return ResNode;
-}
-SDNode *Select_ISD_LOAD_i32(SDNode *N) {
- if ((!Subtarget->isThumb())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (PICLDR:i32 addrmodepc:i32:$addr)
- // Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::PICLDR, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_zextload(N)) {
-
- // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (PICLDRH:i32 addrmodepc:i32:$addr)
- // Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::PICLDRH, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (PICLDRB:i32 addrmodepc:i32:$addr)
- // Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::PICLDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- }
- if (Predicate_sextload(N)) {
-
- // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (PICLDRSH:i32 addrmodepc:i32:$addr)
- // Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::PICLDRSH, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
- // Emits: (PICLDRSB:i32 addrmodepc:i32:$addr)
- // Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_sextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::PICLDRSB, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_sextload(N)) {
-
- // Pattern: (ld:i32 t_addrmode_rr:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
- // Emits: (tLDRSB:i32 t_addrmode_rr:i32:$addr)
- // Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_sextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectThumbAddrModeRR(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::tLDRSB, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 t_addrmode_rr:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (tLDRSH:i32 t_addrmode_rr:i32:$addr)
- // Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectThumbAddrModeRR(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::tLDRSH, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (LDR:i32 addrmode2:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectAddrMode2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::LDR, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- if (Predicate_zextload(N)) {
-
- // Pattern: (ld:i32 addrmode3:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (LDRH:i32 addrmode3:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectAddrMode3(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::LDRH, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (LDRB:i32 addrmode2:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectAddrMode2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::LDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- }
- if (Predicate_sextload(N)) {
-
- // Pattern: (ld:i32 addrmode3:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (LDRSH:i32 addrmode3:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectAddrMode3(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::LDRSH, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addrmode3:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
- // Emits: (LDRSB:i32 addrmode3:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_sextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectAddrMode3(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::LDRSB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:i32 t_addrmode_s4:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (tLDR:i32 t_addrmode_s4:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectThumbAddrModeS4(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::tLDR, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- if (Predicate_zextload(N)) {
-
- // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (tLDRB:i32 t_addrmode_s1:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::tLDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 t_addrmode_s2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (tLDRH:i32 t_addrmode_s2:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectThumbAddrModeS2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::tLDRH, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (t2LDRs:i32 t2addrmode_so_reg:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::t2LDRs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- if (Predicate_zextload(N)) {
-
- // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (t2LDRHs:i32 t2addrmode_so_reg:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::t2LDRHs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (t2LDRBs:i32 t2addrmode_so_reg:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::t2LDRBs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- }
- if (Predicate_sextload(N)) {
-
- // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (t2LDRSHs:i32 t2addrmode_so_reg:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::t2LDRSHs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
- // Emits: (t2LDRSBs:i32 t2addrmode_so_reg:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_sextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::t2LDRSBs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (tLDRB:i32 t_addrmode_s1:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextload(N) &&
- Predicate_zextloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::tLDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- if (Predicate_extload(N)) {
-
- // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (tLDRB:i32 t_addrmode_s1:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::tLDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (tLDRB:i32 t_addrmode_s1:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::tLDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 t_addrmode_s2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (tLDRH:i32 t_addrmode_s2:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectThumbAddrModeS2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::tLDRH, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (t2LDRBs:i32 t2addrmode_so_reg:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextload(N) &&
- Predicate_zextloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::t2LDRBs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- if (Predicate_extload(N)) {
-
- // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (t2LDRBs:i32 t2addrmode_so_reg:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::t2LDRBs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (t2LDRBs:i32 t2addrmode_so_reg:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::t2LDRBs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (t2LDRHs:i32 t2addrmode_so_reg:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectT2AddrModeSoReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::t2LDRHs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (LDRB:i32 addrmode2:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextload(N) &&
- Predicate_zextloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectAddrMode2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::LDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- if (Predicate_extload(N)) {
-
- // Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (LDRB:i32 addrmode2:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectAddrMode2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::LDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (LDRB:i32 addrmode2:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectAddrMode2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::LDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addrmode3:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (LDRH:i32 addrmode3:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectAddrMode3(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_239(N, ARM::LDRH, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_sextload(N)) {
-
- // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
- // Emits: (tSXTB:i32 (tLDRB:i32 t_addrmode_s1:i32:$addr))
- // Pattern complexity = 16 cost = 2 size = 0
- if (Predicate_sextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_241(N, ARM::tLDRB, ARM::tSXTB, MVT::i32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 t_addrmode_s2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (tSXTH:i32 (tLDRH:i32 t_addrmode_s2:i32:$addr))
- // Pattern complexity = 16 cost = 2 size = 0
- if (Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectThumbAddrModeS2(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_241(N, ARM::tLDRH, ARM::tSXTH, MVT::i32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
- if (Predicate_sextload(N)) {
-
- // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
- // Emits: (tASRri:i32 (tLSLri:i32 (tLDRB:i32 t_addrmode_s1:i32:$addr), 24:i32), 24:i32)
- // Pattern complexity = 16 cost = 3 size = 0
- if (Predicate_sextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_242(N, ARM::tLDRB, ARM::tLSLri, ARM::tASRri, MVT::i32, MVT::i32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (tASRri:i32 (tLSLri:i32 (tLDRH:i32 t_addrmode_s1:i32:$addr), 16:i32), 16:i32)
- // Pattern complexity = 16 cost = 3 size = 0
- if (Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectThumbAddrModeS1(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_243(N, ARM::tLDRH, ARM::tLSLri, ARM::tASRri, MVT::i32, MVT::i32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- }
-
- // Pattern: (ld:i32 t_addrmode_sp:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (tLDRspi:i32 t_addrmode_sp:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectThumbAddrModeSP(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::tLDRspi, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
- if (Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (t2LDRi12:i32 t2addrmode_imm12:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (t2LDRi8:i32 t2addrmode_imm8:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_zextload(N)) {
- if (Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (t2LDRHi12:i32 t2addrmode_imm12:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRHi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (t2LDRHi8:i32 t2addrmode_imm8:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRHi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (t2LDRBi12:i32 t2addrmode_imm12:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRBi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (t2LDRBi8:i32 t2addrmode_imm8:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRBi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- }
- if (Predicate_sextload(N)) {
- if (Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (t2LDRSHi12:i32 t2addrmode_imm12:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRSHi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (t2LDRSHi8:i32 t2addrmode_imm8:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRSHi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_sextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
- // Emits: (t2LDRSBi12:i32 t2addrmode_imm12:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRSBi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
- // Emits: (t2LDRSBi8:i32 t2addrmode_imm8:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRSBi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- }
- if (Predicate_zextload(N) &&
- Predicate_zextloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (t2LDRBi12:i32 t2addrmode_imm12:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRBi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (t2LDRBi8:i32 t2addrmode_imm8:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRBi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_extload(N)) {
- if (Predicate_extloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (t2LDRBi12:i32 t2addrmode_imm12:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRBi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (t2LDRBi8:i32 t2addrmode_imm8:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRBi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_extloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (t2LDRBi12:i32 t2addrmode_imm12:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRBi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (t2LDRBi8:i32 t2addrmode_imm8:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRBi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_extloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (t2LDRHi12:i32 t2addrmode_imm12:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm12(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRHi12, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (t2LDRHi8:i32 t2addrmode_imm8:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm8(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::t2LDRHi8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_extload(N)) {
-
- // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (PICLDRB:i32 addrmodepc:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_extloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::PICLDRB, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (PICLDRH:i32 addrmodepc:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_extloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::PICLDRH, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- }
- }
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
- // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (tLDRpci:i32 (tconstpool:i32):$addr)
- // Pattern complexity = 10 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_240(N, ARM::tLDRpci, MVT::i32);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (t2LDRpci:i32 (tconstpool:i32):$addr)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_240(N, ARM::t2LDRpci, MVT::i32);
- return Result;
- }
- }
- }
- if (Predicate_zextload(N)) {
-
- // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (t2LDRHpci:i32 (tconstpool:i32):$addr)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_240(N, ARM::t2LDRHpci, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (t2LDRBpci:i32 (tconstpool:i32):$addr)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_240(N, ARM::t2LDRBpci, MVT::i32);
- return Result;
- }
- }
- }
- }
- if (Predicate_sextload(N)) {
-
- // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (t2LDRSHpci:i32 (tconstpool:i32):$addr)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_240(N, ARM::t2LDRSHpci, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
- // Emits: (t2LDRSBpci:i32 (tconstpool:i32):$addr)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_sextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_240(N, ARM::t2LDRSBpci, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (t2LDRBpci:i32 (tconstpool:i32):$addr)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_zextload(N) &&
- Predicate_zextloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_240(N, ARM::t2LDRBpci, MVT::i32);
- return Result;
- }
- }
- }
- if (Predicate_extload(N)) {
-
- // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (t2LDRBpci:i32 (tconstpool:i32):$addr)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_extloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_240(N, ARM::t2LDRBpci, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (t2LDRBpci:i32 (tconstpool:i32):$addr)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_extloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_240(N, ARM::t2LDRBpci, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (t2LDRHpci:i32 (tconstpool:i32):$addr)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_extloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_240(N, ARM::t2LDRHpci, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
}
+ case 27: { // Predicate_zextload
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
-SDNode *Select_ISD_LOAD_f32(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrMode5(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::VLDRS, MVT::f32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
}
+ case 28: { // Predicate_zextloadi16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
-SDNode *Select_ISD_LOAD_f64(SDNode *N) {
- if ((Subtarget->hasVFP2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrMode5(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::VLDRD, MVT::f64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
}
+ case 29: { // Predicate_zextloadi8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
-SDNode *Select_ISD_LOAD_v2f64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrMode4(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_238(N, ARM::VLDRQ, MVT::v2f64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
}
+ case 30: { // Predicate_sextload
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
-DISABLE_INLINE SDNode *Emit_244(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N10, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_245(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N10, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_246(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N10, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_247(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp10 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp11 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N100, Tmp10, Tmp11 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_248(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N10, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_249(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N10, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_250(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N100, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_251(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N1, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_252(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N10, N00, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_253(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N10, N00, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_254(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp10 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp11 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N100, N000, Tmp10, Tmp11 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_255(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N100, N00, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_256(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, N00, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_257(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N10, N000, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_258(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N10, N0, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ISD_MUL_i32(SDNode *N) {
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp6) {
- int64_t CN7 = Tmp6->getSExtValue();
- if (CN7 == INT64_C(16) &&
- N001.getValueType() == MVT::i32 &&
- N01.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
-
- // Pattern: (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32))
- // Emits: (SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 35 cost = 1 size = 0
- {
- SDNode *Result = Emit_247(N, ARM::SMULBB, MVT::i32);
- return Result;
- }
-
- // Pattern: (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32))
- // Emits: (SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 35 cost = 1 size = 0
- SDNode *Result = Emit_254(N, ARM::SMULBB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 GPR:i32:$b, 16:i32))
- // Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 27 cost = 1 size = 0
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16) &&
- N001.getValueType() == MVT::i32 &&
- N01.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_248(N, ARM::SMULBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16) &&
- N01.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
-
- // Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32))
- // Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 27 cost = 1 size = 0
- {
- SDNode *Result = Emit_250(N, ARM::SMULTB, MVT::i32);
- return Result;
- }
-
- // Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32))
- // Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 27 cost = 1 size = 0
- SDNode *Result = Emit_255(N, ARM::SMULBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 GPR:i32:$a, 16:i32))
- // Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 27 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16) &&
- N001.getValueType() == MVT::i32 &&
- N01.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_257(N, ARM::SMULTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32))
- // Emits: (SMULTT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 19 cost = 1 size = 0
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N01.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_246(N, ARM::SMULTT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
}
+ case 31: { // Predicate_sextloadi16
+ SDNode *N = Node;
- // Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32))
- // Emits: (t2SMULTT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 19 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N01.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_246(N, ARM::t2SMULTT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
- // Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32))
- // Emits: (SMULTT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 19 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N01.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_253(N, ARM::SMULTT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
}
+ case 32: { // Predicate_sextloadi8
+ SDNode *N = Node;
- // Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32))
- // Emits: (t2SMULTT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 19 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N01.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_253(N, ARM::t2SMULTT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32))
- // Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_245(N, ARM::SMULBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other))
- // Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_245(N, ARM::SMULTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32))
- // Emits: (t2SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_245(N, ARM::t2SMULBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other))
- // Emits: (t2SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_245(N, ARM::t2SMULTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other))
- // Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_252(N, ARM::SMULBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32))
- // Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_252(N, ARM::SMULTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other))
- // Emits: (t2SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_252(N, ARM::t2SMULBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32))
- // Emits: (t2SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_252(N, ARM::t2SMULTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, (sra:i32 GPR:i32:$b, 16:i32))
- // Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 12 cost = 1 size = 0
- if (Predicate_sext_16_node(N0.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_249(N, ARM::SMULBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (Predicate_sext_16_node(N1.getNode()) &&
- N01.getValueType() == MVT::i32) {
-
- // Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$b)
- // Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDNode *Result = Emit_251(N, ARM::SMULTB, MVT::i32);
- return Result;
- }
-
- // Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$a)
- // Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 12 cost = 1 size = 0
- SDNode *Result = Emit_256(N, ARM::SMULBT, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$b, (sra:i32 GPR:i32:$a, 16:i32))
- // Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 12 cost = 1 size = 0
- if (Predicate_sext_16_node(N0.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_258(N, ARM::SMULTB, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other))
- // Emits: (SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_244(N, ARM::SMULBB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
- // Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other))
- // Emits: (t2SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 9 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_244(N, ARM::t2SMULBB, MVT::i32);
- return Result;
- }
- }
- }
- }
}
+ case 33: { // Predicate_zextloadi1
+ SDNode *N = Node;
- // Pattern: (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b)
- // Emits: (SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 5 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- if (Predicate_sext_16_node(N0.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (Predicate_sext_16_node(N1.getNode())) {
- SDNode *Result = Emit_44(N, ARM::SMULBB, MVT::i32);
- return Result;
- }
- }
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
- // Pattern: (mul:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (MUL:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDNode *Result = Emit_56(N, ARM::MUL, MVT::i32);
- return Result;
}
+ case 34: { // Predicate_extload
+ SDNode *N = Node;
- // Pattern: (mul:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tMUL:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDNode *Result = Emit_66(N, ARM::tMUL, MVT::i32);
- return Result;
- }
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
- // Pattern: (mul:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (t2MUL:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_44(N, ARM::t2MUL, MVT::i32);
- return Result;
}
+ case 35: { // Predicate_extloadi1
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
-SDNode *Select_ISD_MUL_v8i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_44(N, ARM::VMULv8i8, MVT::v8i8);
- return Result;
}
+ case 36: { // Predicate_extloadi8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
-SDNode *Select_ISD_MUL_v16i8(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_44(N, ARM::VMULv16i8, MVT::v16i8);
- return Result;
}
+ case 37: { // Predicate_extloadi16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
-SDNode *Select_ISD_MUL_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:v4i16 DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
- // Emits: (VMULslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 9 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_126(N, ARM::VMULslv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
-
- // Pattern: (mul:v4i16 (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
- // Emits: (VMULslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_128(N, ARM::VMULslv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (mul:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VMULv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VMULv4i16, MVT::v4i16);
- return Result;
}
+ case 38: { // Predicate_unindexedstore
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_259(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_DSubReg_i16_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N10, Tmp3), 0);
- SDValue Tmp5 = Transform_SubReg_i16_lane(Tmp2.getNode());
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N0, Tmp4, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-DISABLE_INLINE SDNode *Emit_260(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_DSubReg_i16_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp3), 0);
- SDValue Tmp5 = Transform_SubReg_i16_lane(Tmp2.getNode());
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { N1, Tmp4, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-SDNode *Select_ISD_MUL_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:v8i16 QPR:v8i16:$src1, (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
- // Emits: (VMULslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 9 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_126(N, ARM::VMULslv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
-
- // Pattern: (mul:v8i16 (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
- // Emits: (VMULslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_128(N, ARM::VMULslv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:v8i16 QPR:v8i16:$src1, (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane))
- // Emits: (VMULslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 9 cost = 2 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_259(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
- return Result;
- }
- }
- }
-
- // Pattern: (mul:v8i16 (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
- // Emits: (VMULslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 9 cost = 2 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_260(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
+ return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
- // Pattern: (mul:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VMULv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_44(N, ARM::VMULv8i16, MVT::v8i16);
- return Result;
}
+ case 39: { // Predicate_store
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
-SDNode *Select_ISD_MUL_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:v2i32 DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
- // Emits: (VMULslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 9 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_126(N, ARM::VMULslv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
-
- // Pattern: (mul:v2i32 (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
- // Emits: (VMULslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_128(N, ARM::VMULslv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (mul:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VMULv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VMULv2i32, MVT::v2i32);
- return Result;
}
+ case 40: { // Predicate_truncstore
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_MUL_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:v4i32 QPR:v4i32:$src1, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
- // Emits: (VMULslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 9 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_126(N, ARM::VMULslv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (mul:v4i32 (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
- // Emits: (VMULslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_128(N, ARM::VMULslv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:v4i32 QPR:v4i32:$src1, (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane))
- // Emits: (VMULslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 9 cost = 2 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_210(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (mul:v4i32 (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
- // Emits: (VMULslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 9 cost = 2 size = 0
- if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_211(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
+ return cast<StoreSDNode>(N)->isTruncatingStore();
- // Pattern: (mul:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VMULv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_44(N, ARM::VMULv4i32, MVT::v4i32);
- return Result;
}
+ case 41: { // Predicate_truncstorei16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_MULHS_i32(SDNode *N) {
-
- // Pattern: (mulhs:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (SMMUL:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDNode *Result = Emit_44(N, ARM::SMMUL, MVT::i32);
- return Result;
- }
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
- // Pattern: (mulhs:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (t2SMMUL:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_44(N, ARM::t2SMMUL, MVT::i32);
- return Result;
}
+ case 42: { // Predicate_truncstorei8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_261(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_hi16(Tmp2.getNode());
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_262(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue N11000 = N1100.getNode()->getOperand(0);
- SDValue N11001 = N1100.getNode()->getOperand(1);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- SDValue N11100 = N1110.getNode()->getOperand(0);
- SDValue N11101 = N1110.getNode()->getOperand(1);
- SDValue Tmp13 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp14 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N000, Tmp13, Tmp14);
-}
-DISABLE_INLINE SDNode *Emit_263(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N100, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_264(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xFFFFULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_265(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N10, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_266(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N10, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_267(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0x10ULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N10, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_268(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N10000 = N1000.getNode()->getOperand(0);
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- SDValue N10100 = N1010.getNode()->getOperand(0);
- SDValue N10101 = N1010.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue Tmp13 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp14 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N000, Tmp13, Tmp14);
-}
-DISABLE_INLINE SDNode *Emit_269(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- SDValue N00100 = N0010.getNode()->getOperand(0);
- SDValue N00101 = N0010.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue Tmp13 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp14 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00000, Tmp13, Tmp14);
-}
-DISABLE_INLINE SDNode *Emit_270(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N01000 = N0100.getNode()->getOperand(0);
- SDValue N01001 = N0100.getNode()->getOperand(1);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- SDValue N01100 = N0110.getNode()->getOperand(0);
- SDValue N01101 = N0110.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue Tmp13 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp14 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0000, Tmp13, Tmp14);
-}
-DISABLE_INLINE SDNode *Emit_271(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N10, N000, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_272(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N10, N00, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_273(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N10, N00, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_274(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp5 = CurDAG->getTargetConstant(0x10ULL, MVT::i32);
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N10, N00, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-SDNode *Select_ISD_OR_i32(SDNode *N) {
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getNode()->getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::OR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::AND) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp3 &&
- CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
- N100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N000 == N1000) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::OR) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp6 &&
- CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
- N1100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
- N1110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
- // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32))))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getNode()->getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::OR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::AND) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp3 &&
- CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
- N100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N000 == N1000) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::OR) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp6 &&
- CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
- N1100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
- N1110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
}
+ case 43: { // Predicate_istore
+ SDNode *N = Node;
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getNode()->getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::OR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::AND) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp3 &&
- CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
- N100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N000 == N1000) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::OR) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp6 &&
- CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
- N1100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
- N1110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getNode()->getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::OR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::OR) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::AND) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp3) {
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
- N1000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
- N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(4278190080)) &&
- N110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(65280)) &&
- N1000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
- N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
- N110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
- N1000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
- N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
- N110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
- N1000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
- N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
- N110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
- N1000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(16711680)) &&
- N1010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
- N110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N10.getNode()->getOpcode() == ISD::AND) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp3) {
- if (CheckAndMask(N100, Tmp3, INT64_C(4278190080)) &&
- N100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N000 == N1000) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::OR) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp6) {
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
- N1100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
- N1110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
- N1100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
- N1110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (CheckAndMask(N100, Tmp3, INT64_C(16711680)) &&
- N100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N000 == N1000) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::OR) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp6) {
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
- N1100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
- N1110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
- N1100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
- N1110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
- N100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N000 == N1000) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::OR) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp6 &&
- CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
- N1100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
- N1110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::OR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::OR) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::AND) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp0) {
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
- N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
- N0010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
- N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
- N0000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
- N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
- N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
- N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
- N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
- N010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
- N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
- N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
- N010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
- N0000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
- N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
- N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
- N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
- N0010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
- N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N00.getNode()->getOpcode() == ISD::AND) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- if (CheckAndMask(N000, Tmp0, INT64_C(4278190080)) &&
- N000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::OR) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp3) {
-
- // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
- N0100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
- N0110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
- N0100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
- N0110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (CheckAndMask(N000, Tmp0, INT64_C(16711680)) &&
- N000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::OR) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp3) {
-
- // Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
- N0100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
- N0110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
- N0100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
- N0110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (CheckAndMask(N000, Tmp0, INT64_C(65280)) &&
- N000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::OR) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp3) {
-
- // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
- N0100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
- N0110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
- N0100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
- N0110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getNode()->getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::OR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::OR) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::AND) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp3) {
-
- // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
- N1000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
- N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(4278190080)) &&
- N110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(65280)) &&
- N1000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
- N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
- N110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
- N1000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
- N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
- N110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
- N1000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
- N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
- N110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
- N1000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(16711680)) &&
- N1010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
- N110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N10.getNode()->getOpcode() == ISD::AND) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp3) {
- if (CheckAndMask(N100, Tmp3, INT64_C(4278190080)) &&
- N100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N000 == N1000) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::OR) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp6) {
-
- // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32))))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
- N1100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
- N1110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32))))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
- N1100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
- N1110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (CheckAndMask(N100, Tmp3, INT64_C(16711680)) &&
- N100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N000 == N1000) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::OR) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp6) {
-
- // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32))))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
- N1100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
- N1110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32))))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
- N1100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
- N1110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32))))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
- N100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N000 == N1000) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::OR) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp6 &&
- CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
- N1100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
- N1110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::OR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::OR) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::AND) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp0) {
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
- N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
- N0010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
- N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
- N0000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
- N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
- N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
- N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
- N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
- N010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
- N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
- N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
- N010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
- N0000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
- N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
- N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
- N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
- N0010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
- N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N00.getNode()->getOpcode() == ISD::AND) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- if (CheckAndMask(N000, Tmp0, INT64_C(4278190080)) &&
- N000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::OR) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp3) {
-
- // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
- N0100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
- N0110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
- N0100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
- N0110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (CheckAndMask(N000, Tmp0, INT64_C(16711680)) &&
- N000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::OR) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp3) {
-
- // Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
- N0100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
- N0110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
- N0100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
- N0110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (CheckAndMask(N000, Tmp0, INT64_C(65280)) &&
- N000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::OR) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp3) {
-
- // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
- N0100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
- N0110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
- // Emits: (tREV16:i32 tGPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
- N0100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
- N0110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::tREV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getNode()->getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::OR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::OR) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::AND) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp3) {
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
- N1000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
- N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(4278190080)) &&
- N110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(65280)) &&
- N1000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
- N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
- N110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
- N1000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
- N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
- N110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
- N1000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
- N1010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
- N110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
- N1000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getNode()->getOperand(0);
- if (N000 == N10000) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
- if (Tmp6 &&
- CheckAndMask(N1010, Tmp6, INT64_C(16711680)) &&
- N1010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- if (N000 == N10100) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp9 &&
- CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
- N110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- if (N000 == N1100) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N10001.getValueType() == MVT::i32 &&
- N10101.getValueType() == MVT::i32 &&
- N1101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N10.getNode()->getOpcode() == ISD::AND) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp3) {
- if (CheckAndMask(N100, Tmp3, INT64_C(4278190080)) &&
- N100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N000 == N1000) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::OR) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp6) {
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
- N1100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
- N1110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
- N1100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
- N1110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (CheckAndMask(N100, Tmp3, INT64_C(16711680)) &&
- N100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N000 == N1000) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::OR) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp6) {
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
- N1100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
- N1110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
- N1100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
- N1110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
- N100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N000 == N1000) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::OR) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
- if (Tmp6 &&
- CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
- N1100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getNode()->getOperand(0);
- if (N000 == N11000) {
- SDValue N11001 = N1100.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
- if (Tmp9 &&
- CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
- N1110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- if (N000 == N11100) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N001.getValueType() == MVT::i32 &&
- N1001.getValueType() == MVT::i32 &&
- N11001.getValueType() == MVT::i32 &&
- N11101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::OR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::OR) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::AND) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp0) {
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
- N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
- N0010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
- N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
- N0000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
- N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
- N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
- N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
- N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
- N010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
- N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
- N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
- N010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
- N0000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
- N0010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
- N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
- N0000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getNode()->getOperand(0);
- SDValue N00001 = N0000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getNode()->getOperand(0);
- SDValue N0011 = N001.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
- if (Tmp3 &&
- CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
- N0010.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00100 = N0010.getNode()->getOperand(0);
- if (N00000 == N00100) {
- SDValue N00101 = N0010.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::AND) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp6 &&
- CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
- N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- if (N00000 == N0100) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N00000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N00001.getValueType() == MVT::i32 &&
- N00101.getValueType() == MVT::i32 &&
- N0101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N00.getNode()->getOpcode() == ISD::AND) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- if (CheckAndMask(N000, Tmp0, INT64_C(4278190080)) &&
- N000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::OR) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp3) {
-
- // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
- N0100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
- N0110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
- N0100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
- N0110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (CheckAndMask(N000, Tmp0, INT64_C(16711680)) &&
- N000.getNode()->getOpcode() == ISD::SRL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::OR) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp3) {
-
- // Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
- N0100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
- N0110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
- N0100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
- N0110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (CheckAndMask(N000, Tmp0, INT64_C(65280)) &&
- N000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::OR) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp3) {
-
- // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
- N0100.getNode()->getOpcode() == ISD::SRL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
- N0110.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
- // Emits: (t2REV16:i32 GPR:i32:$src)
- // Pattern complexity = 73 cost = 1 size = 0
- if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
- N0100.getNode()->getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getNode()->getOperand(0);
- if (N0000 == N01000) {
- SDValue N01001 = N0100.getNode()->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getNode()->getOperand(0);
- SDValue N0111 = N011.getNode()->getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
- if (Tmp6 &&
- CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
- N0110.getNode()->getOpcode() == ISD::SRL) {
- SDValue N01100 = N0110.getNode()->getOperand(0);
- if (N0000 == N01100) {
- SDValue N01101 = N0110.getNode()->getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
- if (Tmp7) {
- int64_t CN8 = Tmp7->getSExtValue();
- if (CN8 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp9 &&
- CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N0000 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp10) {
- int64_t CN11 = Tmp10->getSExtValue();
- if (CN11 == INT64_C(8) &&
- N0001.getValueType() == MVT::i32 &&
- N01001.getValueType() == MVT::i32 &&
- N01101.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_270(N, ARM::t2REV16, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
- // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (and:i32 (sra:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), 65535:i32))
- // Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
- // Pattern complexity = 26 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(65535)) &&
- N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm16_31(N101.getNode()) &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_263(N, ARM::PKHTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(65535))) {
-
- // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (and:i32 (sra:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), 65535:i32))
- // Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
- // Pattern complexity = 26 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm16_31(N101.getNode()) &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_263(N, ARM::t2PKHTB, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (and:i32 (srl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt), 65535:i32))
- // Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt)
- // Pattern complexity = 26 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm1_15(N101.getNode()) &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_263(N, ARM::t2PKHTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
-
- // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (and:i32 (srl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt), 65535:i32))
- // Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt)
- // Pattern complexity = 26 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(65535)) &&
- N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm1_15(N101.getNode()) &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_263(N, ARM::PKHTB, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (sra:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), 65535:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
- // Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
- // Pattern complexity = 26 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(65535)) &&
- N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm16_31(N001.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
- N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_271(N, ARM::PKHTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(65535))) {
-
- // Pattern: (or:i32 (and:i32 (sra:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), 65535:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
- // Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
- // Pattern complexity = 26 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm16_31(N001.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
- N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_271(N, ARM::t2PKHTB, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt), 65535:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
- // Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt)
- // Pattern complexity = 26 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm1_15(N001.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
- N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_271(N, ARM::t2PKHTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(65535))) {
-
- // Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt), 65535:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
- // Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt)
- // Pattern complexity = 26 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm1_15(N001.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
- N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_271(N, ARM::PKHTB, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (and:i32 (shl:i32 GPR:i32:$src2, (imm:i32):$shamt), 4294901760:i32))
- // Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
- // Pattern complexity = 25 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
- N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_263(N, ARM::PKHBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
}
+ case 44: { // Predicate_pre_store
+ SDNode *N = Node;
- // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (and:i32 (shl:i32 GPR:i32:$src2, (imm:i32):$shamt), 4294901760:i32))
- // Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
- // Pattern complexity = 25 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
- N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant &&
- N101.getValueType() == MVT::i32) {
- SDNode *Result = Emit_263(N, ARM::t2PKHBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
- // Pattern: (or:i32 (and:i32 (shl:i32 GPR:i32:$src2, (imm:i32):$shamt), 4294901760:i32), (and:i32 GPR:i32:$src1, 65535:i32))
- // Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
- // Pattern complexity = 25 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(4294901760)) &&
- N00.getNode()->getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(65535)) &&
- N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_271(N, ARM::PKHBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (or:i32 (and:i32 (shl:i32 GPR:i32:$src2, (imm:i32):$shamt), 4294901760:i32), (and:i32 GPR:i32:$src1, 65535:i32))
- // Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
- // Pattern complexity = 25 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(4294901760)) &&
- N00.getNode()->getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(65535)) &&
- N001.getValueType() == MVT::i32) {
- SDNode *Result = Emit_271(N, ARM::t2PKHBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 GPR:i32:$lhs, (xor:i32 t2_so_reg:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (t2ORNrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 19 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue CPTmpN10_0;
- SDValue CPTmpN10_1;
- if (SelectT2ShifterOperandReg(N, N10, CPTmpN10_0, CPTmpN10_1)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_169(N, ARM::t2ORNrs, MVT::i32, CPTmpN10_0, CPTmpN10_1);
- return Result;
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
-
- // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (and:i32 GPR:i32:$src2, 4294901760:i32))
- // Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, 0:i32)
- // Pattern complexity = 19 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(4294901760))) {
- SDNode *Result = Emit_265(N, ARM::t2PKHBT, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (srl:i32 GPR:i32:$src2, 16:i32))
- // Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, 16:i32)
- // Pattern complexity = 19 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_267(N, ARM::t2PKHTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
-
- // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (and:i32 GPR:i32:$src2, 4294901760:i32))
- // Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, 0:i32)
- // Pattern complexity = 19 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(4294901760))) {
- SDNode *Result = Emit_265(N, ARM::PKHBT, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (srl:i32 GPR:i32:$src2, 16:i32))
- // Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, 16:i32)
- // Pattern complexity = 19 cost = 1 size = 0
- if (CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(16) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_267(N, ARM::PKHTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (or:i32 (xor:i32 t2_so_reg:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
- // Emits: (t2ORNrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 19 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue CPTmpN00_0;
- SDValue CPTmpN00_1;
- if (SelectT2ShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_180(N, ARM::t2ORNrs, MVT::i32, CPTmpN00_0, CPTmpN00_1);
- return Result;
- }
- }
- }
-
- // Pattern: (or:i32 (and:i32 GPR:i32:$src2, 4294901760:i32), (and:i32 GPR:i32:$src1, 65535:i32))
- // Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, 0:i32)
- // Pattern complexity = 19 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(65535))) {
- SDNode *Result = Emit_272(N, ARM::t2PKHBT, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:i32 (srl:i32 GPR:i32:$src2, 16:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
- // Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, 16:i32)
- // Pattern complexity = 19 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp2 &&
- CheckAndMask(N10, Tmp2, INT64_C(4294901760)) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_274(N, ARM::t2PKHTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (or:i32 (and:i32 GPR:i32:$src2, 4294901760:i32), (and:i32 GPR:i32:$src1, 65535:i32))
- // Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, 0:i32)
- // Pattern complexity = 19 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp1 &&
- CheckAndMask(N10, Tmp1, INT64_C(65535))) {
- SDNode *Result = Emit_272(N, ARM::PKHBT, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:i32 (srl:i32 GPR:i32:$src2, 16:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
- // Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, 16:i32)
- // Pattern complexity = 19 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp2 &&
- CheckAndMask(N10, Tmp2, INT64_C(4294901760)) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_274(N, ARM::PKHTB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
}
+ case 45: { // Predicate_post_store
+ SDNode *N = Node;
- // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (shl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt))
- // Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt)
- // Pattern complexity = 18 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm16_31(N11.getNode()) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_266(N, ARM::t2PKHBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::POST_INC || AM == ISD::POST_DEC;
- // Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (shl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt))
- // Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt)
- // Pattern complexity = 18 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm16_31(N11.getNode()) &&
- N11.getValueType() == MVT::i32) {
- SDNode *Result = Emit_266(N, ARM::PKHBT, MVT::i32);
- return Result;
- }
- }
- }
- }
}
+ case 46: { // Predicate_itruncstore
+ SDNode *N = Node;
- // Pattern: (or:i32 (shl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), (and:i32 GPR:i32:$src1, 65535:i32))
- // Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt)
- // Pattern complexity = 18 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm16_31(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(65535)) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_273(N, ARM::t2PKHBT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
+ return cast<StoreSDNode>(N)->isTruncatingStore();
- // Pattern: (or:i32 (shl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), (and:i32 GPR:i32:$src1, 65535:i32))
- // Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt)
- // Pattern complexity = 18 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm16_31(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(65535)) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_273(N, ARM::PKHBT, MVT::i32);
- return Result;
- }
- }
- }
- }
}
+ case 47: { // Predicate_pre_truncst
+ SDNode *N = Node;
- // Pattern: (or:i32 (and:i32 GPR:i32:$src, 65535:i32), (imm:i32)<<P:Predicate_lo16AllZero>><<X:hi16>>:$imm)
- // Emits: (MOVTi16:i32 GPR:i32:$src, (hi16:i32 (imm:i32):$imm))
- // Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_lo16AllZero(N1.getNode())) {
- SDNode *Result = Emit_261(N, ARM::MOVTi16, MVT::i32);
- return Result;
- }
- }
- }
- }
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
- // Pattern: (or:i32 GPR:i32:$a, so_reg:i32:$b)
- // Emits: (ORRrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
- SDNode *Result = Emit_57(N, ARM::ORRrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
}
+ case 48: { // Predicate_pre_truncsti16
+ SDNode *N = Node;
- // Pattern: (or:i32 (and:i32 GPR:i32:$src, 65535:i32), (imm:i32)<<P:Predicate_lo16AllZero>><<X:hi16>>:$imm)
- // Emits: (t2MOVTi16:i32 GPR:i32:$src, (hi16:i32 (imm:i32):$imm))
- // Pattern complexity = 15 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0 &&
- CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_lo16AllZero(N1.getNode())) {
- SDNode *Result = Emit_261(N, ARM::t2MOVTi16, MVT::i32);
- return Result;
- }
- }
- }
- }
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
- // Pattern: (or:i32 so_reg:i32:$b, GPR:i32:$a)
- // Emits: (ORRrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- SDValue CPTmpN0_2;
- if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDNode *Result = Emit_88(N, ARM::ORRrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (or:i32 GPR:i32:$lhs, (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (t2ORNri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 14 cost = 1 size = 0
- if (Predicate_t2_so_imm(N10.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_165(N, ARM::t2ORNri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (or:i32 GPR:i32:$lhs, (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs))
- // Emits: (t2ORNri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 14 cost = 1 size = 0
- if (Predicate_immAllOnes(N10.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N11.getNode())) {
- SDNode *Result = Emit_174(N, ARM::t2ORNri, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (or:i32 (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
- // Emits: (t2ORNri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 14 cost = 1 size = 0
- if (Predicate_t2_so_imm(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_175(N, ARM::t2ORNri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (or:i32 (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), GPR:i32:$lhs)
- // Emits: (t2ORNri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 14 cost = 1 size = 0
- if (Predicate_immAllOnes(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N01.getNode())) {
- SDNode *Result = Emit_176(N, ARM::t2ORNri, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2ORRrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_68(N, ARM::t2ORRrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (or:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
- // Emits: (t2ORRrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDNode *Result = Emit_103(N, ARM::t2ORRrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
- return Result;
- }
- }
-
- // Pattern: (or:i32 GPR:i32:$lhs, (xor:i32 GPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (t2ORNrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_166(N, ARM::t2ORNrr, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (or:i32 (xor:i32 GPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
- // Emits: (t2ORNrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_177(N, ARM::t2ORNrr, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (or:i32 GPR:i32:$src, 4294901760:i32)
- // Emits: (t2MOVTi16:i32 GPR:i32:$src, 65535:i32)
- // Pattern complexity = 8 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0 &&
- CheckOrMask(N0, Tmp0, INT64_C(4294901760))) {
- SDNode *Result = Emit_264(N, ARM::t2MOVTi16, MVT::i32);
- return Result;
- }
}
+ case 49: { // Predicate_post_truncst
+ SDNode *N = Node;
- // Pattern: (or:i32 GPR:i32:$src, 4294901760:i32)
- // Emits: (MOVTi16:i32 GPR:i32:$src, 65535:i32)
- // Pattern complexity = 8 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0 &&
- CheckOrMask(N0, Tmp0, INT64_C(4294901760))) {
- SDNode *Result = Emit_264(N, ARM::MOVTi16, MVT::i32);
- return Result;
- }
- }
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::POST_INC || AM == ISD::POST_DEC;
- // Pattern: (or:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (ORRri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N1.getNode())) {
- SDNode *Result = Emit_55(N, ARM::ORRri, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (or:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2ORRri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_t2_so_imm(N1.getNode())) {
- SDNode *Result = Emit_55(N, ARM::t2ORRri, MVT::i32);
- return Result;
- }
-
- // Pattern: (or:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_t2_so_imm_not>><<X:t2_so_imm_not_XFORM>>:$imm)
- // Emits: (t2ORNri:i32 GPR:i32:$src, (t2_so_imm_not_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_not>>:$imm))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_t2_so_imm_not(N1.getNode())) {
- SDNode *Result = Emit_172(N, ARM::t2ORNri, MVT::i32);
- return Result;
- }
-
- // Pattern: (or:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_t2_so_imm2part>>:$RHS)
- // Emits: (t2ORRri:i32 (t2ORRri:i32 GPR:i32:$LHS, (t2_so_imm2part_1:i32 (imm:i32):$RHS)), (t2_so_imm2part_2:i32 (imm:i32):$RHS))
- // Pattern complexity = 7 cost = 2 size = 0
- if (Predicate_t2_so_imm2part(N1.getNode())) {
- SDNode *Result = Emit_71(N, ARM::t2ORRri, ARM::t2ORRri, MVT::i32, MVT::i32);
- return Result;
- }
- }
- }
- if ((!Subtarget->isThumb())) {
-
- // Pattern: (or:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_so_imm2part>>:$RHS)
- // Emits: (ORRri:i32 (ORRri:i32 GPR:i32:$LHS, (so_imm2part_1:i32 (imm:i32):$RHS)), (so_imm2part_2:i32 (imm:i32):$RHS))
- // Pattern complexity = 7 cost = 2 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm2part(N1.getNode())) {
- SDNode *Result = Emit_74(N, ARM::ORRri, ARM::ORRri, MVT::i32, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (or:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (ORRrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_56(N, ARM::ORRrr, MVT::i32);
- return Result;
}
+ case 50: { // Predicate_post_truncsti16
+ SDNode *N = Node;
- // Pattern: (or:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tORR:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDNode *Result = Emit_66(N, ARM::tORR, MVT::i32);
- return Result;
- }
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
- // Pattern: (or:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2ORRrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_56(N, ARM::t2ORRrr, MVT::i32);
- return Result;
}
+ case 51: { // Predicate_pre_truncsti8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
-DISABLE_INLINE SDNode *Emit_275(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N01, N00, N10, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_276(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N01, N00, N11, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_277(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N01, N10, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_278(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N01, N11, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_279(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N010, N10, N00, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_280(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N010, N11, N00, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_281(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N011, N10, N00, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_282(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N011, N11, N00, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_283(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N10, N01, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_284(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N000, N11, N01, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_285(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N001, N10, N01, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_286(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N001, N11, N01, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-SDNode *Select_ISD_OR_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::XOR) {
- SDValue N110 = N11.getNode()->getOperand(0);
-
- // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1), (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N01 == N110) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N111.getNode())) {
- SDNode *Result = Emit_275(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1), (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1)))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N110.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N01 == N111) {
- SDNode *Result = Emit_275(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
- }
- }
- if (N10.getNode()->getOpcode() == ISD::XOR) {
- SDValue N100 = N10.getNode()->getOperand(0);
-
- // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1), (and:v2i32 (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src3))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N01 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N101.getNode())) {
- SDNode *Result = Emit_276(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1), (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1), DPR:v2i32:$src3))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N01 == N101) {
- SDNode *Result = Emit_276(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
- }
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::XOR) {
- SDValue N110 = N11.getNode()->getOperand(0);
-
- // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2), (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N00 == N110) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N111.getNode())) {
- SDNode *Result = Emit_277(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2), (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1)))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N110.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N00 == N111) {
- SDNode *Result = Emit_277(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
- }
- }
- if (N10.getNode()->getOpcode() == ISD::XOR) {
- SDValue N100 = N10.getNode()->getOperand(0);
-
- // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2), (and:v2i32 (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src3))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N00 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N101.getNode())) {
- SDNode *Result = Emit_278(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2), (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1), DPR:v2i32:$src3))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N00 == N101) {
- SDNode *Result = Emit_278(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
- }
- }
- }
- if (N01.getNode()->getOpcode() == ISD::XOR) {
- SDValue N010 = N01.getNode()->getOperand(0);
- {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N011.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)), (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N010 == N11) {
- SDNode *Result = Emit_279(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)), (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N010 == N10) {
- SDNode *Result = Emit_280(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
- }
- }
- if (N010.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N010.getNode())) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1)), (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N011 == N11) {
- SDNode *Result = Emit_281(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1)), (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N011 == N10) {
- SDNode *Result = Emit_282(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
- }
- }
- }
- if (N00.getNode()->getOpcode() == ISD::XOR) {
- SDValue N000 = N00.getNode()->getOperand(0);
- {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N001.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (or:v2i32 (and:v2i32 (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src3), (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N000 == N11) {
- SDNode *Result = Emit_283(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (or:v2i32 (and:v2i32 (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src3), (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N000 == N10) {
- SDNode *Result = Emit_284(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
- }
- }
- if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (or:v2i32 (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1), DPR:v2i32:$src3), (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N001 == N11) {
- SDNode *Result = Emit_285(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (or:v2i32 (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1), DPR:v2i32:$src3), (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2))
- // Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N001 == N10) {
- SDNode *Result = Emit_286(N, ARM::VBSLd, MVT::v2i32);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (or:v2i32 DPR:v2i32:$src1, (xor:v2i32 DPR:v2i32:$src2, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>))
- // Emits: (VORNd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N11.getNode())) {
- SDNode *Result = Emit_51(N, ARM::VORNd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (or:v2i32 DPR:v2i32:$src1, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src2))
- // Emits: (VORNd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N10.getNode())) {
- SDNode *Result = Emit_181(N, ARM::VORNd, MVT::v2i32);
- return Result;
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (or:v2i32 (xor:v2i32 DPR:v2i32:$src2, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src1)
- // Emits: (VORNd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N01.getNode())) {
- SDNode *Result = Emit_84(N, ARM::VORNd, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (or:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src2), DPR:v2i32:$src1)
- // Emits: (VORNd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N00.getNode())) {
- SDNode *Result = Emit_182(N, ARM::VORNd, MVT::v2i32);
- return Result;
- }
- }
- }
-
- // Pattern: (or:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VORRd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VORRd, MVT::v2i32);
- return Result;
}
+ case 52: { // Predicate_post_truncsti8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
-SDNode *Select_ISD_OR_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::XOR) {
- SDValue N110 = N11.getNode()->getOperand(0);
-
- // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1), (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N01 == N110) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N111.getNode())) {
- SDNode *Result = Emit_275(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1), (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1)))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N110.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N01 == N111) {
- SDNode *Result = Emit_275(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- if (N10.getNode()->getOpcode() == ISD::XOR) {
- SDValue N100 = N10.getNode()->getOperand(0);
-
- // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1), (and:v4i32 (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src3))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N01 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N101.getNode())) {
- SDNode *Result = Emit_276(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1), (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1), QPR:v4i32:$src3))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N01 == N101) {
- SDNode *Result = Emit_276(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
- }
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::XOR) {
- SDValue N110 = N11.getNode()->getOperand(0);
-
- // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2), (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N00 == N110) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N111.getNode())) {
- SDNode *Result = Emit_277(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2), (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1)))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N110.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N00 == N111) {
- SDNode *Result = Emit_277(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- if (N10.getNode()->getOpcode() == ISD::XOR) {
- SDValue N100 = N10.getNode()->getOperand(0);
-
- // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2), (and:v4i32 (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src3))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N00 == N100) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N101.getNode())) {
- SDNode *Result = Emit_278(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2), (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1), QPR:v4i32:$src3))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N00 == N101) {
- SDNode *Result = Emit_278(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- }
- if (N01.getNode()->getOpcode() == ISD::XOR) {
- SDValue N010 = N01.getNode()->getOperand(0);
- {
- SDValue N011 = N01.getNode()->getOperand(1);
- if (N011.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N011.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)), (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N010 == N11) {
- SDNode *Result = Emit_279(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)), (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N010 == N10) {
- SDNode *Result = Emit_280(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- if (N010.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N010.getNode())) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1)), (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N011 == N11) {
- SDNode *Result = Emit_281(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1)), (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N011 == N10) {
- SDNode *Result = Emit_282(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- }
- if (N00.getNode()->getOpcode() == ISD::XOR) {
- SDValue N000 = N00.getNode()->getOperand(0);
- {
- SDValue N001 = N00.getNode()->getOperand(1);
- if (N001.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N001.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (or:v4i32 (and:v4i32 (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src3), (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N000 == N11) {
- SDNode *Result = Emit_283(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (or:v4i32 (and:v4i32 (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src3), (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N000 == N10) {
- SDNode *Result = Emit_284(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (or:v4i32 (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1), QPR:v4i32:$src3), (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N001 == N11) {
- SDNode *Result = Emit_285(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (or:v4i32 (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1), QPR:v4i32:$src3), (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2))
- // Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 16 cost = 1 size = 0
- if (N001 == N10) {
- SDNode *Result = Emit_286(N, ARM::VBSLq, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (or:v4i32 QPR:v4i32:$src1, (xor:v4i32 QPR:v4i32:$src2, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>))
- // Emits: (VORNq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N11.getNode())) {
- SDNode *Result = Emit_51(N, ARM::VORNq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (or:v4i32 QPR:v4i32:$src1, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src2))
- // Emits: (VORNq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N10.getNode())) {
- SDNode *Result = Emit_181(N, ARM::VORNq, MVT::v4i32);
- return Result;
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (or:v4i32 (xor:v4i32 QPR:v4i32:$src2, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src1)
- // Emits: (VORNq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N01.getNode())) {
- SDNode *Result = Emit_84(N, ARM::VORNq, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (or:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src2), QPR:v4i32:$src1)
- // Emits: (VORNq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N00.getNode())) {
- SDNode *Result = Emit_182(N, ARM::VORNq, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (or:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VORRq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VORRq, MVT::v4i32);
- return Result;
}
+ case 53: { // Predicate_imm0_255
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ return (uint32_t)N->getZExtValue() < 256;
-DISABLE_INLINE SDNode *Emit_287(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN_0, SDValue &CPTmpN_1, SDValue &CPTmpN_2) {
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { CPTmpN_0, CPTmpN_1, CPTmpN_2, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-SDNode *Select_ISD_ROTR_i32(SDNode *N) {
-
- // Pattern: so_reg:i32:$src
- // Emits: (MOVs:i32 so_reg:i32:$src)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- if (SelectShifterOperandReg(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
- SDNode *Result = Emit_287(N, ARM::MOVs, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2);
- return Result;
- }
}
+ case 54: { // Predicate_immAllOnesV
+ SDNode *N = Node;
- // Pattern: (rotr:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_imm1_31>>:$rhs)
- // Emits: (t2RORri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm1_31(N1.getNode()) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_55(N, ARM::t2RORri, MVT::i32);
- return Result;
- }
- }
+ return ISD::isBuildVectorAllOnes(N);
- // Pattern: (rotr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tROR:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_66(N, ARM::tROR, MVT::i32);
- return Result;
- }
}
-
- // Pattern: (rotr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2RORrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_56(N, ARM::t2RORrr, MVT::i32);
- return Result;
- }
+ case 55: { // Predicate_adde_dead_carry
+ SDNode *N = Node;
+return !N->hasAnyUseOfValue(1);
}
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_288(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops1[] = { Tmp0, N0, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
-}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_288(N, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi8, MVT::v8i8, MVT::v8i8);
- return Result;
+ case 56: { // Predicate_adde_live_carry
+ SDNode *N = Node;
+return N->hasAnyUseOfValue(1);
}
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_289(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
- SDValue Tmp1(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1), 0);
- SDValue Tmp3 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops2[] = { Tmp1, N0, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Ops2, 5), 0);
- SDValue Tmp7 = CurDAG->getTargetConstant(0x5ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc3, VT3, Tmp0, Tmp6, Tmp7);
-}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v16i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_289(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi8, TargetOpcode::INSERT_SUBREG, MVT::v16i8, MVT::v8i8, MVT::f64, MVT::v16i8);
- return Result;
+ case 57: { // Predicate_sube_dead_carry
+ SDNode *N = Node;
+return !N->hasAnyUseOfValue(1);
}
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_288(N, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi16, MVT::v4i16, MVT::v4i16);
- return Result;
+ case 58: { // Predicate_sube_live_carry
+ SDNode *N = Node;
+return N->hasAnyUseOfValue(1);
}
+ case 59: { // Predicate_immAllZerosV
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return ISD::isBuildVectorAllZeros(N);
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_289(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi16, TargetOpcode::INSERT_SUBREG, MVT::v8i16, MVT::v4i16, MVT::f64, MVT::v8i16);
- return Result;
}
+ case 60: { // Predicate_immAllZerosV_bc
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return ISD::isBuildVectorAllZeros(N);
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_288(N, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi32, MVT::v2i32, MVT::v2i32);
- return Result;
}
+ case 61: { // Predicate_imm0_65535
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ return (uint32_t)N->getZExtValue() < 65536;
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_289(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi32, TargetOpcode::INSERT_SUBREG, MVT::v4i32, MVT::v2i32, MVT::f64, MVT::v4i32);
- return Result;
}
+ case 62: { // Predicate_thumb_immshifted
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
-DISABLE_INLINE SDNode *Emit_290(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp0, N0, Tmp2);
-}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_290(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
- return Result;
}
+ case 63: { // Predicate_imm0_255_comp
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ return ~((uint32_t)N->getZExtValue()) < 256;
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_290(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
- return Result;
}
+ case 64: { // Predicate_vfp_f64imm
+ ConstantFPSDNode*N = cast<ConstantFPSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_291(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x5ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp0, N0, Tmp2);
-}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_291(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, MVT::v2f64, MVT::v2f64);
- return Result;
+ return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
+
}
+ case 65: { // Predicate_vfp_f32imm
+ ConstantFPSDNode*N = cast<ConstantFPSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SHL_i32(SDNode *N) {
-
- // Pattern: so_reg:i32:$src
- // Emits: (MOVs:i32 so_reg:i32:$src)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- if (SelectShifterOperandReg(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
- SDNode *Result = Emit_287(N, ARM::MOVs, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2);
- return Result;
- }
+ return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
+
}
+ case 66: { // Predicate_vmovImm8
+ SDNode *N = Node;
- // Pattern: (shl:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_imm1_31>>:$rhs)
- // Emits: (t2LSLri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm1_31(N1.getNode()) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_55(N, ARM::t2LSLri, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (shl:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
- // Emits: (tLSLri:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_65(N, ARM::tLSLri, MVT::i32);
- return Result;
- }
-
- // Pattern: (shl:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tLSLrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_66(N, ARM::tLSLrr, MVT::i32);
- return Result;
- }
- }
+ return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
- // Pattern: (shl:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2LSLrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_56(N, ARM::t2LSLrr, MVT::i32);
- return Result;
- }
}
+ case 67: { // Predicate_vmovImm16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
-DISABLE_INLINE SDNode *Emit_292(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_293(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_294(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0000, Tmp6, Tmp7);
-}
-DISABLE_INLINE SDNode *Emit_295(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N000, Tmp6, Tmp7);
-}
-SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(SDNode *N) {
-
- // Pattern: (sext_inreg:i32 (or:i32 (srl:i32 (and:i32 GPR:i32:$src, 65280:i32), 8:i32), (shl:i32 GPR:i32:$src, 8:i32)), i16:Other)
- // Emits: (REVSH:i32 GPR:i32:$src)
- // Pattern complexity = 30 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::OR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::AND) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp0 &&
- CheckAndMask(N0000, Tmp0, INT64_C(65280))) {
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SHL) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N0000 == N010) {
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp3) {
- int64_t CN4 = Tmp3->getSExtValue();
- if (CN4 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
- N001.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_294(N, ARM::REVSH, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
}
+ case 68: { // Predicate_vmovImm32
+ SDNode *N = Node;
- // Pattern: (sext_inreg:i32 (or:i32 (srl:i32 (and:i32 tGPR:i32:$src, 65280:i32), 8:i32), (shl:i32 tGPR:i32:$src, 8:i32)), i16:Other)
- // Emits: (tREVSH:i32 tGPR:i32:$src)
- // Pattern complexity = 30 cost = 1 size = 0
- if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::OR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::AND) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp0 &&
- CheckAndMask(N0000, Tmp0, INT64_C(65280))) {
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SHL) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N0000 == N010) {
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp3) {
- int64_t CN4 = Tmp3->getSExtValue();
- if (CN4 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
- N001.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_294(N, ARM::tREVSH, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
+ return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
- // Pattern: (sext_inreg:i32 (or:i32 (srl:i32 (and:i32 GPR:i32:$src, 65280:i32), 8:i32), (shl:i32 GPR:i32:$src, 8:i32)), i16:Other)
- // Emits: (t2REVSH:i32 GPR:i32:$src)
- // Pattern complexity = 30 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::OR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::AND) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp0 &&
- CheckAndMask(N0000, Tmp0, INT64_C(65280))) {
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SHL) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N0000 == N010) {
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp3) {
- int64_t CN4 = Tmp3->getSExtValue();
- if (CN4 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
- N001.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_294(N, ARM::t2REVSH, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
}
+ case 69: { // Predicate_vmovImm64
+ SDNode *N = Node;
- // Pattern: (sext_inreg:i32 (or:i32 (shl:i32 GPR:i32:$src, 8:i32), (srl:i32 (and:i32 GPR:i32:$src, 65280:i32), 8:i32)), i16:Other)
- // Emits: (REVSH:i32 GPR:i32:$src)
- // Pattern complexity = 30 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::OR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRL) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp2 &&
- CheckAndMask(N0100, Tmp2, INT64_C(65280)) &&
- N000 == N0100) {
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp3) {
- int64_t CN4 = Tmp3->getSExtValue();
- if (CN4 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
- N001.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_295(N, ARM::REVSH, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
+ return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
- // Pattern: (sext_inreg:i32 (or:i32 (shl:i32 tGPR:i32:$src, 8:i32), (srl:i32 (and:i32 tGPR:i32:$src, 65280:i32), 8:i32)), i16:Other)
- // Emits: (tREVSH:i32 tGPR:i32:$src)
- // Pattern complexity = 30 cost = 1 size = 0
- if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::OR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRL) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp2 &&
- CheckAndMask(N0100, Tmp2, INT64_C(65280)) &&
- N000 == N0100) {
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp3) {
- int64_t CN4 = Tmp3->getSExtValue();
- if (CN4 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
- N001.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_295(N, ARM::tREVSH, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
}
+ case 70: { // Predicate_atomic_load_add_8
+ SDNode *N = Node;
- // Pattern: (sext_inreg:i32 (or:i32 (shl:i32 GPR:i32:$src, 8:i32), (srl:i32 (and:i32 GPR:i32:$src, 65280:i32), 8:i32)), i16:Other)
- // Emits: (t2REVSH:i32 GPR:i32:$src)
- // Pattern complexity = 30 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::OR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRL) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp2 &&
- CheckAndMask(N0100, Tmp2, INT64_C(65280)) &&
- N000 == N0100) {
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp3) {
- int64_t CN4 = Tmp3->getSExtValue();
- if (CN4 == INT64_C(8)) {
- SDValue N1 = N->getOperand(1);
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
- N001.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32) {
- SDNode *Result = Emit_295(N, ARM::t2REVSH, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sext_inreg:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other)
- // Emits: (SXTBr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
- // Pattern complexity = 10 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_293(N, ARM::SXTBr_rot, MVT::i32);
- return Result;
- }
-
- // Pattern: (sext_inreg:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other)
- // Emits: (SXTHr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
- // Pattern complexity = 10 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_293(N, ARM::SXTHr_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_rot_imm(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sext_inreg:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other)
- // Emits: (t2SXTBr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
- // Pattern complexity = 10 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_293(N, ARM::t2SXTBr_rot, MVT::i32);
- return Result;
- }
-
- // Pattern: (sext_inreg:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other)
- // Emits: (t2SXTHr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
- // Pattern complexity = 10 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_293(N, ARM::t2SXTHr_rot, MVT::i32);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sext_inreg:i32 GPR:i32:$src, i8:Other)
- // Emits: (SXTBr:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_292(N, ARM::SXTBr, MVT::i32);
- return Result;
- }
-
- // Pattern: (sext_inreg:i32 GPR:i32:$src, i16:Other)
- // Emits: (SXTHr:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_292(N, ARM::SXTHr, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sext_inreg:i32 tGPR:i32:$src, i8:Other)
- // Emits: (tSXTB:i32 tGPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_292(N, ARM::tSXTB, MVT::i32);
- return Result;
- }
-
- // Pattern: (sext_inreg:i32 tGPR:i32:$src, i16:Other)
- // Emits: (tSXTH:i32 tGPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_292(N, ARM::tSXTH, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sext_inreg:i32 GPR:i32:$src, i8:Other)
- // Emits: (t2SXTBr:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_292(N, ARM::t2SXTBr, MVT::i32);
- return Result;
- }
-
- // Pattern: (sext_inreg:i32 GPR:i32:$src, i16:Other)
- // Emits: (t2SXTHr:i32 GPR:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_292(N, ARM::t2SXTHr, MVT::i32);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 71: { // Predicate_atomic_load_add_16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SINT_TO_FP_v2f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_31(N, ARM::VCVTs2fd, MVT::v2f32);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 72: { // Predicate_atomic_load_add_32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SINT_TO_FP_v4f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_31(N, ARM::VCVTs2fq, MVT::v4f32);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 73: { // Predicate_atomic_load_sub_8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_296(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N010, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_297(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N010, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_298(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N0100, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_299(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N00, N01, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_300(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N01, N000, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_301(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N01, N000, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_302(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N01, N0000, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_303(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N01, N00, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ISD_SRA_i32(SDNode *N) {
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), 16:i32)
- // Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 27 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16) &&
- N0101.getValueType() == MVT::i32 &&
- N011.getValueType() == MVT::i32 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_298(N, ARM::SMULWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (sra:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), GPR:i32:$a), 16:i32)
- // Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 27 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(16) &&
- N0001.getValueType() == MVT::i32 &&
- N001.getValueType() == MVT::i32 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_302(N, ARM::SMULWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32)
- // Emits: (SMULWT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 19 cost = 1 size = 0
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N011.getValueType() == MVT::i32 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_297(N, ARM::SMULWT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 74: { // Predicate_atomic_load_sub_16
+ SDNode *N = Node;
- // Pattern: (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32)
- // Emits: (t2SMULWT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 19 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N011.getValueType() == MVT::i32 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_297(N, ARM::t2SMULWT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 75: { // Predicate_atomic_load_sub_32
+ SDNode *N = Node;
- // Pattern: (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32)
- // Emits: (SMULWT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 19 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N001.getValueType() == MVT::i32 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_301(N, ARM::SMULWT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 76: { // Predicate_atomic_load_and_8
+ SDNode *N = Node;
- // Pattern: (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32)
- // Emits: (t2SMULWT:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 19 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(16) &&
- N001.getValueType() == MVT::i32 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_301(N, ARM::t2SMULWT, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 77: { // Predicate_atomic_load_and_16
+ SDNode *N = Node;
- // Pattern: (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32)
- // Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_296(N, ARM::SMULWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 78: { // Predicate_atomic_load_and_32
+ SDNode *N = Node;
- // Pattern: (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32)
- // Emits: (t2SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_296(N, ARM::t2SMULWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 79: { // Predicate_atomic_load_or_8
+ SDNode *N = Node;
- // Pattern: (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32)
- // Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_300(N, ARM::SMULWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 80: { // Predicate_atomic_load_or_16
+ SDNode *N = Node;
- // Pattern: (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32)
- // Emits: (t2SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 14 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_300(N, ARM::t2SMULWB, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 81: { // Predicate_atomic_load_or_32
+ SDNode *N = Node;
- // Pattern: so_reg:i32:$src
- // Emits: (MOVs:i32 so_reg:i32:$src)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- if (SelectShifterOperandReg(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
- SDNode *Result = Emit_287(N, ARM::MOVs, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2);
- return Result;
- }
- }
- if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (sra:i32 (mul:i32 GPR:i32:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b), 16:i32)
- // Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (Predicate_sext_16_node(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_299(N, ARM::SMULWB, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (sra:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$b, GPR:i32:$a), 16:i32)
- // Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 12 cost = 1 size = 0
- if (Predicate_sext_16_node(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_303(N, ARM::SMULWB, MVT::i32);
- return Result;
- }
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 82: { // Predicate_atomic_load_xor_8
+ SDNode *N = Node;
- // Pattern: (sra:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_imm1_31>>:$rhs)
- // Emits: (t2ASRri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm1_31(N1.getNode()) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_55(N, ARM::t2ASRri, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sra:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
- // Emits: (tASRri:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_65(N, ARM::tASRri, MVT::i32);
- return Result;
- }
-
- // Pattern: (sra:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tASRrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_66(N, ARM::tASRrr, MVT::i32);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 83: { // Predicate_atomic_load_xor_16
+ SDNode *N = Node;
- // Pattern: (sra:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2ASRrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_56(N, ARM::t2ASRrr, MVT::i32);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 84: { // Predicate_atomic_load_xor_32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRL_i32(SDNode *N) {
-
- // Pattern: so_reg:i32:$src
- // Emits: (MOVs:i32 so_reg:i32:$src)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- if (SelectShifterOperandReg(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
- SDNode *Result = Emit_287(N, ARM::MOVs, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 85: { // Predicate_atomic_load_nand_8
+ SDNode *N = Node;
- // Pattern: (srl:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_imm1_31>>:$rhs)
- // Emits: (t2LSRri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_imm1_31(N1.getNode()) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_55(N, ARM::t2LSRri, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (srl:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
- // Emits: (tLSRri:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_65(N, ARM::tLSRri, MVT::i32);
- return Result;
- }
-
- // Pattern: (srl:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tLSRrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_66(N, ARM::tLSRrr, MVT::i32);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 86: { // Predicate_atomic_load_nand_16
+ SDNode *N = Node;
- // Pattern: (srl:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2LSRrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_56(N, ARM::t2LSRrr, MVT::i32);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 87: { // Predicate_atomic_load_nand_32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_304(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN3_0, SDValue &CPTmpN3_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { N1, N2, CPTmpN3_0, CPTmpN3_1, Tmp3, Tmp4, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_305(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN3_0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { N1, N2, CPTmpN3_0, Tmp3, Tmp4, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_STORE_i32(SDNode *N) {
- if ((!Subtarget->isThumb())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_istore(N)) {
-
- // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)<<P:Predicate_istore>><<P:Predicate_pre_store>>
- // Emits: (STR_PRE:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_pre_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- SDValue CPTmpN3_1;
- if (SelectAddrMode2Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
- N1.getValueType() == MVT::i32 &&
- N3.getValueType() == MVT::i32) {
- SDNode *Result = Emit_304(N, ARM::STR_PRE, MVT::i32, CPTmpN3_0, CPTmpN3_1);
- return Result;
- }
- }
-
- // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)<<P:Predicate_istore>><<P:Predicate_post_store>>
- // Emits: (STR_POST:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_post_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- SDValue CPTmpN3_1;
- if (SelectAddrMode2Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
- N1.getValueType() == MVT::i32 &&
- N3.getValueType() == MVT::i32) {
- SDNode *Result = Emit_304(N, ARM::STR_POST, MVT::i32, CPTmpN3_0, CPTmpN3_1);
- return Result;
- }
- }
- }
- if (Predicate_itruncstore(N)) {
-
- // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am3offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti16>>
- // Emits: (STRH_PRE:i32 GPR:i32:$src, GPR:i32:$base, am3offset:i32:$offset)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_pre_truncst(N) &&
- Predicate_pre_truncsti16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- SDValue CPTmpN3_1;
- if (SelectAddrMode3Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
- N1.getValueType() == MVT::i32 &&
- N3.getValueType() == MVT::i32) {
- SDNode *Result = Emit_304(N, ARM::STRH_PRE, MVT::i32, CPTmpN3_0, CPTmpN3_1);
- return Result;
- }
- }
-
- // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am3offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_post_truncst>><<P:Predicate_post_truncsti16>>
- // Emits: (STRH_POST:i32 GPR:i32:$src, GPR:i32:$base, am3offset:i32:$offset)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_post_truncst(N) &&
- Predicate_post_truncsti16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- SDValue CPTmpN3_1;
- if (SelectAddrMode3Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
- N1.getValueType() == MVT::i32 &&
- N3.getValueType() == MVT::i32) {
- SDNode *Result = Emit_304(N, ARM::STRH_POST, MVT::i32, CPTmpN3_0, CPTmpN3_1);
- return Result;
- }
- }
-
- // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti8>>
- // Emits: (STRB_PRE:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_pre_truncst(N) &&
- Predicate_pre_truncsti8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- SDValue CPTmpN3_1;
- if (SelectAddrMode2Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
- N1.getValueType() == MVT::i32 &&
- N3.getValueType() == MVT::i32) {
- SDNode *Result = Emit_304(N, ARM::STRB_PRE, MVT::i32, CPTmpN3_0, CPTmpN3_1);
- return Result;
- }
- }
-
- // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_post_truncst>><<P:Predicate_post_truncsti8>>
- // Emits: (STRB_POST:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_post_truncst(N) &&
- Predicate_post_truncsti8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- SDValue CPTmpN3_1;
- if (SelectAddrMode2Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
- N1.getValueType() == MVT::i32 &&
- N3.getValueType() == MVT::i32) {
- SDNode *Result = Emit_304(N, ARM::STRB_POST, MVT::i32, CPTmpN3_0, CPTmpN3_1);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_istore(N)) {
-
- // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_istore>><<P:Predicate_pre_store>>
- // Emits: (t2STR_PRE:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
- N1.getValueType() == MVT::i32 &&
- N3.getValueType() == MVT::i32) {
- SDNode *Result = Emit_305(N, ARM::t2STR_PRE, MVT::i32, CPTmpN3_0);
- return Result;
- }
- }
-
- // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_istore>><<P:Predicate_post_store>>
- // Emits: (t2STR_POST:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_post_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
- N1.getValueType() == MVT::i32 &&
- N3.getValueType() == MVT::i32) {
- SDNode *Result = Emit_305(N, ARM::t2STR_POST, MVT::i32, CPTmpN3_0);
- return Result;
- }
- }
- }
- if (Predicate_itruncstore(N)) {
-
- // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti16>>
- // Emits: (t2STRH_PRE:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_truncst(N) &&
- Predicate_pre_truncsti16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
- N1.getValueType() == MVT::i32 &&
- N3.getValueType() == MVT::i32) {
- SDNode *Result = Emit_305(N, ARM::t2STRH_PRE, MVT::i32, CPTmpN3_0);
- return Result;
- }
- }
-
- // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_post_truncst>><<P:Predicate_post_truncsti16>>
- // Emits: (t2STRH_POST:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_post_truncst(N) &&
- Predicate_post_truncsti16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
- N1.getValueType() == MVT::i32 &&
- N3.getValueType() == MVT::i32) {
- SDNode *Result = Emit_305(N, ARM::t2STRH_POST, MVT::i32, CPTmpN3_0);
- return Result;
- }
- }
-
- // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti8>>
- // Emits: (t2STRB_PRE:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_truncst(N) &&
- Predicate_pre_truncsti8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
- N1.getValueType() == MVT::i32 &&
- N3.getValueType() == MVT::i32) {
- SDNode *Result = Emit_305(N, ARM::t2STRB_PRE, MVT::i32, CPTmpN3_0);
- return Result;
- }
- }
-
- // Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_post_truncst>><<P:Predicate_post_truncsti8>>
- // Emits: (t2STRB_POST:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_post_truncst(N) &&
- Predicate_post_truncsti8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
- N1.getValueType() == MVT::i32 &&
- N3.getValueType() == MVT::i32) {
- SDNode *Result = Emit_305(N, ARM::t2STRB_POST, MVT::i32, CPTmpN3_0);
- return Result;
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 88: { // Predicate_atomic_swap_8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_306(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Tmp2, Tmp3, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_307(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, Tmp2, Tmp3, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_STORE(SDNode *N) {
- if ((!Subtarget->isThumb())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N)) {
-
- // Pattern: (st:isVoid GPR:i32:$src, addrmodepc:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (PICSTR:isVoid GPR:i32:$src, addrmodepc:i32:$addr)
- // Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrModePC(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::PICSTR, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
- if (Predicate_truncstore(N)) {
-
- // Pattern: (st:isVoid GPR:i32:$src, addrmodepc:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (PICSTRH:isVoid GPR:i32:$src, addrmodepc:i32:$addr)
- // Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_truncstorei16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrModePC(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::PICSTRH, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid GPR:i32:$src, addrmodepc:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
- // Emits: (PICSTRB:isVoid GPR:i32:$src, addrmodepc:i32:$addr)
- // Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_truncstorei8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrModePC(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::PICSTRB, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid GPR:i32:$src, addrmode2:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (STR:isVoid GPR:i32:$src, addrmode2:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- if (SelectAddrMode2(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_307(N, ARM::STR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
- return Result;
- }
- }
- if (Predicate_truncstore(N)) {
-
- // Pattern: (st:isVoid GPR:i32:$src, addrmode3:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (STRH:isVoid GPR:i32:$src, addrmode3:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_truncstorei16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- if (SelectAddrMode3(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_307(N, ARM::STRH, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid GPR:i32:$src, addrmode2:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
- // Emits: (STRB:isVoid GPR:i32:$src, addrmode2:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_truncstorei8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- if (SelectAddrMode2(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_307(N, ARM::STRB, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N)) {
-
- // Pattern: (st:isVoid tGPR:i32:$src, t_addrmode_s4:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (tSTR:isVoid tGPR:i32:$src, t_addrmode_s4:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- if (SelectThumbAddrModeS4(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_307(N, ARM::tSTR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
- return Result;
- }
- }
- if (Predicate_truncstore(N)) {
-
- // Pattern: (st:isVoid tGPR:i32:$src, t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
- // Emits: (tSTRB:isVoid tGPR:i32:$src, t_addrmode_s1:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_truncstorei8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- if (SelectThumbAddrModeS1(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_307(N, ARM::tSTRB, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid tGPR:i32:$src, t_addrmode_s2:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (tSTRH:isVoid tGPR:i32:$src, t_addrmode_s2:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_truncstorei16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- if (SelectThumbAddrModeS2(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_307(N, ARM::tSTRH, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N)) {
-
- // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (t2STRs:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- if (SelectT2AddrModeSoReg(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_307(N, ARM::t2STRs, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
- return Result;
- }
- }
- if (Predicate_truncstore(N)) {
-
- // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
- // Emits: (t2STRBs:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_truncstorei8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- if (SelectT2AddrModeSoReg(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_307(N, ARM::t2STRBs, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (t2STRHs:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)
- // Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_truncstorei16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- if (SelectT2AddrModeSoReg(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_307(N, ARM::t2STRHs, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2);
- return Result;
- }
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 89: { // Predicate_atomic_swap_16
+ SDNode *N = Node;
- // Pattern: (st:isVoid tGPR:i32:$src, t_addrmode_sp:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (tSTRspi:isVoid tGPR:i32:$src, t_addrmode_sp:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectThumbAddrModeSP(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::tSTRspi, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N)) {
- if (Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
-
- // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (t2STRi12:isVoid GPR:i32:$src, t2addrmode_imm12:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm12(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::t2STRi12, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
-
- // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (t2STRi8:isVoid GPR:i32:$src, t2addrmode_imm8:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm8(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::t2STRi8, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
- if (Predicate_truncstore(N)) {
- if (Predicate_truncstorei8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
-
- // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
- // Emits: (t2STRBi12:isVoid GPR:i32:$src, t2addrmode_imm12:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm12(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::t2STRBi12, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
-
- // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
- // Emits: (t2STRBi8:isVoid GPR:i32:$src, t2addrmode_imm8:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm8(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::t2STRBi8, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
- if (Predicate_truncstorei16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
-
- // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_imm12:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (t2STRHi12:isVoid GPR:i32:$src, t2addrmode_imm12:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm12(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::t2STRHi12, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
-
- // Pattern: (st:isVoid GPR:i32:$src, t2addrmode_imm8:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (t2STRHi8:isVoid GPR:i32:$src, t2addrmode_imm8:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectT2AddrModeImm8(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::t2STRHi8, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasVFP2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrMode5(N, N2, CPTmpN2_0, CPTmpN2_1)) {
-
- // Pattern: (st:isVoid DPR:f64:$src, addrmode5:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (VSTRD:isVoid DPR:f64:$src, addrmode5:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (N1.getValueType() == MVT::f64 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::VSTRD, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
-
- // Pattern: (st:isVoid SPR:f32:$src, addrmode5:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (VSTRS:isVoid SPR:f32:$src, addrmode5:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if (N1.getValueType() == MVT::f32 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::VSTRS, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 90: { // Predicate_atomic_swap_32
+ SDNode *N = Node;
- // Pattern: (st:isVoid QPR:v2f64:$src, addrmode4:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (VSTRQ:isVoid QPR:v2f64:$src, addrmode4:i32:$addr)
- // Pattern complexity = 13 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrMode4(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::v2f64 &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, ARM::VSTRQ, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 91: { // Predicate_atomic_cmp_swap_8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
-DISABLE_INLINE SDNode *Emit_308(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_309(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp2, N1, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_310(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_311(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
-}
-SDNode *Select_ISD_SUB_i32(SDNode *N) {
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (sub:i32 GPR:i32:$a, so_reg:i32:$b)
- // Emits: (SUBrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
- SDNode *Result = Emit_57(N, ARM::SUBrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (sub:i32 so_reg:i32:$b, GPR:i32:$a)
- // Emits: (RSBrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- SDValue CPTmpN0_2;
- if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDNode *Result = Emit_88(N, ARM::RSBrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (sub:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2SUBrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_68(N, ARM::t2SUBrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (sub:i32 t2_so_reg:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2RSBrs:i32 GPR:i32:$rhs, t2_so_reg:i32:$lhs)
- // Pattern complexity = 12 cost = 1 size = 0
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDNode *Result = Emit_311(N, ARM::t2RSBrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
- return Result;
- }
}
+ case 92: { // Predicate_atomic_cmp_swap_16
+ SDNode *N = Node;
- // Pattern: (sub:i32 0:i32, tGPR:i32:$src)
- // Emits: (tRSB:i32 tGPR:i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_309(N, ARM::tRSB, MVT::i32);
- return Result;
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (sub:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (SUBri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N1.getNode())) {
- SDNode *Result = Emit_55(N, ARM::SUBri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (sub:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, GPR:i32:$a)
- // Emits: (RSBri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N0.getNode())) {
- SDNode *Result = Emit_308(N, ARM::RSBri, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (sub:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2SUBri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_t2_so_imm(N1.getNode())) {
- SDNode *Result = Emit_55(N, ARM::t2SUBri, MVT::i32);
- return Result;
- }
-
- // Pattern: (sub:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_4095>>:$rhs)
- // Emits: (t2SUBri12:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm0_4095(N1.getNode())) {
- SDNode *Result = Emit_55(N, ARM::t2SUBri12, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (sub:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$lhs, GPR:i32:$rhs)
- // Emits: (t2RSBri:i32 GPR:i32:$rhs, (imm:i32):$lhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N0.getNode())) {
- SDNode *Result = Emit_310(N, ARM::t2RSBri, MVT::i32);
- return Result;
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
- // Pattern: (sub:i32 GPR:i32:$c, (mul:i32 GPR:i32:$a, GPR:i32:$b))
- // Emits: (MLS:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_77(N, ARM::MLS, MVT::i32);
- return Result;
- }
}
+ case 93: { // Predicate_atomic_cmp_swap_32
+ SDNode *N = Node;
- // Pattern: (sub:i32 GPR:i32:$c, (mulhs:i32 GPR:i32:$a, GPR:i32:$b))
- // Emits: (SMMLS:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MULHS) {
- SDNode *Result = Emit_77(N, ARM::SMMLS, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sub:i32 GPR:i32:$c, (mul:i32 GPR:i32:$a, GPR:i32:$b))
- // Emits: (t2MLS:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_77(N, ARM::t2MLS, MVT::i32);
- return Result;
- }
-
- // Pattern: (sub:i32 GPR:i32:$c, (mulhs:i32 GPR:i32:$a, GPR:i32:$b))
- // Emits: (t2SMMLS:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::MULHS) {
- SDNode *Result = Emit_77(N, ARM::t2SMMLS, MVT::i32);
- return Result;
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
- // Pattern: (sub:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (SUBrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDNode *Result = Emit_56(N, ARM::SUBrr, MVT::i32);
- return Result;
}
-
- // Pattern: (sub:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tSUBrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDNode *Result = Emit_66(N, ARM::tSUBrr, MVT::i32);
- return Result;
}
-
- // Pattern: (sub:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2SUBrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_56(N, ARM::t2SUBrr, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
}
-DISABLE_INLINE SDNode *Emit_312(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, Tmp1, Tmp2);
-}
-SDNode *Select_ISD_SUB_v8i8(SDNode *N) {
-
- // Pattern: (sub:v8i8 (build_vector:v8i8)<<P:Predicate_immAllZerosV>>, DPR:v8i8:$src)
- // Emits: (VNEGs8d:v8i8 DPR:v8i8:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllZerosV(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VNEGs8d, MVT::v8i8);
- return Result;
- }
- }
+bool CheckComplexPattern(SDNode *Root, SDValue N,
+ unsigned PatternNo, SmallVectorImpl<SDValue> &Result) {
+ switch (PatternNo) {
+ default: assert(0 && "Invalid pattern # in table?");
+ case 0:
+ Result.resize(Result.size()+2);
+ return SelectT2ShifterOperandReg(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 1:
+ Result.resize(Result.size()+3);
+ return SelectShifterOperandReg(Root, N, Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 2:
+ Result.resize(Result.size()+3);
+ return SelectAddrMode2(Root, N, Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 3:
+ Result.resize(Result.size()+2);
+ return SelectAddrModePC(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 4:
+ Result.resize(Result.size()+2);
+ return SelectThumbAddrModeRR(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 5:
+ Result.resize(Result.size()+3);
+ return SelectAddrMode3(Root, N, Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 6:
+ Result.resize(Result.size()+3);
+ return SelectThumbAddrModeS4(Root, N, Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 7:
+ Result.resize(Result.size()+3);
+ return SelectThumbAddrModeS1(Root, N, Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 8:
+ Result.resize(Result.size()+3);
+ return SelectThumbAddrModeS2(Root, N, Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 9:
+ Result.resize(Result.size()+3);
+ return SelectT2AddrModeSoReg(Root, N, Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 10:
+ Result.resize(Result.size()+2);
+ return SelectThumbAddrModeSP(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 11:
+ Result.resize(Result.size()+2);
+ return SelectT2AddrModeImm12(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 12:
+ Result.resize(Result.size()+2);
+ return SelectT2AddrModeImm8(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 13:
+ Result.resize(Result.size()+2);
+ return SelectAddrMode5(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 14:
+ Result.resize(Result.size()+2);
+ return SelectAddrMode4(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 15:
+ Result.resize(Result.size()+2);
+ return SelectAddrMode2Offset(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 16:
+ Result.resize(Result.size()+2);
+ return SelectAddrMode3Offset(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 17:
+ Result.resize(Result.size()+1);
+ return SelectT2AddrModeImm8Offset(Root, N, Result[Result.size()-1]);
+ case 18:
+ Result.resize(Result.size()+4);
+ return SelectAddrMode6(Root, N, Result[Result.size()-4], Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ }
+}
+
+SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
+ switch (XFormNo) {
+ default: assert(0 && "Invalid xform # in table?");
+ case 0: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (sub:v8i8 (bitconvert:v8i8)<<P:Predicate_immAllZerosV_bc>>, DPR:v8i8:$src)
- // Emits: (VNEGs8d:v8i8 DPR:f64:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllZerosV_bc(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VNEGs8d, MVT::v8i8);
- return Result;
- }
- }
- if ((Subtarget->hasNEON())) {
-
- // Pattern: (sub:v8i8 DPR:v8i8:$src1, (mul:v8i8 DPR:v8i8:$src2, DPR:v8i8:$src3))
- // Emits: (VMLSv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_125(N, ARM::VMLSv8i8, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (sub:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Emits: (VSUBv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VSUBv8i8, MVT::v8i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
+ return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
-SDNode *Select_ISD_SUB_v16i8(SDNode *N) {
-
- // Pattern: (sub:v16i8 (build_vector:v16i8)<<P:Predicate_immAllZerosV>>, QPR:v16i8:$src)
- // Emits: (VNEGs8q:v16i8 QPR:v16i8:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllZerosV(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VNEGs8q, MVT::v16i8);
- return Result;
- }
}
+ case 1: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (sub:v16i8 (bitconvert:v16i8)<<P:Predicate_immAllZerosV_bc>>, QPR:v16i8:$src)
- // Emits: (VNEGs8q:v16i8 QPR:v16i8:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllZerosV_bc(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VNEGs8q, MVT::v16i8);
- return Result;
- }
- }
- if ((Subtarget->hasNEON())) {
-
- // Pattern: (sub:v16i8 QPR:v16i8:$src1, (mul:v16i8 QPR:v16i8:$src2, QPR:v16i8:$src3))
- // Emits: (VMLSv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_125(N, ARM::VMLSv16i8, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (sub:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Emits: (VSUBv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VSUBv16i8, MVT::v16i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SUB_v4i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (sub:v4i16 DPR:v4i16:$src1, (mul:v4i16 DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane)))
- // Emits: (VMLSslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_129(N, ARM::VMLSslv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
-
- // Pattern: (sub:v4i16 DPR:v4i16:$src1, (mul:v4i16 (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane), DPR:v4i16:$src2))
- // Emits: (VMLSslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_130(N, ARM::VMLSslv4i16, MVT::v4i16);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (sub:v4i16 (build_vector:v4i16)<<P:Predicate_immAllZerosV>>, DPR:v4i16:$src)
- // Emits: (VNEGs16d:v4i16 DPR:v4i16:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllZerosV(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VNEGs16d, MVT::v4i16);
- return Result;
- }
- }
+ return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
- // Pattern: (sub:v4i16 (bitconvert:v4i16)<<P:Predicate_immAllZerosV_bc>>, DPR:v4i16:$src)
- // Emits: (VNEGs16d:v4i16 DPR:f64:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllZerosV_bc(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VNEGs16d, MVT::v4i16);
- return Result;
- }
- }
- if ((Subtarget->hasNEON())) {
-
- // Pattern: (sub:v4i16 DPR:v4i16:$src1, (mul:v4i16 DPR:v4i16:$src2, DPR:v4i16:$src3))
- // Emits: (VMLSv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_125(N, ARM::VMLSv4i16, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (sub:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Emits: (VSUBv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VSUBv4i16, MVT::v4i16);
- return Result;
}
+ case 2: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
-SDNode *Select_ISD_SUB_v8i16(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane)))
- // Emits: (VMLSslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_129(N, ARM::VMLSslv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
-
- // Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2))
- // Emits: (VMLSslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_130(N, ARM::VMLSslv8i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane)))
- // Emits: (VMLSslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_133(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
- return Result;
- }
- }
- }
-
- // Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2))
- // Emits: (VMLSslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_134(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
- return Result;
- }
- }
- }
- }
}
+ case 3: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (sub:v8i16 (build_vector:v8i16)<<P:Predicate_immAllZerosV>>, QPR:v8i16:$src)
- // Emits: (VNEGs16q:v8i16 QPR:v8i16:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllZerosV(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VNEGs16q, MVT::v8i16);
- return Result;
- }
- }
+ unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
- // Pattern: (sub:v8i16 (bitconvert:v8i16)<<P:Predicate_immAllZerosV_bc>>, QPR:v8i16:$src)
- // Emits: (VNEGs16q:v8i16 QPR:v16i8:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllZerosV_bc(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VNEGs16q, MVT::v8i16);
- return Result;
- }
}
- if ((Subtarget->hasNEON())) {
-
- // Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, QPR:v8i16:$src3))
- // Emits: (VMLSv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_125(N, ARM::VMLSv8i16, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (sub:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Emits: (VSUBv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VSUBv8i16, MVT::v8i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
+ case 4: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
-SDNode *Select_ISD_SUB_v2i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (sub:v2i32 DPR:v2i32:$src1, (mul:v2i32 DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)))
- // Emits: (VMLSslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_129(N, ARM::VMLSslv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
-
- // Pattern: (sub:v2i32 DPR:v2i32:$src1, (mul:v2i32 (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), DPR:v2i32:$src2))
- // Emits: (VMLSslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_130(N, ARM::VMLSslv2i32, MVT::v2i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (sub:v2i32 (build_vector:v2i32)<<P:Predicate_immAllZerosV>>, DPR:v2i32:$src)
- // Emits: (VNEGs32d:v2i32 DPR:v2i32:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllZerosV(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VNEGs32d, MVT::v2i32);
- return Result;
- }
- }
+ unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
- // Pattern: (sub:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllZerosV_bc>>, DPR:v2i32:$src)
- // Emits: (VNEGs32d:v2i32 DPR:f64:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllZerosV_bc(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VNEGs32d, MVT::v2i32);
- return Result;
- }
- }
- if ((Subtarget->hasNEON())) {
-
- // Pattern: (sub:v2i32 DPR:v2i32:$src1, (mul:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src3))
- // Emits: (VMLSv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_125(N, ARM::VMLSv2i32, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (sub:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VSUBv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VSUBv2i32, MVT::v2i32);
- return Result;
}
+ case 5: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
-SDNode *Select_ISD_SUB_v4i32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)))
- // Emits: (VMLSslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_129(N, ARM::VMLSslv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2))
- // Emits: (VMLSslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_130(N, ARM::VMLSslv4i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane)))
- // Emits: (VMLSslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant &&
- N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_137(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2))
- // Emits: (VMLSslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
- // Pattern complexity = 12 cost = 2 size = 0
- if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_138(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
- return Result;
- }
- }
- }
- }
}
+ case 6: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (sub:v4i32 (build_vector:v4i32)<<P:Predicate_immAllZerosV>>, QPR:v4i32:$src)
- // Emits: (VNEGs32q:v4i32 QPR:v4i32:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllZerosV(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VNEGs32q, MVT::v4i32);
- return Result;
- }
- }
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
- // Pattern: (sub:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllZerosV_bc>>, QPR:v4i32:$src)
- // Emits: (VNEGs32q:v4i32 QPR:v16i8:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllZerosV_bc(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VNEGs32q, MVT::v4i32);
- return Result;
- }
- }
- if ((Subtarget->hasNEON())) {
-
- // Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src3))
- // Emits: (VMLSv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::MUL) {
- SDNode *Result = Emit_125(N, ARM::VMLSv4i32, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (sub:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VSUBv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_44(N, ARM::VSUBv4i32, MVT::v4i32);
- return Result;
}
+ case 7: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
-SDNode *Select_ISD_SUB_v1i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_44(N, ARM::VSUBv1i64, MVT::v1i64);
- return Result;
}
+ case 8: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
-SDNode *Select_ISD_SUB_v2i64(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_44(N, ARM::VSUBv2i64, MVT::v2i64);
- return Result;
}
+ case 9: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_313(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_314(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, Tmp1, Tmp2);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_315(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_SUBC_i32(SDNode *N) {
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (subc:i32 GPR:i32:$a, so_reg:i32:$b)
- // Emits: (SUBSrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
- SDNode *Result = Emit_143(N, ARM::SUBSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (subc:i32 so_reg:i32:$b, GPR:i32:$a)
- // Emits: (RSBSrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- SDValue CPTmpN0_2;
- if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDNode *Result = Emit_148(N, ARM::RSBSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (subc:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2SUBSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_144(N, ARM::t2SUBSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (subc:i32 t2_so_reg:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2RSBSrs:i32 GPR:i32:$rhs, t2_so_reg:i32:$lhs)
- // Pattern complexity = 12 cost = 1 size = 0
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDNode *Result = Emit_315(N, ARM::t2RSBSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
- return Result;
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (subc:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (SUBSri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N1.getNode())) {
- SDNode *Result = Emit_141(N, ARM::SUBSri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (subc:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, GPR:i32:$a)
- // Emits: (RSBSri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N0.getNode())) {
- SDNode *Result = Emit_313(N, ARM::RSBSri, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (subc:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2SUBSri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N1.getNode())) {
- SDNode *Result = Emit_141(N, ARM::t2SUBSri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (subc:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$lhs, GPR:i32:$rhs)
- // Emits: (t2RSBSri:i32 GPR:i32:$rhs, (imm:i32):$lhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N0.getNode())) {
- SDNode *Result = Emit_314(N, ARM::t2RSBSri, MVT::i32);
- return Result;
- }
- }
+ return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
- // Pattern: (subc:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (SUBSrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDNode *Result = Emit_142(N, ARM::SUBSrr, MVT::i32);
- return Result;
}
+ case 10: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (subc:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2SUBSrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_142(N, ARM::t2SUBSrr, MVT::i32);
- return Result;
- }
+ return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
- // Pattern: (subc:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tSUBrr:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDNode *Result = Emit_146(N, ARM::tSUBrr, MVT::i32);
- return Result;
}
+ case 11: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
-DISABLE_INLINE SDNode *Emit_316(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 6);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_317(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, Tmp1, InFlag);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_SUBE_i32(SDNode *N) {
-
- // Pattern: (sube:i32 GPR:i32:$a, so_reg:i32:$b)
- // Emits: (SBCrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
- SDNode *Result = Emit_152(N, ARM::SBCrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
}
+ case 12: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (sube:i32 GPR:i32:$a, so_reg:i32:$b)
- // Emits: (SBCSSrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
- SDNode *Result = Emit_155(N, ARM::SBCSSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- SDValue CPTmpN0_2;
- if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
-
- // Pattern: (sube:i32 so_reg:i32:$b, GPR:i32:$a)
- // Emits: (RSCrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDNode *Result = Emit_159(N, ARM::RSCrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
-
- // Pattern: (sube:i32 so_reg:i32:$b, GPR:i32:$a)
- // Emits: (RSCSrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- SDNode *Result = Emit_160(N, ARM::RSCSrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
- }
+ return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
- // Pattern: (sube:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2SBCrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_157(N, ARM::t2SBCrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
}
+ case 13: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (sube:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2SBCSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_158(N, ARM::t2SBCSrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
+ unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
- // Pattern: (sube:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (SBCri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N1.getNode())) {
- SDNode *Result = Emit_150(N, ARM::SBCri, MVT::i32);
- return Result;
- }
}
+ case 14: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (sube:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (SBCSSri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N1.getNode())) {
- SDNode *Result = Emit_153(N, ARM::SBCSSri, MVT::i32);
- return Result;
- }
- }
- if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm(N0.getNode())) {
-
- // Pattern: (sube:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, GPR:i32:$a)
- // Emits: (RSCri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDNode *Result = Emit_316(N, ARM::RSCri, MVT::i32);
- return Result;
- }
-
- // Pattern: (sube:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, GPR:i32:$a)
- // Emits: (RSCSri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- SDNode *Result = Emit_317(N, ARM::RSCSri, MVT::i32);
- return Result;
- }
- }
+ unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
- // Pattern: (sube:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2SBCri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N1.getNode())) {
- SDNode *Result = Emit_150(N, ARM::t2SBCri, MVT::i32);
- return Result;
- }
}
+ case 15: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (sube:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2SBCSri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N1.getNode())) {
- SDNode *Result = Emit_153(N, ARM::t2SBCSri, MVT::i32);
- return Result;
- }
- }
+ unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
- // Pattern: (sube:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (SBCrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
- SDNode *Result = Emit_151(N, ARM::SBCrr, MVT::i32);
- return Result;
}
+ case 16: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (sube:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (SBCSSrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
- SDNode *Result = Emit_154(N, ARM::SBCSSrr, MVT::i32);
- return Result;
- }
+ unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
- // Pattern: (sube:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tSBC:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDNode *Result = Emit_156(N, ARM::tSBC, MVT::i32);
- return Result;
}
+ case 17: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (sube:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2SBCrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
- SDNode *Result = Emit_151(N, ARM::t2SBCrr, MVT::i32);
- return Result;
- }
+ return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
- // Pattern: (sube:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2SBCSrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
- SDNode *Result = Emit_154(N, ARM::t2SBCSrr, MVT::i32);
- return Result;
}
+ case 18: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
-SDNode *Select_ISD_UINT_TO_FP_v2f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_31(N, ARM::VCVTu2fd, MVT::v2f32);
- return Result;
- }
}
+ case 19: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
-SDNode *Select_ISD_UINT_TO_FP_v4f32(SDNode *N) {
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_31(N, ARM::VCVTu2fq, MVT::v4f32);
- return Result;
- }
}
+ case 20: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
-DISABLE_INLINE SDNode *Emit_318(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_319(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_320(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, N0, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_321(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_322(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { CPTmpN0_0, CPTmpN0_1, Tmp1, Tmp2 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_323(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { Tmp0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ISD_XOR_i32(SDNode *N) {
-
- // Pattern: (xor:i32 so_reg:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
- // Emits: (MVNs:i32 so_reg:i32:$src)
- // Pattern complexity = 19 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- SDValue CPTmpN0_2;
- if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_319(N, ARM::MVNs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
- }
}
+ case 21: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (xor:i32 t2_so_reg:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
- // Emits: (t2MVNs:i32 t2_so_reg:i32:$src)
- // Pattern complexity = 17 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_322(N, ARM::t2MVNs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
- return Result;
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (xor:i32 GPR:i32:$a, so_reg:i32:$b)
- // Emits: (EORrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2)) {
- SDNode *Result = Emit_57(N, ARM::EORrs, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
-
- // Pattern: (xor:i32 so_reg:i32:$b, GPR:i32:$a)
- // Emits: (EORrs:i32 GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- SDValue CPTmpN0_2;
- if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDNode *Result = Emit_88(N, ARM::EORrs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (xor:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2EORrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_68(N, ARM::t2EORrs, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
- // Emits: (t2MVNi:i32 (imm:i32):$src)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N0.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_321(N, ARM::t2MVNi, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (xor:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
- // Emits: (t2EORrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
- {
- SDValue CPTmpN0_0;
- SDValue CPTmpN0_1;
- if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDNode *Result = Emit_103(N, ARM::t2EORrs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
- return Result;
- }
- }
-
- // Pattern: (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_t2_so_imm>>:$src)
- // Emits: (t2MVNi:i32 (imm:i32):$src)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N0.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N1.getNode())) {
- SDNode *Result = Emit_323(N, ARM::t2MVNi, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (xor:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
- // Emits: (t2MVNr:i32 GPR:i32:$src)
- // Pattern complexity = 8 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_292(N, ARM::t2MVNr, MVT::i32);
- return Result;
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (xor:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
- // Emits: (EORri:i32 GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_so_imm(N1.getNode())) {
- SDNode *Result = Emit_55(N, ARM::EORri, MVT::i32);
- return Result;
- }
-
- // Pattern: (xor:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
- // Emits: (MVNr:i32 GPR:i32:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_318(N, ARM::MVNr, MVT::i32);
- return Result;
- }
- }
- }
+ return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
- // Pattern: (xor:i32 tGPR:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
- // Emits: (tMVN:i32 tGPR:i32:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_320(N, ARM::tMVN, MVT::i32);
- return Result;
- }
- }
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (xor:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2EORri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_t2_so_imm(N1.getNode())) {
- SDNode *Result = Emit_55(N, ARM::t2EORri, MVT::i32);
- return Result;
- }
-
- // Pattern: (xor:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_t2_so_imm2part>>:$RHS)
- // Emits: (t2EORri:i32 (t2EORri:i32 GPR:i32:$LHS, (t2_so_imm2part_1:i32 (imm:i32):$RHS)), (t2_so_imm2part_2:i32 (imm:i32):$RHS))
- // Pattern complexity = 7 cost = 2 size = 0
- if (Predicate_t2_so_imm2part(N1.getNode())) {
- SDNode *Result = Emit_71(N, ARM::t2EORri, ARM::t2EORri, MVT::i32, MVT::i32);
- return Result;
- }
- }
- }
- if ((!Subtarget->isThumb())) {
-
- // Pattern: (xor:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_so_imm2part>>:$RHS)
- // Emits: (EORri:i32 (EORri:i32 GPR:i32:$LHS, (so_imm2part_1:i32 (imm:i32):$RHS)), (so_imm2part_2:i32 (imm:i32):$RHS))
- // Pattern complexity = 7 cost = 2 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_so_imm2part(N1.getNode())) {
- SDNode *Result = Emit_74(N, ARM::EORri, ARM::EORri, MVT::i32, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (xor:i32 GPR:i32:$a, GPR:i32:$b)
- // Emits: (EORrr:i32 GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_56(N, ARM::EORrr, MVT::i32);
- return Result;
}
+ case 22: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (xor:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Emits: (tEOR:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDNode *Result = Emit_66(N, ARM::tEOR, MVT::i32);
- return Result;
- }
+ return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
- // Pattern: (xor:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Emits: (t2EORrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDNode *Result = Emit_56(N, ARM::t2EORrr, MVT::i32);
- return Result;
}
+ case 23: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
-SDNode *Select_ISD_XOR_v2i32(SDNode *N) {
-
- // Pattern: (xor:v2i32 DPR:v2i32:$src, (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)
- // Emits: (VMVNd:v2i32 DPR:v2i32:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N1.getNode())) {
- SDNode *Result = Emit_292(N, ARM::VMVNd, MVT::v2i32);
- return Result;
- }
}
+ case 24: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (xor:v2i32 DPR:v2i32:$src, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)
- // Emits: (VMVNd:v2i32 DPR:f64:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N1.getNode())) {
- SDNode *Result = Emit_292(N, ARM::VMVNd, MVT::v2i32);
- return Result;
- }
- }
+ unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
- // Pattern: (xor:v2i32 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>, DPR:v2i32:$src)
- // Emits: (VMVNd:v2i32 DPR:v2i32:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VMVNd, MVT::v2i32);
- return Result;
- }
}
+ case 25: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src)
- // Emits: (VMVNd:v2i32 DPR:f64:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VMVNd, MVT::v2i32);
- return Result;
- }
- }
+ return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
- // Pattern: (xor:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Emits: (VEORd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_44(N, ARM::VEORd, MVT::v2i32);
- return Result;
}
+ case 26: {
+ SDNode *N = V.getNode();
- CannotYetSelect(N);
- return NULL;
-}
+ return ARM::getVMOVImm(N, 1, *CurDAG);
-SDNode *Select_ISD_XOR_v4i32(SDNode *N) {
-
- // Pattern: (xor:v4i32 QPR:v4i32:$src, (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)
- // Emits: (VMVNq:v4i32 QPR:v4i32:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N1.getNode())) {
- SDNode *Result = Emit_292(N, ARM::VMVNq, MVT::v4i32);
- return Result;
- }
}
+ case 27: {
+ SDNode *N = V.getNode();
- // Pattern: (xor:v4i32 QPR:v4i32:$src, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)
- // Emits: (VMVNq:v4i32 QPR:v16i8:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N1.getNode())) {
- SDNode *Result = Emit_292(N, ARM::VMVNq, MVT::v4i32);
- return Result;
- }
- }
+ return ARM::getVMOVImm(N, 2, *CurDAG);
- // Pattern: (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, QPR:v4i32:$src)
- // Emits: (VMVNq:v4i32 QPR:v4i32:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VMVNq, MVT::v4i32);
- return Result;
- }
}
+ case 28: {
+ SDNode *N = V.getNode();
- // Pattern: (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src)
- // Emits: (VMVNq:v4i32 QPR:v16i8:$src)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N0.getNode())) {
- SDNode *Result = Emit_312(N, ARM::VMVNq, MVT::v4i32);
- return Result;
- }
- }
+ return ARM::getVMOVImm(N, 4, *CurDAG);
- // Pattern: (xor:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Emits: (VEORq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->hasNEON())) {
- SDNode *Result = Emit_44(N, ARM::VEORq, MVT::v4i32);
- return Result;
}
+ case 29: {
+ SDNode *N = V.getNode();
- CannotYetSelect(N);
- return NULL;
-}
+ return ARM::getVMOVImm(N, 8, *CurDAG);
-// The main instruction selector code.
-SDNode *SelectCode(SDNode *N) {
- MVT::SimpleValueType NVT = N->getValueType(0).getSimpleVT().SimpleTy;
- switch (N->getOpcode()) {
- default:
- assert(!N->isMachineOpcode() && "Node already selected!");
- break;
- case ISD::EntryToken: // These nodes remain the same.
- case ISD::BasicBlock:
- case ISD::Register:
- case ISD::HANDLENODE:
- case ISD::TargetConstant:
- case ISD::TargetConstantFP:
- case ISD::TargetConstantPool:
- case ISD::TargetFrameIndex:
- case ISD::TargetExternalSymbol:
- case ISD::TargetBlockAddress:
- case ISD::TargetJumpTable:
- case ISD::TargetGlobalTLSAddress:
- case ISD::TargetGlobalAddress:
- case ISD::TokenFactor:
- case ISD::CopyFromReg:
- case ISD::CopyToReg: {
- return NULL;
- }
- case ISD::AssertSext:
- case ISD::AssertZext: {
- ReplaceUses(SDValue(N, 0), N->getOperand(0));
- return NULL;
- }
- case ISD::INLINEASM: return Select_INLINEASM(N);
- case ISD::EH_LABEL: return Select_EH_LABEL(N);
- case ISD::UNDEF: return Select_UNDEF(N);
- case ARMISD::BR2_JT: {
- return Select_ARMISD_BR2_JT(N);
- break;
- }
- case ARMISD::BR_JT: {
- return Select_ARMISD_BR_JT(N);
- break;
- }
- case ARMISD::CALL: {
- return Select_ARMISD_CALL(N);
- break;
- }
- case ARMISD::CALL_NOLINK: {
- return Select_ARMISD_CALL_NOLINK(N);
- break;
- }
- case ARMISD::CALL_PRED: {
- return Select_ARMISD_CALL_PRED(N);
- break;
- }
- case ARMISD::CMP: {
- return Select_ARMISD_CMP(N);
- break;
- }
- case ARMISD::CMPFP: {
- return Select_ARMISD_CMPFP(N);
- break;
- }
- case ARMISD::CMPFPw0: {
- return Select_ARMISD_CMPFPw0(N);
- break;
- }
- case ARMISD::CMPZ: {
- return Select_ARMISD_CMPZ(N);
- break;
- }
- case ARMISD::EH_SJLJ_SETJMP: {
- switch (NVT) {
- case MVT::i32:
- return Select_ARMISD_EH_SJLJ_SETJMP_i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::FMSTAT: {
- return Select_ARMISD_FMSTAT(N);
- break;
- }
- case ARMISD::FTOSI: {
- switch (NVT) {
- case MVT::f32:
- return Select_ARMISD_FTOSI_f32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::FTOUI: {
- switch (NVT) {
- case MVT::f32:
- return Select_ARMISD_FTOUI_f32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::MEMBARRIER: {
- return Select_ARMISD_MEMBARRIER(N);
- break;
- }
- case ARMISD::PIC_ADD: {
- switch (NVT) {
- case MVT::i32:
- return Select_ARMISD_PIC_ADD_i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::RBIT: {
- switch (NVT) {
- case MVT::i32:
- return Select_ARMISD_RBIT_i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::RET_FLAG: {
- return Select_ARMISD_RET_FLAG(N);
- break;
- }
- case ARMISD::RRX: {
- switch (NVT) {
- case MVT::i32:
- return Select_ARMISD_RRX_i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::SITOF: {
- switch (NVT) {
- case MVT::f32:
- return Select_ARMISD_SITOF_f32(N);
- case MVT::f64:
- return Select_ARMISD_SITOF_f64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::SRA_FLAG: {
- switch (NVT) {
- case MVT::i32:
- return Select_ARMISD_SRA_FLAG_i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::SRL_FLAG: {
- switch (NVT) {
- case MVT::i32:
- return Select_ARMISD_SRL_FLAG_i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::SYNCBARRIER: {
- return Select_ARMISD_SYNCBARRIER(N);
- break;
- }
- case ARMISD::THREAD_POINTER: {
- switch (NVT) {
- case MVT::i32:
- return Select_ARMISD_THREAD_POINTER_i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::UITOF: {
- switch (NVT) {
- case MVT::f32:
- return Select_ARMISD_UITOF_f32(N);
- case MVT::f64:
- return Select_ARMISD_UITOF_f64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VCEQ: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VCEQ_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VCEQ_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VCEQ_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VCEQ_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VCEQ_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VCEQ_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VCGE: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VCGE_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VCGE_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VCGE_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VCGE_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VCGE_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VCGE_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VCGEU: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VCGEU_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VCGEU_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VCGEU_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VCGEU_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VCGEU_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VCGEU_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VCGT: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VCGT_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VCGT_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VCGT_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VCGT_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VCGT_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VCGT_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VCGTU: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VCGTU_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VCGTU_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VCGTU_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VCGTU_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VCGTU_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VCGTU_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VDUP: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VDUP_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VDUP_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VDUP_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VDUP_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VDUP_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VDUP_v4i32(N);
- case MVT::v2f32:
- return Select_ARMISD_VDUP_v2f32(N);
- case MVT::v4f32:
- return Select_ARMISD_VDUP_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VDUPLANE: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VDUPLANE_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VDUPLANE_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VDUPLANE_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VDUPLANE_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VDUPLANE_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VDUPLANE_v4i32(N);
- case MVT::v2i64:
- return Select_ARMISD_VDUPLANE_v2i64(N);
- case MVT::v2f32:
- return Select_ARMISD_VDUPLANE_v2f32(N);
- case MVT::v4f32:
- return Select_ARMISD_VDUPLANE_v4f32(N);
- case MVT::v2f64:
- return Select_ARMISD_VDUPLANE_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VEXT: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VEXT_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VEXT_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VEXT_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VEXT_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VEXT_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VEXT_v4i32(N);
- case MVT::v2f32:
- return Select_ARMISD_VEXT_v2f32(N);
- case MVT::v4f32:
- return Select_ARMISD_VEXT_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VGETLANEs: {
- switch (NVT) {
- case MVT::i32:
- return Select_ARMISD_VGETLANEs_i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VGETLANEu: {
- switch (NVT) {
- case MVT::i32:
- return Select_ARMISD_VGETLANEu_i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VMOVDRR: {
- switch (NVT) {
- case MVT::f64:
- return Select_ARMISD_VMOVDRR_f64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VQRSHRNs: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VQRSHRNs_v8i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VQRSHRNs_v4i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VQRSHRNs_v2i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VQRSHRNsu: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VQRSHRNsu_v8i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VQRSHRNsu_v4i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VQRSHRNsu_v2i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VQRSHRNu: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VQRSHRNu_v8i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VQRSHRNu_v4i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VQRSHRNu_v2i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VQSHLs: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VQSHLs_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VQSHLs_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VQSHLs_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VQSHLs_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VQSHLs_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VQSHLs_v4i32(N);
- case MVT::v1i64:
- return Select_ARMISD_VQSHLs_v1i64(N);
- case MVT::v2i64:
- return Select_ARMISD_VQSHLs_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VQSHLsu: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VQSHLsu_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VQSHLsu_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VQSHLsu_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VQSHLsu_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VQSHLsu_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VQSHLsu_v4i32(N);
- case MVT::v1i64:
- return Select_ARMISD_VQSHLsu_v1i64(N);
- case MVT::v2i64:
- return Select_ARMISD_VQSHLsu_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VQSHLu: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VQSHLu_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VQSHLu_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VQSHLu_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VQSHLu_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VQSHLu_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VQSHLu_v4i32(N);
- case MVT::v1i64:
- return Select_ARMISD_VQSHLu_v1i64(N);
- case MVT::v2i64:
- return Select_ARMISD_VQSHLu_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VQSHRNs: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VQSHRNs_v8i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VQSHRNs_v4i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VQSHRNs_v2i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VQSHRNsu: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VQSHRNsu_v8i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VQSHRNsu_v4i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VQSHRNsu_v2i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VQSHRNu: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VQSHRNu_v8i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VQSHRNu_v4i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VQSHRNu_v2i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VREV16: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VREV16_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VREV16_v16i8(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VREV32: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VREV32_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VREV32_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VREV32_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VREV32_v8i16(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VREV64: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VREV64_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VREV64_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VREV64_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VREV64_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VREV64_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VREV64_v4i32(N);
- case MVT::v2f32:
- return Select_ARMISD_VREV64_v2f32(N);
- case MVT::v4f32:
- return Select_ARMISD_VREV64_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VRSHRN: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VRSHRN_v8i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VRSHRN_v4i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VRSHRN_v2i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VRSHRs: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VRSHRs_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VRSHRs_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VRSHRs_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VRSHRs_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VRSHRs_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VRSHRs_v4i32(N);
- case MVT::v1i64:
- return Select_ARMISD_VRSHRs_v1i64(N);
- case MVT::v2i64:
- return Select_ARMISD_VRSHRs_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VRSHRu: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VRSHRu_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VRSHRu_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VRSHRu_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VRSHRu_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VRSHRu_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VRSHRu_v4i32(N);
- case MVT::v1i64:
- return Select_ARMISD_VRSHRu_v1i64(N);
- case MVT::v2i64:
- return Select_ARMISD_VRSHRu_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VSHL: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VSHL_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VSHL_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VSHL_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VSHL_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VSHL_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VSHL_v4i32(N);
- case MVT::v1i64:
- return Select_ARMISD_VSHL_v1i64(N);
- case MVT::v2i64:
- return Select_ARMISD_VSHL_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VSHLLi: {
- switch (NVT) {
- case MVT::v8i16:
- return Select_ARMISD_VSHLLi_v8i16(N);
- case MVT::v4i32:
- return Select_ARMISD_VSHLLi_v4i32(N);
- case MVT::v2i64:
- return Select_ARMISD_VSHLLi_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VSHLLs: {
- switch (NVT) {
- case MVT::v8i16:
- return Select_ARMISD_VSHLLs_v8i16(N);
- case MVT::v4i32:
- return Select_ARMISD_VSHLLs_v4i32(N);
- case MVT::v2i64:
- return Select_ARMISD_VSHLLs_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VSHLLu: {
- switch (NVT) {
- case MVT::v8i16:
- return Select_ARMISD_VSHLLu_v8i16(N);
- case MVT::v4i32:
- return Select_ARMISD_VSHLLu_v4i32(N);
- case MVT::v2i64:
- return Select_ARMISD_VSHLLu_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VSHRN: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VSHRN_v8i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VSHRN_v4i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VSHRN_v2i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VSHRs: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VSHRs_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VSHRs_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VSHRs_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VSHRs_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VSHRs_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VSHRs_v4i32(N);
- case MVT::v1i64:
- return Select_ARMISD_VSHRs_v1i64(N);
- case MVT::v2i64:
- return Select_ARMISD_VSHRs_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VSHRu: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VSHRu_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VSHRu_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VSHRu_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VSHRu_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VSHRu_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VSHRu_v4i32(N);
- case MVT::v1i64:
- return Select_ARMISD_VSHRu_v1i64(N);
- case MVT::v2i64:
- return Select_ARMISD_VSHRu_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VSLI: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VSLI_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VSLI_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VSLI_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VSLI_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VSLI_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VSLI_v4i32(N);
- case MVT::v1i64:
- return Select_ARMISD_VSLI_v1i64(N);
- case MVT::v2i64:
- return Select_ARMISD_VSLI_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VSRI: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VSRI_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VSRI_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VSRI_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VSRI_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VSRI_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VSRI_v4i32(N);
- case MVT::v1i64:
- return Select_ARMISD_VSRI_v1i64(N);
- case MVT::v2i64:
- return Select_ARMISD_VSRI_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::VTST: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ARMISD_VTST_v8i8(N);
- case MVT::v16i8:
- return Select_ARMISD_VTST_v16i8(N);
- case MVT::v4i16:
- return Select_ARMISD_VTST_v4i16(N);
- case MVT::v8i16:
- return Select_ARMISD_VTST_v8i16(N);
- case MVT::v2i32:
- return Select_ARMISD_VTST_v2i32(N);
- case MVT::v4i32:
- return Select_ARMISD_VTST_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::Wrapper: {
- switch (NVT) {
- case MVT::i32:
- return Select_ARMISD_Wrapper_i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::WrapperJT: {
- switch (NVT) {
- case MVT::i32:
- return Select_ARMISD_WrapperJT_i32(N);
- default:
- break;
- }
- break;
- }
- case ARMISD::tCALL: {
- return Select_ARMISD_tCALL(N);
- break;
- }
- case ISD::ADD: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ADD_i32(N);
- case MVT::v8i8:
- return Select_ISD_ADD_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_ADD_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_ADD_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_ADD_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_ADD_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_ADD_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_ADD_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_ADD_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ADDC: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ADDC_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ADDE: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ADDE_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::AND: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_AND_i32(N);
- case MVT::v2i32:
- return Select_ISD_AND_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_AND_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_CMP_SWAP: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_CMP_SWAP_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_ADD: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_ADD_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_AND: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_AND_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_NAND: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_NAND_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_OR: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_OR_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_SUB: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_SUB_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_XOR: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_XOR_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_SWAP: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_SWAP_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::BIT_CONVERT: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_BIT_CONVERT_i32(N);
- case MVT::f32:
- return Select_ISD_BIT_CONVERT_f32(N);
- case MVT::f64:
- return Select_ISD_BIT_CONVERT_f64(N);
- case MVT::v8i8:
- return Select_ISD_BIT_CONVERT_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_BIT_CONVERT_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_BIT_CONVERT_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_BIT_CONVERT_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_BIT_CONVERT_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_BIT_CONVERT_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_BIT_CONVERT_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_BIT_CONVERT_v2i64(N);
- case MVT::v2f32:
- return Select_ISD_BIT_CONVERT_v2f32(N);
- case MVT::v4f32:
- return Select_ISD_BIT_CONVERT_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_BIT_CONVERT_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::BR: {
- return Select_ISD_BR(N);
- break;
- }
- case ISD::BRIND: {
- return Select_ISD_BRIND(N);
- break;
- }
- case ISD::BSWAP: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_BSWAP_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::BUILD_VECTOR: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ISD_BUILD_VECTOR_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_BUILD_VECTOR_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_BUILD_VECTOR_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_BUILD_VECTOR_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_BUILD_VECTOR_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_BUILD_VECTOR_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_BUILD_VECTOR_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_BUILD_VECTOR_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::CALLSEQ_END: {
- return Select_ISD_CALLSEQ_END(N);
- break;
- }
- case ISD::CALLSEQ_START: {
- return Select_ISD_CALLSEQ_START(N);
- break;
- }
- case ISD::CTLZ: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_CTLZ_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::Constant: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_Constant_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ConstantFP: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_ConstantFP_f32(N);
- case MVT::f64:
- return Select_ISD_ConstantFP_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::EXTRACT_VECTOR_ELT: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_EXTRACT_VECTOR_ELT_i32(N);
- case MVT::f32:
- return Select_ISD_EXTRACT_VECTOR_ELT_f32(N);
- case MVT::f64:
- return Select_ISD_EXTRACT_VECTOR_ELT_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FABS: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FABS_f32(N);
- case MVT::f64:
- return Select_ISD_FABS_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FADD: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FADD_f32(N);
- case MVT::f64:
- return Select_ISD_FADD_f64(N);
- case MVT::v2f32:
- return Select_ISD_FADD_v2f32(N);
- case MVT::v4f32:
- return Select_ISD_FADD_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::FDIV: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FDIV_f32(N);
- case MVT::f64:
- return Select_ISD_FDIV_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FMUL: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FMUL_f32(N);
- case MVT::f64:
- return Select_ISD_FMUL_f64(N);
- case MVT::v2f32:
- return Select_ISD_FMUL_v2f32(N);
- case MVT::v4f32:
- return Select_ISD_FMUL_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::FNEG: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FNEG_f32(N);
- case MVT::f64:
- return Select_ISD_FNEG_f64(N);
- case MVT::v2f32:
- return Select_ISD_FNEG_v2f32(N);
- case MVT::v4f32:
- return Select_ISD_FNEG_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::FP_EXTEND: {
- switch (NVT) {
- case MVT::f64:
- return Select_ISD_FP_EXTEND_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FP_ROUND: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FP_ROUND_f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::FP_TO_SINT: {
- switch (NVT) {
- case MVT::v2i32:
- return Select_ISD_FP_TO_SINT_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_FP_TO_SINT_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::FP_TO_UINT: {
- switch (NVT) {
- case MVT::v2i32:
- return Select_ISD_FP_TO_UINT_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_FP_TO_UINT_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::FSQRT: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FSQRT_f32(N);
- case MVT::f64:
- return Select_ISD_FSQRT_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FSUB: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FSUB_f32(N);
- case MVT::f64:
- return Select_ISD_FSUB_f64(N);
- case MVT::v2f32:
- return Select_ISD_FSUB_v2f32(N);
- case MVT::v4f32:
- return Select_ISD_FSUB_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::INSERT_VECTOR_ELT: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ISD_INSERT_VECTOR_ELT_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_INSERT_VECTOR_ELT_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_INSERT_VECTOR_ELT_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_INSERT_VECTOR_ELT_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_INSERT_VECTOR_ELT_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_INSERT_VECTOR_ELT_v4i32(N);
- case MVT::v2f32:
- return Select_ISD_INSERT_VECTOR_ELT_v2f32(N);
- case MVT::v4f32:
- return Select_ISD_INSERT_VECTOR_ELT_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_INSERT_VECTOR_ELT_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::INTRINSIC_VOID: {
- return Select_ISD_INTRINSIC_VOID(N);
- break;
- }
- case ISD::INTRINSIC_WO_CHAIN: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ISD_INTRINSIC_WO_CHAIN_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_INTRINSIC_WO_CHAIN_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_INTRINSIC_WO_CHAIN_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_INTRINSIC_WO_CHAIN_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_INTRINSIC_WO_CHAIN_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_INTRINSIC_WO_CHAIN_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_INTRINSIC_WO_CHAIN_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_INTRINSIC_WO_CHAIN_v2i64(N);
- case MVT::v2f32:
- return Select_ISD_INTRINSIC_WO_CHAIN_v2f32(N);
- case MVT::v4f32:
- return Select_ISD_INTRINSIC_WO_CHAIN_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::INTRINSIC_W_CHAIN: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ISD_INTRINSIC_W_CHAIN_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_INTRINSIC_W_CHAIN_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_INTRINSIC_W_CHAIN_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_INTRINSIC_W_CHAIN_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_INTRINSIC_W_CHAIN_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_INTRINSIC_W_CHAIN_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_INTRINSIC_W_CHAIN_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_INTRINSIC_W_CHAIN_v2i64(N);
- case MVT::v2f32:
- return Select_ISD_INTRINSIC_W_CHAIN_v2f32(N);
- case MVT::v4f32:
- return Select_ISD_INTRINSIC_W_CHAIN_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::LOAD: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_LOAD_i32(N);
- case MVT::f32:
- return Select_ISD_LOAD_f32(N);
- case MVT::f64:
- return Select_ISD_LOAD_f64(N);
- case MVT::v2f64:
- return Select_ISD_LOAD_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::MUL: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_MUL_i32(N);
- case MVT::v8i8:
- return Select_ISD_MUL_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_MUL_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_MUL_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_MUL_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_MUL_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_MUL_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::MULHS: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_MULHS_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::OR: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_OR_i32(N);
- case MVT::v2i32:
- return Select_ISD_OR_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_OR_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ROTR: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ROTR_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::SCALAR_TO_VECTOR: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ISD_SCALAR_TO_VECTOR_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_SCALAR_TO_VECTOR_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_SCALAR_TO_VECTOR_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_SCALAR_TO_VECTOR_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_SCALAR_TO_VECTOR_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_SCALAR_TO_VECTOR_v4i32(N);
- case MVT::v2f32:
- return Select_ISD_SCALAR_TO_VECTOR_v2f32(N);
- case MVT::v4f32:
- return Select_ISD_SCALAR_TO_VECTOR_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_SCALAR_TO_VECTOR_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SHL: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SHL_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::SIGN_EXTEND_INREG: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SIGN_EXTEND_INREG_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::SINT_TO_FP: {
- switch (NVT) {
- case MVT::v2f32:
- return Select_ISD_SINT_TO_FP_v2f32(N);
- case MVT::v4f32:
- return Select_ISD_SINT_TO_FP_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::SRA: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SRA_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::SRL: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SRL_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::STORE: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_STORE_i32(N);
- default:
- return Select_ISD_STORE(N);
- break;
- }
- break;
- }
- case ISD::SUB: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SUB_i32(N);
- case MVT::v8i8:
- return Select_ISD_SUB_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_SUB_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_SUB_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_SUB_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_SUB_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_SUB_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_SUB_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_SUB_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SUBC: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SUBC_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::SUBE: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SUBE_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::UINT_TO_FP: {
- switch (NVT) {
- case MVT::v2f32:
- return Select_ISD_UINT_TO_FP_v2f32(N);
- case MVT::v4f32:
- return Select_ISD_UINT_TO_FP_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::XOR: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_XOR_i32(N);
- case MVT::v2i32:
- return Select_ISD_XOR_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_XOR_v4i32(N);
- default:
- break;
- }
- break;
}
- } // end of big switch.
-
- if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
- N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
- N->getOpcode() != ISD::INTRINSIC_VOID) {
- CannotYetSelect(N);
- } else {
- CannotYetSelectIntrinsic(N);
}
- return NULL;
}
diff --git a/libclamav/c++/ARMGenInstrInfo.inc b/libclamav/c++/ARMGenInstrInfo.inc
index 26f9fa6..9b4a39c 100644
--- a/libclamav/c++/ARMGenInstrInfo.inc
+++ b/libclamav/c++/ARMGenInstrInfo.inc
@@ -41,157 +41,164 @@ static const TargetOperandInfo OperandInfo16[] = { { ARM::GPRRegClassID, 0, 0 },
static const TargetOperandInfo OperandInfo17[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo18[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo19[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo20[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo21[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo22[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo23[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo24[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo25[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo26[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo27[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo28[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo29[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo30[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo31[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo32[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo33[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo34[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo35[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo36[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo37[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo38[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo39[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo40[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo41[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo42[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo43[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo44[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo45[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo46[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo47[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo48[] = { { ARM::GPRRegClassID, 0, (1 << TOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo49[] = { { ARM::GPRRegClassID, 0, (1 << TOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo50[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo51[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo52[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo53[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo54[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo55[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo56[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo57[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo58[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo59[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo60[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo61[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo62[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo63[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo64[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo65[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo66[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo67[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo68[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo69[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo70[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo71[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo72[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo73[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo74[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo75[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo76[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo77[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo78[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo79[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo80[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo81[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo82[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo83[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo84[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo85[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo86[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo87[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((4 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo88[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo89[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo90[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo91[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo92[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo93[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo94[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo95[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo96[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo97[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo98[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo99[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo100[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo101[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo102[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo103[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo104[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo105[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo106[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo107[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo108[] = { { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo109[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo110[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo111[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo112[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo113[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo114[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo115[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo116[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo117[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo118[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo119[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo120[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo121[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo122[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo123[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo124[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo125[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo126[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo127[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo128[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo129[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo130[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo131[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo132[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo133[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo134[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo135[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo136[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo137[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo138[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo139[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo140[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo141[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo142[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo143[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo144[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo145[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo146[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo147[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo148[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo149[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo150[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo151[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo152[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo153[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo154[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo155[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo156[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo157[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo158[] = { { ARM::tGPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo159[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo160[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo161[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo162[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo163[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo164[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo165[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo166[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo167[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo168[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo169[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo170[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo20[] = { { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo21[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo22[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo23[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo24[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo25[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo26[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo27[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo28[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo29[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo30[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo31[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo32[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo33[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo34[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo35[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo36[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo37[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo38[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo39[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo40[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo41[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo42[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo43[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo44[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo45[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo46[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo47[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo48[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo49[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo50[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo51[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo52[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo53[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo54[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo55[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo56[] = { { ARM::GPRRegClassID, 0, (1 << TOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo57[] = { { ARM::GPRRegClassID, 0, (1 << TOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo58[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo59[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo60[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo61[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo62[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo63[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo64[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo65[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo66[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo67[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo68[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo69[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo70[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo71[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo72[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo73[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo74[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo75[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo76[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo77[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo78[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo79[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo80[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo81[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo82[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo83[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo84[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo85[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo86[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo87[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo88[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo89[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo90[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo91[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo92[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo93[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo94[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo95[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((4 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo96[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo97[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo98[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo99[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo100[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo101[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo102[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo103[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo104[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo105[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo106[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo107[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo108[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo109[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo110[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo111[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo112[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo113[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo114[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo115[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo116[] = { { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo117[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo118[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo119[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo120[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo121[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo122[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo123[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo124[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo125[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo126[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo127[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo128[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo129[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo130[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo131[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo132[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo133[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo134[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo135[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo136[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo137[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo138[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo139[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo140[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo141[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo142[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo143[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo144[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo145[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo146[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo147[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo148[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo149[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo150[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo151[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo152[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo153[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo154[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo155[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo156[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo157[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo158[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo159[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo160[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo161[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo162[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo163[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo164[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo165[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo166[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo167[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo168[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo169[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo170[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo171[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo172[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo173[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo174[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo175[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo176[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo177[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
static const TargetInstrDesc ARMInsts[] = {
{ 0, 0, 0, 128, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #0 = PHI
@@ -200,11 +207,11 @@ static const TargetInstrDesc ARMInsts[] = {
{ 3, 1, 0, 128, "EH_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo14 }, // Inst #3 = EH_LABEL
{ 4, 1, 0, 128, "GC_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo14 }, // Inst #4 = GC_LABEL
{ 5, 0, 0, 128, "KILL", 0|(1<<TID::Variadic), 0, NULL, NULL, NULL, 0 }, // Inst #5 = KILL
- { 6, 3, 1, 128, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo27 }, // Inst #6 = EXTRACT_SUBREG
- { 7, 4, 1, 128, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo30 }, // Inst #7 = INSERT_SUBREG
+ { 6, 3, 1, 128, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo28 }, // Inst #6 = EXTRACT_SUBREG
+ { 7, 4, 1, 128, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo31 }, // Inst #7 = INSERT_SUBREG
{ 8, 1, 1, 128, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo14 }, // Inst #8 = IMPLICIT_DEF
- { 9, 4, 1, 128, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo50 }, // Inst #9 = SUBREG_TO_REG
- { 10, 3, 1, 128, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo27 }, // Inst #10 = COPY_TO_REGCLASS
+ { 9, 4, 1, 128, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo58 }, // Inst #9 = SUBREG_TO_REG
+ { 10, 3, 1, 128, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo28 }, // Inst #10 = COPY_TO_REGCLASS
{ 11, 0, 0, 128, "DBG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DBG_VALUE
{ 12, 3, 1, 88, "ADCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #12 = ADCSSri
{ 13, 3, 1, 89, "ADCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #13 = ADCSSrr
@@ -218,8 +225,8 @@ static const TargetInstrDesc ARMInsts[] = {
{ 21, 6, 1, 88, "ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #21 = ADDri
{ 22, 6, 1, 89, "ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #22 = ADDrr
{ 23, 8, 1, 91, "ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #23 = ADDrs
- { 24, 3, 0, 128, "ADJCALLSTACKDOWN", 0|(1<<TID::Predicable), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo11 }, // Inst #24 = ADJCALLSTACKDOWN
- { 25, 4, 0, 128, "ADJCALLSTACKUP", 0|(1<<TID::Predicable), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo12 }, // Inst #25 = ADJCALLSTACKUP
+ { 24, 3, 0, 128, "ADJCALLSTACKDOWN", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo11 }, // Inst #24 = ADJCALLSTACKDOWN
+ { 25, 4, 0, 128, "ADJCALLSTACKUP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo12 }, // Inst #25 = ADJCALLSTACKUP
{ 26, 6, 1, 88, "ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #26 = ANDri
{ 27, 6, 1, 89, "ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #27 = ANDrr
{ 28, 8, 1, 91, "ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #28 = ANDrs
@@ -249,1561 +256,1895 @@ static const TargetInstrDesc ARMInsts[] = {
{ 52, 3, 1, 128, "ATOMIC_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #52 = ATOMIC_SWAP_I8
{ 53, 1, 0, 0, "B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #53 = B
{ 54, 5, 1, 126, "BFC", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #54 = BFC
- { 55, 6, 1, 88, "BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #55 = BICri
- { 56, 6, 1, 89, "BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #56 = BICrr
- { 57, 8, 1, 91, "BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #57 = BICrs
- { 58, 3, 0, 128, "BKPT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #58 = BKPT
- { 59, 1, 0, 0, "BL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #59 = BL
- { 60, 1, 0, 0, "BLX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #60 = BLX
- { 61, 1, 0, 0, "BLXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #61 = BLXr9
- { 62, 3, 0, 0, "BL_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo11 }, // Inst #62 = BL_pred
- { 63, 1, 0, 0, "BLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #63 = BLr9
- { 64, 3, 0, 0, "BLr9_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo11 }, // Inst #64 = BLr9_pred
- { 65, 1, 0, 0, "BRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #65 = BRIND
- { 66, 4, 0, 0, "BR_JTadd", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #66 = BR_JTadd
- { 67, 5, 0, 0, "BR_JTm", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo18 }, // Inst #67 = BR_JTm
- { 68, 3, 0, 0, "BR_JTr", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #68 = BR_JTr
- { 69, 1, 0, 0, "BX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #69 = BX
- { 70, 3, 0, 128, "BXJ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #70 = BXJ
- { 71, 2, 0, 0, "BX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #71 = BX_RET
- { 72, 1, 0, 0, "BXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #72 = BXr9
- { 73, 3, 0, 0, "Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #73 = Bcc
- { 74, 8, 0, 128, "CDP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #74 = CDP
- { 75, 6, 0, 128, "CDP2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #75 = CDP2
- { 76, 4, 1, 125, "CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #76 = CLZ
- { 77, 4, 0, 97, "CMNzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #77 = CMNzri
- { 78, 4, 0, 98, "CMNzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #78 = CMNzrr
- { 79, 6, 0, 100, "CMNzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #79 = CMNzrs
- { 80, 4, 0, 97, "CMPri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #80 = CMPri
- { 81, 4, 0, 98, "CMPrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #81 = CMPrr
- { 82, 6, 0, 100, "CMPrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #82 = CMPrs
- { 83, 4, 0, 97, "CMPzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #83 = CMPzri
- { 84, 4, 0, 98, "CMPzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #84 = CMPzrr
- { 85, 6, 0, 100, "CMPzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #85 = CMPzrs
- { 86, 3, 0, 128, "CONSTPOOL_ENTRY", 0|(1<<TID::NotDuplicable), 0|(1<<4), NULL, NULL, NULL, OperandInfo27 }, // Inst #86 = CONSTPOOL_ENTRY
- { 87, 1, 0, 128, "CPS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #87 = CPS
- { 88, 3, 0, 128, "DBG", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #88 = DBG
- { 89, 6, 1, 88, "EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #89 = EORri
- { 90, 6, 1, 89, "EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #90 = EORrr
- { 91, 8, 1, 91, "EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #91 = EORrs
- { 92, 4, 1, 26, "FCONSTD", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #92 = FCONSTD
- { 93, 4, 1, 26, "FCONSTS", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #93 = FCONSTS
- { 94, 2, 0, 82, "FMSTAT", 0|(1<<TID::Predicable), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #94 = FMSTAT
- { 95, 1, 0, 128, "Int_MemBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #95 = Int_MemBarrierV6
- { 96, 0, 0, 128, "Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #96 = Int_MemBarrierV7
- { 97, 1, 0, 128, "Int_SyncBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #97 = Int_SyncBarrierV6
- { 98, 0, 0, 128, "Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #98 = Int_SyncBarrierV7
- { 99, 2, 0, 128, "Int_eh_sjlj_setjmp", 0, 0|(1<<4), NULL, ImplicitList6, Barriers3, OperandInfo31 }, // Inst #99 = Int_eh_sjlj_setjmp
- { 100, 5, 0, 103, "LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #100 = LDM
- { 101, 5, 0, 0, "LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #101 = LDM_RET
- { 102, 6, 1, 104, "LDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #102 = LDR
- { 103, 6, 1, 104, "LDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #103 = LDRB
- { 104, 7, 2, 105, "LDRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #104 = LDRBT
- { 105, 7, 2, 105, "LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #105 = LDRB_POST
- { 106, 7, 2, 105, "LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #106 = LDRB_PRE
- { 107, 7, 2, 104, "LDRD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #107 = LDRD
- { 108, 4, 1, 128, "LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #108 = LDREX
- { 109, 4, 1, 128, "LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #109 = LDREXB
- { 110, 5, 2, 128, "LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #110 = LDREXD
- { 111, 4, 1, 128, "LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #111 = LDREXH
- { 112, 6, 1, 104, "LDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #112 = LDRH
- { 113, 7, 2, 105, "LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #113 = LDRH_POST
- { 114, 7, 2, 105, "LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #114 = LDRH_PRE
- { 115, 6, 1, 104, "LDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #115 = LDRSB
- { 116, 7, 2, 105, "LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #116 = LDRSB_POST
- { 117, 7, 2, 105, "LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #117 = LDRSB_PRE
- { 118, 6, 1, 104, "LDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #118 = LDRSH
- { 119, 7, 2, 105, "LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #119 = LDRSH_POST
- { 120, 7, 2, 105, "LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #120 = LDRSH_PRE
- { 121, 7, 2, 105, "LDRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #121 = LDRT
- { 122, 7, 2, 105, "LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #122 = LDR_POST
- { 123, 7, 2, 105, "LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #123 = LDR_PRE
- { 124, 6, 1, 104, "LDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #124 = LDRcp
- { 125, 4, 1, 88, "LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo25 }, // Inst #125 = LEApcrel
- { 126, 5, 1, 88, "LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo34 }, // Inst #126 = LEApcrelJT
- { 127, 8, 0, 128, "MCR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #127 = MCR
- { 128, 6, 0, 128, "MCR2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #128 = MCR2
- { 129, 7, 0, 128, "MCRR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #129 = MCRR
- { 130, 5, 0, 128, "MCRR2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #130 = MCRR2
- { 131, 7, 1, 109, "MLA", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #131 = MLA
- { 132, 6, 1, 109, "MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #132 = MLS
- { 133, 5, 1, 93, "MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #133 = MOVCCi
- { 134, 5, 1, 94, "MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo41 }, // Inst #134 = MOVCCr
- { 135, 7, 1, 96, "MOVCCs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo42 }, // Inst #135 = MOVCCs
- { 136, 5, 1, 111, "MOVTi16", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #136 = MOVTi16
- { 137, 5, 1, 111, "MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo43 }, // Inst #137 = MOVi
- { 138, 4, 1, 111, "MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo25 }, // Inst #138 = MOVi16
- { 139, 4, 1, 111, "MOVi2pieces", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo25 }, // Inst #139 = MOVi2pieces
- { 140, 4, 1, 111, "MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo25 }, // Inst #140 = MOVi32imm
- { 141, 5, 1, 112, "MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo44 }, // Inst #141 = MOVr
- { 142, 5, 1, 113, "MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(1<<15), ImplicitList1, NULL, NULL, OperandInfo44 }, // Inst #142 = MOVrx
- { 143, 7, 1, 114, "MOVs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo45 }, // Inst #143 = MOVs
- { 144, 4, 1, 113, "MOVsra_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #144 = MOVsra_flag
- { 145, 4, 1, 113, "MOVsrl_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #145 = MOVsrl_flag
- { 146, 8, 0, 128, "MRC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #146 = MRC
- { 147, 6, 0, 128, "MRC2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #147 = MRC2
- { 148, 7, 0, 128, "MRRC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #148 = MRRC
- { 149, 5, 0, 128, "MRRC2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #149 = MRRC2
- { 150, 3, 1, 128, "MRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #150 = MRS
- { 151, 3, 1, 128, "MRSsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #151 = MRSsys
- { 152, 3, 0, 128, "MSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #152 = MSR
- { 153, 3, 0, 128, "MSRsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #153 = MSRsys
- { 154, 6, 1, 116, "MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #154 = MUL
- { 155, 5, 1, 111, "MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo43 }, // Inst #155 = MVNi
- { 156, 5, 1, 112, "MVNr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo44 }, // Inst #156 = MVNr
- { 157, 7, 1, 114, "MVNs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo45 }, // Inst #157 = MVNs
- { 158, 2, 0, 128, "NOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #158 = NOP
- { 159, 6, 1, 88, "ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #159 = ORRri
- { 160, 6, 1, 89, "ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #160 = ORRrr
- { 161, 8, 1, 91, "ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #161 = ORRrs
- { 162, 5, 1, 89, "PICADD", 0|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #162 = PICADD
- { 163, 5, 1, 104, "PICLDR", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #163 = PICLDR
- { 164, 5, 1, 104, "PICLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #164 = PICLDRB
- { 165, 5, 1, 104, "PICLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #165 = PICLDRH
- { 166, 5, 1, 104, "PICLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #166 = PICLDRSB
- { 167, 5, 1, 104, "PICLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #167 = PICLDRSH
- { 168, 5, 0, 121, "PICSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #168 = PICSTR
- { 169, 5, 0, 121, "PICSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #169 = PICSTRB
- { 170, 5, 0, 121, "PICSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #170 = PICSTRH
- { 171, 6, 1, 90, "PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #171 = PKHBT
- { 172, 6, 1, 90, "PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #172 = PKHTB
- { 173, 5, 1, 89, "QADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #173 = QADD
- { 174, 5, 1, 89, "QADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #174 = QADD16
- { 175, 5, 1, 89, "QADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #175 = QADD8
- { 176, 5, 1, 89, "QASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #176 = QASX
- { 177, 5, 1, 89, "QDADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #177 = QDADD
- { 178, 5, 1, 89, "QDSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #178 = QDSUB
- { 179, 5, 1, 89, "QSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #179 = QSAX
- { 180, 5, 1, 89, "QSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #180 = QSUB
- { 181, 5, 1, 89, "QSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #181 = QSUB16
- { 182, 5, 1, 89, "QSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #182 = QSUB8
- { 183, 4, 1, 125, "RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #183 = RBIT
- { 184, 4, 1, 125, "REV", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #184 = REV
- { 185, 4, 1, 125, "REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #185 = REV16
- { 186, 4, 1, 125, "REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #186 = REVSH
- { 187, 5, 1, 88, "RSBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #187 = RSBSri
- { 188, 7, 1, 91, "RSBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #188 = RSBSrs
- { 189, 6, 1, 88, "RSBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #189 = RSBri
- { 190, 8, 1, 91, "RSBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #190 = RSBrs
- { 191, 3, 1, 88, "RSCSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #191 = RSCSri
- { 192, 5, 1, 91, "RSCSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #192 = RSCSrs
- { 193, 6, 1, 88, "RSCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #193 = RSCri
- { 194, 8, 1, 91, "RSCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #194 = RSCrs
- { 195, 3, 1, 88, "SBCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #195 = SBCSSri
- { 196, 3, 1, 89, "SBCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #196 = SBCSSrr
- { 197, 5, 1, 91, "SBCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #197 = SBCSSrs
- { 198, 6, 1, 88, "SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #198 = SBCri
- { 199, 6, 1, 89, "SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #199 = SBCrr
- { 200, 8, 1, 91, "SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #200 = SBCrs
- { 201, 6, 1, 88, "SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #201 = SBFX
- { 202, 0, 0, 128, "SETENDBE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #202 = SETENDBE
- { 203, 0, 0, 128, "SETENDLE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #203 = SETENDLE
- { 204, 2, 0, 128, "SEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #204 = SEV
- { 205, 6, 1, 108, "SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #205 = SMLABB
- { 206, 6, 1, 108, "SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #206 = SMLABT
- { 207, 7, 2, 110, "SMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #207 = SMLAL
- { 208, 6, 2, 110, "SMLALBB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #208 = SMLALBB
- { 209, 6, 2, 110, "SMLALBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #209 = SMLALBT
- { 210, 6, 2, 110, "SMLALTB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #210 = SMLALTB
- { 211, 6, 2, 110, "SMLALTT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #211 = SMLALTT
- { 212, 6, 1, 108, "SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #212 = SMLATB
- { 213, 6, 1, 108, "SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #213 = SMLATT
- { 214, 6, 1, 108, "SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #214 = SMLAWB
- { 215, 6, 1, 108, "SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #215 = SMLAWT
- { 216, 6, 1, 109, "SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #216 = SMMLA
- { 217, 6, 1, 109, "SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #217 = SMMLS
- { 218, 5, 1, 116, "SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #218 = SMMUL
- { 219, 5, 1, 116, "SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #219 = SMULBB
- { 220, 5, 1, 116, "SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #220 = SMULBT
- { 221, 7, 2, 117, "SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #221 = SMULL
- { 222, 5, 1, 116, "SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #222 = SMULTB
- { 223, 5, 1, 116, "SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #223 = SMULTT
- { 224, 5, 1, 115, "SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #224 = SMULWB
- { 225, 5, 1, 115, "SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #225 = SMULWT
- { 226, 5, 0, 120, "STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #226 = STM
- { 227, 6, 0, 121, "STR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #227 = STR
- { 228, 6, 0, 121, "STRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #228 = STRB
- { 229, 7, 1, 122, "STRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #229 = STRBT
- { 230, 7, 1, 122, "STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #230 = STRB_POST
- { 231, 7, 1, 122, "STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #231 = STRB_PRE
- { 232, 7, 0, 121, "STRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #232 = STRD
- { 233, 5, 1, 128, "STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #233 = STREX
- { 234, 5, 1, 128, "STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #234 = STREXB
- { 235, 6, 1, 128, "STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #235 = STREXD
- { 236, 5, 1, 128, "STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #236 = STREXH
- { 237, 6, 0, 121, "STRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #237 = STRH
- { 238, 7, 1, 122, "STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #238 = STRH_POST
- { 239, 7, 1, 122, "STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #239 = STRH_PRE
- { 240, 7, 1, 122, "STRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #240 = STRT
- { 241, 7, 1, 122, "STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #241 = STR_POST
- { 242, 7, 1, 122, "STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #242 = STR_PRE
- { 243, 5, 1, 88, "SUBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #243 = SUBSri
- { 244, 5, 1, 89, "SUBSrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #244 = SUBSrr
- { 245, 7, 1, 91, "SUBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #245 = SUBSrs
- { 246, 6, 1, 88, "SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #246 = SUBri
- { 247, 6, 1, 89, "SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #247 = SUBrr
- { 248, 8, 1, 91, "SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #248 = SUBrs
- { 249, 3, 0, 0, "SVC", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #249 = SVC
- { 250, 5, 1, 128, "SWP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #250 = SWP
- { 251, 5, 1, 128, "SWPB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #251 = SWPB
- { 252, 5, 1, 89, "SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #252 = SXTABrr
- { 253, 6, 1, 90, "SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #253 = SXTABrr_rot
- { 254, 5, 1, 89, "SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #254 = SXTAHrr
- { 255, 6, 1, 90, "SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #255 = SXTAHrr_rot
- { 256, 4, 1, 125, "SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #256 = SXTBr
- { 257, 5, 1, 126, "SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #257 = SXTBr_rot
- { 258, 4, 1, 125, "SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #258 = SXTHr
- { 259, 5, 1, 126, "SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #259 = SXTHr_rot
- { 260, 4, 0, 97, "TEQri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #260 = TEQri
- { 261, 4, 0, 98, "TEQrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #261 = TEQrr
- { 262, 6, 0, 100, "TEQrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #262 = TEQrs
- { 263, 0, 0, 0, "TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(2<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #263 = TPsoft
- { 264, 2, 0, 128, "TRAP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #264 = TRAP
- { 265, 4, 0, 97, "TSTri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #265 = TSTri
- { 266, 4, 0, 98, "TSTrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #266 = TSTrr
- { 267, 6, 0, 100, "TSTrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #267 = TSTrs
- { 268, 6, 1, 88, "UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #268 = UBFX
- { 269, 6, 2, 110, "UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #269 = UMAAL
- { 270, 7, 2, 110, "UMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #270 = UMLAL
- { 271, 7, 2, 117, "UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #271 = UMULL
- { 272, 5, 1, 89, "UQADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #272 = UQADD16
- { 273, 5, 1, 89, "UQADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #273 = UQADD8
- { 274, 5, 1, 89, "UQASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #274 = UQASX
- { 275, 5, 1, 89, "UQSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #275 = UQSAX
- { 276, 5, 1, 89, "UQSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #276 = UQSUB16
- { 277, 5, 1, 89, "UQSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #277 = UQSUB8
- { 278, 5, 1, 89, "UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #278 = UXTABrr
- { 279, 6, 1, 90, "UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #279 = UXTABrr_rot
- { 280, 5, 1, 89, "UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #280 = UXTAHrr
- { 281, 6, 1, 90, "UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #281 = UXTAHrr_rot
- { 282, 4, 1, 125, "UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #282 = UXTB16r
- { 283, 5, 1, 126, "UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #283 = UXTB16r_rot
- { 284, 4, 1, 125, "UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #284 = UXTBr
- { 285, 5, 1, 126, "UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #285 = UXTBr_rot
- { 286, 4, 1, 125, "UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #286 = UXTHr
- { 287, 5, 1, 126, "UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #287 = UXTHr_rot
- { 288, 6, 1, 17, "VABALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #288 = VABALsv2i64
- { 289, 6, 1, 17, "VABALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #289 = VABALsv4i32
- { 290, 6, 1, 17, "VABALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #290 = VABALsv8i16
- { 291, 6, 1, 17, "VABALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #291 = VABALuv2i64
- { 292, 6, 1, 17, "VABALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #292 = VABALuv4i32
- { 293, 6, 1, 17, "VABALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #293 = VABALuv8i16
- { 294, 6, 1, 18, "VABAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #294 = VABAsv16i8
- { 295, 6, 1, 19, "VABAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #295 = VABAsv2i32
- { 296, 6, 1, 17, "VABAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #296 = VABAsv4i16
- { 297, 6, 1, 20, "VABAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #297 = VABAsv4i32
- { 298, 6, 1, 18, "VABAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #298 = VABAsv8i16
- { 299, 6, 1, 17, "VABAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #299 = VABAsv8i8
- { 300, 6, 1, 18, "VABAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #300 = VABAuv16i8
- { 301, 6, 1, 19, "VABAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #301 = VABAuv2i32
- { 302, 6, 1, 17, "VABAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #302 = VABAuv4i16
- { 303, 6, 1, 20, "VABAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #303 = VABAuv4i32
- { 304, 6, 1, 18, "VABAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #304 = VABAuv8i16
- { 305, 6, 1, 17, "VABAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #305 = VABAuv8i8
- { 306, 5, 1, 4, "VABDLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #306 = VABDLsv2i64
- { 307, 5, 1, 4, "VABDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #307 = VABDLsv4i32
- { 308, 5, 1, 4, "VABDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #308 = VABDLsv8i16
- { 309, 5, 1, 4, "VABDLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #309 = VABDLuv2i64
- { 310, 5, 1, 4, "VABDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #310 = VABDLuv4i32
- { 311, 5, 1, 4, "VABDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #311 = VABDLuv8i16
- { 312, 5, 1, 1, "VABDfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #312 = VABDfd
- { 313, 5, 1, 2, "VABDfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #313 = VABDfq
- { 314, 5, 1, 4, "VABDsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #314 = VABDsv16i8
- { 315, 5, 1, 3, "VABDsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #315 = VABDsv2i32
- { 316, 5, 1, 3, "VABDsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #316 = VABDsv4i16
- { 317, 5, 1, 4, "VABDsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #317 = VABDsv4i32
- { 318, 5, 1, 4, "VABDsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #318 = VABDsv8i16
- { 319, 5, 1, 3, "VABDsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #319 = VABDsv8i8
- { 320, 5, 1, 4, "VABDuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #320 = VABDuv16i8
- { 321, 5, 1, 3, "VABDuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #321 = VABDuv2i32
- { 322, 5, 1, 3, "VABDuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #322 = VABDuv4i16
- { 323, 5, 1, 4, "VABDuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #323 = VABDuv4i32
- { 324, 5, 1, 4, "VABDuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #324 = VABDuv8i16
- { 325, 5, 1, 3, "VABDuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #325 = VABDuv8i8
- { 326, 4, 1, 87, "VABSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #326 = VABSD
- { 327, 4, 1, 86, "VABSS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #327 = VABSS
- { 328, 4, 1, 57, "VABSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #328 = VABSfd
- { 329, 4, 1, 57, "VABSfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #329 = VABSfd_sfp
- { 330, 4, 1, 58, "VABSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #330 = VABSfq
- { 331, 4, 1, 60, "VABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #331 = VABSv16i8
- { 332, 4, 1, 59, "VABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #332 = VABSv2i32
- { 333, 4, 1, 59, "VABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #333 = VABSv4i16
- { 334, 4, 1, 60, "VABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #334 = VABSv4i32
- { 335, 4, 1, 60, "VABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #335 = VABSv8i16
- { 336, 4, 1, 59, "VABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #336 = VABSv8i8
- { 337, 5, 1, 1, "VACGEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #337 = VACGEd
- { 338, 5, 1, 2, "VACGEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #338 = VACGEq
- { 339, 5, 1, 1, "VACGTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #339 = VACGTd
- { 340, 5, 1, 2, "VACGTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #340 = VACGTq
- { 341, 5, 1, 62, "VADDD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #341 = VADDD
- { 342, 5, 1, 3, "VADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #342 = VADDHNv2i32
- { 343, 5, 1, 3, "VADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #343 = VADDHNv4i16
- { 344, 5, 1, 3, "VADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #344 = VADDHNv8i8
- { 345, 5, 1, 44, "VADDLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #345 = VADDLsv2i64
- { 346, 5, 1, 44, "VADDLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #346 = VADDLsv4i32
- { 347, 5, 1, 44, "VADDLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #347 = VADDLsv8i16
- { 348, 5, 1, 44, "VADDLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #348 = VADDLuv2i64
- { 349, 5, 1, 44, "VADDLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #349 = VADDLuv4i32
- { 350, 5, 1, 44, "VADDLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #350 = VADDLuv8i16
- { 351, 5, 1, 61, "VADDS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #351 = VADDS
- { 352, 5, 1, 47, "VADDWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #352 = VADDWsv2i64
- { 353, 5, 1, 47, "VADDWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #353 = VADDWsv4i32
- { 354, 5, 1, 47, "VADDWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #354 = VADDWsv8i16
- { 355, 5, 1, 47, "VADDWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #355 = VADDWuv2i64
- { 356, 5, 1, 47, "VADDWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #356 = VADDWuv4i32
- { 357, 5, 1, 47, "VADDWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #357 = VADDWuv8i16
- { 358, 5, 1, 1, "VADDfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #358 = VADDfd
- { 359, 5, 1, 1, "VADDfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #359 = VADDfd_sfp
- { 360, 5, 1, 2, "VADDfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #360 = VADDfq
- { 361, 5, 1, 6, "VADDv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #361 = VADDv16i8
- { 362, 5, 1, 5, "VADDv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #362 = VADDv1i64
- { 363, 5, 1, 5, "VADDv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #363 = VADDv2i32
- { 364, 5, 1, 6, "VADDv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #364 = VADDv2i64
- { 365, 5, 1, 5, "VADDv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #365 = VADDv4i16
- { 366, 5, 1, 6, "VADDv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #366 = VADDv4i32
- { 367, 5, 1, 6, "VADDv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #367 = VADDv8i16
- { 368, 5, 1, 5, "VADDv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #368 = VADDv8i8
- { 369, 5, 1, 5, "VANDd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #369 = VANDd
- { 370, 5, 1, 6, "VANDq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #370 = VANDq
- { 371, 5, 1, 5, "VBICd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #371 = VBICd
- { 372, 5, 1, 6, "VBICq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #372 = VBICq
- { 373, 6, 1, 5, "VBIFd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #373 = VBIFd
- { 374, 6, 1, 6, "VBIFq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #374 = VBIFq
- { 375, 6, 1, 5, "VBITd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #375 = VBITd
- { 376, 6, 1, 6, "VBITq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #376 = VBITq
- { 377, 6, 1, 7, "VBSLd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #377 = VBSLd
- { 378, 6, 1, 8, "VBSLq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #378 = VBSLq
- { 379, 5, 1, 1, "VCEQfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #379 = VCEQfd
- { 380, 5, 1, 2, "VCEQfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #380 = VCEQfq
- { 381, 5, 1, 4, "VCEQv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #381 = VCEQv16i8
- { 382, 5, 1, 3, "VCEQv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #382 = VCEQv2i32
- { 383, 5, 1, 3, "VCEQv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #383 = VCEQv4i16
- { 384, 5, 1, 4, "VCEQv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #384 = VCEQv4i32
- { 385, 5, 1, 4, "VCEQv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #385 = VCEQv8i16
- { 386, 5, 1, 3, "VCEQv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #386 = VCEQv8i8
- { 387, 5, 1, 1, "VCGEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #387 = VCGEfd
- { 388, 5, 1, 2, "VCGEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #388 = VCGEfq
- { 389, 5, 1, 4, "VCGEsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #389 = VCGEsv16i8
- { 390, 5, 1, 3, "VCGEsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #390 = VCGEsv2i32
- { 391, 5, 1, 3, "VCGEsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #391 = VCGEsv4i16
- { 392, 5, 1, 4, "VCGEsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #392 = VCGEsv4i32
- { 393, 5, 1, 4, "VCGEsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #393 = VCGEsv8i16
- { 394, 5, 1, 3, "VCGEsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #394 = VCGEsv8i8
- { 395, 5, 1, 4, "VCGEuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #395 = VCGEuv16i8
- { 396, 5, 1, 3, "VCGEuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #396 = VCGEuv2i32
- { 397, 5, 1, 3, "VCGEuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #397 = VCGEuv4i16
- { 398, 5, 1, 4, "VCGEuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #398 = VCGEuv4i32
- { 399, 5, 1, 4, "VCGEuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #399 = VCGEuv8i16
- { 400, 5, 1, 3, "VCGEuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #400 = VCGEuv8i8
- { 401, 5, 1, 1, "VCGTfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #401 = VCGTfd
- { 402, 5, 1, 2, "VCGTfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #402 = VCGTfq
- { 403, 5, 1, 4, "VCGTsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #403 = VCGTsv16i8
- { 404, 5, 1, 3, "VCGTsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #404 = VCGTsv2i32
- { 405, 5, 1, 3, "VCGTsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #405 = VCGTsv4i16
- { 406, 5, 1, 4, "VCGTsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #406 = VCGTsv4i32
- { 407, 5, 1, 4, "VCGTsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #407 = VCGTsv8i16
- { 408, 5, 1, 3, "VCGTsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #408 = VCGTsv8i8
- { 409, 5, 1, 4, "VCGTuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #409 = VCGTuv16i8
- { 410, 5, 1, 3, "VCGTuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #410 = VCGTuv2i32
- { 411, 5, 1, 3, "VCGTuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #411 = VCGTuv4i16
- { 412, 5, 1, 4, "VCGTuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #412 = VCGTuv4i32
- { 413, 5, 1, 4, "VCGTuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #413 = VCGTuv8i16
- { 414, 5, 1, 3, "VCGTuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #414 = VCGTuv8i8
- { 415, 4, 1, 8, "VCLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #415 = VCLSv16i8
- { 416, 4, 1, 7, "VCLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #416 = VCLSv2i32
- { 417, 4, 1, 7, "VCLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #417 = VCLSv4i16
- { 418, 4, 1, 8, "VCLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #418 = VCLSv4i32
- { 419, 4, 1, 8, "VCLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #419 = VCLSv8i16
- { 420, 4, 1, 7, "VCLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #420 = VCLSv8i8
- { 421, 4, 1, 8, "VCLZv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #421 = VCLZv16i8
- { 422, 4, 1, 7, "VCLZv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #422 = VCLZv2i32
- { 423, 4, 1, 7, "VCLZv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #423 = VCLZv4i16
- { 424, 4, 1, 8, "VCLZv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #424 = VCLZv4i32
- { 425, 4, 1, 8, "VCLZv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #425 = VCLZv8i16
- { 426, 4, 1, 7, "VCLZv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #426 = VCLZv8i8
- { 427, 4, 0, 64, "VCMPD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo57 }, // Inst #427 = VCMPD
- { 428, 4, 0, 64, "VCMPED", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo57 }, // Inst #428 = VCMPED
- { 429, 4, 0, 63, "VCMPES", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo58 }, // Inst #429 = VCMPES
- { 430, 3, 0, 64, "VCMPEZD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo65 }, // Inst #430 = VCMPEZD
- { 431, 3, 0, 63, "VCMPEZS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo66 }, // Inst #431 = VCMPEZS
- { 432, 4, 0, 63, "VCMPS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo58 }, // Inst #432 = VCMPS
- { 433, 3, 0, 64, "VCMPZD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo65 }, // Inst #433 = VCMPZD
- { 434, 3, 0, 63, "VCMPZS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo66 }, // Inst #434 = VCMPZS
- { 435, 4, 1, 7, "VCNTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #435 = VCNTd
- { 436, 4, 1, 8, "VCNTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #436 = VCNTq
- { 437, 4, 1, 66, "VCVTBHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #437 = VCVTBHS
- { 438, 4, 1, 66, "VCVTBSH", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #438 = VCVTBSH
- { 439, 4, 1, 66, "VCVTDS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #439 = VCVTDS
- { 440, 4, 1, 69, "VCVTSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #440 = VCVTSD
- { 441, 4, 1, 66, "VCVTTHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #441 = VCVTTHS
- { 442, 4, 1, 66, "VCVTTSH", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #442 = VCVTTSH
- { 443, 4, 1, 57, "VCVTf2sd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #443 = VCVTf2sd
- { 444, 4, 1, 57, "VCVTf2sd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #444 = VCVTf2sd_sfp
- { 445, 4, 1, 58, "VCVTf2sq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #445 = VCVTf2sq
- { 446, 4, 1, 57, "VCVTf2ud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #446 = VCVTf2ud
- { 447, 4, 1, 57, "VCVTf2ud_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #447 = VCVTf2ud_sfp
- { 448, 4, 1, 58, "VCVTf2uq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #448 = VCVTf2uq
- { 449, 5, 1, 57, "VCVTf2xsd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #449 = VCVTf2xsd
- { 450, 5, 1, 58, "VCVTf2xsq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #450 = VCVTf2xsq
- { 451, 5, 1, 57, "VCVTf2xud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #451 = VCVTf2xud
- { 452, 5, 1, 58, "VCVTf2xuq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #452 = VCVTf2xuq
- { 453, 4, 1, 57, "VCVTs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #453 = VCVTs2fd
- { 454, 4, 1, 57, "VCVTs2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #454 = VCVTs2fd_sfp
- { 455, 4, 1, 58, "VCVTs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #455 = VCVTs2fq
- { 456, 4, 1, 57, "VCVTu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #456 = VCVTu2fd
- { 457, 4, 1, 57, "VCVTu2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #457 = VCVTu2fd_sfp
- { 458, 4, 1, 58, "VCVTu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #458 = VCVTu2fq
- { 459, 5, 1, 57, "VCVTxs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #459 = VCVTxs2fd
- { 460, 5, 1, 58, "VCVTxs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #460 = VCVTxs2fq
- { 461, 5, 1, 57, "VCVTxu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #461 = VCVTxu2fd
- { 462, 5, 1, 58, "VCVTxu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #462 = VCVTxu2fq
- { 463, 5, 1, 72, "VDIVD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #463 = VDIVD
- { 464, 5, 1, 71, "VDIVS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #464 = VDIVS
- { 465, 4, 1, 24, "VDUP16d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo71 }, // Inst #465 = VDUP16d
- { 466, 4, 1, 24, "VDUP16q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo72 }, // Inst #466 = VDUP16q
- { 467, 4, 1, 24, "VDUP32d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo71 }, // Inst #467 = VDUP32d
- { 468, 4, 1, 24, "VDUP32q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo72 }, // Inst #468 = VDUP32q
- { 469, 4, 1, 24, "VDUP8d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo71 }, // Inst #469 = VDUP8d
- { 470, 4, 1, 24, "VDUP8q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo72 }, // Inst #470 = VDUP8q
- { 471, 5, 1, 21, "VDUPLN16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #471 = VDUPLN16d
- { 472, 5, 1, 21, "VDUPLN16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #472 = VDUPLN16q
- { 473, 5, 1, 21, "VDUPLN32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #473 = VDUPLN32d
- { 474, 5, 1, 21, "VDUPLN32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #474 = VDUPLN32q
- { 475, 5, 1, 21, "VDUPLN8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #475 = VDUPLN8d
- { 476, 5, 1, 21, "VDUPLN8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #476 = VDUPLN8q
- { 477, 5, 1, 21, "VDUPLNfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #477 = VDUPLNfd
- { 478, 5, 1, 21, "VDUPLNfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #478 = VDUPLNfq
- { 479, 4, 1, 24, "VDUPfd", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo71 }, // Inst #479 = VDUPfd
- { 480, 4, 1, 21, "VDUPfdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #480 = VDUPfdf
- { 481, 4, 1, 24, "VDUPfq", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo72 }, // Inst #481 = VDUPfq
- { 482, 4, 1, 21, "VDUPfqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #482 = VDUPfqf
- { 483, 5, 1, 5, "VEORd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #483 = VEORd
- { 484, 5, 1, 6, "VEORq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #484 = VEORq
- { 485, 6, 1, 9, "VEXTd16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #485 = VEXTd16
- { 486, 6, 1, 9, "VEXTd32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #486 = VEXTd32
- { 487, 6, 1, 9, "VEXTd8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #487 = VEXTd8
- { 488, 6, 1, 9, "VEXTdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #488 = VEXTdf
- { 489, 6, 1, 10, "VEXTq16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #489 = VEXTq16
- { 490, 6, 1, 10, "VEXTq32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #490 = VEXTq32
- { 491, 6, 1, 10, "VEXTq8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #491 = VEXTq8
- { 492, 6, 1, 10, "VEXTqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #492 = VEXTqf
- { 493, 5, 1, 28, "VGETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo77 }, // Inst #493 = VGETLNi32
- { 494, 5, 1, 28, "VGETLNs16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo77 }, // Inst #494 = VGETLNs16
- { 495, 5, 1, 28, "VGETLNs8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo77 }, // Inst #495 = VGETLNs8
- { 496, 5, 1, 28, "VGETLNu16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo77 }, // Inst #496 = VGETLNu16
- { 497, 5, 1, 28, "VGETLNu8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo77 }, // Inst #497 = VGETLNu8
- { 498, 5, 1, 4, "VHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #498 = VHADDsv16i8
- { 499, 5, 1, 3, "VHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #499 = VHADDsv2i32
- { 500, 5, 1, 3, "VHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #500 = VHADDsv4i16
- { 501, 5, 1, 4, "VHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #501 = VHADDsv4i32
- { 502, 5, 1, 4, "VHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #502 = VHADDsv8i16
- { 503, 5, 1, 3, "VHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #503 = VHADDsv8i8
- { 504, 5, 1, 4, "VHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #504 = VHADDuv16i8
- { 505, 5, 1, 3, "VHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #505 = VHADDuv2i32
- { 506, 5, 1, 3, "VHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #506 = VHADDuv4i16
- { 507, 5, 1, 4, "VHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #507 = VHADDuv4i32
- { 508, 5, 1, 4, "VHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #508 = VHADDuv8i16
- { 509, 5, 1, 3, "VHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #509 = VHADDuv8i8
- { 510, 5, 1, 4, "VHSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #510 = VHSUBsv16i8
- { 511, 5, 1, 3, "VHSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #511 = VHSUBsv2i32
- { 512, 5, 1, 3, "VHSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #512 = VHSUBsv4i16
- { 513, 5, 1, 4, "VHSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #513 = VHSUBsv4i32
- { 514, 5, 1, 4, "VHSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #514 = VHSUBsv8i16
- { 515, 5, 1, 3, "VHSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #515 = VHSUBsv8i8
- { 516, 5, 1, 4, "VHSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #516 = VHSUBuv16i8
- { 517, 5, 1, 3, "VHSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #517 = VHSUBuv2i32
- { 518, 5, 1, 3, "VHSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #518 = VHSUBuv4i16
- { 519, 5, 1, 4, "VHSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #519 = VHSUBuv4i32
- { 520, 5, 1, 4, "VHSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #520 = VHSUBuv8i16
- { 521, 5, 1, 3, "VHSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #521 = VHSUBuv8i8
- { 522, 7, 1, 11, "VLD1d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #522 = VLD1d16
- { 523, 7, 1, 11, "VLD1d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #523 = VLD1d32
- { 524, 7, 1, 11, "VLD1d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #524 = VLD1d64
- { 525, 7, 1, 11, "VLD1d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #525 = VLD1d8
- { 526, 7, 1, 11, "VLD1df", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #526 = VLD1df
- { 527, 7, 1, 11, "VLD1q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #527 = VLD1q16
- { 528, 7, 1, 11, "VLD1q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #528 = VLD1q32
- { 529, 7, 1, 11, "VLD1q64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #529 = VLD1q64
- { 530, 7, 1, 11, "VLD1q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #530 = VLD1q8
- { 531, 7, 1, 11, "VLD1qf", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #531 = VLD1qf
- { 532, 11, 2, 12, "VLD2LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #532 = VLD2LNd16
- { 533, 11, 2, 12, "VLD2LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #533 = VLD2LNd32
- { 534, 11, 2, 12, "VLD2LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #534 = VLD2LNd8
- { 535, 11, 2, 12, "VLD2LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #535 = VLD2LNq16a
- { 536, 11, 2, 12, "VLD2LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #536 = VLD2LNq16b
- { 537, 11, 2, 12, "VLD2LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #537 = VLD2LNq32a
- { 538, 11, 2, 12, "VLD2LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #538 = VLD2LNq32b
- { 539, 8, 2, 12, "VLD2d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #539 = VLD2d16
- { 540, 8, 2, 12, "VLD2d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #540 = VLD2d32
- { 541, 8, 2, 11, "VLD2d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #541 = VLD2d64
- { 542, 8, 2, 12, "VLD2d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #542 = VLD2d8
- { 543, 10, 4, 12, "VLD2q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #543 = VLD2q16
- { 544, 10, 4, 12, "VLD2q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #544 = VLD2q32
- { 545, 10, 4, 12, "VLD2q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #545 = VLD2q8
- { 546, 13, 3, 13, "VLD3LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #546 = VLD3LNd16
- { 547, 13, 3, 13, "VLD3LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #547 = VLD3LNd32
- { 548, 13, 3, 13, "VLD3LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #548 = VLD3LNd8
- { 549, 13, 3, 13, "VLD3LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #549 = VLD3LNq16a
- { 550, 13, 3, 13, "VLD3LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #550 = VLD3LNq16b
- { 551, 13, 3, 13, "VLD3LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #551 = VLD3LNq32a
- { 552, 13, 3, 13, "VLD3LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #552 = VLD3LNq32b
- { 553, 9, 3, 13, "VLD3d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #553 = VLD3d16
- { 554, 9, 3, 13, "VLD3d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #554 = VLD3d32
- { 555, 9, 3, 11, "VLD3d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #555 = VLD3d64
- { 556, 9, 3, 13, "VLD3d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #556 = VLD3d8
- { 557, 10, 4, 13, "VLD3q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #557 = VLD3q16a
- { 558, 10, 4, 13, "VLD3q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #558 = VLD3q16b
- { 559, 10, 4, 13, "VLD3q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #559 = VLD3q32a
- { 560, 10, 4, 13, "VLD3q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #560 = VLD3q32b
- { 561, 10, 4, 13, "VLD3q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #561 = VLD3q8a
- { 562, 10, 4, 13, "VLD3q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #562 = VLD3q8b
- { 563, 15, 4, 14, "VLD4LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #563 = VLD4LNd16
- { 564, 15, 4, 14, "VLD4LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #564 = VLD4LNd32
- { 565, 15, 4, 14, "VLD4LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #565 = VLD4LNd8
- { 566, 15, 4, 14, "VLD4LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #566 = VLD4LNq16a
- { 567, 15, 4, 14, "VLD4LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #567 = VLD4LNq16b
- { 568, 15, 4, 14, "VLD4LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #568 = VLD4LNq32a
- { 569, 15, 4, 14, "VLD4LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #569 = VLD4LNq32b
- { 570, 10, 4, 14, "VLD4d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #570 = VLD4d16
- { 571, 10, 4, 14, "VLD4d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #571 = VLD4d32
- { 572, 10, 4, 11, "VLD4d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #572 = VLD4d64
- { 573, 10, 4, 14, "VLD4d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #573 = VLD4d8
- { 574, 11, 5, 14, "VLD4q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #574 = VLD4q16a
- { 575, 11, 5, 14, "VLD4q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #575 = VLD4q16b
- { 576, 11, 5, 14, "VLD4q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #576 = VLD4q32a
- { 577, 11, 5, 14, "VLD4q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #577 = VLD4q32b
- { 578, 11, 5, 14, "VLD4q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #578 = VLD4q8a
- { 579, 11, 5, 14, "VLD4q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #579 = VLD4q8b
- { 580, 5, 0, 75, "VLDMD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo32 }, // Inst #580 = VLDMD
- { 581, 5, 0, 75, "VLDMS", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo32 }, // Inst #581 = VLDMS
- { 582, 5, 1, 74, "VLDRD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #582 = VLDRD
- { 583, 5, 1, 75, "VLDRQ", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #583 = VLDRQ
- { 584, 5, 1, 73, "VLDRS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #584 = VLDRS
- { 585, 5, 1, 1, "VMAXfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #585 = VMAXfd
- { 586, 5, 1, 2, "VMAXfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #586 = VMAXfq
- { 587, 5, 1, 4, "VMAXsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #587 = VMAXsv16i8
- { 588, 5, 1, 3, "VMAXsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #588 = VMAXsv2i32
- { 589, 5, 1, 3, "VMAXsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #589 = VMAXsv4i16
- { 590, 5, 1, 4, "VMAXsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #590 = VMAXsv4i32
- { 591, 5, 1, 4, "VMAXsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #591 = VMAXsv8i16
- { 592, 5, 1, 3, "VMAXsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #592 = VMAXsv8i8
- { 593, 5, 1, 4, "VMAXuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #593 = VMAXuv16i8
- { 594, 5, 1, 3, "VMAXuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #594 = VMAXuv2i32
- { 595, 5, 1, 3, "VMAXuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #595 = VMAXuv4i16
- { 596, 5, 1, 4, "VMAXuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #596 = VMAXuv4i32
- { 597, 5, 1, 4, "VMAXuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #597 = VMAXuv8i16
- { 598, 5, 1, 3, "VMAXuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #598 = VMAXuv8i8
- { 599, 5, 1, 1, "VMINfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #599 = VMINfd
- { 600, 5, 1, 2, "VMINfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #600 = VMINfq
- { 601, 5, 1, 4, "VMINsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #601 = VMINsv16i8
- { 602, 5, 1, 3, "VMINsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #602 = VMINsv2i32
- { 603, 5, 1, 3, "VMINsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #603 = VMINsv4i16
- { 604, 5, 1, 4, "VMINsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #604 = VMINsv4i32
- { 605, 5, 1, 4, "VMINsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #605 = VMINsv8i16
- { 606, 5, 1, 3, "VMINsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #606 = VMINsv8i8
- { 607, 5, 1, 4, "VMINuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #607 = VMINuv16i8
- { 608, 5, 1, 3, "VMINuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #608 = VMINuv2i32
- { 609, 5, 1, 3, "VMINuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #609 = VMINuv4i16
- { 610, 5, 1, 4, "VMINuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #610 = VMINuv4i32
- { 611, 5, 1, 4, "VMINuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #611 = VMINuv8i16
- { 612, 5, 1, 3, "VMINuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #612 = VMINuv8i8
- { 613, 6, 1, 77, "VMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #613 = VMLAD
- { 614, 7, 1, 19, "VMLALslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #614 = VMLALslsv2i32
- { 615, 7, 1, 17, "VMLALslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #615 = VMLALslsv4i16
- { 616, 7, 1, 19, "VMLALsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #616 = VMLALsluv2i32
- { 617, 7, 1, 17, "VMLALsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #617 = VMLALsluv4i16
- { 618, 6, 1, 17, "VMLALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #618 = VMLALsv2i64
- { 619, 6, 1, 17, "VMLALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #619 = VMLALsv4i32
- { 620, 6, 1, 17, "VMLALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #620 = VMLALsv8i16
- { 621, 6, 1, 17, "VMLALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #621 = VMLALuv2i64
- { 622, 6, 1, 17, "VMLALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #622 = VMLALuv4i32
- { 623, 6, 1, 17, "VMLALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #623 = VMLALuv8i16
- { 624, 6, 1, 76, "VMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #624 = VMLAS
- { 625, 6, 1, 15, "VMLAfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #625 = VMLAfd
- { 626, 6, 1, 16, "VMLAfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #626 = VMLAfq
- { 627, 7, 1, 15, "VMLAslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #627 = VMLAslfd
- { 628, 7, 1, 16, "VMLAslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #628 = VMLAslfq
- { 629, 7, 1, 19, "VMLAslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #629 = VMLAslv2i32
- { 630, 7, 1, 17, "VMLAslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #630 = VMLAslv4i16
- { 631, 7, 1, 20, "VMLAslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #631 = VMLAslv4i32
- { 632, 7, 1, 18, "VMLAslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #632 = VMLAslv8i16
- { 633, 6, 1, 18, "VMLAv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #633 = VMLAv16i8
- { 634, 6, 1, 19, "VMLAv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #634 = VMLAv2i32
- { 635, 6, 1, 17, "VMLAv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #635 = VMLAv4i16
- { 636, 6, 1, 20, "VMLAv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #636 = VMLAv4i32
- { 637, 6, 1, 18, "VMLAv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #637 = VMLAv8i16
- { 638, 6, 1, 17, "VMLAv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #638 = VMLAv8i8
- { 639, 6, 1, 77, "VMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #639 = VMLSD
- { 640, 7, 1, 19, "VMLSLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #640 = VMLSLslsv2i32
- { 641, 7, 1, 17, "VMLSLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #641 = VMLSLslsv4i16
- { 642, 7, 1, 19, "VMLSLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #642 = VMLSLsluv2i32
- { 643, 7, 1, 17, "VMLSLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #643 = VMLSLsluv4i16
- { 644, 6, 1, 17, "VMLSLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #644 = VMLSLsv2i64
- { 645, 6, 1, 17, "VMLSLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #645 = VMLSLsv4i32
- { 646, 6, 1, 17, "VMLSLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #646 = VMLSLsv8i16
- { 647, 6, 1, 17, "VMLSLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #647 = VMLSLuv2i64
- { 648, 6, 1, 17, "VMLSLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #648 = VMLSLuv4i32
- { 649, 6, 1, 17, "VMLSLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #649 = VMLSLuv8i16
- { 650, 6, 1, 76, "VMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #650 = VMLSS
- { 651, 6, 1, 15, "VMLSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #651 = VMLSfd
- { 652, 6, 1, 16, "VMLSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #652 = VMLSfq
- { 653, 7, 1, 15, "VMLSslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #653 = VMLSslfd
- { 654, 7, 1, 16, "VMLSslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #654 = VMLSslfq
- { 655, 7, 1, 19, "VMLSslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #655 = VMLSslv2i32
- { 656, 7, 1, 17, "VMLSslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #656 = VMLSslv4i16
- { 657, 7, 1, 20, "VMLSslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #657 = VMLSslv4i32
- { 658, 7, 1, 18, "VMLSslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #658 = VMLSslv8i16
- { 659, 6, 1, 18, "VMLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #659 = VMLSv16i8
- { 660, 6, 1, 19, "VMLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #660 = VMLSv2i32
- { 661, 6, 1, 17, "VMLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #661 = VMLSv4i16
- { 662, 6, 1, 20, "VMLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #662 = VMLSv4i32
- { 663, 6, 1, 18, "VMLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #663 = VMLSv8i16
- { 664, 6, 1, 17, "VMLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #664 = VMLSv8i8
- { 665, 4, 1, 87, "VMOVD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #665 = VMOVD
- { 666, 5, 1, 23, "VMOVDRR", 0|(1<<TID::Predicable), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #666 = VMOVDRR
- { 667, 5, 1, 87, "VMOVDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #667 = VMOVDcc
- { 668, 4, 1, 21, "VMOVDneon", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #668 = VMOVDneon
- { 669, 4, 1, 38, "VMOVLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #669 = VMOVLsv2i64
- { 670, 4, 1, 38, "VMOVLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #670 = VMOVLsv4i32
- { 671, 4, 1, 38, "VMOVLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #671 = VMOVLsv8i16
- { 672, 4, 1, 38, "VMOVLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #672 = VMOVLuv2i64
- { 673, 4, 1, 38, "VMOVLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #673 = VMOVLuv4i32
- { 674, 4, 1, 38, "VMOVLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #674 = VMOVLuv8i16
- { 675, 4, 1, 21, "VMOVNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #675 = VMOVNv2i32
- { 676, 4, 1, 21, "VMOVNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #676 = VMOVNv4i16
- { 677, 4, 1, 21, "VMOVNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #677 = VMOVNv8i8
- { 678, 4, 1, 21, "VMOVQ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #678 = VMOVQ
- { 679, 5, 2, 22, "VMOVRRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #679 = VMOVRRD
- { 680, 6, 2, 22, "VMOVRRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #680 = VMOVRRS
- { 681, 4, 1, 28, "VMOVRS", 0|(1<<TID::Predicable), 0|(3<<4)|(16<<9)|(1<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #681 = VMOVRS
- { 682, 4, 1, 86, "VMOVS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #682 = VMOVS
- { 683, 4, 1, 24, "VMOVSR", 0|(1<<TID::Predicable), 0|(3<<4)|(18<<9)|(1<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #683 = VMOVSR
- { 684, 6, 2, 23, "VMOVSRR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #684 = VMOVSRR
- { 685, 5, 1, 86, "VMOVScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #685 = VMOVScc
- { 686, 4, 1, 26, "VMOVv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #686 = VMOVv16i8
- { 687, 4, 1, 26, "VMOVv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #687 = VMOVv1i64
- { 688, 4, 1, 26, "VMOVv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #688 = VMOVv2i32
- { 689, 4, 1, 26, "VMOVv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #689 = VMOVv2i64
- { 690, 4, 1, 26, "VMOVv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #690 = VMOVv4i16
- { 691, 4, 1, 26, "VMOVv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #691 = VMOVv4i32
- { 692, 4, 1, 26, "VMOVv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #692 = VMOVv8i16
- { 693, 4, 1, 26, "VMOVv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #693 = VMOVv8i8
- { 694, 3, 1, 82, "VMRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, NULL, NULL, OperandInfo20 }, // Inst #694 = VMRS
- { 695, 3, 0, 82, "VMSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(22<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo20 }, // Inst #695 = VMSR
- { 696, 5, 1, 79, "VMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #696 = VMULD
- { 697, 5, 1, 29, "VMULLp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #697 = VMULLp
- { 698, 6, 1, 29, "VMULLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #698 = VMULLslsv2i32
- { 699, 6, 1, 29, "VMULLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #699 = VMULLslsv4i16
- { 700, 6, 1, 29, "VMULLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #700 = VMULLsluv2i32
- { 701, 6, 1, 29, "VMULLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #701 = VMULLsluv4i16
- { 702, 5, 1, 29, "VMULLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #702 = VMULLsv2i64
- { 703, 5, 1, 29, "VMULLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #703 = VMULLsv4i32
- { 704, 5, 1, 29, "VMULLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #704 = VMULLsv8i16
- { 705, 5, 1, 29, "VMULLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #705 = VMULLuv2i64
- { 706, 5, 1, 29, "VMULLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #706 = VMULLuv4i32
- { 707, 5, 1, 29, "VMULLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #707 = VMULLuv8i16
- { 708, 5, 1, 78, "VMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #708 = VMULS
- { 709, 5, 1, 1, "VMULfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #709 = VMULfd
- { 710, 5, 1, 1, "VMULfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #710 = VMULfd_sfp
- { 711, 5, 1, 2, "VMULfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #711 = VMULfq
- { 712, 5, 1, 29, "VMULpd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #712 = VMULpd
- { 713, 5, 1, 30, "VMULpq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #713 = VMULpq
- { 714, 6, 1, 1, "VMULslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #714 = VMULslfd
- { 715, 6, 1, 2, "VMULslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #715 = VMULslfq
- { 716, 6, 1, 31, "VMULslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #716 = VMULslv2i32
- { 717, 6, 1, 29, "VMULslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #717 = VMULslv4i16
- { 718, 6, 1, 32, "VMULslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #718 = VMULslv4i32
- { 719, 6, 1, 30, "VMULslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #719 = VMULslv8i16
- { 720, 5, 1, 30, "VMULv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #720 = VMULv16i8
- { 721, 5, 1, 31, "VMULv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #721 = VMULv2i32
- { 722, 5, 1, 29, "VMULv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #722 = VMULv4i16
- { 723, 5, 1, 32, "VMULv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #723 = VMULv4i32
- { 724, 5, 1, 30, "VMULv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #724 = VMULv8i16
- { 725, 5, 1, 29, "VMULv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #725 = VMULv8i8
- { 726, 4, 1, 44, "VMVNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #726 = VMVNd
- { 727, 4, 1, 44, "VMVNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #727 = VMVNq
- { 728, 4, 1, 87, "VNEGD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #728 = VNEGD
- { 729, 5, 1, 87, "VNEGDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #729 = VNEGDcc
- { 730, 4, 1, 86, "VNEGS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #730 = VNEGS
- { 731, 5, 1, 86, "VNEGScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #731 = VNEGScc
- { 732, 4, 1, 57, "VNEGf32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #732 = VNEGf32d
- { 733, 4, 1, 57, "VNEGf32d_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #733 = VNEGf32d_sfp
- { 734, 4, 1, 58, "VNEGf32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #734 = VNEGf32q
- { 735, 4, 1, 44, "VNEGs16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #735 = VNEGs16d
- { 736, 4, 1, 44, "VNEGs16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #736 = VNEGs16q
- { 737, 4, 1, 44, "VNEGs32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #737 = VNEGs32d
- { 738, 4, 1, 44, "VNEGs32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #738 = VNEGs32q
- { 739, 4, 1, 44, "VNEGs8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #739 = VNEGs8d
- { 740, 4, 1, 44, "VNEGs8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #740 = VNEGs8q
- { 741, 6, 1, 77, "VNMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #741 = VNMLAD
- { 742, 6, 1, 76, "VNMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #742 = VNMLAS
- { 743, 6, 1, 77, "VNMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #743 = VNMLSD
- { 744, 6, 1, 76, "VNMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #744 = VNMLSS
- { 745, 5, 1, 79, "VNMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #745 = VNMULD
- { 746, 5, 1, 78, "VNMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #746 = VNMULS
- { 747, 5, 1, 5, "VORNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #747 = VORNd
- { 748, 5, 1, 6, "VORNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #748 = VORNq
- { 749, 5, 1, 5, "VORRd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #749 = VORRd
- { 750, 5, 1, 6, "VORRq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #750 = VORRq
- { 751, 5, 1, 34, "VPADALsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #751 = VPADALsv16i8
- { 752, 5, 1, 33, "VPADALsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #752 = VPADALsv2i32
- { 753, 5, 1, 33, "VPADALsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #753 = VPADALsv4i16
- { 754, 5, 1, 34, "VPADALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #754 = VPADALsv4i32
- { 755, 5, 1, 34, "VPADALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #755 = VPADALsv8i16
- { 756, 5, 1, 33, "VPADALsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #756 = VPADALsv8i8
- { 757, 5, 1, 34, "VPADALuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #757 = VPADALuv16i8
- { 758, 5, 1, 33, "VPADALuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #758 = VPADALuv2i32
- { 759, 5, 1, 33, "VPADALuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #759 = VPADALuv4i16
- { 760, 5, 1, 34, "VPADALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #760 = VPADALuv4i32
- { 761, 5, 1, 34, "VPADALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #761 = VPADALuv8i16
- { 762, 5, 1, 33, "VPADALuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #762 = VPADALuv8i8
- { 763, 4, 1, 44, "VPADDLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #763 = VPADDLsv16i8
- { 764, 4, 1, 44, "VPADDLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #764 = VPADDLsv2i32
- { 765, 4, 1, 44, "VPADDLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #765 = VPADDLsv4i16
- { 766, 4, 1, 44, "VPADDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #766 = VPADDLsv4i32
- { 767, 4, 1, 44, "VPADDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #767 = VPADDLsv8i16
- { 768, 4, 1, 44, "VPADDLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #768 = VPADDLsv8i8
- { 769, 4, 1, 44, "VPADDLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #769 = VPADDLuv16i8
- { 770, 4, 1, 44, "VPADDLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #770 = VPADDLuv2i32
- { 771, 4, 1, 44, "VPADDLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #771 = VPADDLuv4i16
- { 772, 4, 1, 44, "VPADDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #772 = VPADDLuv4i32
- { 773, 4, 1, 44, "VPADDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #773 = VPADDLuv8i16
- { 774, 4, 1, 44, "VPADDLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #774 = VPADDLuv8i8
- { 775, 5, 1, 1, "VPADDf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #775 = VPADDf
- { 776, 5, 1, 5, "VPADDi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #776 = VPADDi16
- { 777, 5, 1, 5, "VPADDi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #777 = VPADDi32
- { 778, 5, 1, 5, "VPADDi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #778 = VPADDi8
- { 779, 5, 1, 3, "VPMAXf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #779 = VPMAXf
- { 780, 5, 1, 3, "VPMAXs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #780 = VPMAXs16
- { 781, 5, 1, 3, "VPMAXs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #781 = VPMAXs32
- { 782, 5, 1, 3, "VPMAXs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #782 = VPMAXs8
- { 783, 5, 1, 3, "VPMAXu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #783 = VPMAXu16
- { 784, 5, 1, 3, "VPMAXu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #784 = VPMAXu32
- { 785, 5, 1, 3, "VPMAXu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #785 = VPMAXu8
- { 786, 5, 1, 3, "VPMINf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #786 = VPMINf
- { 787, 5, 1, 3, "VPMINs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #787 = VPMINs16
- { 788, 5, 1, 3, "VPMINs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #788 = VPMINs32
- { 789, 5, 1, 3, "VPMINs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #789 = VPMINs8
- { 790, 5, 1, 3, "VPMINu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #790 = VPMINu16
- { 791, 5, 1, 3, "VPMINu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #791 = VPMINu32
- { 792, 5, 1, 3, "VPMINu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #792 = VPMINu8
- { 793, 4, 1, 39, "VQABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #793 = VQABSv16i8
- { 794, 4, 1, 38, "VQABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #794 = VQABSv2i32
- { 795, 4, 1, 38, "VQABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #795 = VQABSv4i16
- { 796, 4, 1, 39, "VQABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #796 = VQABSv4i32
- { 797, 4, 1, 39, "VQABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #797 = VQABSv8i16
- { 798, 4, 1, 38, "VQABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #798 = VQABSv8i8
- { 799, 5, 1, 4, "VQADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #799 = VQADDsv16i8
- { 800, 5, 1, 3, "VQADDsv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #800 = VQADDsv1i64
- { 801, 5, 1, 3, "VQADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #801 = VQADDsv2i32
- { 802, 5, 1, 4, "VQADDsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #802 = VQADDsv2i64
- { 803, 5, 1, 3, "VQADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #803 = VQADDsv4i16
- { 804, 5, 1, 4, "VQADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #804 = VQADDsv4i32
- { 805, 5, 1, 4, "VQADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #805 = VQADDsv8i16
- { 806, 5, 1, 3, "VQADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #806 = VQADDsv8i8
- { 807, 5, 1, 4, "VQADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #807 = VQADDuv16i8
- { 808, 5, 1, 3, "VQADDuv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #808 = VQADDuv1i64
- { 809, 5, 1, 3, "VQADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #809 = VQADDuv2i32
- { 810, 5, 1, 4, "VQADDuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #810 = VQADDuv2i64
- { 811, 5, 1, 3, "VQADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #811 = VQADDuv4i16
- { 812, 5, 1, 4, "VQADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #812 = VQADDuv4i32
- { 813, 5, 1, 4, "VQADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #813 = VQADDuv8i16
- { 814, 5, 1, 3, "VQADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #814 = VQADDuv8i8
- { 815, 7, 1, 19, "VQDMLALslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #815 = VQDMLALslv2i32
- { 816, 7, 1, 17, "VQDMLALslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #816 = VQDMLALslv4i16
- { 817, 6, 1, 17, "VQDMLALv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #817 = VQDMLALv2i64
- { 818, 6, 1, 17, "VQDMLALv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #818 = VQDMLALv4i32
- { 819, 7, 1, 19, "VQDMLSLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #819 = VQDMLSLslv2i32
- { 820, 7, 1, 17, "VQDMLSLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #820 = VQDMLSLslv4i16
- { 821, 6, 1, 17, "VQDMLSLv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #821 = VQDMLSLv2i64
- { 822, 6, 1, 17, "VQDMLSLv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #822 = VQDMLSLv4i32
- { 823, 6, 1, 31, "VQDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #823 = VQDMULHslv2i32
- { 824, 6, 1, 29, "VQDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #824 = VQDMULHslv4i16
- { 825, 6, 1, 32, "VQDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #825 = VQDMULHslv4i32
- { 826, 6, 1, 30, "VQDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #826 = VQDMULHslv8i16
- { 827, 5, 1, 31, "VQDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #827 = VQDMULHv2i32
- { 828, 5, 1, 29, "VQDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #828 = VQDMULHv4i16
- { 829, 5, 1, 32, "VQDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #829 = VQDMULHv4i32
- { 830, 5, 1, 30, "VQDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #830 = VQDMULHv8i16
- { 831, 6, 1, 29, "VQDMULLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #831 = VQDMULLslv2i32
- { 832, 6, 1, 29, "VQDMULLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #832 = VQDMULLslv4i16
- { 833, 5, 1, 29, "VQDMULLv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #833 = VQDMULLv2i64
- { 834, 5, 1, 29, "VQDMULLv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #834 = VQDMULLv4i32
- { 835, 4, 1, 38, "VQMOVNsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #835 = VQMOVNsuv2i32
- { 836, 4, 1, 38, "VQMOVNsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #836 = VQMOVNsuv4i16
- { 837, 4, 1, 38, "VQMOVNsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #837 = VQMOVNsuv8i8
- { 838, 4, 1, 38, "VQMOVNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #838 = VQMOVNsv2i32
- { 839, 4, 1, 38, "VQMOVNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #839 = VQMOVNsv4i16
- { 840, 4, 1, 38, "VQMOVNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #840 = VQMOVNsv8i8
- { 841, 4, 1, 38, "VQMOVNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #841 = VQMOVNuv2i32
- { 842, 4, 1, 38, "VQMOVNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #842 = VQMOVNuv4i16
- { 843, 4, 1, 38, "VQMOVNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #843 = VQMOVNuv8i8
- { 844, 4, 1, 39, "VQNEGv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #844 = VQNEGv16i8
- { 845, 4, 1, 38, "VQNEGv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #845 = VQNEGv2i32
- { 846, 4, 1, 38, "VQNEGv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #846 = VQNEGv4i16
- { 847, 4, 1, 39, "VQNEGv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #847 = VQNEGv4i32
- { 848, 4, 1, 39, "VQNEGv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #848 = VQNEGv8i16
- { 849, 4, 1, 38, "VQNEGv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #849 = VQNEGv8i8
- { 850, 6, 1, 31, "VQRDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #850 = VQRDMULHslv2i32
- { 851, 6, 1, 29, "VQRDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #851 = VQRDMULHslv4i16
- { 852, 6, 1, 32, "VQRDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #852 = VQRDMULHslv4i32
- { 853, 6, 1, 30, "VQRDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #853 = VQRDMULHslv8i16
- { 854, 5, 1, 31, "VQRDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #854 = VQRDMULHv2i32
- { 855, 5, 1, 29, "VQRDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #855 = VQRDMULHv4i16
- { 856, 5, 1, 32, "VQRDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #856 = VQRDMULHv4i32
- { 857, 5, 1, 30, "VQRDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #857 = VQRDMULHv8i16
- { 858, 5, 1, 43, "VQRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #858 = VQRSHLsv16i8
- { 859, 5, 1, 42, "VQRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #859 = VQRSHLsv1i64
- { 860, 5, 1, 42, "VQRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #860 = VQRSHLsv2i32
- { 861, 5, 1, 43, "VQRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #861 = VQRSHLsv2i64
- { 862, 5, 1, 42, "VQRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #862 = VQRSHLsv4i16
- { 863, 5, 1, 43, "VQRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #863 = VQRSHLsv4i32
- { 864, 5, 1, 43, "VQRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #864 = VQRSHLsv8i16
- { 865, 5, 1, 42, "VQRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #865 = VQRSHLsv8i8
- { 866, 5, 1, 43, "VQRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #866 = VQRSHLuv16i8
- { 867, 5, 1, 42, "VQRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #867 = VQRSHLuv1i64
- { 868, 5, 1, 42, "VQRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #868 = VQRSHLuv2i32
- { 869, 5, 1, 43, "VQRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #869 = VQRSHLuv2i64
- { 870, 5, 1, 42, "VQRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #870 = VQRSHLuv4i16
- { 871, 5, 1, 43, "VQRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #871 = VQRSHLuv4i32
- { 872, 5, 1, 43, "VQRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #872 = VQRSHLuv8i16
- { 873, 5, 1, 42, "VQRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #873 = VQRSHLuv8i8
- { 874, 5, 1, 42, "VQRSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #874 = VQRSHRNsv2i32
- { 875, 5, 1, 42, "VQRSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #875 = VQRSHRNsv4i16
- { 876, 5, 1, 42, "VQRSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #876 = VQRSHRNsv8i8
- { 877, 5, 1, 42, "VQRSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #877 = VQRSHRNuv2i32
- { 878, 5, 1, 42, "VQRSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #878 = VQRSHRNuv4i16
- { 879, 5, 1, 42, "VQRSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #879 = VQRSHRNuv8i8
- { 880, 5, 1, 42, "VQRSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #880 = VQRSHRUNv2i32
- { 881, 5, 1, 42, "VQRSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #881 = VQRSHRUNv4i16
- { 882, 5, 1, 42, "VQRSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #882 = VQRSHRUNv8i8
- { 883, 5, 1, 42, "VQSHLsiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #883 = VQSHLsiv16i8
- { 884, 5, 1, 42, "VQSHLsiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #884 = VQSHLsiv1i64
- { 885, 5, 1, 42, "VQSHLsiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #885 = VQSHLsiv2i32
- { 886, 5, 1, 42, "VQSHLsiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #886 = VQSHLsiv2i64
- { 887, 5, 1, 42, "VQSHLsiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #887 = VQSHLsiv4i16
- { 888, 5, 1, 42, "VQSHLsiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #888 = VQSHLsiv4i32
- { 889, 5, 1, 42, "VQSHLsiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #889 = VQSHLsiv8i16
- { 890, 5, 1, 42, "VQSHLsiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #890 = VQSHLsiv8i8
- { 891, 5, 1, 42, "VQSHLsuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #891 = VQSHLsuv16i8
- { 892, 5, 1, 42, "VQSHLsuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #892 = VQSHLsuv1i64
- { 893, 5, 1, 42, "VQSHLsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #893 = VQSHLsuv2i32
- { 894, 5, 1, 42, "VQSHLsuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #894 = VQSHLsuv2i64
- { 895, 5, 1, 42, "VQSHLsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #895 = VQSHLsuv4i16
- { 896, 5, 1, 42, "VQSHLsuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #896 = VQSHLsuv4i32
- { 897, 5, 1, 42, "VQSHLsuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #897 = VQSHLsuv8i16
- { 898, 5, 1, 42, "VQSHLsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #898 = VQSHLsuv8i8
- { 899, 5, 1, 43, "VQSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #899 = VQSHLsv16i8
- { 900, 5, 1, 42, "VQSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #900 = VQSHLsv1i64
- { 901, 5, 1, 42, "VQSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #901 = VQSHLsv2i32
- { 902, 5, 1, 43, "VQSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #902 = VQSHLsv2i64
- { 903, 5, 1, 42, "VQSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #903 = VQSHLsv4i16
- { 904, 5, 1, 43, "VQSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #904 = VQSHLsv4i32
- { 905, 5, 1, 43, "VQSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #905 = VQSHLsv8i16
- { 906, 5, 1, 42, "VQSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #906 = VQSHLsv8i8
- { 907, 5, 1, 42, "VQSHLuiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #907 = VQSHLuiv16i8
- { 908, 5, 1, 42, "VQSHLuiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #908 = VQSHLuiv1i64
- { 909, 5, 1, 42, "VQSHLuiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #909 = VQSHLuiv2i32
- { 910, 5, 1, 42, "VQSHLuiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #910 = VQSHLuiv2i64
- { 911, 5, 1, 42, "VQSHLuiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #911 = VQSHLuiv4i16
- { 912, 5, 1, 42, "VQSHLuiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #912 = VQSHLuiv4i32
- { 913, 5, 1, 42, "VQSHLuiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #913 = VQSHLuiv8i16
- { 914, 5, 1, 42, "VQSHLuiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #914 = VQSHLuiv8i8
- { 915, 5, 1, 43, "VQSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #915 = VQSHLuv16i8
- { 916, 5, 1, 42, "VQSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #916 = VQSHLuv1i64
- { 917, 5, 1, 42, "VQSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #917 = VQSHLuv2i32
- { 918, 5, 1, 43, "VQSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #918 = VQSHLuv2i64
- { 919, 5, 1, 42, "VQSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #919 = VQSHLuv4i16
- { 920, 5, 1, 43, "VQSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #920 = VQSHLuv4i32
- { 921, 5, 1, 43, "VQSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #921 = VQSHLuv8i16
- { 922, 5, 1, 42, "VQSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #922 = VQSHLuv8i8
- { 923, 5, 1, 42, "VQSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #923 = VQSHRNsv2i32
- { 924, 5, 1, 42, "VQSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #924 = VQSHRNsv4i16
- { 925, 5, 1, 42, "VQSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #925 = VQSHRNsv8i8
- { 926, 5, 1, 42, "VQSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #926 = VQSHRNuv2i32
- { 927, 5, 1, 42, "VQSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #927 = VQSHRNuv4i16
- { 928, 5, 1, 42, "VQSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #928 = VQSHRNuv8i8
- { 929, 5, 1, 42, "VQSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #929 = VQSHRUNv2i32
- { 930, 5, 1, 42, "VQSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #930 = VQSHRUNv4i16
- { 931, 5, 1, 42, "VQSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #931 = VQSHRUNv8i8
- { 932, 5, 1, 4, "VQSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #932 = VQSUBsv16i8
- { 933, 5, 1, 3, "VQSUBsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #933 = VQSUBsv1i64
- { 934, 5, 1, 3, "VQSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #934 = VQSUBsv2i32
- { 935, 5, 1, 4, "VQSUBsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #935 = VQSUBsv2i64
- { 936, 5, 1, 3, "VQSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #936 = VQSUBsv4i16
- { 937, 5, 1, 4, "VQSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #937 = VQSUBsv4i32
- { 938, 5, 1, 4, "VQSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #938 = VQSUBsv8i16
- { 939, 5, 1, 3, "VQSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #939 = VQSUBsv8i8
- { 940, 5, 1, 4, "VQSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #940 = VQSUBuv16i8
- { 941, 5, 1, 3, "VQSUBuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #941 = VQSUBuv1i64
- { 942, 5, 1, 3, "VQSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #942 = VQSUBuv2i32
- { 943, 5, 1, 4, "VQSUBuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #943 = VQSUBuv2i64
- { 944, 5, 1, 3, "VQSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #944 = VQSUBuv4i16
- { 945, 5, 1, 4, "VQSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #945 = VQSUBuv4i32
- { 946, 5, 1, 4, "VQSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #946 = VQSUBuv8i16
- { 947, 5, 1, 3, "VQSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #947 = VQSUBuv8i8
- { 948, 5, 1, 3, "VRADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #948 = VRADDHNv2i32
- { 949, 5, 1, 3, "VRADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #949 = VRADDHNv4i16
- { 950, 5, 1, 3, "VRADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #950 = VRADDHNv8i8
- { 951, 4, 1, 57, "VRECPEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #951 = VRECPEd
- { 952, 4, 1, 57, "VRECPEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #952 = VRECPEfd
- { 953, 4, 1, 58, "VRECPEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #953 = VRECPEfq
- { 954, 4, 1, 58, "VRECPEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #954 = VRECPEq
- { 955, 5, 1, 40, "VRECPSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #955 = VRECPSfd
- { 956, 5, 1, 41, "VRECPSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #956 = VRECPSfq
- { 957, 4, 1, 21, "VREV16d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #957 = VREV16d8
- { 958, 4, 1, 21, "VREV16q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #958 = VREV16q8
- { 959, 4, 1, 21, "VREV32d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #959 = VREV32d16
- { 960, 4, 1, 21, "VREV32d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #960 = VREV32d8
- { 961, 4, 1, 21, "VREV32q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #961 = VREV32q16
- { 962, 4, 1, 21, "VREV32q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #962 = VREV32q8
- { 963, 4, 1, 21, "VREV64d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #963 = VREV64d16
- { 964, 4, 1, 21, "VREV64d32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #964 = VREV64d32
- { 965, 4, 1, 21, "VREV64d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #965 = VREV64d8
- { 966, 4, 1, 21, "VREV64df", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #966 = VREV64df
- { 967, 4, 1, 21, "VREV64q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #967 = VREV64q16
- { 968, 4, 1, 21, "VREV64q32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #968 = VREV64q32
- { 969, 4, 1, 21, "VREV64q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #969 = VREV64q8
- { 970, 4, 1, 21, "VREV64qf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #970 = VREV64qf
- { 971, 5, 1, 4, "VRHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #971 = VRHADDsv16i8
- { 972, 5, 1, 3, "VRHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #972 = VRHADDsv2i32
- { 973, 5, 1, 3, "VRHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #973 = VRHADDsv4i16
- { 974, 5, 1, 4, "VRHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #974 = VRHADDsv4i32
- { 975, 5, 1, 4, "VRHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #975 = VRHADDsv8i16
- { 976, 5, 1, 3, "VRHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #976 = VRHADDsv8i8
- { 977, 5, 1, 4, "VRHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #977 = VRHADDuv16i8
- { 978, 5, 1, 3, "VRHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #978 = VRHADDuv2i32
- { 979, 5, 1, 3, "VRHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #979 = VRHADDuv4i16
- { 980, 5, 1, 4, "VRHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #980 = VRHADDuv4i32
- { 981, 5, 1, 4, "VRHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #981 = VRHADDuv8i16
- { 982, 5, 1, 3, "VRHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #982 = VRHADDuv8i8
- { 983, 5, 1, 43, "VRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #983 = VRSHLsv16i8
- { 984, 5, 1, 42, "VRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #984 = VRSHLsv1i64
- { 985, 5, 1, 42, "VRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #985 = VRSHLsv2i32
- { 986, 5, 1, 43, "VRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #986 = VRSHLsv2i64
- { 987, 5, 1, 42, "VRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #987 = VRSHLsv4i16
- { 988, 5, 1, 43, "VRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #988 = VRSHLsv4i32
- { 989, 5, 1, 43, "VRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #989 = VRSHLsv8i16
- { 990, 5, 1, 42, "VRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #990 = VRSHLsv8i8
- { 991, 5, 1, 43, "VRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #991 = VRSHLuv16i8
- { 992, 5, 1, 42, "VRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #992 = VRSHLuv1i64
- { 993, 5, 1, 42, "VRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #993 = VRSHLuv2i32
- { 994, 5, 1, 43, "VRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #994 = VRSHLuv2i64
- { 995, 5, 1, 42, "VRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #995 = VRSHLuv4i16
- { 996, 5, 1, 43, "VRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #996 = VRSHLuv4i32
- { 997, 5, 1, 43, "VRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #997 = VRSHLuv8i16
- { 998, 5, 1, 42, "VRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #998 = VRSHLuv8i8
- { 999, 5, 1, 42, "VRSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #999 = VRSHRNv2i32
- { 1000, 5, 1, 42, "VRSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1000 = VRSHRNv4i16
- { 1001, 5, 1, 42, "VRSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1001 = VRSHRNv8i8
- { 1002, 5, 1, 42, "VRSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1002 = VRSHRsv16i8
- { 1003, 5, 1, 42, "VRSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1003 = VRSHRsv1i64
- { 1004, 5, 1, 42, "VRSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1004 = VRSHRsv2i32
- { 1005, 5, 1, 42, "VRSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1005 = VRSHRsv2i64
- { 1006, 5, 1, 42, "VRSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1006 = VRSHRsv4i16
- { 1007, 5, 1, 42, "VRSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1007 = VRSHRsv4i32
- { 1008, 5, 1, 42, "VRSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1008 = VRSHRsv8i16
- { 1009, 5, 1, 42, "VRSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1009 = VRSHRsv8i8
- { 1010, 5, 1, 42, "VRSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1010 = VRSHRuv16i8
- { 1011, 5, 1, 42, "VRSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1011 = VRSHRuv1i64
- { 1012, 5, 1, 42, "VRSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1012 = VRSHRuv2i32
- { 1013, 5, 1, 42, "VRSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1013 = VRSHRuv2i64
- { 1014, 5, 1, 42, "VRSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1014 = VRSHRuv4i16
- { 1015, 5, 1, 42, "VRSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1015 = VRSHRuv4i32
- { 1016, 5, 1, 42, "VRSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1016 = VRSHRuv8i16
- { 1017, 5, 1, 42, "VRSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1017 = VRSHRuv8i8
- { 1018, 4, 1, 57, "VRSQRTEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #1018 = VRSQRTEd
- { 1019, 4, 1, 57, "VRSQRTEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #1019 = VRSQRTEfd
- { 1020, 4, 1, 58, "VRSQRTEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1020 = VRSQRTEfq
- { 1021, 4, 1, 58, "VRSQRTEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1021 = VRSQRTEq
- { 1022, 5, 1, 40, "VRSQRTSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1022 = VRSQRTSfd
- { 1023, 5, 1, 41, "VRSQRTSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1023 = VRSQRTSfq
- { 1024, 6, 1, 33, "VRSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1024 = VRSRAsv16i8
- { 1025, 6, 1, 33, "VRSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1025 = VRSRAsv1i64
- { 1026, 6, 1, 33, "VRSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1026 = VRSRAsv2i32
- { 1027, 6, 1, 33, "VRSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1027 = VRSRAsv2i64
- { 1028, 6, 1, 33, "VRSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1028 = VRSRAsv4i16
- { 1029, 6, 1, 33, "VRSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1029 = VRSRAsv4i32
- { 1030, 6, 1, 33, "VRSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1030 = VRSRAsv8i16
- { 1031, 6, 1, 33, "VRSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1031 = VRSRAsv8i8
- { 1032, 6, 1, 33, "VRSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1032 = VRSRAuv16i8
- { 1033, 6, 1, 33, "VRSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1033 = VRSRAuv1i64
- { 1034, 6, 1, 33, "VRSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1034 = VRSRAuv2i32
- { 1035, 6, 1, 33, "VRSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1035 = VRSRAuv2i64
- { 1036, 6, 1, 33, "VRSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1036 = VRSRAuv4i16
- { 1037, 6, 1, 33, "VRSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1037 = VRSRAuv4i32
- { 1038, 6, 1, 33, "VRSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1038 = VRSRAuv8i16
- { 1039, 6, 1, 33, "VRSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1039 = VRSRAuv8i8
- { 1040, 5, 1, 3, "VRSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1040 = VRSUBHNv2i32
- { 1041, 5, 1, 3, "VRSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1041 = VRSUBHNv4i16
- { 1042, 5, 1, 3, "VRSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1042 = VRSUBHNv8i8
- { 1043, 6, 1, 25, "VSETLNi16", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo119 }, // Inst #1043 = VSETLNi16
- { 1044, 6, 1, 25, "VSETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo119 }, // Inst #1044 = VSETLNi32
- { 1045, 6, 1, 25, "VSETLNi8", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo119 }, // Inst #1045 = VSETLNi8
- { 1046, 5, 1, 44, "VSHLLi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1046 = VSHLLi16
- { 1047, 5, 1, 44, "VSHLLi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1047 = VSHLLi32
- { 1048, 5, 1, 44, "VSHLLi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1048 = VSHLLi8
- { 1049, 5, 1, 44, "VSHLLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1049 = VSHLLsv2i64
- { 1050, 5, 1, 44, "VSHLLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1050 = VSHLLsv4i32
- { 1051, 5, 1, 44, "VSHLLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1051 = VSHLLsv8i16
- { 1052, 5, 1, 44, "VSHLLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1052 = VSHLLuv2i64
- { 1053, 5, 1, 44, "VSHLLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1053 = VSHLLuv4i32
- { 1054, 5, 1, 44, "VSHLLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1054 = VSHLLuv8i16
- { 1055, 5, 1, 44, "VSHLiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1055 = VSHLiv16i8
- { 1056, 5, 1, 44, "VSHLiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1056 = VSHLiv1i64
- { 1057, 5, 1, 44, "VSHLiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1057 = VSHLiv2i32
- { 1058, 5, 1, 44, "VSHLiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1058 = VSHLiv2i64
- { 1059, 5, 1, 44, "VSHLiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1059 = VSHLiv4i16
- { 1060, 5, 1, 44, "VSHLiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1060 = VSHLiv4i32
- { 1061, 5, 1, 44, "VSHLiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1061 = VSHLiv8i16
- { 1062, 5, 1, 44, "VSHLiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1062 = VSHLiv8i8
- { 1063, 5, 1, 45, "VSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1063 = VSHLsv16i8
- { 1064, 5, 1, 44, "VSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1064 = VSHLsv1i64
- { 1065, 5, 1, 44, "VSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1065 = VSHLsv2i32
- { 1066, 5, 1, 45, "VSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1066 = VSHLsv2i64
- { 1067, 5, 1, 44, "VSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1067 = VSHLsv4i16
- { 1068, 5, 1, 45, "VSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1068 = VSHLsv4i32
- { 1069, 5, 1, 45, "VSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1069 = VSHLsv8i16
- { 1070, 5, 1, 44, "VSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1070 = VSHLsv8i8
- { 1071, 5, 1, 45, "VSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1071 = VSHLuv16i8
- { 1072, 5, 1, 44, "VSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1072 = VSHLuv1i64
- { 1073, 5, 1, 44, "VSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1073 = VSHLuv2i32
- { 1074, 5, 1, 45, "VSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1074 = VSHLuv2i64
- { 1075, 5, 1, 44, "VSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1075 = VSHLuv4i16
- { 1076, 5, 1, 45, "VSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1076 = VSHLuv4i32
- { 1077, 5, 1, 45, "VSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1077 = VSHLuv8i16
- { 1078, 5, 1, 44, "VSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1078 = VSHLuv8i8
- { 1079, 5, 1, 44, "VSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1079 = VSHRNv2i32
- { 1080, 5, 1, 44, "VSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1080 = VSHRNv4i16
- { 1081, 5, 1, 44, "VSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1081 = VSHRNv8i8
- { 1082, 5, 1, 44, "VSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1082 = VSHRsv16i8
- { 1083, 5, 1, 44, "VSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1083 = VSHRsv1i64
- { 1084, 5, 1, 44, "VSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1084 = VSHRsv2i32
- { 1085, 5, 1, 44, "VSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1085 = VSHRsv2i64
- { 1086, 5, 1, 44, "VSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1086 = VSHRsv4i16
- { 1087, 5, 1, 44, "VSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1087 = VSHRsv4i32
- { 1088, 5, 1, 44, "VSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1088 = VSHRsv8i16
- { 1089, 5, 1, 44, "VSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1089 = VSHRsv8i8
- { 1090, 5, 1, 44, "VSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1090 = VSHRuv16i8
- { 1091, 5, 1, 44, "VSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1091 = VSHRuv1i64
- { 1092, 5, 1, 44, "VSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1092 = VSHRuv2i32
- { 1093, 5, 1, 44, "VSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1093 = VSHRuv2i64
- { 1094, 5, 1, 44, "VSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1094 = VSHRuv4i16
- { 1095, 5, 1, 44, "VSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1095 = VSHRuv4i32
- { 1096, 5, 1, 44, "VSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1096 = VSHRuv8i16
- { 1097, 5, 1, 44, "VSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1097 = VSHRuv8i8
- { 1098, 5, 1, 67, "VSHTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1098 = VSHTOD
- { 1099, 5, 1, 68, "VSHTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1099 = VSHTOS
- { 1100, 4, 1, 67, "VSITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #1100 = VSITOD
- { 1101, 4, 1, 68, "VSITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1101 = VSITOS
- { 1102, 6, 1, 45, "VSLIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1102 = VSLIv16i8
- { 1103, 6, 1, 44, "VSLIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1103 = VSLIv1i64
- { 1104, 6, 1, 44, "VSLIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1104 = VSLIv2i32
- { 1105, 6, 1, 45, "VSLIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1105 = VSLIv2i64
- { 1106, 6, 1, 44, "VSLIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1106 = VSLIv4i16
- { 1107, 6, 1, 45, "VSLIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1107 = VSLIv4i32
- { 1108, 6, 1, 45, "VSLIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1108 = VSLIv8i16
- { 1109, 6, 1, 44, "VSLIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1109 = VSLIv8i8
- { 1110, 5, 1, 67, "VSLTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1110 = VSLTOD
- { 1111, 5, 1, 68, "VSLTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1111 = VSLTOS
- { 1112, 4, 1, 81, "VSQRTD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #1112 = VSQRTD
- { 1113, 4, 1, 80, "VSQRTS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1113 = VSQRTS
- { 1114, 6, 1, 33, "VSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1114 = VSRAsv16i8
- { 1115, 6, 1, 33, "VSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1115 = VSRAsv1i64
- { 1116, 6, 1, 33, "VSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1116 = VSRAsv2i32
- { 1117, 6, 1, 33, "VSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1117 = VSRAsv2i64
- { 1118, 6, 1, 33, "VSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1118 = VSRAsv4i16
- { 1119, 6, 1, 33, "VSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1119 = VSRAsv4i32
- { 1120, 6, 1, 33, "VSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1120 = VSRAsv8i16
- { 1121, 6, 1, 33, "VSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1121 = VSRAsv8i8
- { 1122, 6, 1, 33, "VSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1122 = VSRAuv16i8
- { 1123, 6, 1, 33, "VSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1123 = VSRAuv1i64
- { 1124, 6, 1, 33, "VSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1124 = VSRAuv2i32
- { 1125, 6, 1, 33, "VSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1125 = VSRAuv2i64
- { 1126, 6, 1, 33, "VSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1126 = VSRAuv4i16
- { 1127, 6, 1, 33, "VSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1127 = VSRAuv4i32
- { 1128, 6, 1, 33, "VSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1128 = VSRAuv8i16
- { 1129, 6, 1, 33, "VSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1129 = VSRAuv8i8
- { 1130, 6, 1, 45, "VSRIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1130 = VSRIv16i8
- { 1131, 6, 1, 44, "VSRIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1131 = VSRIv1i64
- { 1132, 6, 1, 44, "VSRIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1132 = VSRIv2i32
- { 1133, 6, 1, 45, "VSRIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1133 = VSRIv2i64
- { 1134, 6, 1, 44, "VSRIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1134 = VSRIv4i16
- { 1135, 6, 1, 45, "VSRIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1135 = VSRIv4i32
- { 1136, 6, 1, 45, "VSRIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1136 = VSRIv8i16
- { 1137, 6, 1, 44, "VSRIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1137 = VSRIv8i8
- { 1138, 7, 0, 46, "VST1d16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1138 = VST1d16
- { 1139, 7, 0, 46, "VST1d32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1139 = VST1d32
- { 1140, 7, 0, 46, "VST1d64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1140 = VST1d64
- { 1141, 7, 0, 46, "VST1d8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1141 = VST1d8
- { 1142, 7, 0, 46, "VST1df", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1142 = VST1df
- { 1143, 7, 0, 46, "VST1q16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1143 = VST1q16
- { 1144, 7, 0, 46, "VST1q32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1144 = VST1q32
- { 1145, 7, 0, 46, "VST1q64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1145 = VST1q64
- { 1146, 7, 0, 46, "VST1q8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1146 = VST1q8
- { 1147, 7, 0, 46, "VST1qf", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1147 = VST1qf
- { 1148, 9, 0, 46, "VST2LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1148 = VST2LNd16
- { 1149, 9, 0, 46, "VST2LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1149 = VST2LNd32
- { 1150, 9, 0, 46, "VST2LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1150 = VST2LNd8
- { 1151, 9, 0, 46, "VST2LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1151 = VST2LNq16a
- { 1152, 9, 0, 46, "VST2LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1152 = VST2LNq16b
- { 1153, 9, 0, 46, "VST2LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1153 = VST2LNq32a
- { 1154, 9, 0, 46, "VST2LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1154 = VST2LNq32b
- { 1155, 8, 0, 46, "VST2d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1155 = VST2d16
- { 1156, 8, 0, 46, "VST2d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1156 = VST2d32
- { 1157, 8, 0, 46, "VST2d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1157 = VST2d64
- { 1158, 8, 0, 46, "VST2d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1158 = VST2d8
- { 1159, 10, 0, 46, "VST2q16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1159 = VST2q16
- { 1160, 10, 0, 46, "VST2q32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1160 = VST2q32
- { 1161, 10, 0, 46, "VST2q8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1161 = VST2q8
- { 1162, 10, 0, 46, "VST3LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1162 = VST3LNd16
- { 1163, 10, 0, 46, "VST3LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1163 = VST3LNd32
- { 1164, 10, 0, 46, "VST3LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1164 = VST3LNd8
- { 1165, 10, 0, 46, "VST3LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1165 = VST3LNq16a
- { 1166, 10, 0, 46, "VST3LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1166 = VST3LNq16b
- { 1167, 10, 0, 46, "VST3LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1167 = VST3LNq32a
- { 1168, 10, 0, 46, "VST3LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1168 = VST3LNq32b
- { 1169, 9, 0, 46, "VST3d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1169 = VST3d16
- { 1170, 9, 0, 46, "VST3d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1170 = VST3d32
- { 1171, 9, 0, 46, "VST3d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1171 = VST3d64
- { 1172, 9, 0, 46, "VST3d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1172 = VST3d8
- { 1173, 10, 1, 46, "VST3q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1173 = VST3q16a
- { 1174, 10, 1, 46, "VST3q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1174 = VST3q16b
- { 1175, 10, 1, 46, "VST3q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1175 = VST3q32a
- { 1176, 10, 1, 46, "VST3q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1176 = VST3q32b
- { 1177, 10, 1, 46, "VST3q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1177 = VST3q8a
- { 1178, 10, 1, 46, "VST3q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1178 = VST3q8b
- { 1179, 11, 0, 46, "VST4LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1179 = VST4LNd16
- { 1180, 11, 0, 46, "VST4LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1180 = VST4LNd32
- { 1181, 11, 0, 46, "VST4LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1181 = VST4LNd8
- { 1182, 11, 0, 46, "VST4LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1182 = VST4LNq16a
- { 1183, 11, 0, 46, "VST4LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1183 = VST4LNq16b
- { 1184, 11, 0, 46, "VST4LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1184 = VST4LNq32a
- { 1185, 11, 0, 46, "VST4LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1185 = VST4LNq32b
- { 1186, 10, 0, 46, "VST4d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1186 = VST4d16
- { 1187, 10, 0, 46, "VST4d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1187 = VST4d32
- { 1188, 10, 0, 46, "VST4d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1188 = VST4d64
- { 1189, 10, 0, 46, "VST4d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1189 = VST4d8
- { 1190, 11, 1, 46, "VST4q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1190 = VST4q16a
- { 1191, 11, 1, 46, "VST4q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1191 = VST4q16b
- { 1192, 11, 1, 46, "VST4q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1192 = VST4q32a
- { 1193, 11, 1, 46, "VST4q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1193 = VST4q32b
- { 1194, 11, 1, 46, "VST4q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1194 = VST4q8a
- { 1195, 11, 1, 46, "VST4q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1195 = VST4q8b
- { 1196, 5, 0, 85, "VSTMD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo32 }, // Inst #1196 = VSTMD
- { 1197, 5, 0, 85, "VSTMS", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo32 }, // Inst #1197 = VSTMS
- { 1198, 5, 0, 84, "VSTRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #1198 = VSTRD
- { 1199, 5, 0, 85, "VSTRQ", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #1199 = VSTRQ
- { 1200, 5, 0, 83, "VSTRS", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #1200 = VSTRS
- { 1201, 5, 1, 62, "VSUBD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1201 = VSUBD
- { 1202, 5, 1, 3, "VSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1202 = VSUBHNv2i32
- { 1203, 5, 1, 3, "VSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1203 = VSUBHNv4i16
- { 1204, 5, 1, 3, "VSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1204 = VSUBHNv8i8
- { 1205, 5, 1, 44, "VSUBLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1205 = VSUBLsv2i64
- { 1206, 5, 1, 44, "VSUBLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1206 = VSUBLsv4i32
- { 1207, 5, 1, 44, "VSUBLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1207 = VSUBLsv8i16
- { 1208, 5, 1, 44, "VSUBLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1208 = VSUBLuv2i64
- { 1209, 5, 1, 44, "VSUBLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1209 = VSUBLuv4i32
- { 1210, 5, 1, 44, "VSUBLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1210 = VSUBLuv8i16
- { 1211, 5, 1, 61, "VSUBS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1211 = VSUBS
- { 1212, 5, 1, 47, "VSUBWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1212 = VSUBWsv2i64
- { 1213, 5, 1, 47, "VSUBWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1213 = VSUBWsv4i32
- { 1214, 5, 1, 47, "VSUBWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1214 = VSUBWsv8i16
- { 1215, 5, 1, 47, "VSUBWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1215 = VSUBWuv2i64
- { 1216, 5, 1, 47, "VSUBWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1216 = VSUBWuv4i32
- { 1217, 5, 1, 47, "VSUBWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1217 = VSUBWuv8i16
- { 1218, 5, 1, 1, "VSUBfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1218 = VSUBfd
- { 1219, 5, 1, 1, "VSUBfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1219 = VSUBfd_sfp
- { 1220, 5, 1, 2, "VSUBfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1220 = VSUBfq
- { 1221, 5, 1, 48, "VSUBv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1221 = VSUBv16i8
- { 1222, 5, 1, 47, "VSUBv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1222 = VSUBv1i64
- { 1223, 5, 1, 47, "VSUBv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1223 = VSUBv2i32
- { 1224, 5, 1, 48, "VSUBv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1224 = VSUBv2i64
- { 1225, 5, 1, 47, "VSUBv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1225 = VSUBv4i16
- { 1226, 5, 1, 48, "VSUBv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1226 = VSUBv4i32
- { 1227, 5, 1, 48, "VSUBv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1227 = VSUBv8i16
- { 1228, 5, 1, 47, "VSUBv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1228 = VSUBv8i8
- { 1229, 5, 1, 49, "VTBL1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1229 = VTBL1
- { 1230, 6, 1, 50, "VTBL2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1230 = VTBL2
- { 1231, 7, 1, 51, "VTBL3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1231 = VTBL3
- { 1232, 8, 1, 52, "VTBL4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1232 = VTBL4
- { 1233, 6, 1, 53, "VTBX1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1233 = VTBX1
- { 1234, 7, 1, 54, "VTBX2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1234 = VTBX2
- { 1235, 8, 1, 55, "VTBX3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1235 = VTBX3
- { 1236, 9, 1, 56, "VTBX4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1236 = VTBX4
- { 1237, 5, 1, 65, "VTOSHD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1237 = VTOSHD
- { 1238, 5, 1, 70, "VTOSHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1238 = VTOSHS
- { 1239, 4, 1, 65, "VTOSIRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1239 = VTOSIRD
- { 1240, 4, 1, 70, "VTOSIRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1240 = VTOSIRS
- { 1241, 4, 1, 65, "VTOSIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1241 = VTOSIZD
- { 1242, 4, 1, 70, "VTOSIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1242 = VTOSIZS
- { 1243, 5, 1, 65, "VTOSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1243 = VTOSLD
- { 1244, 5, 1, 70, "VTOSLS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1244 = VTOSLS
- { 1245, 5, 1, 65, "VTOUHD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1245 = VTOUHD
- { 1246, 5, 1, 70, "VTOUHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1246 = VTOUHS
- { 1247, 4, 1, 65, "VTOUIRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1247 = VTOUIRD
- { 1248, 4, 1, 70, "VTOUIRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1248 = VTOUIRS
- { 1249, 4, 1, 65, "VTOUIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1249 = VTOUIZD
- { 1250, 4, 1, 70, "VTOUIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1250 = VTOUIZS
- { 1251, 5, 1, 65, "VTOULD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1251 = VTOULD
- { 1252, 5, 1, 70, "VTOULS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1252 = VTOULS
- { 1253, 6, 2, 35, "VTRNd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1253 = VTRNd16
- { 1254, 6, 2, 35, "VTRNd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1254 = VTRNd32
- { 1255, 6, 2, 35, "VTRNd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1255 = VTRNd8
- { 1256, 6, 2, 36, "VTRNq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1256 = VTRNq16
- { 1257, 6, 2, 36, "VTRNq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1257 = VTRNq32
- { 1258, 6, 2, 36, "VTRNq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1258 = VTRNq8
- { 1259, 5, 1, 4, "VTSTv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1259 = VTSTv16i8
- { 1260, 5, 1, 3, "VTSTv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1260 = VTSTv2i32
- { 1261, 5, 1, 3, "VTSTv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1261 = VTSTv4i16
- { 1262, 5, 1, 4, "VTSTv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1262 = VTSTv4i32
- { 1263, 5, 1, 4, "VTSTv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1263 = VTSTv8i16
- { 1264, 5, 1, 3, "VTSTv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1264 = VTSTv8i8
- { 1265, 5, 1, 67, "VUHTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1265 = VUHTOD
- { 1266, 5, 1, 68, "VUHTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1266 = VUHTOS
- { 1267, 4, 1, 67, "VUITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #1267 = VUITOD
- { 1268, 4, 1, 68, "VUITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1268 = VUITOS
- { 1269, 5, 1, 67, "VULTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1269 = VULTOD
- { 1270, 5, 1, 68, "VULTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1270 = VULTOS
- { 1271, 6, 2, 35, "VUZPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1271 = VUZPd16
- { 1272, 6, 2, 35, "VUZPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1272 = VUZPd32
- { 1273, 6, 2, 35, "VUZPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1273 = VUZPd8
- { 1274, 6, 2, 37, "VUZPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1274 = VUZPq16
- { 1275, 6, 2, 37, "VUZPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1275 = VUZPq32
- { 1276, 6, 2, 37, "VUZPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1276 = VUZPq8
- { 1277, 6, 2, 35, "VZIPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1277 = VZIPd16
- { 1278, 6, 2, 35, "VZIPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1278 = VZIPd32
- { 1279, 6, 2, 35, "VZIPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1279 = VZIPd8
- { 1280, 6, 2, 37, "VZIPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1280 = VZIPq16
- { 1281, 6, 2, 37, "VZIPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1281 = VZIPq32
- { 1282, 6, 2, 37, "VZIPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1282 = VZIPq8
- { 1283, 2, 0, 128, "WFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1283 = WFE
- { 1284, 2, 0, 128, "WFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1284 = WFI
- { 1285, 2, 0, 128, "YIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1285 = YIELD
- { 1286, 3, 1, 88, "t2ADCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1286 = t2ADCSri
- { 1287, 3, 1, 89, "t2ADCSrr", 0|(1<<TID::Commutable), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1287 = t2ADCSrr
- { 1288, 4, 1, 90, "t2ADCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo140 }, // Inst #1288 = t2ADCSrs
- { 1289, 6, 1, 88, "t2ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1289 = t2ADCri
- { 1290, 6, 1, 89, "t2ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1290 = t2ADCrr
- { 1291, 7, 1, 90, "t2ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo45 }, // Inst #1291 = t2ADCrs
- { 1292, 5, 1, 88, "t2ADDSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1292 = t2ADDSri
- { 1293, 5, 1, 89, "t2ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1293 = t2ADDSrr
- { 1294, 6, 1, 90, "t2ADDSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1294 = t2ADDSrs
- { 1295, 6, 1, 88, "t2ADDrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1295 = t2ADDrSPi
- { 1296, 5, 1, 88, "t2ADDrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1296 = t2ADDrSPi12
- { 1297, 7, 1, 90, "t2ADDrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1297 = t2ADDrSPs
- { 1298, 6, 1, 88, "t2ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1298 = t2ADDri
- { 1299, 6, 1, 88, "t2ADDri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1299 = t2ADDri12
- { 1300, 6, 1, 89, "t2ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1300 = t2ADDrr
- { 1301, 7, 1, 90, "t2ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1301 = t2ADDrs
- { 1302, 6, 1, 88, "t2ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1302 = t2ANDri
- { 1303, 6, 1, 89, "t2ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1303 = t2ANDrr
- { 1304, 7, 1, 90, "t2ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1304 = t2ANDrs
- { 1305, 6, 1, 113, "t2ASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1305 = t2ASRri
- { 1306, 6, 1, 114, "t2ASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1306 = t2ASRrr
- { 1307, 1, 0, 0, "t2B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1307 = t2B
- { 1308, 5, 1, 126, "t2BFC", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1308 = t2BFC
- { 1309, 6, 1, 88, "t2BFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #1309 = t2BFI
- { 1310, 6, 1, 88, "t2BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1310 = t2BICri
- { 1311, 6, 1, 89, "t2BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1311 = t2BICrr
- { 1312, 7, 1, 90, "t2BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1312 = t2BICrs
- { 1313, 4, 0, 0, "t2BR_JT", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #1313 = t2BR_JT
- { 1314, 3, 0, 0, "t2Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1314 = t2Bcc
- { 1315, 4, 1, 125, "t2CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1315 = t2CLZ
- { 1316, 4, 0, 97, "t2CMNzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1316 = t2CMNzri
- { 1317, 4, 0, 98, "t2CMNzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1317 = t2CMNzrr
- { 1318, 5, 0, 99, "t2CMNzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1318 = t2CMNzrs
- { 1319, 4, 0, 97, "t2CMPri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1319 = t2CMPri
- { 1320, 4, 0, 98, "t2CMPrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1320 = t2CMPrr
- { 1321, 5, 0, 99, "t2CMPrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1321 = t2CMPrs
- { 1322, 4, 0, 97, "t2CMPzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1322 = t2CMPzri
- { 1323, 4, 0, 98, "t2CMPzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1323 = t2CMPzrr
- { 1324, 5, 0, 99, "t2CMPzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1324 = t2CMPzrs
- { 1325, 6, 1, 88, "t2EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1325 = t2EORri
- { 1326, 6, 1, 89, "t2EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1326 = t2EORrr
- { 1327, 7, 1, 90, "t2EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1327 = t2EORrs
- { 1328, 2, 0, 92, "t2IT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo141 }, // Inst #1328 = t2IT
- { 1329, 0, 0, 128, "t2Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1329 = t2Int_MemBarrierV7
- { 1330, 0, 0, 128, "t2Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1330 = t2Int_SyncBarrierV7
- { 1331, 2, 0, 128, "t2Int_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList6, Barriers3, OperandInfo142 }, // Inst #1331 = t2Int_eh_sjlj_setjmp
- { 1332, 5, 0, 103, "t2LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1332 = t2LDM
- { 1333, 5, 0, 0, "t2LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1333 = t2LDM_RET
- { 1334, 6, 2, 102, "t2LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1334 = t2LDRB_POST
- { 1335, 6, 2, 102, "t2LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1335 = t2LDRB_PRE
- { 1336, 5, 1, 101, "t2LDRBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1336 = t2LDRBi12
- { 1337, 5, 1, 101, "t2LDRBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1337 = t2LDRBi8
- { 1338, 4, 1, 101, "t2LDRBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1338 = t2LDRBpci
- { 1339, 6, 1, 104, "t2LDRBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1339 = t2LDRBs
- { 1340, 6, 2, 101, "t2LDRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1340 = t2LDRDi8
- { 1341, 5, 2, 101, "t2LDRDpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1341 = t2LDRDpci
- { 1342, 4, 1, 128, "t2LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1342 = t2LDREX
- { 1343, 4, 1, 128, "t2LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1343 = t2LDREXB
- { 1344, 5, 2, 128, "t2LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1344 = t2LDREXD
- { 1345, 4, 1, 128, "t2LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1345 = t2LDREXH
- { 1346, 6, 2, 102, "t2LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1346 = t2LDRH_POST
- { 1347, 6, 2, 102, "t2LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1347 = t2LDRH_PRE
- { 1348, 5, 1, 101, "t2LDRHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1348 = t2LDRHi12
- { 1349, 5, 1, 101, "t2LDRHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1349 = t2LDRHi8
- { 1350, 4, 1, 101, "t2LDRHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1350 = t2LDRHpci
- { 1351, 6, 1, 104, "t2LDRHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1351 = t2LDRHs
- { 1352, 6, 2, 102, "t2LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1352 = t2LDRSB_POST
- { 1353, 6, 2, 102, "t2LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1353 = t2LDRSB_PRE
- { 1354, 5, 1, 101, "t2LDRSBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1354 = t2LDRSBi12
- { 1355, 5, 1, 101, "t2LDRSBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1355 = t2LDRSBi8
- { 1356, 4, 1, 101, "t2LDRSBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1356 = t2LDRSBpci
- { 1357, 6, 1, 104, "t2LDRSBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1357 = t2LDRSBs
- { 1358, 6, 2, 102, "t2LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1358 = t2LDRSH_POST
- { 1359, 6, 2, 102, "t2LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1359 = t2LDRSH_PRE
- { 1360, 5, 1, 101, "t2LDRSHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1360 = t2LDRSHi12
- { 1361, 5, 1, 101, "t2LDRSHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1361 = t2LDRSHi8
- { 1362, 4, 1, 101, "t2LDRSHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1362 = t2LDRSHpci
- { 1363, 6, 1, 104, "t2LDRSHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1363 = t2LDRSHs
- { 1364, 6, 2, 102, "t2LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1364 = t2LDR_POST
- { 1365, 6, 2, 102, "t2LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1365 = t2LDR_PRE
- { 1366, 5, 1, 101, "t2LDRi12", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1366 = t2LDRi12
- { 1367, 5, 1, 101, "t2LDRi8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1367 = t2LDRi8
- { 1368, 4, 1, 101, "t2LDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1368 = t2LDRpci
- { 1369, 3, 1, 128, "t2LDRpci_pic", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1369 = t2LDRpci_pic
- { 1370, 6, 1, 104, "t2LDRs", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1370 = t2LDRs
- { 1371, 4, 1, 88, "t2LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1371 = t2LEApcrel
- { 1372, 5, 1, 88, "t2LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #1372 = t2LEApcrelJT
- { 1373, 6, 1, 113, "t2LSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1373 = t2LSLri
- { 1374, 6, 1, 114, "t2LSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1374 = t2LSLrr
- { 1375, 6, 1, 113, "t2LSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1375 = t2LSRri
- { 1376, 6, 1, 114, "t2LSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1376 = t2LSRrr
- { 1377, 6, 1, 109, "t2MLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1377 = t2MLA
- { 1378, 6, 1, 109, "t2MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1378 = t2MLS
- { 1379, 6, 1, 95, "t2MOVCCasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo144 }, // Inst #1379 = t2MOVCCasr
- { 1380, 5, 1, 93, "t2MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1380 = t2MOVCCi
- { 1381, 6, 1, 95, "t2MOVCClsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo144 }, // Inst #1381 = t2MOVCClsl
- { 1382, 6, 1, 95, "t2MOVCClsr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo144 }, // Inst #1382 = t2MOVCClsr
- { 1383, 5, 1, 94, "t2MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #1383 = t2MOVCCr
- { 1384, 6, 1, 95, "t2MOVCCror", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo144 }, // Inst #1384 = t2MOVCCror
- { 1385, 5, 1, 111, "t2MOVTi16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1385 = t2MOVTi16
- { 1386, 5, 1, 111, "t2MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1386 = t2MOVi
- { 1387, 4, 1, 111, "t2MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1387 = t2MOVi16
- { 1388, 4, 1, 111, "t2MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(2<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1388 = t2MOVi32imm
- { 1389, 5, 1, 112, "t2MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 }, // Inst #1389 = t2MOVr
- { 1390, 5, 1, 113, "t2MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo44 }, // Inst #1390 = t2MOVrx
- { 1391, 2, 1, 113, "t2MOVsra_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #1391 = t2MOVsra_flag
- { 1392, 2, 1, 113, "t2MOVsrl_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #1392 = t2MOVsrl_flag
- { 1393, 5, 1, 116, "t2MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1393 = t2MUL
- { 1394, 5, 1, 111, "t2MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1394 = t2MVNi
- { 1395, 4, 1, 112, "t2MVNr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1395 = t2MVNr
- { 1396, 5, 1, 113, "t2MVNs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1396 = t2MVNs
- { 1397, 6, 1, 88, "t2ORNri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1397 = t2ORNri
- { 1398, 6, 1, 89, "t2ORNrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1398 = t2ORNrr
- { 1399, 7, 1, 90, "t2ORNrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1399 = t2ORNrs
- { 1400, 6, 1, 88, "t2ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1400 = t2ORRri
- { 1401, 6, 1, 89, "t2ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1401 = t2ORRrr
- { 1402, 7, 1, 90, "t2ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1402 = t2ORRrs
- { 1403, 6, 1, 90, "t2PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1403 = t2PKHBT
- { 1404, 6, 1, 90, "t2PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1404 = t2PKHTB
- { 1405, 4, 1, 125, "t2RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1405 = t2RBIT
- { 1406, 4, 1, 125, "t2REV", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1406 = t2REV
- { 1407, 4, 1, 125, "t2REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1407 = t2REV16
- { 1408, 4, 1, 125, "t2REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1408 = t2REVSH
- { 1409, 6, 1, 113, "t2RORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1409 = t2RORri
- { 1410, 6, 1, 114, "t2RORrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1410 = t2RORrr
- { 1411, 4, 1, 88, "t2RSBSri", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo145 }, // Inst #1411 = t2RSBSri
- { 1412, 5, 1, 90, "t2RSBSrs", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo146 }, // Inst #1412 = t2RSBSrs
- { 1413, 5, 1, 88, "t2RSBri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1413 = t2RSBri
- { 1414, 6, 1, 90, "t2RSBrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1414 = t2RSBrs
- { 1415, 3, 1, 88, "t2SBCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1415 = t2SBCSri
- { 1416, 3, 1, 89, "t2SBCSrr", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1416 = t2SBCSrr
- { 1417, 4, 1, 90, "t2SBCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo140 }, // Inst #1417 = t2SBCSrs
- { 1418, 6, 1, 88, "t2SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1418 = t2SBCri
- { 1419, 6, 1, 89, "t2SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1419 = t2SBCrr
- { 1420, 7, 1, 90, "t2SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo45 }, // Inst #1420 = t2SBCrs
- { 1421, 6, 1, 88, "t2SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #1421 = t2SBFX
- { 1422, 6, 1, 108, "t2SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1422 = t2SMLABB
- { 1423, 6, 1, 108, "t2SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1423 = t2SMLABT
- { 1424, 6, 2, 110, "t2SMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1424 = t2SMLAL
- { 1425, 6, 1, 108, "t2SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1425 = t2SMLATB
- { 1426, 6, 1, 108, "t2SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1426 = t2SMLATT
- { 1427, 6, 1, 108, "t2SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1427 = t2SMLAWB
- { 1428, 6, 1, 108, "t2SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1428 = t2SMLAWT
- { 1429, 6, 1, 109, "t2SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1429 = t2SMMLA
- { 1430, 6, 1, 109, "t2SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1430 = t2SMMLS
- { 1431, 5, 1, 116, "t2SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1431 = t2SMMUL
- { 1432, 5, 1, 116, "t2SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1432 = t2SMULBB
- { 1433, 5, 1, 116, "t2SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1433 = t2SMULBT
- { 1434, 6, 2, 117, "t2SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1434 = t2SMULL
- { 1435, 5, 1, 116, "t2SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1435 = t2SMULTB
- { 1436, 5, 1, 116, "t2SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1436 = t2SMULTT
- { 1437, 5, 1, 115, "t2SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1437 = t2SMULWB
- { 1438, 5, 1, 115, "t2SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1438 = t2SMULWT
- { 1439, 5, 0, 120, "t2STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1439 = t2STM
- { 1440, 6, 1, 119, "t2STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1440 = t2STRB_POST
- { 1441, 6, 1, 119, "t2STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1441 = t2STRB_PRE
- { 1442, 5, 0, 118, "t2STRBi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1442 = t2STRBi12
- { 1443, 5, 0, 118, "t2STRBi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1443 = t2STRBi8
- { 1444, 6, 0, 121, "t2STRBs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1444 = t2STRBs
- { 1445, 6, 0, 121, "t2STRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1445 = t2STRDi8
- { 1446, 5, 1, 128, "t2STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1446 = t2STREX
- { 1447, 5, 1, 128, "t2STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1447 = t2STREXB
- { 1448, 6, 1, 128, "t2STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #1448 = t2STREXD
- { 1449, 5, 1, 128, "t2STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1449 = t2STREXH
- { 1450, 6, 1, 119, "t2STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1450 = t2STRH_POST
- { 1451, 6, 1, 119, "t2STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1451 = t2STRH_PRE
- { 1452, 5, 0, 118, "t2STRHi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1452 = t2STRHi12
- { 1453, 5, 0, 118, "t2STRHi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1453 = t2STRHi8
- { 1454, 6, 0, 121, "t2STRHs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1454 = t2STRHs
- { 1455, 6, 1, 119, "t2STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1455 = t2STR_POST
- { 1456, 6, 1, 119, "t2STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1456 = t2STR_PRE
- { 1457, 5, 0, 118, "t2STRi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1457 = t2STRi12
- { 1458, 5, 0, 118, "t2STRi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1458 = t2STRi8
- { 1459, 6, 0, 121, "t2STRs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1459 = t2STRs
- { 1460, 5, 1, 88, "t2SUBSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1460 = t2SUBSri
- { 1461, 5, 1, 89, "t2SUBSrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1461 = t2SUBSrr
- { 1462, 6, 1, 90, "t2SUBSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1462 = t2SUBSrs
- { 1463, 6, 1, 88, "t2SUBrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1463 = t2SUBrSPi
- { 1464, 5, 1, 88, "t2SUBrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1464 = t2SUBrSPi12
- { 1465, 3, 1, 128, "t2SUBrSPi12_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1465 = t2SUBrSPi12_
- { 1466, 3, 1, 128, "t2SUBrSPi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1466 = t2SUBrSPi_
- { 1467, 7, 1, 90, "t2SUBrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1467 = t2SUBrSPs
- { 1468, 4, 1, 128, "t2SUBrSPs_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo140 }, // Inst #1468 = t2SUBrSPs_
- { 1469, 6, 1, 88, "t2SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1469 = t2SUBri
- { 1470, 6, 1, 88, "t2SUBri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1470 = t2SUBri12
- { 1471, 6, 1, 89, "t2SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1471 = t2SUBrr
- { 1472, 7, 1, 90, "t2SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1472 = t2SUBrs
- { 1473, 5, 1, 89, "t2SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1473 = t2SXTABrr
- { 1474, 6, 1, 91, "t2SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1474 = t2SXTABrr_rot
- { 1475, 5, 1, 89, "t2SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1475 = t2SXTAHrr
- { 1476, 6, 1, 91, "t2SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1476 = t2SXTAHrr_rot
- { 1477, 4, 1, 125, "t2SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1477 = t2SXTBr
- { 1478, 5, 1, 126, "t2SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1478 = t2SXTBr_rot
- { 1479, 4, 1, 125, "t2SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1479 = t2SXTHr
- { 1480, 5, 1, 126, "t2SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1480 = t2SXTHr_rot
- { 1481, 3, 0, 0, "t2TBB", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1481 = t2TBB
- { 1482, 3, 0, 0, "t2TBH", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1482 = t2TBH
- { 1483, 4, 0, 97, "t2TEQri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1483 = t2TEQri
- { 1484, 4, 0, 98, "t2TEQrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1484 = t2TEQrr
- { 1485, 5, 0, 99, "t2TEQrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1485 = t2TEQrs
- { 1486, 0, 0, 0, "t2TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #1486 = t2TPsoft
- { 1487, 4, 0, 97, "t2TSTri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1487 = t2TSTri
- { 1488, 4, 0, 98, "t2TSTrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1488 = t2TSTrr
- { 1489, 5, 0, 99, "t2TSTrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1489 = t2TSTrs
- { 1490, 6, 1, 88, "t2UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #1490 = t2UBFX
- { 1491, 6, 2, 110, "t2UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1491 = t2UMAAL
- { 1492, 6, 2, 110, "t2UMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1492 = t2UMLAL
- { 1493, 6, 2, 117, "t2UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1493 = t2UMULL
- { 1494, 5, 1, 89, "t2UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1494 = t2UXTABrr
- { 1495, 6, 1, 91, "t2UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1495 = t2UXTABrr_rot
- { 1496, 5, 1, 89, "t2UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1496 = t2UXTAHrr
- { 1497, 6, 1, 91, "t2UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1497 = t2UXTAHrr_rot
- { 1498, 4, 1, 125, "t2UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1498 = t2UXTB16r
- { 1499, 5, 1, 126, "t2UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1499 = t2UXTB16r_rot
- { 1500, 4, 1, 125, "t2UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1500 = t2UXTBr
- { 1501, 5, 1, 126, "t2UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1501 = t2UXTBr_rot
- { 1502, 4, 1, 125, "t2UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1502 = t2UXTHr
- { 1503, 5, 1, 126, "t2UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1503 = t2UXTHr_rot
- { 1504, 6, 2, 89, "tADC", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo148 }, // Inst #1504 = tADC
- { 1505, 5, 1, 89, "tADDhirr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #1505 = tADDhirr
- { 1506, 6, 2, 88, "tADDi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1506 = tADDi3
- { 1507, 6, 2, 88, "tADDi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1507 = tADDi8
- { 1508, 2, 1, 88, "tADDrPCi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1508 = tADDrPCi
- { 1509, 3, 1, 89, "tADDrSP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo152 }, // Inst #1509 = tADDrSP
- { 1510, 3, 1, 88, "tADDrSPi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo153 }, // Inst #1510 = tADDrSPi
- { 1511, 6, 2, 89, "tADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1511 = tADDrr
- { 1512, 3, 1, 88, "tADDspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1512 = tADDspi
- { 1513, 3, 1, 89, "tADDspr", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo152 }, // Inst #1513 = tADDspr
- { 1514, 3, 1, 128, "tADDspr_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo3 }, // Inst #1514 = tADDspr_
- { 1515, 1, 0, 128, "tADJCALLSTACKDOWN", 0, 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo14 }, // Inst #1515 = tADJCALLSTACKDOWN
- { 1516, 2, 0, 128, "tADJCALLSTACKUP", 0, 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo141 }, // Inst #1516 = tADJCALLSTACKUP
- { 1517, 6, 2, 89, "tAND", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1517 = tAND
- { 1518, 3, 1, 128, "tANDsp", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, ImplicitList1, Barriers1, OperandInfo156 }, // Inst #1518 = tANDsp
- { 1519, 6, 2, 113, "tASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1519 = tASRri
- { 1520, 6, 2, 114, "tASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1520 = tASRrr
- { 1521, 1, 0, 0, "tB", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1521 = tB
- { 1522, 6, 2, 89, "tBIC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1522 = tBIC
- { 1523, 1, 0, 128, "tBKPT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1523 = tBKPT
- { 1524, 1, 0, 0, "tBL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1524 = tBL
- { 1525, 1, 0, 0, "tBLXi", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1525 = tBLXi
- { 1526, 1, 0, 0, "tBLXi_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1526 = tBLXi_r9
- { 1527, 1, 0, 0, "tBLXr", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #1527 = tBLXr
- { 1528, 1, 0, 0, "tBLXr_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #1528 = tBLXr_r9
- { 1529, 1, 0, 0, "tBLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1529 = tBLr9
- { 1530, 1, 0, 0, "tBRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #1530 = tBRIND
- { 1531, 3, 0, 0, "tBR_JTr", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1531 = tBR_JTr
- { 1532, 1, 0, 0, "tBX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo158 }, // Inst #1532 = tBX
- { 1533, 0, 0, 0, "tBX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1533 = tBX_RET
- { 1534, 1, 0, 0, "tBX_RET_vararg", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 }, // Inst #1534 = tBX_RET_vararg
- { 1535, 1, 0, 0, "tBXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo158 }, // Inst #1535 = tBXr9
- { 1536, 3, 0, 0, "tBcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1536 = tBcc
- { 1537, 1, 0, 0, "tBfar", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, ImplicitList8, NULL, OperandInfo14 }, // Inst #1537 = tBfar
- { 1538, 2, 0, 0, "tCBNZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1538 = tCBNZ
- { 1539, 2, 0, 0, "tCBZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1539 = tCBZ
- { 1540, 4, 0, 98, "tCMNz", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo159 }, // Inst #1540 = tCMNz
- { 1541, 4, 0, 98, "tCMPhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1541 = tCMPhir
- { 1542, 4, 0, 97, "tCMPi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo160 }, // Inst #1542 = tCMPi8
- { 1543, 4, 0, 98, "tCMPr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo159 }, // Inst #1543 = tCMPr
- { 1544, 4, 0, 98, "tCMPzhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1544 = tCMPzhir
- { 1545, 4, 0, 97, "tCMPzi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo160 }, // Inst #1545 = tCMPzi8
- { 1546, 4, 0, 98, "tCMPzr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo159 }, // Inst #1546 = tCMPzr
- { 1547, 6, 2, 89, "tEOR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1547 = tEOR
- { 1548, 2, 0, 128, "tInt_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList9, Barriers4, OperandInfo161 }, // Inst #1548 = tInt_eh_sjlj_setjmp
- { 1549, 5, 0, 103, "tLDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1549 = tLDM
- { 1550, 6, 1, 104, "tLDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1550 = tLDR
- { 1551, 6, 1, 104, "tLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1551 = tLDRB
- { 1552, 6, 1, 104, "tLDRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1552 = tLDRBi
- { 1553, 6, 1, 104, "tLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1553 = tLDRH
- { 1554, 6, 1, 104, "tLDRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1554 = tLDRHi
- { 1555, 5, 1, 104, "tLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1555 = tLDRSB
- { 1556, 5, 1, 104, "tLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1556 = tLDRSH
- { 1557, 4, 1, 101, "tLDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 }, // Inst #1557 = tLDRcp
- { 1558, 6, 1, 104, "tLDRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1558 = tLDRi
- { 1559, 4, 1, 101, "tLDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 }, // Inst #1559 = tLDRpci
- { 1560, 3, 1, 128, "tLDRpci_pic", 0|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1560 = tLDRpci_pic
- { 1561, 5, 1, 101, "tLDRspi", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo164 }, // Inst #1561 = tLDRspi
- { 1562, 4, 1, 88, "tLEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 }, // Inst #1562 = tLEApcrel
- { 1563, 5, 1, 88, "tLEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo165 }, // Inst #1563 = tLEApcrelJT
- { 1564, 6, 2, 113, "tLSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1564 = tLSLri
- { 1565, 6, 2, 114, "tLSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1565 = tLSLrr
- { 1566, 6, 2, 113, "tLSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1566 = tLSRri
- { 1567, 6, 2, 114, "tLSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1567 = tLSRrr
- { 1568, 5, 1, 93, "tMOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1568 = tMOVCCi
- { 1569, 5, 1, 94, "tMOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #1569 = tMOVCCr
- { 1570, 5, 1, 128, "tMOVCCr_pseudo", 0|(1<<TID::Predicable)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo163 }, // Inst #1570 = tMOVCCr_pseudo
- { 1571, 2, 1, 112, "tMOVSr", 0, 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo161 }, // Inst #1571 = tMOVSr
- { 1572, 2, 1, 112, "tMOVgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #1572 = tMOVgpr2gpr
- { 1573, 2, 1, 112, "tMOVgpr2tgpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 }, // Inst #1573 = tMOVgpr2tgpr
- { 1574, 5, 2, 111, "tMOVi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo168 }, // Inst #1574 = tMOVi8
- { 1575, 2, 1, 112, "tMOVr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo161 }, // Inst #1575 = tMOVr
- { 1576, 2, 1, 112, "tMOVtgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo142 }, // Inst #1576 = tMOVtgpr2gpr
- { 1577, 6, 2, 116, "tMUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1577 = tMUL
- { 1578, 5, 2, 112, "tMVN", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1578 = tMVN
- { 1579, 6, 2, 89, "tORR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1579 = tORR
- { 1580, 3, 1, 89, "tPICADD", 0|(1<<TID::NotDuplicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1580 = tPICADD
- { 1581, 3, 0, 0, "tPOP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo170 }, // Inst #1581 = tPOP
- { 1582, 3, 0, 0, "tPOP_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo170 }, // Inst #1582 = tPOP_RET
- { 1583, 3, 0, 0, "tPUSH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo170 }, // Inst #1583 = tPUSH
- { 1584, 4, 1, 125, "tREV", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1584 = tREV
- { 1585, 4, 1, 125, "tREV16", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1585 = tREV16
- { 1586, 4, 1, 125, "tREVSH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1586 = tREVSH
- { 1587, 6, 2, 114, "tROR", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1587 = tROR
- { 1588, 5, 2, 88, "tRSB", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1588 = tRSB
- { 1589, 5, 1, 101, "tRestore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo164 }, // Inst #1589 = tRestore
- { 1590, 6, 2, 89, "tSBC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo148 }, // Inst #1590 = tSBC
- { 1591, 5, 0, 120, "tSTM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1591 = tSTM
- { 1592, 6, 0, 121, "tSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1592 = tSTR
- { 1593, 6, 0, 121, "tSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1593 = tSTRB
- { 1594, 6, 0, 121, "tSTRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1594 = tSTRBi
- { 1595, 6, 0, 121, "tSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1595 = tSTRH
- { 1596, 6, 0, 121, "tSTRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1596 = tSTRHi
- { 1597, 6, 0, 121, "tSTRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1597 = tSTRi
- { 1598, 5, 0, 118, "tSTRspi", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo164 }, // Inst #1598 = tSTRspi
- { 1599, 6, 2, 88, "tSUBi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1599 = tSUBi3
- { 1600, 6, 2, 88, "tSUBi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1600 = tSUBi8
- { 1601, 6, 2, 89, "tSUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1601 = tSUBrr
- { 1602, 3, 1, 88, "tSUBspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1602 = tSUBspi
- { 1603, 3, 1, 128, "tSUBspi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1603 = tSUBspi_
- { 1604, 4, 1, 125, "tSXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1604 = tSXTB
- { 1605, 4, 1, 125, "tSXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1605 = tSXTH
- { 1606, 5, 0, 118, "tSpill", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo164 }, // Inst #1606 = tSpill
- { 1607, 0, 0, 0, "tTPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList10, NULL, 0 }, // Inst #1607 = tTPsoft
- { 1608, 4, 0, 98, "tTST", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo159 }, // Inst #1608 = tTST
- { 1609, 4, 1, 125, "tUXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1609 = tUXTB
- { 1610, 4, 1, 125, "tUXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1610 = tUXTH
+ { 55, 5, 1, 126, "BFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #55 = BFI
+ { 56, 6, 1, 88, "BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #56 = BICri
+ { 57, 6, 1, 89, "BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #57 = BICrr
+ { 58, 8, 1, 91, "BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #58 = BICrs
+ { 59, 3, 0, 128, "BKPT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #59 = BKPT
+ { 60, 1, 0, 0, "BL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #60 = BL
+ { 61, 1, 0, 0, "BLX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #61 = BLX
+ { 62, 1, 0, 0, "BLXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #62 = BLXr9
+ { 63, 3, 0, 0, "BL_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo11 }, // Inst #63 = BL_pred
+ { 64, 1, 0, 0, "BLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #64 = BLr9
+ { 65, 3, 0, 0, "BLr9_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo11 }, // Inst #65 = BLr9_pred
+ { 66, 1, 0, 0, "BRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #66 = BRIND
+ { 67, 4, 0, 0, "BR_JTadd", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #67 = BR_JTadd
+ { 68, 5, 0, 0, "BR_JTm", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo18 }, // Inst #68 = BR_JTm
+ { 69, 3, 0, 0, "BR_JTr", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #69 = BR_JTr
+ { 70, 1, 0, 0, "BX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo20 }, // Inst #70 = BX
+ { 71, 3, 0, 128, "BXJ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #71 = BXJ
+ { 72, 2, 0, 0, "BX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #72 = BX_RET
+ { 73, 1, 0, 0, "BXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo20 }, // Inst #73 = BXr9
+ { 74, 3, 0, 0, "Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #74 = Bcc
+ { 75, 8, 0, 128, "CDP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #75 = CDP
+ { 76, 6, 0, 128, "CDP2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #76 = CDP2
+ { 77, 0, 0, 128, "CLREX", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #77 = CLREX
+ { 78, 4, 1, 125, "CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #78 = CLZ
+ { 79, 4, 0, 97, "CMNzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #79 = CMNzri
+ { 80, 4, 0, 98, "CMNzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #80 = CMNzrr
+ { 81, 6, 0, 100, "CMNzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #81 = CMNzrs
+ { 82, 4, 0, 97, "CMPri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #82 = CMPri
+ { 83, 4, 0, 98, "CMPrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #83 = CMPrr
+ { 84, 6, 0, 100, "CMPrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #84 = CMPrs
+ { 85, 4, 0, 97, "CMPzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #85 = CMPzri
+ { 86, 4, 0, 98, "CMPzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #86 = CMPzrr
+ { 87, 6, 0, 100, "CMPzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #87 = CMPzrs
+ { 88, 3, 0, 128, "CONSTPOOL_ENTRY", 0|(1<<TID::NotDuplicable), 0|(1<<4), NULL, NULL, NULL, OperandInfo28 }, // Inst #88 = CONSTPOOL_ENTRY
+ { 89, 1, 0, 128, "CPS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #89 = CPS
+ { 90, 3, 0, 128, "DBG", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #90 = DBG
+ { 91, 0, 0, 128, "DMBish", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #91 = DMBish
+ { 92, 0, 0, 128, "DMBishst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #92 = DMBishst
+ { 93, 0, 0, 128, "DMBnsh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #93 = DMBnsh
+ { 94, 0, 0, 128, "DMBnshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #94 = DMBnshst
+ { 95, 0, 0, 128, "DMBosh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #95 = DMBosh
+ { 96, 0, 0, 128, "DMBoshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #96 = DMBoshst
+ { 97, 0, 0, 128, "DMBst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #97 = DMBst
+ { 98, 0, 0, 128, "DSBish", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #98 = DSBish
+ { 99, 0, 0, 128, "DSBishst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #99 = DSBishst
+ { 100, 0, 0, 128, "DSBnsh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #100 = DSBnsh
+ { 101, 0, 0, 128, "DSBnshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #101 = DSBnshst
+ { 102, 0, 0, 128, "DSBosh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #102 = DSBosh
+ { 103, 0, 0, 128, "DSBoshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #103 = DSBoshst
+ { 104, 0, 0, 128, "DSBst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #104 = DSBst
+ { 105, 6, 1, 88, "EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #105 = EORri
+ { 106, 6, 1, 89, "EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #106 = EORrr
+ { 107, 8, 1, 91, "EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #107 = EORrs
+ { 108, 4, 1, 26, "FCONSTD", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #108 = FCONSTD
+ { 109, 4, 1, 26, "FCONSTS", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo30 }, // Inst #109 = FCONSTS
+ { 110, 2, 0, 82, "FMSTAT", 0|(1<<TID::Predicable), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #110 = FMSTAT
+ { 111, 0, 0, 128, "ISBsy", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #111 = ISBsy
+ { 112, 1, 0, 128, "Int_MemBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #112 = Int_MemBarrierV6
+ { 113, 0, 0, 128, "Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #113 = Int_MemBarrierV7
+ { 114, 1, 0, 128, "Int_SyncBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #114 = Int_SyncBarrierV6
+ { 115, 0, 0, 128, "Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #115 = Int_SyncBarrierV7
+ { 116, 2, 0, 128, "Int_eh_sjlj_setjmp", 0, 0|(1<<4), NULL, ImplicitList6, Barriers3, OperandInfo32 }, // Inst #116 = Int_eh_sjlj_setjmp
+ { 117, 7, 0, 128, "LDC2L_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #117 = LDC2L_OFFSET
+ { 118, 6, 0, 128, "LDC2L_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #118 = LDC2L_OPTION
+ { 119, 7, 0, 128, "LDC2L_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #119 = LDC2L_POST
+ { 120, 7, 0, 128, "LDC2L_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #120 = LDC2L_PRE
+ { 121, 7, 0, 128, "LDC2_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #121 = LDC2_OFFSET
+ { 122, 6, 0, 128, "LDC2_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #122 = LDC2_OPTION
+ { 123, 7, 0, 128, "LDC2_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #123 = LDC2_POST
+ { 124, 7, 0, 128, "LDC2_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #124 = LDC2_PRE
+ { 125, 7, 0, 128, "LDCL_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #125 = LDCL_OFFSET
+ { 126, 6, 0, 128, "LDCL_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #126 = LDCL_OPTION
+ { 127, 7, 0, 128, "LDCL_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #127 = LDCL_POST
+ { 128, 7, 0, 128, "LDCL_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #128 = LDCL_PRE
+ { 129, 7, 0, 128, "LDC_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #129 = LDC_OFFSET
+ { 130, 6, 0, 128, "LDC_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #130 = LDC_OPTION
+ { 131, 7, 0, 128, "LDC_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #131 = LDC_POST
+ { 132, 7, 0, 128, "LDC_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #132 = LDC_PRE
+ { 133, 5, 0, 103, "LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #133 = LDM
+ { 134, 5, 0, 0, "LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #134 = LDM_RET
+ { 135, 6, 1, 104, "LDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #135 = LDR
+ { 136, 6, 1, 104, "LDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #136 = LDRB
+ { 137, 7, 2, 105, "LDRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #137 = LDRBT
+ { 138, 7, 2, 105, "LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #138 = LDRB_POST
+ { 139, 7, 2, 105, "LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #139 = LDRB_PRE
+ { 140, 7, 2, 104, "LDRD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #140 = LDRD
+ { 141, 8, 3, 104, "LDRD_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #141 = LDRD_POST
+ { 142, 8, 3, 104, "LDRD_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #142 = LDRD_PRE
+ { 143, 4, 1, 128, "LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #143 = LDREX
+ { 144, 4, 1, 128, "LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #144 = LDREXB
+ { 145, 5, 2, 128, "LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #145 = LDREXD
+ { 146, 4, 1, 128, "LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #146 = LDREXH
+ { 147, 6, 1, 104, "LDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #147 = LDRH
+ { 148, 7, 2, 105, "LDRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #148 = LDRHT
+ { 149, 7, 2, 105, "LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #149 = LDRH_POST
+ { 150, 7, 2, 105, "LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #150 = LDRH_PRE
+ { 151, 6, 1, 104, "LDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #151 = LDRSB
+ { 152, 7, 2, 105, "LDRSBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #152 = LDRSBT
+ { 153, 7, 2, 105, "LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #153 = LDRSB_POST
+ { 154, 7, 2, 105, "LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #154 = LDRSB_PRE
+ { 155, 6, 1, 104, "LDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #155 = LDRSH
+ { 156, 7, 2, 105, "LDRSHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #156 = LDRSHT
+ { 157, 7, 2, 105, "LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #157 = LDRSH_POST
+ { 158, 7, 2, 105, "LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #158 = LDRSH_PRE
+ { 159, 7, 2, 105, "LDRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #159 = LDRT
+ { 160, 7, 2, 105, "LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #160 = LDR_POST
+ { 161, 7, 2, 105, "LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #161 = LDR_PRE
+ { 162, 6, 1, 104, "LDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #162 = LDRcp
+ { 163, 4, 1, 88, "LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo26 }, // Inst #163 = LEApcrel
+ { 164, 5, 1, 88, "LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo38 }, // Inst #164 = LEApcrelJT
+ { 165, 8, 0, 128, "MCR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #165 = MCR
+ { 166, 6, 0, 128, "MCR2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #166 = MCR2
+ { 167, 7, 0, 128, "MCRR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #167 = MCRR
+ { 168, 5, 0, 128, "MCRR2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #168 = MCRR2
+ { 169, 7, 1, 109, "MLA", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #169 = MLA
+ { 170, 6, 1, 109, "MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #170 = MLS
+ { 171, 5, 1, 93, "MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #171 = MOVCCi
+ { 172, 5, 1, 94, "MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo44 }, // Inst #172 = MOVCCr
+ { 173, 7, 1, 96, "MOVCCs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo45 }, // Inst #173 = MOVCCs
+ { 174, 5, 1, 111, "MOVTi16", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #174 = MOVTi16
+ { 175, 5, 1, 111, "MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo46 }, // Inst #175 = MOVi
+ { 176, 4, 1, 111, "MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo26 }, // Inst #176 = MOVi16
+ { 177, 4, 1, 111, "MOVi2pieces", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo26 }, // Inst #177 = MOVi2pieces
+ { 178, 4, 1, 111, "MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo26 }, // Inst #178 = MOVi32imm
+ { 179, 5, 1, 112, "MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo47 }, // Inst #179 = MOVr
+ { 180, 5, 1, 113, "MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(1<<15), ImplicitList1, NULL, NULL, OperandInfo47 }, // Inst #180 = MOVrx
+ { 181, 7, 1, 114, "MOVs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo48 }, // Inst #181 = MOVs
+ { 182, 4, 1, 113, "MOVsra_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #182 = MOVsra_flag
+ { 183, 4, 1, 113, "MOVsrl_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #183 = MOVsrl_flag
+ { 184, 8, 0, 128, "MRC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #184 = MRC
+ { 185, 6, 0, 128, "MRC2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #185 = MRC2
+ { 186, 7, 0, 128, "MRRC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #186 = MRRC
+ { 187, 5, 0, 128, "MRRC2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #187 = MRRC2
+ { 188, 3, 1, 128, "MRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #188 = MRS
+ { 189, 3, 1, 128, "MRSsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #189 = MRSsys
+ { 190, 3, 0, 128, "MSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #190 = MSR
+ { 191, 3, 0, 128, "MSRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #191 = MSRi
+ { 192, 3, 0, 128, "MSRsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #192 = MSRsys
+ { 193, 3, 0, 128, "MSRsysi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #193 = MSRsysi
+ { 194, 6, 1, 116, "MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #194 = MUL
+ { 195, 5, 1, 111, "MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo46 }, // Inst #195 = MVNi
+ { 196, 5, 1, 112, "MVNr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo47 }, // Inst #196 = MVNr
+ { 197, 7, 1, 114, "MVNs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo48 }, // Inst #197 = MVNs
+ { 198, 2, 0, 128, "NOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #198 = NOP
+ { 199, 6, 1, 88, "ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #199 = ORRri
+ { 200, 6, 1, 89, "ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #200 = ORRrr
+ { 201, 8, 1, 91, "ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #201 = ORRrs
+ { 202, 5, 1, 89, "PICADD", 0|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #202 = PICADD
+ { 203, 5, 1, 104, "PICLDR", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #203 = PICLDR
+ { 204, 5, 1, 104, "PICLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #204 = PICLDRB
+ { 205, 5, 1, 104, "PICLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #205 = PICLDRH
+ { 206, 5, 1, 104, "PICLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #206 = PICLDRSB
+ { 207, 5, 1, 104, "PICLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #207 = PICLDRSH
+ { 208, 5, 0, 121, "PICSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #208 = PICSTR
+ { 209, 5, 0, 121, "PICSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #209 = PICSTRB
+ { 210, 5, 0, 121, "PICSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #210 = PICSTRH
+ { 211, 6, 1, 90, "PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #211 = PKHBT
+ { 212, 6, 1, 90, "PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #212 = PKHTB
+ { 213, 2, 0, 128, "PLDWi", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #213 = PLDWi
+ { 214, 3, 0, 128, "PLDWr", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo2 }, // Inst #214 = PLDWr
+ { 215, 2, 0, 128, "PLDi", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #215 = PLDi
+ { 216, 3, 0, 128, "PLDr", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo2 }, // Inst #216 = PLDr
+ { 217, 2, 0, 128, "PLIi", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #217 = PLIi
+ { 218, 3, 0, 128, "PLIr", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo2 }, // Inst #218 = PLIr
+ { 219, 5, 1, 89, "QADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #219 = QADD
+ { 220, 5, 1, 89, "QADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #220 = QADD16
+ { 221, 5, 1, 89, "QADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #221 = QADD8
+ { 222, 5, 1, 89, "QASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #222 = QASX
+ { 223, 5, 1, 89, "QDADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #223 = QDADD
+ { 224, 5, 1, 89, "QDSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #224 = QDSUB
+ { 225, 5, 1, 89, "QSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #225 = QSAX
+ { 226, 5, 1, 89, "QSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #226 = QSUB
+ { 227, 5, 1, 89, "QSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #227 = QSUB16
+ { 228, 5, 1, 89, "QSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #228 = QSUB8
+ { 229, 4, 1, 125, "RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #229 = RBIT
+ { 230, 4, 1, 125, "REV", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #230 = REV
+ { 231, 4, 1, 125, "REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #231 = REV16
+ { 232, 4, 1, 125, "REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #232 = REVSH
+ { 233, 3, 0, 128, "RFE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo50 }, // Inst #233 = RFE
+ { 234, 3, 0, 128, "RFEW", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo50 }, // Inst #234 = RFEW
+ { 235, 5, 1, 88, "RSBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #235 = RSBSri
+ { 236, 7, 1, 91, "RSBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #236 = RSBSrs
+ { 237, 6, 1, 88, "RSBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #237 = RSBri
+ { 238, 8, 1, 91, "RSBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #238 = RSBrs
+ { 239, 3, 1, 88, "RSCSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #239 = RSCSri
+ { 240, 5, 1, 91, "RSCSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #240 = RSCSrs
+ { 241, 6, 1, 88, "RSCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #241 = RSCri
+ { 242, 8, 1, 91, "RSCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #242 = RSCrs
+ { 243, 5, 1, 89, "SADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #243 = SADD16
+ { 244, 5, 1, 89, "SADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #244 = SADD8
+ { 245, 5, 1, 89, "SASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #245 = SASX
+ { 246, 3, 1, 88, "SBCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #246 = SBCSSri
+ { 247, 3, 1, 89, "SBCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #247 = SBCSSrr
+ { 248, 5, 1, 91, "SBCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #248 = SBCSSrs
+ { 249, 6, 1, 88, "SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #249 = SBCri
+ { 250, 6, 1, 89, "SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #250 = SBCrr
+ { 251, 8, 1, 91, "SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #251 = SBCrs
+ { 252, 6, 1, 88, "SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #252 = SBFX
+ { 253, 5, 1, 128, "SEL", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #253 = SEL
+ { 254, 0, 0, 128, "SETENDBE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #254 = SETENDBE
+ { 255, 0, 0, 128, "SETENDLE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #255 = SETENDLE
+ { 256, 2, 0, 128, "SEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #256 = SEV
+ { 257, 5, 1, 89, "SHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #257 = SHADD16
+ { 258, 5, 1, 89, "SHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #258 = SHADD8
+ { 259, 5, 1, 89, "SHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #259 = SHASX
+ { 260, 5, 1, 89, "SHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #260 = SHSAX
+ { 261, 5, 1, 89, "SHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #261 = SHSUB16
+ { 262, 5, 1, 89, "SHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #262 = SHSUB8
+ { 263, 3, 0, 128, "SMC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #263 = SMC
+ { 264, 6, 1, 108, "SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #264 = SMLABB
+ { 265, 6, 1, 108, "SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #265 = SMLABT
+ { 266, 6, 1, 128, "SMLAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #266 = SMLAD
+ { 267, 6, 1, 128, "SMLADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #267 = SMLADX
+ { 268, 7, 2, 110, "SMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #268 = SMLAL
+ { 269, 6, 2, 110, "SMLALBB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #269 = SMLALBB
+ { 270, 6, 2, 110, "SMLALBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #270 = SMLALBT
+ { 271, 6, 2, 128, "SMLALD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #271 = SMLALD
+ { 272, 6, 2, 128, "SMLALDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #272 = SMLALDX
+ { 273, 6, 2, 110, "SMLALTB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #273 = SMLALTB
+ { 274, 6, 2, 110, "SMLALTT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #274 = SMLALTT
+ { 275, 6, 1, 108, "SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #275 = SMLATB
+ { 276, 6, 1, 108, "SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #276 = SMLATT
+ { 277, 6, 1, 108, "SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #277 = SMLAWB
+ { 278, 6, 1, 108, "SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #278 = SMLAWT
+ { 279, 6, 1, 128, "SMLSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #279 = SMLSD
+ { 280, 6, 1, 128, "SMLSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #280 = SMLSDX
+ { 281, 6, 2, 128, "SMLSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #281 = SMLSLD
+ { 282, 6, 2, 128, "SMLSLDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #282 = SMLSLDX
+ { 283, 6, 1, 109, "SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #283 = SMMLA
+ { 284, 6, 1, 109, "SMMLAR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #284 = SMMLAR
+ { 285, 6, 1, 109, "SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #285 = SMMLS
+ { 286, 6, 1, 109, "SMMLSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #286 = SMMLSR
+ { 287, 5, 1, 116, "SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #287 = SMMUL
+ { 288, 5, 1, 116, "SMMULR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #288 = SMMULR
+ { 289, 5, 1, 128, "SMUAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #289 = SMUAD
+ { 290, 5, 1, 128, "SMUADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #290 = SMUADX
+ { 291, 5, 1, 116, "SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #291 = SMULBB
+ { 292, 5, 1, 116, "SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #292 = SMULBT
+ { 293, 7, 2, 117, "SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #293 = SMULL
+ { 294, 5, 1, 116, "SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #294 = SMULTB
+ { 295, 5, 1, 116, "SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #295 = SMULTT
+ { 296, 5, 1, 115, "SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #296 = SMULWB
+ { 297, 5, 1, 115, "SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #297 = SMULWT
+ { 298, 5, 1, 128, "SMUSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #298 = SMUSD
+ { 299, 5, 1, 128, "SMUSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #299 = SMUSDX
+ { 300, 3, 0, 128, "SRS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #300 = SRS
+ { 301, 3, 0, 128, "SRSW", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #301 = SRSW
+ { 302, 5, 1, 128, "SSAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo52 }, // Inst #302 = SSAT16
+ { 303, 6, 1, 128, "SSATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #303 = SSATasr
+ { 304, 6, 1, 128, "SSATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #304 = SSATlsl
+ { 305, 5, 1, 89, "SSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #305 = SSAX
+ { 306, 5, 1, 89, "SSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #306 = SSUB16
+ { 307, 5, 1, 89, "SSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #307 = SSUB8
+ { 308, 7, 0, 128, "STC2L_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #308 = STC2L_OFFSET
+ { 309, 6, 0, 128, "STC2L_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #309 = STC2L_OPTION
+ { 310, 7, 0, 128, "STC2L_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #310 = STC2L_POST
+ { 311, 7, 0, 128, "STC2L_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #311 = STC2L_PRE
+ { 312, 7, 0, 128, "STC2_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #312 = STC2_OFFSET
+ { 313, 6, 0, 128, "STC2_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #313 = STC2_OPTION
+ { 314, 7, 0, 128, "STC2_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #314 = STC2_POST
+ { 315, 7, 0, 128, "STC2_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #315 = STC2_PRE
+ { 316, 7, 0, 128, "STCL_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #316 = STCL_OFFSET
+ { 317, 6, 0, 128, "STCL_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #317 = STCL_OPTION
+ { 318, 7, 0, 128, "STCL_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #318 = STCL_POST
+ { 319, 7, 0, 128, "STCL_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #319 = STCL_PRE
+ { 320, 7, 0, 128, "STC_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #320 = STC_OFFSET
+ { 321, 6, 0, 128, "STC_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #321 = STC_OPTION
+ { 322, 7, 0, 128, "STC_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #322 = STC_POST
+ { 323, 7, 0, 128, "STC_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #323 = STC_PRE
+ { 324, 5, 0, 120, "STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #324 = STM
+ { 325, 6, 0, 121, "STR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #325 = STR
+ { 326, 6, 0, 121, "STRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #326 = STRB
+ { 327, 7, 1, 122, "STRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #327 = STRBT
+ { 328, 7, 1, 122, "STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #328 = STRB_POST
+ { 329, 7, 1, 122, "STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #329 = STRB_PRE
+ { 330, 7, 0, 121, "STRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #330 = STRD
+ { 331, 8, 1, 122, "STRD_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo55 }, // Inst #331 = STRD_POST
+ { 332, 8, 1, 122, "STRD_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo55 }, // Inst #332 = STRD_PRE
+ { 333, 5, 1, 128, "STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #333 = STREX
+ { 334, 5, 1, 128, "STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #334 = STREXB
+ { 335, 6, 1, 128, "STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo57 }, // Inst #335 = STREXD
+ { 336, 5, 1, 128, "STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #336 = STREXH
+ { 337, 6, 0, 121, "STRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #337 = STRH
+ { 338, 7, 1, 122, "STRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #338 = STRHT
+ { 339, 7, 1, 122, "STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #339 = STRH_POST
+ { 340, 7, 1, 122, "STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #340 = STRH_PRE
+ { 341, 7, 1, 122, "STRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #341 = STRT
+ { 342, 7, 1, 122, "STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #342 = STR_POST
+ { 343, 7, 1, 122, "STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #343 = STR_PRE
+ { 344, 5, 1, 88, "SUBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #344 = SUBSri
+ { 345, 5, 1, 89, "SUBSrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #345 = SUBSrr
+ { 346, 7, 1, 91, "SUBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #346 = SUBSrs
+ { 347, 6, 1, 88, "SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #347 = SUBri
+ { 348, 6, 1, 89, "SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #348 = SUBrr
+ { 349, 8, 1, 91, "SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #349 = SUBrs
+ { 350, 3, 0, 0, "SVC", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #350 = SVC
+ { 351, 5, 1, 128, "SWP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #351 = SWP
+ { 352, 5, 1, 128, "SWPB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #352 = SWPB
+ { 353, 5, 1, 89, "SXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #353 = SXTAB16rr
+ { 354, 6, 1, 90, "SXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #354 = SXTAB16rr_rot
+ { 355, 5, 1, 89, "SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #355 = SXTABrr
+ { 356, 6, 1, 90, "SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #356 = SXTABrr_rot
+ { 357, 5, 1, 89, "SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #357 = SXTAHrr
+ { 358, 6, 1, 90, "SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #358 = SXTAHrr_rot
+ { 359, 4, 1, 125, "SXTB16r", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #359 = SXTB16r
+ { 360, 5, 1, 126, "SXTB16r_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #360 = SXTB16r_rot
+ { 361, 4, 1, 125, "SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #361 = SXTBr
+ { 362, 5, 1, 126, "SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #362 = SXTBr_rot
+ { 363, 4, 1, 125, "SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #363 = SXTHr
+ { 364, 5, 1, 126, "SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #364 = SXTHr_rot
+ { 365, 4, 0, 97, "TEQri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #365 = TEQri
+ { 366, 4, 0, 98, "TEQrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #366 = TEQrr
+ { 367, 6, 0, 100, "TEQrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #367 = TEQrs
+ { 368, 0, 0, 0, "TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(2<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #368 = TPsoft
+ { 369, 2, 0, 128, "TRAP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #369 = TRAP
+ { 370, 4, 0, 97, "TSTri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #370 = TSTri
+ { 371, 4, 0, 98, "TSTrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #371 = TSTrr
+ { 372, 6, 0, 100, "TSTrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #372 = TSTrs
+ { 373, 5, 1, 89, "UADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #373 = UADD16
+ { 374, 5, 1, 89, "UADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #374 = UADD8
+ { 375, 5, 1, 89, "UASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #375 = UASX
+ { 376, 6, 1, 88, "UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #376 = UBFX
+ { 377, 5, 1, 89, "UHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #377 = UHADD16
+ { 378, 5, 1, 89, "UHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #378 = UHADD8
+ { 379, 5, 1, 89, "UHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #379 = UHASX
+ { 380, 5, 1, 89, "UHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #380 = UHSAX
+ { 381, 5, 1, 89, "UHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #381 = UHSUB16
+ { 382, 5, 1, 89, "UHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #382 = UHSUB8
+ { 383, 6, 2, 110, "UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #383 = UMAAL
+ { 384, 7, 2, 110, "UMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #384 = UMLAL
+ { 385, 7, 2, 117, "UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #385 = UMULL
+ { 386, 5, 1, 89, "UQADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #386 = UQADD16
+ { 387, 5, 1, 89, "UQADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #387 = UQADD8
+ { 388, 5, 1, 89, "UQASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #388 = UQASX
+ { 389, 5, 1, 89, "UQSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #389 = UQSAX
+ { 390, 5, 1, 89, "UQSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #390 = UQSUB16
+ { 391, 5, 1, 89, "UQSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #391 = UQSUB8
+ { 392, 5, 1, 128, "USAD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #392 = USAD8
+ { 393, 6, 1, 128, "USADA8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #393 = USADA8
+ { 394, 5, 1, 128, "USAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo52 }, // Inst #394 = USAT16
+ { 395, 6, 1, 128, "USATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #395 = USATasr
+ { 396, 6, 1, 128, "USATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #396 = USATlsl
+ { 397, 5, 1, 89, "USAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #397 = USAX
+ { 398, 5, 1, 89, "USUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #398 = USUB16
+ { 399, 5, 1, 89, "USUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #399 = USUB8
+ { 400, 5, 1, 89, "UXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #400 = UXTAB16rr
+ { 401, 6, 1, 90, "UXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #401 = UXTAB16rr_rot
+ { 402, 5, 1, 89, "UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #402 = UXTABrr
+ { 403, 6, 1, 90, "UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #403 = UXTABrr_rot
+ { 404, 5, 1, 89, "UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #404 = UXTAHrr
+ { 405, 6, 1, 90, "UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #405 = UXTAHrr_rot
+ { 406, 4, 1, 125, "UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #406 = UXTB16r
+ { 407, 5, 1, 126, "UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #407 = UXTB16r_rot
+ { 408, 4, 1, 125, "UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #408 = UXTBr
+ { 409, 5, 1, 126, "UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #409 = UXTBr_rot
+ { 410, 4, 1, 125, "UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #410 = UXTHr
+ { 411, 5, 1, 126, "UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #411 = UXTHr_rot
+ { 412, 6, 1, 17, "VABALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #412 = VABALsv2i64
+ { 413, 6, 1, 17, "VABALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #413 = VABALsv4i32
+ { 414, 6, 1, 17, "VABALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #414 = VABALsv8i16
+ { 415, 6, 1, 17, "VABALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #415 = VABALuv2i64
+ { 416, 6, 1, 17, "VABALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #416 = VABALuv4i32
+ { 417, 6, 1, 17, "VABALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #417 = VABALuv8i16
+ { 418, 6, 1, 18, "VABAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #418 = VABAsv16i8
+ { 419, 6, 1, 19, "VABAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #419 = VABAsv2i32
+ { 420, 6, 1, 17, "VABAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #420 = VABAsv4i16
+ { 421, 6, 1, 20, "VABAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #421 = VABAsv4i32
+ { 422, 6, 1, 18, "VABAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #422 = VABAsv8i16
+ { 423, 6, 1, 17, "VABAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #423 = VABAsv8i8
+ { 424, 6, 1, 18, "VABAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #424 = VABAuv16i8
+ { 425, 6, 1, 19, "VABAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #425 = VABAuv2i32
+ { 426, 6, 1, 17, "VABAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #426 = VABAuv4i16
+ { 427, 6, 1, 20, "VABAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #427 = VABAuv4i32
+ { 428, 6, 1, 18, "VABAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #428 = VABAuv8i16
+ { 429, 6, 1, 17, "VABAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #429 = VABAuv8i8
+ { 430, 5, 1, 4, "VABDLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #430 = VABDLsv2i64
+ { 431, 5, 1, 4, "VABDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #431 = VABDLsv4i32
+ { 432, 5, 1, 4, "VABDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #432 = VABDLsv8i16
+ { 433, 5, 1, 4, "VABDLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #433 = VABDLuv2i64
+ { 434, 5, 1, 4, "VABDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #434 = VABDLuv4i32
+ { 435, 5, 1, 4, "VABDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #435 = VABDLuv8i16
+ { 436, 5, 1, 1, "VABDfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #436 = VABDfd
+ { 437, 5, 1, 2, "VABDfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #437 = VABDfq
+ { 438, 5, 1, 4, "VABDsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #438 = VABDsv16i8
+ { 439, 5, 1, 3, "VABDsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #439 = VABDsv2i32
+ { 440, 5, 1, 3, "VABDsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #440 = VABDsv4i16
+ { 441, 5, 1, 4, "VABDsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #441 = VABDsv4i32
+ { 442, 5, 1, 4, "VABDsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #442 = VABDsv8i16
+ { 443, 5, 1, 3, "VABDsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #443 = VABDsv8i8
+ { 444, 5, 1, 4, "VABDuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #444 = VABDuv16i8
+ { 445, 5, 1, 3, "VABDuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #445 = VABDuv2i32
+ { 446, 5, 1, 3, "VABDuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #446 = VABDuv4i16
+ { 447, 5, 1, 4, "VABDuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #447 = VABDuv4i32
+ { 448, 5, 1, 4, "VABDuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #448 = VABDuv8i16
+ { 449, 5, 1, 3, "VABDuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #449 = VABDuv8i8
+ { 450, 4, 1, 87, "VABSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #450 = VABSD
+ { 451, 4, 1, 86, "VABSS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #451 = VABSS
+ { 452, 4, 1, 57, "VABSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #452 = VABSfd
+ { 453, 4, 1, 57, "VABSfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #453 = VABSfd_sfp
+ { 454, 4, 1, 58, "VABSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #454 = VABSfq
+ { 455, 4, 1, 60, "VABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #455 = VABSv16i8
+ { 456, 4, 1, 59, "VABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #456 = VABSv2i32
+ { 457, 4, 1, 59, "VABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #457 = VABSv4i16
+ { 458, 4, 1, 60, "VABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #458 = VABSv4i32
+ { 459, 4, 1, 60, "VABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #459 = VABSv8i16
+ { 460, 4, 1, 59, "VABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #460 = VABSv8i8
+ { 461, 5, 1, 1, "VACGEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #461 = VACGEd
+ { 462, 5, 1, 2, "VACGEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #462 = VACGEq
+ { 463, 5, 1, 1, "VACGTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #463 = VACGTd
+ { 464, 5, 1, 2, "VACGTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #464 = VACGTq
+ { 465, 5, 1, 62, "VADDD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #465 = VADDD
+ { 466, 5, 1, 3, "VADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #466 = VADDHNv2i32
+ { 467, 5, 1, 3, "VADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #467 = VADDHNv4i16
+ { 468, 5, 1, 3, "VADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #468 = VADDHNv8i8
+ { 469, 5, 1, 44, "VADDLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #469 = VADDLsv2i64
+ { 470, 5, 1, 44, "VADDLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #470 = VADDLsv4i32
+ { 471, 5, 1, 44, "VADDLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #471 = VADDLsv8i16
+ { 472, 5, 1, 44, "VADDLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #472 = VADDLuv2i64
+ { 473, 5, 1, 44, "VADDLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #473 = VADDLuv4i32
+ { 474, 5, 1, 44, "VADDLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #474 = VADDLuv8i16
+ { 475, 5, 1, 61, "VADDS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #475 = VADDS
+ { 476, 5, 1, 47, "VADDWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #476 = VADDWsv2i64
+ { 477, 5, 1, 47, "VADDWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #477 = VADDWsv4i32
+ { 478, 5, 1, 47, "VADDWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #478 = VADDWsv8i16
+ { 479, 5, 1, 47, "VADDWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #479 = VADDWuv2i64
+ { 480, 5, 1, 47, "VADDWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #480 = VADDWuv4i32
+ { 481, 5, 1, 47, "VADDWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #481 = VADDWuv8i16
+ { 482, 5, 1, 1, "VADDfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #482 = VADDfd
+ { 483, 5, 1, 1, "VADDfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #483 = VADDfd_sfp
+ { 484, 5, 1, 2, "VADDfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #484 = VADDfq
+ { 485, 5, 1, 6, "VADDv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #485 = VADDv16i8
+ { 486, 5, 1, 5, "VADDv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #486 = VADDv1i64
+ { 487, 5, 1, 5, "VADDv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #487 = VADDv2i32
+ { 488, 5, 1, 6, "VADDv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #488 = VADDv2i64
+ { 489, 5, 1, 5, "VADDv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #489 = VADDv4i16
+ { 490, 5, 1, 6, "VADDv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #490 = VADDv4i32
+ { 491, 5, 1, 6, "VADDv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #491 = VADDv8i16
+ { 492, 5, 1, 5, "VADDv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #492 = VADDv8i8
+ { 493, 5, 1, 5, "VANDd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #493 = VANDd
+ { 494, 5, 1, 6, "VANDq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #494 = VANDq
+ { 495, 5, 1, 5, "VBICd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #495 = VBICd
+ { 496, 5, 1, 6, "VBICq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #496 = VBICq
+ { 497, 6, 1, 5, "VBIFd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #497 = VBIFd
+ { 498, 6, 1, 6, "VBIFq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #498 = VBIFq
+ { 499, 6, 1, 5, "VBITd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #499 = VBITd
+ { 500, 6, 1, 6, "VBITq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #500 = VBITq
+ { 501, 6, 1, 7, "VBSLd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #501 = VBSLd
+ { 502, 6, 1, 8, "VBSLq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #502 = VBSLq
+ { 503, 5, 1, 1, "VCEQfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #503 = VCEQfd
+ { 504, 5, 1, 2, "VCEQfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #504 = VCEQfq
+ { 505, 5, 1, 4, "VCEQv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #505 = VCEQv16i8
+ { 506, 5, 1, 3, "VCEQv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #506 = VCEQv2i32
+ { 507, 5, 1, 3, "VCEQv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #507 = VCEQv4i16
+ { 508, 5, 1, 4, "VCEQv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #508 = VCEQv4i32
+ { 509, 5, 1, 4, "VCEQv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #509 = VCEQv8i16
+ { 510, 5, 1, 3, "VCEQv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #510 = VCEQv8i8
+ { 511, 4, 1, 128, "VCEQzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #511 = VCEQzv16i8
+ { 512, 4, 1, 128, "VCEQzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #512 = VCEQzv2f32
+ { 513, 4, 1, 128, "VCEQzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #513 = VCEQzv2i32
+ { 514, 4, 1, 128, "VCEQzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #514 = VCEQzv4f32
+ { 515, 4, 1, 128, "VCEQzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #515 = VCEQzv4i16
+ { 516, 4, 1, 128, "VCEQzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #516 = VCEQzv4i32
+ { 517, 4, 1, 128, "VCEQzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #517 = VCEQzv8i16
+ { 518, 4, 1, 128, "VCEQzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #518 = VCEQzv8i8
+ { 519, 5, 1, 1, "VCGEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #519 = VCGEfd
+ { 520, 5, 1, 2, "VCGEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #520 = VCGEfq
+ { 521, 5, 1, 4, "VCGEsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #521 = VCGEsv16i8
+ { 522, 5, 1, 3, "VCGEsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #522 = VCGEsv2i32
+ { 523, 5, 1, 3, "VCGEsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #523 = VCGEsv4i16
+ { 524, 5, 1, 4, "VCGEsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #524 = VCGEsv4i32
+ { 525, 5, 1, 4, "VCGEsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #525 = VCGEsv8i16
+ { 526, 5, 1, 3, "VCGEsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #526 = VCGEsv8i8
+ { 527, 5, 1, 4, "VCGEuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #527 = VCGEuv16i8
+ { 528, 5, 1, 3, "VCGEuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #528 = VCGEuv2i32
+ { 529, 5, 1, 3, "VCGEuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #529 = VCGEuv4i16
+ { 530, 5, 1, 4, "VCGEuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #530 = VCGEuv4i32
+ { 531, 5, 1, 4, "VCGEuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #531 = VCGEuv8i16
+ { 532, 5, 1, 3, "VCGEuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #532 = VCGEuv8i8
+ { 533, 4, 1, 128, "VCGEzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #533 = VCGEzv16i8
+ { 534, 4, 1, 128, "VCGEzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #534 = VCGEzv2f32
+ { 535, 4, 1, 128, "VCGEzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #535 = VCGEzv2i32
+ { 536, 4, 1, 128, "VCGEzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #536 = VCGEzv4f32
+ { 537, 4, 1, 128, "VCGEzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #537 = VCGEzv4i16
+ { 538, 4, 1, 128, "VCGEzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #538 = VCGEzv4i32
+ { 539, 4, 1, 128, "VCGEzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #539 = VCGEzv8i16
+ { 540, 4, 1, 128, "VCGEzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #540 = VCGEzv8i8
+ { 541, 5, 1, 1, "VCGTfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #541 = VCGTfd
+ { 542, 5, 1, 2, "VCGTfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #542 = VCGTfq
+ { 543, 5, 1, 4, "VCGTsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #543 = VCGTsv16i8
+ { 544, 5, 1, 3, "VCGTsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #544 = VCGTsv2i32
+ { 545, 5, 1, 3, "VCGTsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #545 = VCGTsv4i16
+ { 546, 5, 1, 4, "VCGTsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #546 = VCGTsv4i32
+ { 547, 5, 1, 4, "VCGTsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #547 = VCGTsv8i16
+ { 548, 5, 1, 3, "VCGTsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #548 = VCGTsv8i8
+ { 549, 5, 1, 4, "VCGTuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #549 = VCGTuv16i8
+ { 550, 5, 1, 3, "VCGTuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #550 = VCGTuv2i32
+ { 551, 5, 1, 3, "VCGTuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #551 = VCGTuv4i16
+ { 552, 5, 1, 4, "VCGTuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #552 = VCGTuv4i32
+ { 553, 5, 1, 4, "VCGTuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #553 = VCGTuv8i16
+ { 554, 5, 1, 3, "VCGTuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #554 = VCGTuv8i8
+ { 555, 4, 1, 128, "VCGTzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #555 = VCGTzv16i8
+ { 556, 4, 1, 128, "VCGTzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #556 = VCGTzv2f32
+ { 557, 4, 1, 128, "VCGTzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #557 = VCGTzv2i32
+ { 558, 4, 1, 128, "VCGTzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #558 = VCGTzv4f32
+ { 559, 4, 1, 128, "VCGTzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #559 = VCGTzv4i16
+ { 560, 4, 1, 128, "VCGTzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #560 = VCGTzv4i32
+ { 561, 4, 1, 128, "VCGTzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #561 = VCGTzv8i16
+ { 562, 4, 1, 128, "VCGTzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #562 = VCGTzv8i8
+ { 563, 4, 1, 128, "VCLEzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #563 = VCLEzv16i8
+ { 564, 4, 1, 128, "VCLEzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #564 = VCLEzv2f32
+ { 565, 4, 1, 128, "VCLEzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #565 = VCLEzv2i32
+ { 566, 4, 1, 128, "VCLEzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #566 = VCLEzv4f32
+ { 567, 4, 1, 128, "VCLEzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #567 = VCLEzv4i16
+ { 568, 4, 1, 128, "VCLEzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #568 = VCLEzv4i32
+ { 569, 4, 1, 128, "VCLEzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #569 = VCLEzv8i16
+ { 570, 4, 1, 128, "VCLEzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #570 = VCLEzv8i8
+ { 571, 4, 1, 8, "VCLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #571 = VCLSv16i8
+ { 572, 4, 1, 7, "VCLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #572 = VCLSv2i32
+ { 573, 4, 1, 7, "VCLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #573 = VCLSv4i16
+ { 574, 4, 1, 8, "VCLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #574 = VCLSv4i32
+ { 575, 4, 1, 8, "VCLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #575 = VCLSv8i16
+ { 576, 4, 1, 7, "VCLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #576 = VCLSv8i8
+ { 577, 4, 1, 128, "VCLTzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #577 = VCLTzv16i8
+ { 578, 4, 1, 128, "VCLTzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #578 = VCLTzv2f32
+ { 579, 4, 1, 128, "VCLTzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #579 = VCLTzv2i32
+ { 580, 4, 1, 128, "VCLTzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #580 = VCLTzv4f32
+ { 581, 4, 1, 128, "VCLTzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #581 = VCLTzv4i16
+ { 582, 4, 1, 128, "VCLTzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #582 = VCLTzv4i32
+ { 583, 4, 1, 128, "VCLTzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #583 = VCLTzv8i16
+ { 584, 4, 1, 128, "VCLTzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #584 = VCLTzv8i8
+ { 585, 4, 1, 8, "VCLZv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #585 = VCLZv16i8
+ { 586, 4, 1, 7, "VCLZv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #586 = VCLZv2i32
+ { 587, 4, 1, 7, "VCLZv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #587 = VCLZv4i16
+ { 588, 4, 1, 8, "VCLZv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #588 = VCLZv4i32
+ { 589, 4, 1, 8, "VCLZv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #589 = VCLZv8i16
+ { 590, 4, 1, 7, "VCLZv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #590 = VCLZv8i8
+ { 591, 4, 0, 64, "VCMPD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo65 }, // Inst #591 = VCMPD
+ { 592, 4, 0, 64, "VCMPED", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo65 }, // Inst #592 = VCMPED
+ { 593, 4, 0, 63, "VCMPES", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo66 }, // Inst #593 = VCMPES
+ { 594, 3, 0, 64, "VCMPEZD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo73 }, // Inst #594 = VCMPEZD
+ { 595, 3, 0, 63, "VCMPEZS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo74 }, // Inst #595 = VCMPEZS
+ { 596, 4, 0, 63, "VCMPS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo66 }, // Inst #596 = VCMPS
+ { 597, 3, 0, 64, "VCMPZD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo73 }, // Inst #597 = VCMPZD
+ { 598, 3, 0, 63, "VCMPZS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo74 }, // Inst #598 = VCMPZS
+ { 599, 4, 1, 7, "VCNTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #599 = VCNTd
+ { 600, 4, 1, 8, "VCNTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #600 = VCNTq
+ { 601, 4, 1, 66, "VCVTBHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #601 = VCVTBHS
+ { 602, 4, 1, 66, "VCVTBSH", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #602 = VCVTBSH
+ { 603, 4, 1, 66, "VCVTDS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #603 = VCVTDS
+ { 604, 4, 1, 69, "VCVTSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #604 = VCVTSD
+ { 605, 4, 1, 66, "VCVTTHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #605 = VCVTTHS
+ { 606, 4, 1, 66, "VCVTTSH", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #606 = VCVTTSH
+ { 607, 4, 1, 57, "VCVTf2sd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #607 = VCVTf2sd
+ { 608, 4, 1, 57, "VCVTf2sd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #608 = VCVTf2sd_sfp
+ { 609, 4, 1, 58, "VCVTf2sq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #609 = VCVTf2sq
+ { 610, 4, 1, 57, "VCVTf2ud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #610 = VCVTf2ud
+ { 611, 4, 1, 57, "VCVTf2ud_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #611 = VCVTf2ud_sfp
+ { 612, 4, 1, 58, "VCVTf2uq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #612 = VCVTf2uq
+ { 613, 5, 1, 57, "VCVTf2xsd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #613 = VCVTf2xsd
+ { 614, 5, 1, 58, "VCVTf2xsq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #614 = VCVTf2xsq
+ { 615, 5, 1, 57, "VCVTf2xud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #615 = VCVTf2xud
+ { 616, 5, 1, 58, "VCVTf2xuq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #616 = VCVTf2xuq
+ { 617, 4, 1, 57, "VCVTs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #617 = VCVTs2fd
+ { 618, 4, 1, 57, "VCVTs2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #618 = VCVTs2fd_sfp
+ { 619, 4, 1, 58, "VCVTs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #619 = VCVTs2fq
+ { 620, 4, 1, 57, "VCVTu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #620 = VCVTu2fd
+ { 621, 4, 1, 57, "VCVTu2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #621 = VCVTu2fd_sfp
+ { 622, 4, 1, 58, "VCVTu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #622 = VCVTu2fq
+ { 623, 5, 1, 57, "VCVTxs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #623 = VCVTxs2fd
+ { 624, 5, 1, 58, "VCVTxs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #624 = VCVTxs2fq
+ { 625, 5, 1, 57, "VCVTxu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #625 = VCVTxu2fd
+ { 626, 5, 1, 58, "VCVTxu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #626 = VCVTxu2fq
+ { 627, 5, 1, 72, "VDIVD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #627 = VDIVD
+ { 628, 5, 1, 71, "VDIVS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #628 = VDIVS
+ { 629, 4, 1, 24, "VDUP16d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 }, // Inst #629 = VDUP16d
+ { 630, 4, 1, 24, "VDUP16q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 }, // Inst #630 = VDUP16q
+ { 631, 4, 1, 24, "VDUP32d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 }, // Inst #631 = VDUP32d
+ { 632, 4, 1, 24, "VDUP32q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 }, // Inst #632 = VDUP32q
+ { 633, 4, 1, 24, "VDUP8d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 }, // Inst #633 = VDUP8d
+ { 634, 4, 1, 24, "VDUP8q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 }, // Inst #634 = VDUP8q
+ { 635, 5, 1, 21, "VDUPLN16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #635 = VDUPLN16d
+ { 636, 5, 1, 21, "VDUPLN16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #636 = VDUPLN16q
+ { 637, 5, 1, 21, "VDUPLN32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #637 = VDUPLN32d
+ { 638, 5, 1, 21, "VDUPLN32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #638 = VDUPLN32q
+ { 639, 5, 1, 21, "VDUPLN8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #639 = VDUPLN8d
+ { 640, 5, 1, 21, "VDUPLN8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #640 = VDUPLN8q
+ { 641, 5, 1, 21, "VDUPLNfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #641 = VDUPLNfd
+ { 642, 5, 1, 21, "VDUPLNfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #642 = VDUPLNfq
+ { 643, 4, 1, 24, "VDUPfd", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 }, // Inst #643 = VDUPfd
+ { 644, 4, 1, 21, "VDUPfdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #644 = VDUPfdf
+ { 645, 4, 1, 24, "VDUPfq", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 }, // Inst #645 = VDUPfq
+ { 646, 4, 1, 21, "VDUPfqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #646 = VDUPfqf
+ { 647, 5, 1, 5, "VEORd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #647 = VEORd
+ { 648, 5, 1, 6, "VEORq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #648 = VEORq
+ { 649, 6, 1, 9, "VEXTd16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #649 = VEXTd16
+ { 650, 6, 1, 9, "VEXTd32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #650 = VEXTd32
+ { 651, 6, 1, 9, "VEXTd8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #651 = VEXTd8
+ { 652, 6, 1, 9, "VEXTdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #652 = VEXTdf
+ { 653, 6, 1, 10, "VEXTq16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #653 = VEXTq16
+ { 654, 6, 1, 10, "VEXTq32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #654 = VEXTq32
+ { 655, 6, 1, 10, "VEXTq8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #655 = VEXTq8
+ { 656, 6, 1, 10, "VEXTqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #656 = VEXTqf
+ { 657, 5, 1, 28, "VGETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #657 = VGETLNi32
+ { 658, 5, 1, 28, "VGETLNs16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #658 = VGETLNs16
+ { 659, 5, 1, 28, "VGETLNs8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #659 = VGETLNs8
+ { 660, 5, 1, 28, "VGETLNu16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #660 = VGETLNu16
+ { 661, 5, 1, 28, "VGETLNu8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #661 = VGETLNu8
+ { 662, 5, 1, 4, "VHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #662 = VHADDsv16i8
+ { 663, 5, 1, 3, "VHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #663 = VHADDsv2i32
+ { 664, 5, 1, 3, "VHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #664 = VHADDsv4i16
+ { 665, 5, 1, 4, "VHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #665 = VHADDsv4i32
+ { 666, 5, 1, 4, "VHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #666 = VHADDsv8i16
+ { 667, 5, 1, 3, "VHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #667 = VHADDsv8i8
+ { 668, 5, 1, 4, "VHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #668 = VHADDuv16i8
+ { 669, 5, 1, 3, "VHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #669 = VHADDuv2i32
+ { 670, 5, 1, 3, "VHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #670 = VHADDuv4i16
+ { 671, 5, 1, 4, "VHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #671 = VHADDuv4i32
+ { 672, 5, 1, 4, "VHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #672 = VHADDuv8i16
+ { 673, 5, 1, 3, "VHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #673 = VHADDuv8i8
+ { 674, 5, 1, 4, "VHSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #674 = VHSUBsv16i8
+ { 675, 5, 1, 3, "VHSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #675 = VHSUBsv2i32
+ { 676, 5, 1, 3, "VHSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #676 = VHSUBsv4i16
+ { 677, 5, 1, 4, "VHSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #677 = VHSUBsv4i32
+ { 678, 5, 1, 4, "VHSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #678 = VHSUBsv8i16
+ { 679, 5, 1, 3, "VHSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #679 = VHSUBsv8i8
+ { 680, 5, 1, 4, "VHSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #680 = VHSUBuv16i8
+ { 681, 5, 1, 3, "VHSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #681 = VHSUBuv2i32
+ { 682, 5, 1, 3, "VHSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #682 = VHSUBuv4i16
+ { 683, 5, 1, 4, "VHSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #683 = VHSUBuv4i32
+ { 684, 5, 1, 4, "VHSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #684 = VHSUBuv8i16
+ { 685, 5, 1, 3, "VHSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #685 = VHSUBuv8i8
+ { 686, 7, 1, 11, "VLD1d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #686 = VLD1d16
+ { 687, 10, 4, 11, "VLD1d16Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #687 = VLD1d16Q
+ { 688, 9, 3, 11, "VLD1d16T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #688 = VLD1d16T
+ { 689, 7, 1, 11, "VLD1d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #689 = VLD1d32
+ { 690, 10, 4, 11, "VLD1d32Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #690 = VLD1d32Q
+ { 691, 9, 3, 11, "VLD1d32T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #691 = VLD1d32T
+ { 692, 7, 1, 11, "VLD1d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #692 = VLD1d64
+ { 693, 7, 1, 11, "VLD1d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #693 = VLD1d8
+ { 694, 10, 4, 11, "VLD1d8Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #694 = VLD1d8Q
+ { 695, 9, 3, 11, "VLD1d8T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #695 = VLD1d8T
+ { 696, 7, 1, 11, "VLD1df", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #696 = VLD1df
+ { 697, 7, 1, 11, "VLD1q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #697 = VLD1q16
+ { 698, 7, 1, 11, "VLD1q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #698 = VLD1q32
+ { 699, 7, 1, 11, "VLD1q64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #699 = VLD1q64
+ { 700, 7, 1, 11, "VLD1q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #700 = VLD1q8
+ { 701, 7, 1, 11, "VLD1qf", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #701 = VLD1qf
+ { 702, 11, 2, 12, "VLD2LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #702 = VLD2LNd16
+ { 703, 11, 2, 12, "VLD2LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #703 = VLD2LNd32
+ { 704, 11, 2, 12, "VLD2LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #704 = VLD2LNd8
+ { 705, 11, 2, 12, "VLD2LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #705 = VLD2LNq16a
+ { 706, 11, 2, 12, "VLD2LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #706 = VLD2LNq16b
+ { 707, 11, 2, 12, "VLD2LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #707 = VLD2LNq32a
+ { 708, 11, 2, 12, "VLD2LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #708 = VLD2LNq32b
+ { 709, 8, 2, 12, "VLD2d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #709 = VLD2d16
+ { 710, 8, 2, 12, "VLD2d16D", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #710 = VLD2d16D
+ { 711, 8, 2, 12, "VLD2d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #711 = VLD2d32
+ { 712, 8, 2, 12, "VLD2d32D", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #712 = VLD2d32D
+ { 713, 8, 2, 11, "VLD2d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #713 = VLD2d64
+ { 714, 8, 2, 12, "VLD2d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #714 = VLD2d8
+ { 715, 8, 2, 12, "VLD2d8D", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #715 = VLD2d8D
+ { 716, 10, 4, 12, "VLD2q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #716 = VLD2q16
+ { 717, 10, 4, 12, "VLD2q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #717 = VLD2q32
+ { 718, 10, 4, 12, "VLD2q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #718 = VLD2q8
+ { 719, 13, 3, 13, "VLD3LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #719 = VLD3LNd16
+ { 720, 13, 3, 13, "VLD3LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #720 = VLD3LNd32
+ { 721, 13, 3, 13, "VLD3LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #721 = VLD3LNd8
+ { 722, 13, 3, 13, "VLD3LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #722 = VLD3LNq16a
+ { 723, 13, 3, 13, "VLD3LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #723 = VLD3LNq16b
+ { 724, 13, 3, 13, "VLD3LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #724 = VLD3LNq32a
+ { 725, 13, 3, 13, "VLD3LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #725 = VLD3LNq32b
+ { 726, 9, 3, 13, "VLD3d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #726 = VLD3d16
+ { 727, 9, 3, 13, "VLD3d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #727 = VLD3d32
+ { 728, 9, 3, 11, "VLD3d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #728 = VLD3d64
+ { 729, 9, 3, 13, "VLD3d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #729 = VLD3d8
+ { 730, 10, 4, 13, "VLD3q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #730 = VLD3q16a
+ { 731, 10, 4, 13, "VLD3q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #731 = VLD3q16b
+ { 732, 10, 4, 13, "VLD3q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #732 = VLD3q32a
+ { 733, 10, 4, 13, "VLD3q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #733 = VLD3q32b
+ { 734, 10, 4, 13, "VLD3q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #734 = VLD3q8a
+ { 735, 10, 4, 13, "VLD3q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #735 = VLD3q8b
+ { 736, 15, 4, 14, "VLD4LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #736 = VLD4LNd16
+ { 737, 15, 4, 14, "VLD4LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #737 = VLD4LNd32
+ { 738, 15, 4, 14, "VLD4LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #738 = VLD4LNd8
+ { 739, 15, 4, 14, "VLD4LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #739 = VLD4LNq16a
+ { 740, 15, 4, 14, "VLD4LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #740 = VLD4LNq16b
+ { 741, 15, 4, 14, "VLD4LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #741 = VLD4LNq32a
+ { 742, 15, 4, 14, "VLD4LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #742 = VLD4LNq32b
+ { 743, 10, 4, 14, "VLD4d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #743 = VLD4d16
+ { 744, 10, 4, 14, "VLD4d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #744 = VLD4d32
+ { 745, 10, 4, 11, "VLD4d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #745 = VLD4d64
+ { 746, 10, 4, 14, "VLD4d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #746 = VLD4d8
+ { 747, 11, 5, 14, "VLD4q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #747 = VLD4q16a
+ { 748, 11, 5, 14, "VLD4q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #748 = VLD4q16b
+ { 749, 11, 5, 14, "VLD4q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #749 = VLD4q32a
+ { 750, 11, 5, 14, "VLD4q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #750 = VLD4q32b
+ { 751, 11, 5, 14, "VLD4q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #751 = VLD4q8a
+ { 752, 11, 5, 14, "VLD4q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #752 = VLD4q8b
+ { 753, 5, 0, 75, "VLDMD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo35 }, // Inst #753 = VLDMD
+ { 754, 5, 0, 75, "VLDMS", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo35 }, // Inst #754 = VLDMS
+ { 755, 5, 1, 74, "VLDRD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #755 = VLDRD
+ { 756, 5, 1, 75, "VLDRQ", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #756 = VLDRQ
+ { 757, 5, 1, 73, "VLDRS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #757 = VLDRS
+ { 758, 5, 1, 1, "VMAXfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #758 = VMAXfd
+ { 759, 5, 1, 1, "VMAXfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #759 = VMAXfd_sfp
+ { 760, 5, 1, 2, "VMAXfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #760 = VMAXfq
+ { 761, 5, 1, 4, "VMAXsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #761 = VMAXsv16i8
+ { 762, 5, 1, 3, "VMAXsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #762 = VMAXsv2i32
+ { 763, 5, 1, 3, "VMAXsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #763 = VMAXsv4i16
+ { 764, 5, 1, 4, "VMAXsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #764 = VMAXsv4i32
+ { 765, 5, 1, 4, "VMAXsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #765 = VMAXsv8i16
+ { 766, 5, 1, 3, "VMAXsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #766 = VMAXsv8i8
+ { 767, 5, 1, 4, "VMAXuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #767 = VMAXuv16i8
+ { 768, 5, 1, 3, "VMAXuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #768 = VMAXuv2i32
+ { 769, 5, 1, 3, "VMAXuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #769 = VMAXuv4i16
+ { 770, 5, 1, 4, "VMAXuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #770 = VMAXuv4i32
+ { 771, 5, 1, 4, "VMAXuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #771 = VMAXuv8i16
+ { 772, 5, 1, 3, "VMAXuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #772 = VMAXuv8i8
+ { 773, 5, 1, 1, "VMINfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #773 = VMINfd
+ { 774, 5, 1, 1, "VMINfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #774 = VMINfd_sfp
+ { 775, 5, 1, 2, "VMINfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #775 = VMINfq
+ { 776, 5, 1, 4, "VMINsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #776 = VMINsv16i8
+ { 777, 5, 1, 3, "VMINsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #777 = VMINsv2i32
+ { 778, 5, 1, 3, "VMINsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #778 = VMINsv4i16
+ { 779, 5, 1, 4, "VMINsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #779 = VMINsv4i32
+ { 780, 5, 1, 4, "VMINsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #780 = VMINsv8i16
+ { 781, 5, 1, 3, "VMINsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #781 = VMINsv8i8
+ { 782, 5, 1, 4, "VMINuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #782 = VMINuv16i8
+ { 783, 5, 1, 3, "VMINuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #783 = VMINuv2i32
+ { 784, 5, 1, 3, "VMINuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #784 = VMINuv4i16
+ { 785, 5, 1, 4, "VMINuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #785 = VMINuv4i32
+ { 786, 5, 1, 4, "VMINuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #786 = VMINuv8i16
+ { 787, 5, 1, 3, "VMINuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #787 = VMINuv8i8
+ { 788, 6, 1, 77, "VMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #788 = VMLAD
+ { 789, 7, 1, 19, "VMLALslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #789 = VMLALslsv2i32
+ { 790, 7, 1, 17, "VMLALslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #790 = VMLALslsv4i16
+ { 791, 7, 1, 19, "VMLALsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #791 = VMLALsluv2i32
+ { 792, 7, 1, 17, "VMLALsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #792 = VMLALsluv4i16
+ { 793, 6, 1, 17, "VMLALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #793 = VMLALsv2i64
+ { 794, 6, 1, 17, "VMLALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #794 = VMLALsv4i32
+ { 795, 6, 1, 17, "VMLALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #795 = VMLALsv8i16
+ { 796, 6, 1, 17, "VMLALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #796 = VMLALuv2i64
+ { 797, 6, 1, 17, "VMLALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #797 = VMLALuv4i32
+ { 798, 6, 1, 17, "VMLALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #798 = VMLALuv8i16
+ { 799, 6, 1, 76, "VMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #799 = VMLAS
+ { 800, 6, 1, 15, "VMLAfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #800 = VMLAfd
+ { 801, 6, 1, 16, "VMLAfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #801 = VMLAfq
+ { 802, 7, 1, 15, "VMLAslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #802 = VMLAslfd
+ { 803, 7, 1, 16, "VMLAslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #803 = VMLAslfq
+ { 804, 7, 1, 19, "VMLAslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #804 = VMLAslv2i32
+ { 805, 7, 1, 17, "VMLAslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #805 = VMLAslv4i16
+ { 806, 7, 1, 20, "VMLAslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #806 = VMLAslv4i32
+ { 807, 7, 1, 18, "VMLAslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #807 = VMLAslv8i16
+ { 808, 6, 1, 18, "VMLAv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #808 = VMLAv16i8
+ { 809, 6, 1, 19, "VMLAv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #809 = VMLAv2i32
+ { 810, 6, 1, 17, "VMLAv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #810 = VMLAv4i16
+ { 811, 6, 1, 20, "VMLAv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #811 = VMLAv4i32
+ { 812, 6, 1, 18, "VMLAv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #812 = VMLAv8i16
+ { 813, 6, 1, 17, "VMLAv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #813 = VMLAv8i8
+ { 814, 6, 1, 77, "VMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #814 = VMLSD
+ { 815, 7, 1, 19, "VMLSLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #815 = VMLSLslsv2i32
+ { 816, 7, 1, 17, "VMLSLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #816 = VMLSLslsv4i16
+ { 817, 7, 1, 19, "VMLSLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #817 = VMLSLsluv2i32
+ { 818, 7, 1, 17, "VMLSLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #818 = VMLSLsluv4i16
+ { 819, 6, 1, 17, "VMLSLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #819 = VMLSLsv2i64
+ { 820, 6, 1, 17, "VMLSLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #820 = VMLSLsv4i32
+ { 821, 6, 1, 17, "VMLSLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #821 = VMLSLsv8i16
+ { 822, 6, 1, 17, "VMLSLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #822 = VMLSLuv2i64
+ { 823, 6, 1, 17, "VMLSLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #823 = VMLSLuv4i32
+ { 824, 6, 1, 17, "VMLSLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #824 = VMLSLuv8i16
+ { 825, 6, 1, 76, "VMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #825 = VMLSS
+ { 826, 6, 1, 15, "VMLSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #826 = VMLSfd
+ { 827, 6, 1, 16, "VMLSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #827 = VMLSfq
+ { 828, 7, 1, 15, "VMLSslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #828 = VMLSslfd
+ { 829, 7, 1, 16, "VMLSslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #829 = VMLSslfq
+ { 830, 7, 1, 19, "VMLSslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #830 = VMLSslv2i32
+ { 831, 7, 1, 17, "VMLSslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #831 = VMLSslv4i16
+ { 832, 7, 1, 20, "VMLSslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #832 = VMLSslv4i32
+ { 833, 7, 1, 18, "VMLSslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #833 = VMLSslv8i16
+ { 834, 6, 1, 18, "VMLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #834 = VMLSv16i8
+ { 835, 6, 1, 19, "VMLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #835 = VMLSv2i32
+ { 836, 6, 1, 17, "VMLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #836 = VMLSv4i16
+ { 837, 6, 1, 20, "VMLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #837 = VMLSv4i32
+ { 838, 6, 1, 18, "VMLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #838 = VMLSv8i16
+ { 839, 6, 1, 17, "VMLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #839 = VMLSv8i8
+ { 840, 4, 1, 87, "VMOVD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #840 = VMOVD
+ { 841, 5, 1, 23, "VMOVDRR", 0|(1<<TID::Predicable), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #841 = VMOVDRR
+ { 842, 5, 1, 87, "VMOVDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #842 = VMOVDcc
+ { 843, 4, 1, 21, "VMOVDneon", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #843 = VMOVDneon
+ { 844, 4, 1, 38, "VMOVLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #844 = VMOVLsv2i64
+ { 845, 4, 1, 38, "VMOVLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #845 = VMOVLsv4i32
+ { 846, 4, 1, 38, "VMOVLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #846 = VMOVLsv8i16
+ { 847, 4, 1, 38, "VMOVLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #847 = VMOVLuv2i64
+ { 848, 4, 1, 38, "VMOVLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #848 = VMOVLuv4i32
+ { 849, 4, 1, 38, "VMOVLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #849 = VMOVLuv8i16
+ { 850, 4, 1, 21, "VMOVNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #850 = VMOVNv2i32
+ { 851, 4, 1, 21, "VMOVNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #851 = VMOVNv4i16
+ { 852, 4, 1, 21, "VMOVNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #852 = VMOVNv8i8
+ { 853, 4, 1, 21, "VMOVQ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #853 = VMOVQ
+ { 854, 5, 2, 22, "VMOVRRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #854 = VMOVRRD
+ { 855, 6, 2, 22, "VMOVRRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #855 = VMOVRRS
+ { 856, 4, 1, 28, "VMOVRS", 0|(1<<TID::Predicable), 0|(3<<4)|(16<<9)|(1<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #856 = VMOVRS
+ { 857, 4, 1, 86, "VMOVS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #857 = VMOVS
+ { 858, 4, 1, 24, "VMOVSR", 0|(1<<TID::Predicable), 0|(3<<4)|(18<<9)|(1<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #858 = VMOVSR
+ { 859, 6, 2, 23, "VMOVSRR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #859 = VMOVSRR
+ { 860, 5, 1, 86, "VMOVScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #860 = VMOVScc
+ { 861, 4, 1, 26, "VMOVv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #861 = VMOVv16i8
+ { 862, 4, 1, 26, "VMOVv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #862 = VMOVv1i64
+ { 863, 4, 1, 26, "VMOVv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #863 = VMOVv2i32
+ { 864, 4, 1, 26, "VMOVv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #864 = VMOVv2i64
+ { 865, 4, 1, 26, "VMOVv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #865 = VMOVv4i16
+ { 866, 4, 1, 26, "VMOVv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #866 = VMOVv4i32
+ { 867, 4, 1, 26, "VMOVv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #867 = VMOVv8i16
+ { 868, 4, 1, 26, "VMOVv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #868 = VMOVv8i8
+ { 869, 3, 1, 82, "VMRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, NULL, NULL, OperandInfo21 }, // Inst #869 = VMRS
+ { 870, 3, 0, 82, "VMSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(22<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo21 }, // Inst #870 = VMSR
+ { 871, 5, 1, 79, "VMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #871 = VMULD
+ { 872, 5, 1, 29, "VMULLp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #872 = VMULLp
+ { 873, 6, 1, 29, "VMULLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #873 = VMULLslsv2i32
+ { 874, 6, 1, 29, "VMULLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #874 = VMULLslsv4i16
+ { 875, 6, 1, 29, "VMULLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #875 = VMULLsluv2i32
+ { 876, 6, 1, 29, "VMULLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #876 = VMULLsluv4i16
+ { 877, 5, 1, 29, "VMULLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #877 = VMULLsv2i64
+ { 878, 5, 1, 29, "VMULLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #878 = VMULLsv4i32
+ { 879, 5, 1, 29, "VMULLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #879 = VMULLsv8i16
+ { 880, 5, 1, 29, "VMULLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #880 = VMULLuv2i64
+ { 881, 5, 1, 29, "VMULLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #881 = VMULLuv4i32
+ { 882, 5, 1, 29, "VMULLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #882 = VMULLuv8i16
+ { 883, 5, 1, 78, "VMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #883 = VMULS
+ { 884, 5, 1, 1, "VMULfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #884 = VMULfd
+ { 885, 5, 1, 1, "VMULfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #885 = VMULfd_sfp
+ { 886, 5, 1, 2, "VMULfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #886 = VMULfq
+ { 887, 5, 1, 29, "VMULpd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #887 = VMULpd
+ { 888, 5, 1, 30, "VMULpq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #888 = VMULpq
+ { 889, 6, 1, 1, "VMULslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #889 = VMULslfd
+ { 890, 6, 1, 2, "VMULslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #890 = VMULslfq
+ { 891, 6, 1, 31, "VMULslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #891 = VMULslv2i32
+ { 892, 6, 1, 29, "VMULslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #892 = VMULslv4i16
+ { 893, 6, 1, 32, "VMULslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #893 = VMULslv4i32
+ { 894, 6, 1, 30, "VMULslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #894 = VMULslv8i16
+ { 895, 5, 1, 30, "VMULv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #895 = VMULv16i8
+ { 896, 5, 1, 31, "VMULv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #896 = VMULv2i32
+ { 897, 5, 1, 29, "VMULv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #897 = VMULv4i16
+ { 898, 5, 1, 32, "VMULv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #898 = VMULv4i32
+ { 899, 5, 1, 30, "VMULv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #899 = VMULv8i16
+ { 900, 5, 1, 29, "VMULv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #900 = VMULv8i8
+ { 901, 4, 1, 44, "VMVNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #901 = VMVNd
+ { 902, 4, 1, 44, "VMVNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #902 = VMVNq
+ { 903, 4, 1, 87, "VNEGD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #903 = VNEGD
+ { 904, 5, 1, 87, "VNEGDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #904 = VNEGDcc
+ { 905, 4, 1, 86, "VNEGS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #905 = VNEGS
+ { 906, 5, 1, 86, "VNEGScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #906 = VNEGScc
+ { 907, 4, 1, 58, "VNEGf32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #907 = VNEGf32q
+ { 908, 4, 1, 57, "VNEGfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #908 = VNEGfd
+ { 909, 4, 1, 57, "VNEGfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #909 = VNEGfd_sfp
+ { 910, 4, 1, 44, "VNEGs16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #910 = VNEGs16d
+ { 911, 4, 1, 44, "VNEGs16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #911 = VNEGs16q
+ { 912, 4, 1, 44, "VNEGs32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #912 = VNEGs32d
+ { 913, 4, 1, 44, "VNEGs32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #913 = VNEGs32q
+ { 914, 4, 1, 44, "VNEGs8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #914 = VNEGs8d
+ { 915, 4, 1, 44, "VNEGs8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #915 = VNEGs8q
+ { 916, 6, 1, 77, "VNMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #916 = VNMLAD
+ { 917, 6, 1, 76, "VNMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #917 = VNMLAS
+ { 918, 6, 1, 77, "VNMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #918 = VNMLSD
+ { 919, 6, 1, 76, "VNMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #919 = VNMLSS
+ { 920, 5, 1, 79, "VNMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #920 = VNMULD
+ { 921, 5, 1, 78, "VNMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #921 = VNMULS
+ { 922, 5, 1, 5, "VORNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #922 = VORNd
+ { 923, 5, 1, 6, "VORNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #923 = VORNq
+ { 924, 5, 1, 5, "VORRd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #924 = VORRd
+ { 925, 5, 1, 6, "VORRq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #925 = VORRq
+ { 926, 5, 1, 34, "VPADALsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #926 = VPADALsv16i8
+ { 927, 5, 1, 33, "VPADALsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #927 = VPADALsv2i32
+ { 928, 5, 1, 33, "VPADALsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #928 = VPADALsv4i16
+ { 929, 5, 1, 34, "VPADALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #929 = VPADALsv4i32
+ { 930, 5, 1, 34, "VPADALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #930 = VPADALsv8i16
+ { 931, 5, 1, 33, "VPADALsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #931 = VPADALsv8i8
+ { 932, 5, 1, 34, "VPADALuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #932 = VPADALuv16i8
+ { 933, 5, 1, 33, "VPADALuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #933 = VPADALuv2i32
+ { 934, 5, 1, 33, "VPADALuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #934 = VPADALuv4i16
+ { 935, 5, 1, 34, "VPADALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #935 = VPADALuv4i32
+ { 936, 5, 1, 34, "VPADALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #936 = VPADALuv8i16
+ { 937, 5, 1, 33, "VPADALuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #937 = VPADALuv8i8
+ { 938, 4, 1, 44, "VPADDLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #938 = VPADDLsv16i8
+ { 939, 4, 1, 44, "VPADDLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #939 = VPADDLsv2i32
+ { 940, 4, 1, 44, "VPADDLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #940 = VPADDLsv4i16
+ { 941, 4, 1, 44, "VPADDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #941 = VPADDLsv4i32
+ { 942, 4, 1, 44, "VPADDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #942 = VPADDLsv8i16
+ { 943, 4, 1, 44, "VPADDLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #943 = VPADDLsv8i8
+ { 944, 4, 1, 44, "VPADDLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #944 = VPADDLuv16i8
+ { 945, 4, 1, 44, "VPADDLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #945 = VPADDLuv2i32
+ { 946, 4, 1, 44, "VPADDLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #946 = VPADDLuv4i16
+ { 947, 4, 1, 44, "VPADDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #947 = VPADDLuv4i32
+ { 948, 4, 1, 44, "VPADDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #948 = VPADDLuv8i16
+ { 949, 4, 1, 44, "VPADDLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #949 = VPADDLuv8i8
+ { 950, 5, 1, 1, "VPADDf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #950 = VPADDf
+ { 951, 5, 1, 5, "VPADDi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #951 = VPADDi16
+ { 952, 5, 1, 5, "VPADDi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #952 = VPADDi32
+ { 953, 5, 1, 5, "VPADDi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #953 = VPADDi8
+ { 954, 5, 1, 3, "VPMAXf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #954 = VPMAXf
+ { 955, 5, 1, 3, "VPMAXs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #955 = VPMAXs16
+ { 956, 5, 1, 3, "VPMAXs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #956 = VPMAXs32
+ { 957, 5, 1, 3, "VPMAXs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #957 = VPMAXs8
+ { 958, 5, 1, 3, "VPMAXu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #958 = VPMAXu16
+ { 959, 5, 1, 3, "VPMAXu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #959 = VPMAXu32
+ { 960, 5, 1, 3, "VPMAXu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #960 = VPMAXu8
+ { 961, 5, 1, 3, "VPMINf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #961 = VPMINf
+ { 962, 5, 1, 3, "VPMINs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #962 = VPMINs16
+ { 963, 5, 1, 3, "VPMINs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #963 = VPMINs32
+ { 964, 5, 1, 3, "VPMINs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #964 = VPMINs8
+ { 965, 5, 1, 3, "VPMINu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #965 = VPMINu16
+ { 966, 5, 1, 3, "VPMINu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #966 = VPMINu32
+ { 967, 5, 1, 3, "VPMINu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #967 = VPMINu8
+ { 968, 4, 1, 39, "VQABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #968 = VQABSv16i8
+ { 969, 4, 1, 38, "VQABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #969 = VQABSv2i32
+ { 970, 4, 1, 38, "VQABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #970 = VQABSv4i16
+ { 971, 4, 1, 39, "VQABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #971 = VQABSv4i32
+ { 972, 4, 1, 39, "VQABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #972 = VQABSv8i16
+ { 973, 4, 1, 38, "VQABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #973 = VQABSv8i8
+ { 974, 5, 1, 4, "VQADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #974 = VQADDsv16i8
+ { 975, 5, 1, 3, "VQADDsv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #975 = VQADDsv1i64
+ { 976, 5, 1, 3, "VQADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #976 = VQADDsv2i32
+ { 977, 5, 1, 4, "VQADDsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #977 = VQADDsv2i64
+ { 978, 5, 1, 3, "VQADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #978 = VQADDsv4i16
+ { 979, 5, 1, 4, "VQADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #979 = VQADDsv4i32
+ { 980, 5, 1, 4, "VQADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #980 = VQADDsv8i16
+ { 981, 5, 1, 3, "VQADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #981 = VQADDsv8i8
+ { 982, 5, 1, 4, "VQADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #982 = VQADDuv16i8
+ { 983, 5, 1, 3, "VQADDuv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #983 = VQADDuv1i64
+ { 984, 5, 1, 3, "VQADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #984 = VQADDuv2i32
+ { 985, 5, 1, 4, "VQADDuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #985 = VQADDuv2i64
+ { 986, 5, 1, 3, "VQADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #986 = VQADDuv4i16
+ { 987, 5, 1, 4, "VQADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #987 = VQADDuv4i32
+ { 988, 5, 1, 4, "VQADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #988 = VQADDuv8i16
+ { 989, 5, 1, 3, "VQADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #989 = VQADDuv8i8
+ { 990, 7, 1, 19, "VQDMLALslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #990 = VQDMLALslv2i32
+ { 991, 7, 1, 17, "VQDMLALslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #991 = VQDMLALslv4i16
+ { 992, 6, 1, 17, "VQDMLALv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #992 = VQDMLALv2i64
+ { 993, 6, 1, 17, "VQDMLALv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #993 = VQDMLALv4i32
+ { 994, 7, 1, 19, "VQDMLSLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #994 = VQDMLSLslv2i32
+ { 995, 7, 1, 17, "VQDMLSLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #995 = VQDMLSLslv4i16
+ { 996, 6, 1, 17, "VQDMLSLv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #996 = VQDMLSLv2i64
+ { 997, 6, 1, 17, "VQDMLSLv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #997 = VQDMLSLv4i32
+ { 998, 6, 1, 31, "VQDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #998 = VQDMULHslv2i32
+ { 999, 6, 1, 29, "VQDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #999 = VQDMULHslv4i16
+ { 1000, 6, 1, 32, "VQDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1000 = VQDMULHslv4i32
+ { 1001, 6, 1, 30, "VQDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1001 = VQDMULHslv8i16
+ { 1002, 5, 1, 31, "VQDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1002 = VQDMULHv2i32
+ { 1003, 5, 1, 29, "VQDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1003 = VQDMULHv4i16
+ { 1004, 5, 1, 32, "VQDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1004 = VQDMULHv4i32
+ { 1005, 5, 1, 30, "VQDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1005 = VQDMULHv8i16
+ { 1006, 6, 1, 29, "VQDMULLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1006 = VQDMULLslv2i32
+ { 1007, 6, 1, 29, "VQDMULLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1007 = VQDMULLslv4i16
+ { 1008, 5, 1, 29, "VQDMULLv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1008 = VQDMULLv2i64
+ { 1009, 5, 1, 29, "VQDMULLv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1009 = VQDMULLv4i32
+ { 1010, 4, 1, 38, "VQMOVNsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1010 = VQMOVNsuv2i32
+ { 1011, 4, 1, 38, "VQMOVNsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1011 = VQMOVNsuv4i16
+ { 1012, 4, 1, 38, "VQMOVNsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1012 = VQMOVNsuv8i8
+ { 1013, 4, 1, 38, "VQMOVNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1013 = VQMOVNsv2i32
+ { 1014, 4, 1, 38, "VQMOVNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1014 = VQMOVNsv4i16
+ { 1015, 4, 1, 38, "VQMOVNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1015 = VQMOVNsv8i8
+ { 1016, 4, 1, 38, "VQMOVNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1016 = VQMOVNuv2i32
+ { 1017, 4, 1, 38, "VQMOVNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1017 = VQMOVNuv4i16
+ { 1018, 4, 1, 38, "VQMOVNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1018 = VQMOVNuv8i8
+ { 1019, 4, 1, 39, "VQNEGv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1019 = VQNEGv16i8
+ { 1020, 4, 1, 38, "VQNEGv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1020 = VQNEGv2i32
+ { 1021, 4, 1, 38, "VQNEGv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1021 = VQNEGv4i16
+ { 1022, 4, 1, 39, "VQNEGv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1022 = VQNEGv4i32
+ { 1023, 4, 1, 39, "VQNEGv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1023 = VQNEGv8i16
+ { 1024, 4, 1, 38, "VQNEGv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1024 = VQNEGv8i8
+ { 1025, 6, 1, 31, "VQRDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1025 = VQRDMULHslv2i32
+ { 1026, 6, 1, 29, "VQRDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1026 = VQRDMULHslv4i16
+ { 1027, 6, 1, 32, "VQRDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1027 = VQRDMULHslv4i32
+ { 1028, 6, 1, 30, "VQRDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1028 = VQRDMULHslv8i16
+ { 1029, 5, 1, 31, "VQRDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1029 = VQRDMULHv2i32
+ { 1030, 5, 1, 29, "VQRDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1030 = VQRDMULHv4i16
+ { 1031, 5, 1, 32, "VQRDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1031 = VQRDMULHv4i32
+ { 1032, 5, 1, 30, "VQRDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1032 = VQRDMULHv8i16
+ { 1033, 5, 1, 43, "VQRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1033 = VQRSHLsv16i8
+ { 1034, 5, 1, 42, "VQRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1034 = VQRSHLsv1i64
+ { 1035, 5, 1, 42, "VQRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1035 = VQRSHLsv2i32
+ { 1036, 5, 1, 43, "VQRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1036 = VQRSHLsv2i64
+ { 1037, 5, 1, 42, "VQRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1037 = VQRSHLsv4i16
+ { 1038, 5, 1, 43, "VQRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1038 = VQRSHLsv4i32
+ { 1039, 5, 1, 43, "VQRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1039 = VQRSHLsv8i16
+ { 1040, 5, 1, 42, "VQRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1040 = VQRSHLsv8i8
+ { 1041, 5, 1, 43, "VQRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1041 = VQRSHLuv16i8
+ { 1042, 5, 1, 42, "VQRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1042 = VQRSHLuv1i64
+ { 1043, 5, 1, 42, "VQRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1043 = VQRSHLuv2i32
+ { 1044, 5, 1, 43, "VQRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1044 = VQRSHLuv2i64
+ { 1045, 5, 1, 42, "VQRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1045 = VQRSHLuv4i16
+ { 1046, 5, 1, 43, "VQRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1046 = VQRSHLuv4i32
+ { 1047, 5, 1, 43, "VQRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1047 = VQRSHLuv8i16
+ { 1048, 5, 1, 42, "VQRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1048 = VQRSHLuv8i8
+ { 1049, 5, 1, 42, "VQRSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1049 = VQRSHRNsv2i32
+ { 1050, 5, 1, 42, "VQRSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1050 = VQRSHRNsv4i16
+ { 1051, 5, 1, 42, "VQRSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1051 = VQRSHRNsv8i8
+ { 1052, 5, 1, 42, "VQRSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1052 = VQRSHRNuv2i32
+ { 1053, 5, 1, 42, "VQRSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1053 = VQRSHRNuv4i16
+ { 1054, 5, 1, 42, "VQRSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1054 = VQRSHRNuv8i8
+ { 1055, 5, 1, 42, "VQRSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1055 = VQRSHRUNv2i32
+ { 1056, 5, 1, 42, "VQRSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1056 = VQRSHRUNv4i16
+ { 1057, 5, 1, 42, "VQRSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1057 = VQRSHRUNv8i8
+ { 1058, 5, 1, 42, "VQSHLsiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1058 = VQSHLsiv16i8
+ { 1059, 5, 1, 42, "VQSHLsiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1059 = VQSHLsiv1i64
+ { 1060, 5, 1, 42, "VQSHLsiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1060 = VQSHLsiv2i32
+ { 1061, 5, 1, 42, "VQSHLsiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1061 = VQSHLsiv2i64
+ { 1062, 5, 1, 42, "VQSHLsiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1062 = VQSHLsiv4i16
+ { 1063, 5, 1, 42, "VQSHLsiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1063 = VQSHLsiv4i32
+ { 1064, 5, 1, 42, "VQSHLsiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1064 = VQSHLsiv8i16
+ { 1065, 5, 1, 42, "VQSHLsiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1065 = VQSHLsiv8i8
+ { 1066, 5, 1, 42, "VQSHLsuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1066 = VQSHLsuv16i8
+ { 1067, 5, 1, 42, "VQSHLsuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1067 = VQSHLsuv1i64
+ { 1068, 5, 1, 42, "VQSHLsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1068 = VQSHLsuv2i32
+ { 1069, 5, 1, 42, "VQSHLsuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1069 = VQSHLsuv2i64
+ { 1070, 5, 1, 42, "VQSHLsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1070 = VQSHLsuv4i16
+ { 1071, 5, 1, 42, "VQSHLsuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1071 = VQSHLsuv4i32
+ { 1072, 5, 1, 42, "VQSHLsuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1072 = VQSHLsuv8i16
+ { 1073, 5, 1, 42, "VQSHLsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1073 = VQSHLsuv8i8
+ { 1074, 5, 1, 43, "VQSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1074 = VQSHLsv16i8
+ { 1075, 5, 1, 42, "VQSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1075 = VQSHLsv1i64
+ { 1076, 5, 1, 42, "VQSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1076 = VQSHLsv2i32
+ { 1077, 5, 1, 43, "VQSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1077 = VQSHLsv2i64
+ { 1078, 5, 1, 42, "VQSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1078 = VQSHLsv4i16
+ { 1079, 5, 1, 43, "VQSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1079 = VQSHLsv4i32
+ { 1080, 5, 1, 43, "VQSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1080 = VQSHLsv8i16
+ { 1081, 5, 1, 42, "VQSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1081 = VQSHLsv8i8
+ { 1082, 5, 1, 42, "VQSHLuiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1082 = VQSHLuiv16i8
+ { 1083, 5, 1, 42, "VQSHLuiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1083 = VQSHLuiv1i64
+ { 1084, 5, 1, 42, "VQSHLuiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1084 = VQSHLuiv2i32
+ { 1085, 5, 1, 42, "VQSHLuiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1085 = VQSHLuiv2i64
+ { 1086, 5, 1, 42, "VQSHLuiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1086 = VQSHLuiv4i16
+ { 1087, 5, 1, 42, "VQSHLuiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1087 = VQSHLuiv4i32
+ { 1088, 5, 1, 42, "VQSHLuiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1088 = VQSHLuiv8i16
+ { 1089, 5, 1, 42, "VQSHLuiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1089 = VQSHLuiv8i8
+ { 1090, 5, 1, 43, "VQSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1090 = VQSHLuv16i8
+ { 1091, 5, 1, 42, "VQSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1091 = VQSHLuv1i64
+ { 1092, 5, 1, 42, "VQSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1092 = VQSHLuv2i32
+ { 1093, 5, 1, 43, "VQSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1093 = VQSHLuv2i64
+ { 1094, 5, 1, 42, "VQSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1094 = VQSHLuv4i16
+ { 1095, 5, 1, 43, "VQSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1095 = VQSHLuv4i32
+ { 1096, 5, 1, 43, "VQSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1096 = VQSHLuv8i16
+ { 1097, 5, 1, 42, "VQSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1097 = VQSHLuv8i8
+ { 1098, 5, 1, 42, "VQSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1098 = VQSHRNsv2i32
+ { 1099, 5, 1, 42, "VQSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1099 = VQSHRNsv4i16
+ { 1100, 5, 1, 42, "VQSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1100 = VQSHRNsv8i8
+ { 1101, 5, 1, 42, "VQSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1101 = VQSHRNuv2i32
+ { 1102, 5, 1, 42, "VQSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1102 = VQSHRNuv4i16
+ { 1103, 5, 1, 42, "VQSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1103 = VQSHRNuv8i8
+ { 1104, 5, 1, 42, "VQSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1104 = VQSHRUNv2i32
+ { 1105, 5, 1, 42, "VQSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1105 = VQSHRUNv4i16
+ { 1106, 5, 1, 42, "VQSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1106 = VQSHRUNv8i8
+ { 1107, 5, 1, 4, "VQSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1107 = VQSUBsv16i8
+ { 1108, 5, 1, 3, "VQSUBsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1108 = VQSUBsv1i64
+ { 1109, 5, 1, 3, "VQSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1109 = VQSUBsv2i32
+ { 1110, 5, 1, 4, "VQSUBsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1110 = VQSUBsv2i64
+ { 1111, 5, 1, 3, "VQSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1111 = VQSUBsv4i16
+ { 1112, 5, 1, 4, "VQSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1112 = VQSUBsv4i32
+ { 1113, 5, 1, 4, "VQSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1113 = VQSUBsv8i16
+ { 1114, 5, 1, 3, "VQSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1114 = VQSUBsv8i8
+ { 1115, 5, 1, 4, "VQSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1115 = VQSUBuv16i8
+ { 1116, 5, 1, 3, "VQSUBuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1116 = VQSUBuv1i64
+ { 1117, 5, 1, 3, "VQSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1117 = VQSUBuv2i32
+ { 1118, 5, 1, 4, "VQSUBuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1118 = VQSUBuv2i64
+ { 1119, 5, 1, 3, "VQSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1119 = VQSUBuv4i16
+ { 1120, 5, 1, 4, "VQSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1120 = VQSUBuv4i32
+ { 1121, 5, 1, 4, "VQSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1121 = VQSUBuv8i16
+ { 1122, 5, 1, 3, "VQSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1122 = VQSUBuv8i8
+ { 1123, 5, 1, 3, "VRADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1123 = VRADDHNv2i32
+ { 1124, 5, 1, 3, "VRADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1124 = VRADDHNv4i16
+ { 1125, 5, 1, 3, "VRADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1125 = VRADDHNv8i8
+ { 1126, 4, 1, 57, "VRECPEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1126 = VRECPEd
+ { 1127, 4, 1, 57, "VRECPEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1127 = VRECPEfd
+ { 1128, 4, 1, 58, "VRECPEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1128 = VRECPEfq
+ { 1129, 4, 1, 58, "VRECPEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1129 = VRECPEq
+ { 1130, 5, 1, 40, "VRECPSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1130 = VRECPSfd
+ { 1131, 5, 1, 41, "VRECPSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1131 = VRECPSfq
+ { 1132, 4, 1, 21, "VREV16d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1132 = VREV16d8
+ { 1133, 4, 1, 21, "VREV16q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1133 = VREV16q8
+ { 1134, 4, 1, 21, "VREV32d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1134 = VREV32d16
+ { 1135, 4, 1, 21, "VREV32d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1135 = VREV32d8
+ { 1136, 4, 1, 21, "VREV32q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1136 = VREV32q16
+ { 1137, 4, 1, 21, "VREV32q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1137 = VREV32q8
+ { 1138, 4, 1, 21, "VREV64d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1138 = VREV64d16
+ { 1139, 4, 1, 21, "VREV64d32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1139 = VREV64d32
+ { 1140, 4, 1, 21, "VREV64d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1140 = VREV64d8
+ { 1141, 4, 1, 21, "VREV64df", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1141 = VREV64df
+ { 1142, 4, 1, 21, "VREV64q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1142 = VREV64q16
+ { 1143, 4, 1, 21, "VREV64q32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1143 = VREV64q32
+ { 1144, 4, 1, 21, "VREV64q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1144 = VREV64q8
+ { 1145, 4, 1, 21, "VREV64qf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1145 = VREV64qf
+ { 1146, 5, 1, 4, "VRHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1146 = VRHADDsv16i8
+ { 1147, 5, 1, 3, "VRHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1147 = VRHADDsv2i32
+ { 1148, 5, 1, 3, "VRHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1148 = VRHADDsv4i16
+ { 1149, 5, 1, 4, "VRHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1149 = VRHADDsv4i32
+ { 1150, 5, 1, 4, "VRHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1150 = VRHADDsv8i16
+ { 1151, 5, 1, 3, "VRHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1151 = VRHADDsv8i8
+ { 1152, 5, 1, 4, "VRHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1152 = VRHADDuv16i8
+ { 1153, 5, 1, 3, "VRHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1153 = VRHADDuv2i32
+ { 1154, 5, 1, 3, "VRHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1154 = VRHADDuv4i16
+ { 1155, 5, 1, 4, "VRHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1155 = VRHADDuv4i32
+ { 1156, 5, 1, 4, "VRHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1156 = VRHADDuv8i16
+ { 1157, 5, 1, 3, "VRHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1157 = VRHADDuv8i8
+ { 1158, 5, 1, 43, "VRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1158 = VRSHLsv16i8
+ { 1159, 5, 1, 42, "VRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1159 = VRSHLsv1i64
+ { 1160, 5, 1, 42, "VRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1160 = VRSHLsv2i32
+ { 1161, 5, 1, 43, "VRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1161 = VRSHLsv2i64
+ { 1162, 5, 1, 42, "VRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1162 = VRSHLsv4i16
+ { 1163, 5, 1, 43, "VRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1163 = VRSHLsv4i32
+ { 1164, 5, 1, 43, "VRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1164 = VRSHLsv8i16
+ { 1165, 5, 1, 42, "VRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1165 = VRSHLsv8i8
+ { 1166, 5, 1, 43, "VRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1166 = VRSHLuv16i8
+ { 1167, 5, 1, 42, "VRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1167 = VRSHLuv1i64
+ { 1168, 5, 1, 42, "VRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1168 = VRSHLuv2i32
+ { 1169, 5, 1, 43, "VRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1169 = VRSHLuv2i64
+ { 1170, 5, 1, 42, "VRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1170 = VRSHLuv4i16
+ { 1171, 5, 1, 43, "VRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1171 = VRSHLuv4i32
+ { 1172, 5, 1, 43, "VRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1172 = VRSHLuv8i16
+ { 1173, 5, 1, 42, "VRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1173 = VRSHLuv8i8
+ { 1174, 5, 1, 42, "VRSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1174 = VRSHRNv2i32
+ { 1175, 5, 1, 42, "VRSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1175 = VRSHRNv4i16
+ { 1176, 5, 1, 42, "VRSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1176 = VRSHRNv8i8
+ { 1177, 5, 1, 42, "VRSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1177 = VRSHRsv16i8
+ { 1178, 5, 1, 42, "VRSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1178 = VRSHRsv1i64
+ { 1179, 5, 1, 42, "VRSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1179 = VRSHRsv2i32
+ { 1180, 5, 1, 42, "VRSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1180 = VRSHRsv2i64
+ { 1181, 5, 1, 42, "VRSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1181 = VRSHRsv4i16
+ { 1182, 5, 1, 42, "VRSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1182 = VRSHRsv4i32
+ { 1183, 5, 1, 42, "VRSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1183 = VRSHRsv8i16
+ { 1184, 5, 1, 42, "VRSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1184 = VRSHRsv8i8
+ { 1185, 5, 1, 42, "VRSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1185 = VRSHRuv16i8
+ { 1186, 5, 1, 42, "VRSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1186 = VRSHRuv1i64
+ { 1187, 5, 1, 42, "VRSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1187 = VRSHRuv2i32
+ { 1188, 5, 1, 42, "VRSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1188 = VRSHRuv2i64
+ { 1189, 5, 1, 42, "VRSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1189 = VRSHRuv4i16
+ { 1190, 5, 1, 42, "VRSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1190 = VRSHRuv4i32
+ { 1191, 5, 1, 42, "VRSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1191 = VRSHRuv8i16
+ { 1192, 5, 1, 42, "VRSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1192 = VRSHRuv8i8
+ { 1193, 4, 1, 57, "VRSQRTEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1193 = VRSQRTEd
+ { 1194, 4, 1, 57, "VRSQRTEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1194 = VRSQRTEfd
+ { 1195, 4, 1, 58, "VRSQRTEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1195 = VRSQRTEfq
+ { 1196, 4, 1, 58, "VRSQRTEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1196 = VRSQRTEq
+ { 1197, 5, 1, 40, "VRSQRTSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1197 = VRSQRTSfd
+ { 1198, 5, 1, 41, "VRSQRTSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1198 = VRSQRTSfq
+ { 1199, 6, 1, 33, "VRSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1199 = VRSRAsv16i8
+ { 1200, 6, 1, 33, "VRSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1200 = VRSRAsv1i64
+ { 1201, 6, 1, 33, "VRSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1201 = VRSRAsv2i32
+ { 1202, 6, 1, 33, "VRSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1202 = VRSRAsv2i64
+ { 1203, 6, 1, 33, "VRSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1203 = VRSRAsv4i16
+ { 1204, 6, 1, 33, "VRSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1204 = VRSRAsv4i32
+ { 1205, 6, 1, 33, "VRSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1205 = VRSRAsv8i16
+ { 1206, 6, 1, 33, "VRSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1206 = VRSRAsv8i8
+ { 1207, 6, 1, 33, "VRSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1207 = VRSRAuv16i8
+ { 1208, 6, 1, 33, "VRSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1208 = VRSRAuv1i64
+ { 1209, 6, 1, 33, "VRSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1209 = VRSRAuv2i32
+ { 1210, 6, 1, 33, "VRSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1210 = VRSRAuv2i64
+ { 1211, 6, 1, 33, "VRSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1211 = VRSRAuv4i16
+ { 1212, 6, 1, 33, "VRSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1212 = VRSRAuv4i32
+ { 1213, 6, 1, 33, "VRSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1213 = VRSRAuv8i16
+ { 1214, 6, 1, 33, "VRSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1214 = VRSRAuv8i8
+ { 1215, 5, 1, 3, "VRSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1215 = VRSUBHNv2i32
+ { 1216, 5, 1, 3, "VRSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1216 = VRSUBHNv4i16
+ { 1217, 5, 1, 3, "VRSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1217 = VRSUBHNv8i8
+ { 1218, 6, 1, 25, "VSETLNi16", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo127 }, // Inst #1218 = VSETLNi16
+ { 1219, 6, 1, 25, "VSETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo127 }, // Inst #1219 = VSETLNi32
+ { 1220, 6, 1, 25, "VSETLNi8", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo127 }, // Inst #1220 = VSETLNi8
+ { 1221, 5, 1, 44, "VSHLLi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1221 = VSHLLi16
+ { 1222, 5, 1, 44, "VSHLLi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1222 = VSHLLi32
+ { 1223, 5, 1, 44, "VSHLLi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1223 = VSHLLi8
+ { 1224, 5, 1, 44, "VSHLLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1224 = VSHLLsv2i64
+ { 1225, 5, 1, 44, "VSHLLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1225 = VSHLLsv4i32
+ { 1226, 5, 1, 44, "VSHLLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1226 = VSHLLsv8i16
+ { 1227, 5, 1, 44, "VSHLLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1227 = VSHLLuv2i64
+ { 1228, 5, 1, 44, "VSHLLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1228 = VSHLLuv4i32
+ { 1229, 5, 1, 44, "VSHLLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1229 = VSHLLuv8i16
+ { 1230, 5, 1, 44, "VSHLiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1230 = VSHLiv16i8
+ { 1231, 5, 1, 44, "VSHLiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1231 = VSHLiv1i64
+ { 1232, 5, 1, 44, "VSHLiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1232 = VSHLiv2i32
+ { 1233, 5, 1, 44, "VSHLiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1233 = VSHLiv2i64
+ { 1234, 5, 1, 44, "VSHLiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1234 = VSHLiv4i16
+ { 1235, 5, 1, 44, "VSHLiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1235 = VSHLiv4i32
+ { 1236, 5, 1, 44, "VSHLiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1236 = VSHLiv8i16
+ { 1237, 5, 1, 44, "VSHLiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1237 = VSHLiv8i8
+ { 1238, 5, 1, 45, "VSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1238 = VSHLsv16i8
+ { 1239, 5, 1, 44, "VSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1239 = VSHLsv1i64
+ { 1240, 5, 1, 44, "VSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1240 = VSHLsv2i32
+ { 1241, 5, 1, 45, "VSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1241 = VSHLsv2i64
+ { 1242, 5, 1, 44, "VSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1242 = VSHLsv4i16
+ { 1243, 5, 1, 45, "VSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1243 = VSHLsv4i32
+ { 1244, 5, 1, 45, "VSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1244 = VSHLsv8i16
+ { 1245, 5, 1, 44, "VSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1245 = VSHLsv8i8
+ { 1246, 5, 1, 45, "VSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1246 = VSHLuv16i8
+ { 1247, 5, 1, 44, "VSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1247 = VSHLuv1i64
+ { 1248, 5, 1, 44, "VSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1248 = VSHLuv2i32
+ { 1249, 5, 1, 45, "VSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1249 = VSHLuv2i64
+ { 1250, 5, 1, 44, "VSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1250 = VSHLuv4i16
+ { 1251, 5, 1, 45, "VSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1251 = VSHLuv4i32
+ { 1252, 5, 1, 45, "VSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1252 = VSHLuv8i16
+ { 1253, 5, 1, 44, "VSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1253 = VSHLuv8i8
+ { 1254, 5, 1, 44, "VSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1254 = VSHRNv2i32
+ { 1255, 5, 1, 44, "VSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1255 = VSHRNv4i16
+ { 1256, 5, 1, 44, "VSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1256 = VSHRNv8i8
+ { 1257, 5, 1, 44, "VSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1257 = VSHRsv16i8
+ { 1258, 5, 1, 44, "VSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1258 = VSHRsv1i64
+ { 1259, 5, 1, 44, "VSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1259 = VSHRsv2i32
+ { 1260, 5, 1, 44, "VSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1260 = VSHRsv2i64
+ { 1261, 5, 1, 44, "VSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1261 = VSHRsv4i16
+ { 1262, 5, 1, 44, "VSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1262 = VSHRsv4i32
+ { 1263, 5, 1, 44, "VSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1263 = VSHRsv8i16
+ { 1264, 5, 1, 44, "VSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1264 = VSHRsv8i8
+ { 1265, 5, 1, 44, "VSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1265 = VSHRuv16i8
+ { 1266, 5, 1, 44, "VSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1266 = VSHRuv1i64
+ { 1267, 5, 1, 44, "VSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1267 = VSHRuv2i32
+ { 1268, 5, 1, 44, "VSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1268 = VSHRuv2i64
+ { 1269, 5, 1, 44, "VSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1269 = VSHRuv4i16
+ { 1270, 5, 1, 44, "VSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1270 = VSHRuv4i32
+ { 1271, 5, 1, 44, "VSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1271 = VSHRuv8i16
+ { 1272, 5, 1, 44, "VSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1272 = VSHRuv8i8
+ { 1273, 5, 1, 67, "VSHTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1273 = VSHTOD
+ { 1274, 5, 1, 68, "VSHTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1274 = VSHTOS
+ { 1275, 4, 1, 67, "VSITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #1275 = VSITOD
+ { 1276, 4, 1, 68, "VSITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1276 = VSITOS
+ { 1277, 6, 1, 45, "VSLIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1277 = VSLIv16i8
+ { 1278, 6, 1, 44, "VSLIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1278 = VSLIv1i64
+ { 1279, 6, 1, 44, "VSLIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1279 = VSLIv2i32
+ { 1280, 6, 1, 45, "VSLIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1280 = VSLIv2i64
+ { 1281, 6, 1, 44, "VSLIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1281 = VSLIv4i16
+ { 1282, 6, 1, 45, "VSLIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1282 = VSLIv4i32
+ { 1283, 6, 1, 45, "VSLIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1283 = VSLIv8i16
+ { 1284, 6, 1, 44, "VSLIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1284 = VSLIv8i8
+ { 1285, 5, 1, 67, "VSLTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1285 = VSLTOD
+ { 1286, 5, 1, 68, "VSLTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1286 = VSLTOS
+ { 1287, 4, 1, 81, "VSQRTD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1287 = VSQRTD
+ { 1288, 4, 1, 80, "VSQRTS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1288 = VSQRTS
+ { 1289, 6, 1, 33, "VSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1289 = VSRAsv16i8
+ { 1290, 6, 1, 33, "VSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1290 = VSRAsv1i64
+ { 1291, 6, 1, 33, "VSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1291 = VSRAsv2i32
+ { 1292, 6, 1, 33, "VSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1292 = VSRAsv2i64
+ { 1293, 6, 1, 33, "VSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1293 = VSRAsv4i16
+ { 1294, 6, 1, 33, "VSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1294 = VSRAsv4i32
+ { 1295, 6, 1, 33, "VSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1295 = VSRAsv8i16
+ { 1296, 6, 1, 33, "VSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1296 = VSRAsv8i8
+ { 1297, 6, 1, 33, "VSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1297 = VSRAuv16i8
+ { 1298, 6, 1, 33, "VSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1298 = VSRAuv1i64
+ { 1299, 6, 1, 33, "VSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1299 = VSRAuv2i32
+ { 1300, 6, 1, 33, "VSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1300 = VSRAuv2i64
+ { 1301, 6, 1, 33, "VSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1301 = VSRAuv4i16
+ { 1302, 6, 1, 33, "VSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1302 = VSRAuv4i32
+ { 1303, 6, 1, 33, "VSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1303 = VSRAuv8i16
+ { 1304, 6, 1, 33, "VSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1304 = VSRAuv8i8
+ { 1305, 6, 1, 45, "VSRIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1305 = VSRIv16i8
+ { 1306, 6, 1, 44, "VSRIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1306 = VSRIv1i64
+ { 1307, 6, 1, 44, "VSRIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1307 = VSRIv2i32
+ { 1308, 6, 1, 45, "VSRIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1308 = VSRIv2i64
+ { 1309, 6, 1, 44, "VSRIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1309 = VSRIv4i16
+ { 1310, 6, 1, 45, "VSRIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1310 = VSRIv4i32
+ { 1311, 6, 1, 45, "VSRIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1311 = VSRIv8i16
+ { 1312, 6, 1, 44, "VSRIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1312 = VSRIv8i8
+ { 1313, 7, 0, 46, "VST1d16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1313 = VST1d16
+ { 1314, 10, 0, 46, "VST1d16Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1314 = VST1d16Q
+ { 1315, 9, 0, 46, "VST1d16T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1315 = VST1d16T
+ { 1316, 7, 0, 46, "VST1d32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1316 = VST1d32
+ { 1317, 10, 0, 46, "VST1d32Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1317 = VST1d32Q
+ { 1318, 9, 0, 46, "VST1d32T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1318 = VST1d32T
+ { 1319, 7, 0, 46, "VST1d64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1319 = VST1d64
+ { 1320, 7, 0, 46, "VST1d8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1320 = VST1d8
+ { 1321, 10, 0, 46, "VST1d8Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1321 = VST1d8Q
+ { 1322, 9, 0, 46, "VST1d8T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1322 = VST1d8T
+ { 1323, 7, 0, 46, "VST1df", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1323 = VST1df
+ { 1324, 7, 0, 46, "VST1q16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1324 = VST1q16
+ { 1325, 7, 0, 46, "VST1q32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1325 = VST1q32
+ { 1326, 7, 0, 46, "VST1q64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1326 = VST1q64
+ { 1327, 7, 0, 46, "VST1q8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1327 = VST1q8
+ { 1328, 7, 0, 46, "VST1qf", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1328 = VST1qf
+ { 1329, 9, 0, 46, "VST2LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1329 = VST2LNd16
+ { 1330, 9, 0, 46, "VST2LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1330 = VST2LNd32
+ { 1331, 9, 0, 46, "VST2LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1331 = VST2LNd8
+ { 1332, 9, 0, 46, "VST2LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1332 = VST2LNq16a
+ { 1333, 9, 0, 46, "VST2LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1333 = VST2LNq16b
+ { 1334, 9, 0, 46, "VST2LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1334 = VST2LNq32a
+ { 1335, 9, 0, 46, "VST2LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1335 = VST2LNq32b
+ { 1336, 8, 0, 46, "VST2d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1336 = VST2d16
+ { 1337, 8, 0, 46, "VST2d16D", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1337 = VST2d16D
+ { 1338, 8, 0, 46, "VST2d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1338 = VST2d32
+ { 1339, 8, 0, 46, "VST2d32D", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1339 = VST2d32D
+ { 1340, 8, 0, 46, "VST2d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1340 = VST2d64
+ { 1341, 8, 0, 46, "VST2d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1341 = VST2d8
+ { 1342, 8, 0, 46, "VST2d8D", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1342 = VST2d8D
+ { 1343, 10, 0, 46, "VST2q16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1343 = VST2q16
+ { 1344, 10, 0, 46, "VST2q32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1344 = VST2q32
+ { 1345, 10, 0, 46, "VST2q8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1345 = VST2q8
+ { 1346, 10, 0, 46, "VST3LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1346 = VST3LNd16
+ { 1347, 10, 0, 46, "VST3LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1347 = VST3LNd32
+ { 1348, 10, 0, 46, "VST3LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1348 = VST3LNd8
+ { 1349, 10, 0, 46, "VST3LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1349 = VST3LNq16a
+ { 1350, 10, 0, 46, "VST3LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1350 = VST3LNq16b
+ { 1351, 10, 0, 46, "VST3LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1351 = VST3LNq32a
+ { 1352, 10, 0, 46, "VST3LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1352 = VST3LNq32b
+ { 1353, 9, 0, 46, "VST3d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1353 = VST3d16
+ { 1354, 9, 0, 46, "VST3d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1354 = VST3d32
+ { 1355, 9, 0, 46, "VST3d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1355 = VST3d64
+ { 1356, 9, 0, 46, "VST3d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1356 = VST3d8
+ { 1357, 10, 1, 46, "VST3q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1357 = VST3q16a
+ { 1358, 10, 1, 46, "VST3q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1358 = VST3q16b
+ { 1359, 10, 1, 46, "VST3q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1359 = VST3q32a
+ { 1360, 10, 1, 46, "VST3q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1360 = VST3q32b
+ { 1361, 10, 1, 46, "VST3q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1361 = VST3q8a
+ { 1362, 10, 1, 46, "VST3q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1362 = VST3q8b
+ { 1363, 11, 0, 46, "VST4LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1363 = VST4LNd16
+ { 1364, 11, 0, 46, "VST4LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1364 = VST4LNd32
+ { 1365, 11, 0, 46, "VST4LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1365 = VST4LNd8
+ { 1366, 11, 0, 46, "VST4LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1366 = VST4LNq16a
+ { 1367, 11, 0, 46, "VST4LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1367 = VST4LNq16b
+ { 1368, 11, 0, 46, "VST4LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1368 = VST4LNq32a
+ { 1369, 11, 0, 46, "VST4LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1369 = VST4LNq32b
+ { 1370, 10, 0, 46, "VST4d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1370 = VST4d16
+ { 1371, 10, 0, 46, "VST4d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1371 = VST4d32
+ { 1372, 10, 0, 46, "VST4d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1372 = VST4d64
+ { 1373, 10, 0, 46, "VST4d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1373 = VST4d8
+ { 1374, 11, 1, 46, "VST4q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1374 = VST4q16a
+ { 1375, 11, 1, 46, "VST4q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1375 = VST4q16b
+ { 1376, 11, 1, 46, "VST4q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1376 = VST4q32a
+ { 1377, 11, 1, 46, "VST4q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1377 = VST4q32b
+ { 1378, 11, 1, 46, "VST4q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1378 = VST4q8a
+ { 1379, 11, 1, 46, "VST4q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1379 = VST4q8b
+ { 1380, 5, 0, 85, "VSTMD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo35 }, // Inst #1380 = VSTMD
+ { 1381, 5, 0, 85, "VSTMS", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo35 }, // Inst #1381 = VSTMS
+ { 1382, 5, 0, 84, "VSTRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #1382 = VSTRD
+ { 1383, 5, 0, 85, "VSTRQ", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #1383 = VSTRQ
+ { 1384, 5, 0, 83, "VSTRS", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #1384 = VSTRS
+ { 1385, 5, 1, 62, "VSUBD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1385 = VSUBD
+ { 1386, 5, 1, 3, "VSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1386 = VSUBHNv2i32
+ { 1387, 5, 1, 3, "VSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1387 = VSUBHNv4i16
+ { 1388, 5, 1, 3, "VSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1388 = VSUBHNv8i8
+ { 1389, 5, 1, 44, "VSUBLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1389 = VSUBLsv2i64
+ { 1390, 5, 1, 44, "VSUBLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1390 = VSUBLsv4i32
+ { 1391, 5, 1, 44, "VSUBLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1391 = VSUBLsv8i16
+ { 1392, 5, 1, 44, "VSUBLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1392 = VSUBLuv2i64
+ { 1393, 5, 1, 44, "VSUBLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1393 = VSUBLuv4i32
+ { 1394, 5, 1, 44, "VSUBLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1394 = VSUBLuv8i16
+ { 1395, 5, 1, 61, "VSUBS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1395 = VSUBS
+ { 1396, 5, 1, 47, "VSUBWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1396 = VSUBWsv2i64
+ { 1397, 5, 1, 47, "VSUBWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1397 = VSUBWsv4i32
+ { 1398, 5, 1, 47, "VSUBWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1398 = VSUBWsv8i16
+ { 1399, 5, 1, 47, "VSUBWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1399 = VSUBWuv2i64
+ { 1400, 5, 1, 47, "VSUBWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1400 = VSUBWuv4i32
+ { 1401, 5, 1, 47, "VSUBWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1401 = VSUBWuv8i16
+ { 1402, 5, 1, 1, "VSUBfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1402 = VSUBfd
+ { 1403, 5, 1, 1, "VSUBfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #1403 = VSUBfd_sfp
+ { 1404, 5, 1, 2, "VSUBfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1404 = VSUBfq
+ { 1405, 5, 1, 48, "VSUBv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1405 = VSUBv16i8
+ { 1406, 5, 1, 47, "VSUBv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1406 = VSUBv1i64
+ { 1407, 5, 1, 47, "VSUBv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1407 = VSUBv2i32
+ { 1408, 5, 1, 48, "VSUBv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1408 = VSUBv2i64
+ { 1409, 5, 1, 47, "VSUBv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1409 = VSUBv4i16
+ { 1410, 5, 1, 48, "VSUBv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1410 = VSUBv4i32
+ { 1411, 5, 1, 48, "VSUBv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1411 = VSUBv8i16
+ { 1412, 5, 1, 47, "VSUBv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1412 = VSUBv8i8
+ { 1413, 4, 1, 128, "VSWPd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1413 = VSWPd
+ { 1414, 4, 1, 128, "VSWPq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1414 = VSWPq
+ { 1415, 5, 1, 49, "VTBL1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1415 = VTBL1
+ { 1416, 6, 1, 50, "VTBL2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo140 }, // Inst #1416 = VTBL2
+ { 1417, 7, 1, 51, "VTBL3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo141 }, // Inst #1417 = VTBL3
+ { 1418, 8, 1, 52, "VTBL4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo142 }, // Inst #1418 = VTBL4
+ { 1419, 6, 1, 53, "VTBX1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1419 = VTBX1
+ { 1420, 7, 1, 54, "VTBX2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo143 }, // Inst #1420 = VTBX2
+ { 1421, 8, 1, 55, "VTBX3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo144 }, // Inst #1421 = VTBX3
+ { 1422, 9, 1, 56, "VTBX4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo145 }, // Inst #1422 = VTBX4
+ { 1423, 5, 1, 65, "VTOSHD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1423 = VTOSHD
+ { 1424, 5, 1, 70, "VTOSHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1424 = VTOSHS
+ { 1425, 4, 1, 65, "VTOSIRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #1425 = VTOSIRD
+ { 1426, 4, 1, 70, "VTOSIRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1426 = VTOSIRS
+ { 1427, 4, 1, 65, "VTOSIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #1427 = VTOSIZD
+ { 1428, 4, 1, 70, "VTOSIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1428 = VTOSIZS
+ { 1429, 5, 1, 65, "VTOSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1429 = VTOSLD
+ { 1430, 5, 1, 70, "VTOSLS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1430 = VTOSLS
+ { 1431, 5, 1, 65, "VTOUHD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1431 = VTOUHD
+ { 1432, 5, 1, 70, "VTOUHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1432 = VTOUHS
+ { 1433, 4, 1, 65, "VTOUIRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #1433 = VTOUIRD
+ { 1434, 4, 1, 70, "VTOUIRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1434 = VTOUIRS
+ { 1435, 4, 1, 65, "VTOUIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #1435 = VTOUIZD
+ { 1436, 4, 1, 70, "VTOUIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1436 = VTOUIZS
+ { 1437, 5, 1, 65, "VTOULD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1437 = VTOULD
+ { 1438, 5, 1, 70, "VTOULS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1438 = VTOULS
+ { 1439, 6, 2, 35, "VTRNd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1439 = VTRNd16
+ { 1440, 6, 2, 35, "VTRNd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1440 = VTRNd32
+ { 1441, 6, 2, 35, "VTRNd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1441 = VTRNd8
+ { 1442, 6, 2, 36, "VTRNq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1442 = VTRNq16
+ { 1443, 6, 2, 36, "VTRNq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1443 = VTRNq32
+ { 1444, 6, 2, 36, "VTRNq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1444 = VTRNq8
+ { 1445, 5, 1, 4, "VTSTv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1445 = VTSTv16i8
+ { 1446, 5, 1, 3, "VTSTv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1446 = VTSTv2i32
+ { 1447, 5, 1, 3, "VTSTv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1447 = VTSTv4i16
+ { 1448, 5, 1, 4, "VTSTv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1448 = VTSTv4i32
+ { 1449, 5, 1, 4, "VTSTv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1449 = VTSTv8i16
+ { 1450, 5, 1, 3, "VTSTv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1450 = VTSTv8i8
+ { 1451, 5, 1, 67, "VUHTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1451 = VUHTOD
+ { 1452, 5, 1, 68, "VUHTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1452 = VUHTOS
+ { 1453, 4, 1, 67, "VUITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #1453 = VUITOD
+ { 1454, 4, 1, 68, "VUITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1454 = VUITOS
+ { 1455, 5, 1, 67, "VULTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1455 = VULTOD
+ { 1456, 5, 1, 68, "VULTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1456 = VULTOS
+ { 1457, 6, 2, 35, "VUZPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1457 = VUZPd16
+ { 1458, 6, 2, 35, "VUZPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1458 = VUZPd32
+ { 1459, 6, 2, 35, "VUZPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1459 = VUZPd8
+ { 1460, 6, 2, 37, "VUZPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1460 = VUZPq16
+ { 1461, 6, 2, 37, "VUZPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1461 = VUZPq32
+ { 1462, 6, 2, 37, "VUZPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1462 = VUZPq8
+ { 1463, 6, 2, 35, "VZIPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1463 = VZIPd16
+ { 1464, 6, 2, 35, "VZIPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1464 = VZIPd32
+ { 1465, 6, 2, 35, "VZIPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1465 = VZIPd8
+ { 1466, 6, 2, 37, "VZIPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1466 = VZIPq16
+ { 1467, 6, 2, 37, "VZIPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1467 = VZIPq32
+ { 1468, 6, 2, 37, "VZIPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1468 = VZIPq8
+ { 1469, 2, 0, 128, "WFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1469 = WFE
+ { 1470, 2, 0, 128, "WFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1470 = WFI
+ { 1471, 2, 0, 128, "YIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1471 = YIELD
+ { 1472, 6, 1, 88, "t2ADCSri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1472 = t2ADCSri
+ { 1473, 6, 1, 89, "t2ADCSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1473 = t2ADCSrr
+ { 1474, 7, 1, 90, "t2ADCSrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #1474 = t2ADCSrs
+ { 1475, 6, 1, 88, "t2ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1475 = t2ADCri
+ { 1476, 6, 1, 89, "t2ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1476 = t2ADCrr
+ { 1477, 7, 1, 90, "t2ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo48 }, // Inst #1477 = t2ADCrs
+ { 1478, 5, 1, 88, "t2ADDSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1478 = t2ADDSri
+ { 1479, 5, 1, 89, "t2ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1479 = t2ADDSrr
+ { 1480, 6, 1, 90, "t2ADDSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #1480 = t2ADDSrs
+ { 1481, 6, 1, 88, "t2ADDrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1481 = t2ADDrSPi
+ { 1482, 5, 1, 88, "t2ADDrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1482 = t2ADDrSPi12
+ { 1483, 7, 1, 90, "t2ADDrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1483 = t2ADDrSPs
+ { 1484, 6, 1, 88, "t2ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1484 = t2ADDri
+ { 1485, 6, 1, 88, "t2ADDri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1485 = t2ADDri12
+ { 1486, 6, 1, 89, "t2ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1486 = t2ADDrr
+ { 1487, 7, 1, 90, "t2ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1487 = t2ADDrs
+ { 1488, 6, 1, 88, "t2ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1488 = t2ANDri
+ { 1489, 6, 1, 89, "t2ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1489 = t2ANDrr
+ { 1490, 7, 1, 90, "t2ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1490 = t2ANDrs
+ { 1491, 6, 1, 113, "t2ASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1491 = t2ASRri
+ { 1492, 6, 1, 114, "t2ASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1492 = t2ASRrr
+ { 1493, 1, 0, 0, "t2B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1493 = t2B
+ { 1494, 5, 1, 126, "t2BFC", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1494 = t2BFC
+ { 1495, 6, 1, 88, "t2BFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #1495 = t2BFI
+ { 1496, 6, 1, 88, "t2BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1496 = t2BICri
+ { 1497, 6, 1, 89, "t2BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1497 = t2BICrr
+ { 1498, 7, 1, 90, "t2BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1498 = t2BICrs
+ { 1499, 4, 0, 0, "t2BR_JT", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #1499 = t2BR_JT
+ { 1500, 3, 0, 128, "t2BXJ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1500 = t2BXJ
+ { 1501, 3, 0, 0, "t2Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1501 = t2Bcc
+ { 1502, 2, 0, 128, "t2CLREX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1502 = t2CLREX
+ { 1503, 4, 1, 125, "t2CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1503 = t2CLZ
+ { 1504, 4, 0, 97, "t2CMNzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1504 = t2CMNzri
+ { 1505, 4, 0, 98, "t2CMNzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1505 = t2CMNzrr
+ { 1506, 5, 0, 99, "t2CMNzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1506 = t2CMNzrs
+ { 1507, 4, 0, 97, "t2CMPri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1507 = t2CMPri
+ { 1508, 4, 0, 98, "t2CMPrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1508 = t2CMPrr
+ { 1509, 5, 0, 99, "t2CMPrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1509 = t2CMPrs
+ { 1510, 4, 0, 97, "t2CMPzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1510 = t2CMPzri
+ { 1511, 4, 0, 98, "t2CMPzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1511 = t2CMPzrr
+ { 1512, 5, 0, 99, "t2CMPzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1512 = t2CMPzrs
+ { 1513, 1, 0, 128, "t2CPS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1513 = t2CPS
+ { 1514, 3, 0, 128, "t2DBG", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1514 = t2DBG
+ { 1515, 2, 0, 128, "t2DMBish", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1515 = t2DMBish
+ { 1516, 2, 0, 128, "t2DMBishst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1516 = t2DMBishst
+ { 1517, 2, 0, 128, "t2DMBnsh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1517 = t2DMBnsh
+ { 1518, 2, 0, 128, "t2DMBnshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1518 = t2DMBnshst
+ { 1519, 2, 0, 128, "t2DMBosh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1519 = t2DMBosh
+ { 1520, 2, 0, 128, "t2DMBoshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1520 = t2DMBoshst
+ { 1521, 2, 0, 128, "t2DMBst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1521 = t2DMBst
+ { 1522, 2, 0, 128, "t2DSBish", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1522 = t2DSBish
+ { 1523, 2, 0, 128, "t2DSBishst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1523 = t2DSBishst
+ { 1524, 2, 0, 128, "t2DSBnsh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1524 = t2DSBnsh
+ { 1525, 2, 0, 128, "t2DSBnshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1525 = t2DSBnshst
+ { 1526, 2, 0, 128, "t2DSBosh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1526 = t2DSBosh
+ { 1527, 2, 0, 128, "t2DSBoshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1527 = t2DSBoshst
+ { 1528, 2, 0, 128, "t2DSBst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1528 = t2DSBst
+ { 1529, 6, 1, 88, "t2EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1529 = t2EORri
+ { 1530, 6, 1, 89, "t2EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1530 = t2EORrr
+ { 1531, 7, 1, 90, "t2EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1531 = t2EORrs
+ { 1532, 2, 0, 128, "t2ISBsy", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1532 = t2ISBsy
+ { 1533, 2, 0, 92, "t2IT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1533 = t2IT
+ { 1534, 0, 0, 128, "t2Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1534 = t2Int_MemBarrierV7
+ { 1535, 0, 0, 128, "t2Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1535 = t2Int_SyncBarrierV7
+ { 1536, 2, 0, 128, "t2Int_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList6, Barriers3, OperandInfo149 }, // Inst #1536 = t2Int_eh_sjlj_setjmp
+ { 1537, 5, 0, 103, "t2LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1537 = t2LDM
+ { 1538, 5, 0, 0, "t2LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1538 = t2LDM_RET
+ { 1539, 5, 1, 101, "t2LDRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1539 = t2LDRBT
+ { 1540, 6, 2, 102, "t2LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1540 = t2LDRB_POST
+ { 1541, 6, 2, 102, "t2LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1541 = t2LDRB_PRE
+ { 1542, 5, 1, 101, "t2LDRBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1542 = t2LDRBi12
+ { 1543, 5, 1, 101, "t2LDRBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1543 = t2LDRBi8
+ { 1544, 4, 1, 101, "t2LDRBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1544 = t2LDRBpci
+ { 1545, 6, 1, 104, "t2LDRBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1545 = t2LDRBs
+ { 1546, 6, 2, 101, "t2LDRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1546 = t2LDRDi8
+ { 1547, 5, 2, 101, "t2LDRDpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1547 = t2LDRDpci
+ { 1548, 4, 1, 128, "t2LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1548 = t2LDREX
+ { 1549, 4, 1, 128, "t2LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1549 = t2LDREXB
+ { 1550, 5, 2, 128, "t2LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1550 = t2LDREXD
+ { 1551, 4, 1, 128, "t2LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1551 = t2LDREXH
+ { 1552, 5, 1, 101, "t2LDRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1552 = t2LDRHT
+ { 1553, 6, 2, 102, "t2LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1553 = t2LDRH_POST
+ { 1554, 6, 2, 102, "t2LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1554 = t2LDRH_PRE
+ { 1555, 5, 1, 101, "t2LDRHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1555 = t2LDRHi12
+ { 1556, 5, 1, 101, "t2LDRHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1556 = t2LDRHi8
+ { 1557, 4, 1, 101, "t2LDRHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1557 = t2LDRHpci
+ { 1558, 6, 1, 104, "t2LDRHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1558 = t2LDRHs
+ { 1559, 5, 1, 101, "t2LDRSBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1559 = t2LDRSBT
+ { 1560, 6, 2, 102, "t2LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1560 = t2LDRSB_POST
+ { 1561, 6, 2, 102, "t2LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1561 = t2LDRSB_PRE
+ { 1562, 5, 1, 101, "t2LDRSBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1562 = t2LDRSBi12
+ { 1563, 5, 1, 101, "t2LDRSBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1563 = t2LDRSBi8
+ { 1564, 4, 1, 101, "t2LDRSBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1564 = t2LDRSBpci
+ { 1565, 6, 1, 104, "t2LDRSBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1565 = t2LDRSBs
+ { 1566, 5, 1, 101, "t2LDRSHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1566 = t2LDRSHT
+ { 1567, 6, 2, 102, "t2LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1567 = t2LDRSH_POST
+ { 1568, 6, 2, 102, "t2LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1568 = t2LDRSH_PRE
+ { 1569, 5, 1, 101, "t2LDRSHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1569 = t2LDRSHi12
+ { 1570, 5, 1, 101, "t2LDRSHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1570 = t2LDRSHi8
+ { 1571, 4, 1, 101, "t2LDRSHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1571 = t2LDRSHpci
+ { 1572, 6, 1, 104, "t2LDRSHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1572 = t2LDRSHs
+ { 1573, 5, 1, 101, "t2LDRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1573 = t2LDRT
+ { 1574, 6, 2, 102, "t2LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1574 = t2LDR_POST
+ { 1575, 6, 2, 102, "t2LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1575 = t2LDR_PRE
+ { 1576, 5, 1, 101, "t2LDRi12", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1576 = t2LDRi12
+ { 1577, 5, 1, 101, "t2LDRi8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1577 = t2LDRi8
+ { 1578, 4, 1, 101, "t2LDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1578 = t2LDRpci
+ { 1579, 3, 1, 128, "t2LDRpci_pic", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1579 = t2LDRpci_pic
+ { 1580, 6, 1, 104, "t2LDRs", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1580 = t2LDRs
+ { 1581, 4, 1, 88, "t2LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1581 = t2LEApcrel
+ { 1582, 5, 1, 88, "t2LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #1582 = t2LEApcrelJT
+ { 1583, 6, 1, 113, "t2LSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1583 = t2LSLri
+ { 1584, 6, 1, 114, "t2LSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1584 = t2LSLrr
+ { 1585, 6, 1, 113, "t2LSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1585 = t2LSRri
+ { 1586, 6, 1, 114, "t2LSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1586 = t2LSRrr
+ { 1587, 6, 1, 109, "t2MLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1587 = t2MLA
+ { 1588, 6, 1, 109, "t2MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1588 = t2MLS
+ { 1589, 6, 1, 95, "t2MOVCCasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1589 = t2MOVCCasr
+ { 1590, 5, 1, 93, "t2MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1590 = t2MOVCCi
+ { 1591, 6, 1, 95, "t2MOVCClsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1591 = t2MOVCClsl
+ { 1592, 6, 1, 95, "t2MOVCClsr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1592 = t2MOVCClsr
+ { 1593, 5, 1, 94, "t2MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 }, // Inst #1593 = t2MOVCCr
+ { 1594, 6, 1, 95, "t2MOVCCror", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1594 = t2MOVCCror
+ { 1595, 5, 1, 111, "t2MOVTi16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1595 = t2MOVTi16
+ { 1596, 5, 1, 111, "t2MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #1596 = t2MOVi
+ { 1597, 4, 1, 111, "t2MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1597 = t2MOVi16
+ { 1598, 4, 1, 111, "t2MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(2<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1598 = t2MOVi32imm
+ { 1599, 5, 1, 112, "t2MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #1599 = t2MOVr
+ { 1600, 5, 1, 113, "t2MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo47 }, // Inst #1600 = t2MOVrx
+ { 1601, 2, 1, 113, "t2MOVsra_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo32 }, // Inst #1601 = t2MOVsra_flag
+ { 1602, 2, 1, 113, "t2MOVsrl_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo32 }, // Inst #1602 = t2MOVsrl_flag
+ { 1603, 3, 1, 128, "t2MRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1603 = t2MRS
+ { 1604, 3, 1, 128, "t2MRSsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1604 = t2MRSsys
+ { 1605, 3, 0, 128, "t2MSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1605 = t2MSR
+ { 1606, 3, 0, 128, "t2MSRsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1606 = t2MSRsys
+ { 1607, 5, 1, 116, "t2MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1607 = t2MUL
+ { 1608, 5, 1, 111, "t2MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #1608 = t2MVNi
+ { 1609, 4, 1, 112, "t2MVNr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1609 = t2MVNr
+ { 1610, 5, 1, 113, "t2MVNs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1610 = t2MVNs
+ { 1611, 2, 0, 128, "t2NOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1611 = t2NOP
+ { 1612, 6, 1, 88, "t2ORNri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1612 = t2ORNri
+ { 1613, 6, 1, 89, "t2ORNrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1613 = t2ORNrr
+ { 1614, 7, 1, 90, "t2ORNrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1614 = t2ORNrs
+ { 1615, 6, 1, 88, "t2ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1615 = t2ORRri
+ { 1616, 6, 1, 89, "t2ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1616 = t2ORRrr
+ { 1617, 7, 1, 90, "t2ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1617 = t2ORRrs
+ { 1618, 6, 1, 90, "t2PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1618 = t2PKHBT
+ { 1619, 6, 1, 90, "t2PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1619 = t2PKHTB
+ { 1620, 4, 0, 101, "t2PLDWi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1620 = t2PLDWi12
+ { 1621, 4, 0, 101, "t2PLDWi8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1621 = t2PLDWi8
+ { 1622, 4, 0, 101, "t2PLDWpci", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1622 = t2PLDWpci
+ { 1623, 4, 0, 101, "t2PLDWr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1623 = t2PLDWr
+ { 1624, 5, 0, 101, "t2PLDWs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1624 = t2PLDWs
+ { 1625, 4, 0, 101, "t2PLDi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1625 = t2PLDi12
+ { 1626, 4, 0, 101, "t2PLDi8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1626 = t2PLDi8
+ { 1627, 4, 0, 101, "t2PLDpci", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1627 = t2PLDpci
+ { 1628, 4, 0, 101, "t2PLDr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1628 = t2PLDr
+ { 1629, 5, 0, 101, "t2PLDs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1629 = t2PLDs
+ { 1630, 4, 0, 101, "t2PLIi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1630 = t2PLIi12
+ { 1631, 4, 0, 101, "t2PLIi8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1631 = t2PLIi8
+ { 1632, 4, 0, 101, "t2PLIpci", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1632 = t2PLIpci
+ { 1633, 4, 0, 101, "t2PLIr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1633 = t2PLIr
+ { 1634, 5, 0, 101, "t2PLIs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1634 = t2PLIs
+ { 1635, 5, 1, 128, "t2QADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1635 = t2QADD
+ { 1636, 5, 1, 128, "t2QADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1636 = t2QADD16
+ { 1637, 5, 1, 128, "t2QADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1637 = t2QADD8
+ { 1638, 5, 1, 128, "t2QASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1638 = t2QASX
+ { 1639, 5, 1, 128, "t2QDADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1639 = t2QDADD
+ { 1640, 5, 1, 128, "t2QDSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1640 = t2QDSUB
+ { 1641, 5, 1, 128, "t2QSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1641 = t2QSAX
+ { 1642, 5, 1, 128, "t2QSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1642 = t2QSUB
+ { 1643, 5, 1, 128, "t2QSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1643 = t2QSUB16
+ { 1644, 5, 1, 128, "t2QSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1644 = t2QSUB8
+ { 1645, 4, 1, 125, "t2RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1645 = t2RBIT
+ { 1646, 4, 1, 125, "t2REV", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1646 = t2REV
+ { 1647, 4, 1, 125, "t2REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1647 = t2REV16
+ { 1648, 4, 1, 125, "t2REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1648 = t2REVSH
+ { 1649, 3, 0, 128, "t2RFEDB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1649 = t2RFEDB
+ { 1650, 3, 0, 128, "t2RFEDBW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1650 = t2RFEDBW
+ { 1651, 3, 0, 128, "t2RFEIA", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1651 = t2RFEIA
+ { 1652, 3, 0, 128, "t2RFEIAW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1652 = t2RFEIAW
+ { 1653, 6, 1, 113, "t2RORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1653 = t2RORri
+ { 1654, 6, 1, 114, "t2RORrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1654 = t2RORrr
+ { 1655, 4, 1, 88, "t2RSBSri", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo152 }, // Inst #1655 = t2RSBSri
+ { 1656, 5, 1, 90, "t2RSBSrs", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo153 }, // Inst #1656 = t2RSBSrs
+ { 1657, 5, 1, 88, "t2RSBri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1657 = t2RSBri
+ { 1658, 6, 1, 90, "t2RSBrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1658 = t2RSBrs
+ { 1659, 5, 1, 128, "t2SADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1659 = t2SADD16
+ { 1660, 5, 1, 128, "t2SADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1660 = t2SADD8
+ { 1661, 5, 1, 128, "t2SASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1661 = t2SASX
+ { 1662, 6, 1, 88, "t2SBCSri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1662 = t2SBCSri
+ { 1663, 6, 1, 89, "t2SBCSrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1663 = t2SBCSrr
+ { 1664, 7, 1, 90, "t2SBCSrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #1664 = t2SBCSrs
+ { 1665, 6, 1, 88, "t2SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1665 = t2SBCri
+ { 1666, 6, 1, 89, "t2SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1666 = t2SBCrr
+ { 1667, 7, 1, 90, "t2SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo48 }, // Inst #1667 = t2SBCrs
+ { 1668, 6, 1, 88, "t2SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #1668 = t2SBFX
+ { 1669, 5, 1, 88, "t2SDIV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1669 = t2SDIV
+ { 1670, 5, 1, 128, "t2SEL", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1670 = t2SEL
+ { 1671, 2, 0, 128, "t2SEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1671 = t2SEV
+ { 1672, 5, 1, 128, "t2SHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1672 = t2SHADD16
+ { 1673, 5, 1, 128, "t2SHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1673 = t2SHADD8
+ { 1674, 5, 1, 128, "t2SHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1674 = t2SHASX
+ { 1675, 5, 1, 128, "t2SHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1675 = t2SHSAX
+ { 1676, 5, 1, 128, "t2SHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1676 = t2SHSUB16
+ { 1677, 5, 1, 128, "t2SHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1677 = t2SHSUB8
+ { 1678, 3, 0, 128, "t2SMC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1678 = t2SMC
+ { 1679, 6, 1, 108, "t2SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1679 = t2SMLABB
+ { 1680, 6, 1, 108, "t2SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1680 = t2SMLABT
+ { 1681, 6, 1, 109, "t2SMLAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1681 = t2SMLAD
+ { 1682, 6, 1, 109, "t2SMLADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1682 = t2SMLADX
+ { 1683, 6, 2, 110, "t2SMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1683 = t2SMLAL
+ { 1684, 6, 2, 110, "t2SMLALBB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1684 = t2SMLALBB
+ { 1685, 6, 2, 110, "t2SMLALBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1685 = t2SMLALBT
+ { 1686, 6, 2, 110, "t2SMLALD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1686 = t2SMLALD
+ { 1687, 6, 2, 110, "t2SMLALDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1687 = t2SMLALDX
+ { 1688, 6, 2, 110, "t2SMLALTB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1688 = t2SMLALTB
+ { 1689, 6, 2, 110, "t2SMLALTT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1689 = t2SMLALTT
+ { 1690, 6, 1, 108, "t2SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1690 = t2SMLATB
+ { 1691, 6, 1, 108, "t2SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1691 = t2SMLATT
+ { 1692, 6, 1, 108, "t2SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1692 = t2SMLAWB
+ { 1693, 6, 1, 108, "t2SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1693 = t2SMLAWT
+ { 1694, 6, 1, 109, "t2SMLSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1694 = t2SMLSD
+ { 1695, 6, 1, 109, "t2SMLSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1695 = t2SMLSDX
+ { 1696, 6, 2, 110, "t2SMLSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1696 = t2SMLSLD
+ { 1697, 6, 2, 110, "t2SMLSLDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1697 = t2SMLSLDX
+ { 1698, 6, 1, 109, "t2SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1698 = t2SMMLA
+ { 1699, 6, 1, 109, "t2SMMLAR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1699 = t2SMMLAR
+ { 1700, 6, 1, 109, "t2SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1700 = t2SMMLS
+ { 1701, 6, 1, 109, "t2SMMLSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1701 = t2SMMLSR
+ { 1702, 5, 1, 116, "t2SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1702 = t2SMMUL
+ { 1703, 5, 1, 116, "t2SMMULR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1703 = t2SMMULR
+ { 1704, 5, 1, 109, "t2SMUAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1704 = t2SMUAD
+ { 1705, 5, 1, 109, "t2SMUADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1705 = t2SMUADX
+ { 1706, 5, 1, 116, "t2SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1706 = t2SMULBB
+ { 1707, 5, 1, 116, "t2SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1707 = t2SMULBT
+ { 1708, 6, 2, 117, "t2SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1708 = t2SMULL
+ { 1709, 5, 1, 116, "t2SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1709 = t2SMULTB
+ { 1710, 5, 1, 116, "t2SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1710 = t2SMULTT
+ { 1711, 5, 1, 115, "t2SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1711 = t2SMULWB
+ { 1712, 5, 1, 115, "t2SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1712 = t2SMULWT
+ { 1713, 5, 1, 109, "t2SMUSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1713 = t2SMUSD
+ { 1714, 5, 1, 109, "t2SMUSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1714 = t2SMUSDX
+ { 1715, 3, 0, 128, "t2SRSDB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1715 = t2SRSDB
+ { 1716, 3, 0, 128, "t2SRSDBW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1716 = t2SRSDBW
+ { 1717, 3, 0, 128, "t2SRSIA", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1717 = t2SRSIA
+ { 1718, 3, 0, 128, "t2SRSIAW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1718 = t2SRSIAW
+ { 1719, 5, 1, 128, "t2SSAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo52 }, // Inst #1719 = t2SSAT16
+ { 1720, 6, 1, 128, "t2SSATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #1720 = t2SSATasr
+ { 1721, 6, 1, 128, "t2SSATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #1721 = t2SSATlsl
+ { 1722, 5, 1, 128, "t2SSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1722 = t2SSAX
+ { 1723, 5, 1, 128, "t2SSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1723 = t2SSUB16
+ { 1724, 5, 1, 128, "t2SSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1724 = t2SSUB8
+ { 1725, 5, 0, 120, "t2STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1725 = t2STM
+ { 1726, 5, 1, 118, "t2STRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1726 = t2STRBT
+ { 1727, 6, 1, 119, "t2STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1727 = t2STRB_POST
+ { 1728, 6, 1, 119, "t2STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1728 = t2STRB_PRE
+ { 1729, 5, 0, 118, "t2STRBi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1729 = t2STRBi12
+ { 1730, 5, 0, 118, "t2STRBi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1730 = t2STRBi8
+ { 1731, 6, 0, 121, "t2STRBs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1731 = t2STRBs
+ { 1732, 6, 0, 121, "t2STRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1732 = t2STRDi8
+ { 1733, 5, 1, 128, "t2STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #1733 = t2STREX
+ { 1734, 5, 1, 128, "t2STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #1734 = t2STREXB
+ { 1735, 6, 1, 128, "t2STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo57 }, // Inst #1735 = t2STREXD
+ { 1736, 5, 1, 128, "t2STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #1736 = t2STREXH
+ { 1737, 5, 1, 118, "t2STRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1737 = t2STRHT
+ { 1738, 6, 1, 119, "t2STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1738 = t2STRH_POST
+ { 1739, 6, 1, 119, "t2STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1739 = t2STRH_PRE
+ { 1740, 5, 0, 118, "t2STRHi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1740 = t2STRHi12
+ { 1741, 5, 0, 118, "t2STRHi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1741 = t2STRHi8
+ { 1742, 6, 0, 121, "t2STRHs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1742 = t2STRHs
+ { 1743, 5, 1, 118, "t2STRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1743 = t2STRT
+ { 1744, 6, 1, 119, "t2STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1744 = t2STR_POST
+ { 1745, 6, 1, 119, "t2STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1745 = t2STR_PRE
+ { 1746, 5, 0, 118, "t2STRi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1746 = t2STRi12
+ { 1747, 5, 0, 118, "t2STRi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1747 = t2STRi8
+ { 1748, 6, 0, 121, "t2STRs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1748 = t2STRs
+ { 1749, 5, 1, 88, "t2SUBSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1749 = t2SUBSri
+ { 1750, 5, 1, 89, "t2SUBSrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1750 = t2SUBSrr
+ { 1751, 6, 1, 90, "t2SUBSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #1751 = t2SUBSrs
+ { 1752, 6, 1, 88, "t2SUBrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1752 = t2SUBrSPi
+ { 1753, 5, 1, 88, "t2SUBrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1753 = t2SUBrSPi12
+ { 1754, 3, 1, 128, "t2SUBrSPi12_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1754 = t2SUBrSPi12_
+ { 1755, 3, 1, 128, "t2SUBrSPi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1755 = t2SUBrSPi_
+ { 1756, 7, 1, 90, "t2SUBrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1756 = t2SUBrSPs
+ { 1757, 4, 1, 128, "t2SUBrSPs_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo155 }, // Inst #1757 = t2SUBrSPs_
+ { 1758, 6, 1, 88, "t2SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1758 = t2SUBri
+ { 1759, 6, 1, 88, "t2SUBri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1759 = t2SUBri12
+ { 1760, 6, 1, 89, "t2SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1760 = t2SUBrr
+ { 1761, 7, 1, 90, "t2SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1761 = t2SUBrs
+ { 1762, 5, 1, 89, "t2SXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1762 = t2SXTAB16rr
+ { 1763, 6, 1, 91, "t2SXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1763 = t2SXTAB16rr_rot
+ { 1764, 5, 1, 89, "t2SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1764 = t2SXTABrr
+ { 1765, 6, 1, 91, "t2SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1765 = t2SXTABrr_rot
+ { 1766, 5, 1, 89, "t2SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1766 = t2SXTAHrr
+ { 1767, 6, 1, 91, "t2SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1767 = t2SXTAHrr_rot
+ { 1768, 4, 1, 125, "t2SXTB16r", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1768 = t2SXTB16r
+ { 1769, 5, 1, 126, "t2SXTB16r_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1769 = t2SXTB16r_rot
+ { 1770, 4, 1, 125, "t2SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1770 = t2SXTBr
+ { 1771, 5, 1, 126, "t2SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1771 = t2SXTBr_rot
+ { 1772, 4, 1, 125, "t2SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1772 = t2SXTHr
+ { 1773, 5, 1, 126, "t2SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1773 = t2SXTHr_rot
+ { 1774, 3, 0, 0, "t2TBB", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1774 = t2TBB
+ { 1775, 4, 0, 0, "t2TBBgen", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1775 = t2TBBgen
+ { 1776, 3, 0, 0, "t2TBH", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1776 = t2TBH
+ { 1777, 4, 0, 0, "t2TBHgen", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1777 = t2TBHgen
+ { 1778, 4, 0, 97, "t2TEQri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1778 = t2TEQri
+ { 1779, 4, 0, 98, "t2TEQrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1779 = t2TEQrr
+ { 1780, 5, 0, 99, "t2TEQrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1780 = t2TEQrs
+ { 1781, 0, 0, 0, "t2TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #1781 = t2TPsoft
+ { 1782, 4, 0, 97, "t2TSTri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1782 = t2TSTri
+ { 1783, 4, 0, 98, "t2TSTrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1783 = t2TSTrr
+ { 1784, 5, 0, 99, "t2TSTrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1784 = t2TSTrs
+ { 1785, 5, 1, 128, "t2UADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1785 = t2UADD16
+ { 1786, 5, 1, 128, "t2UADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1786 = t2UADD8
+ { 1787, 5, 1, 128, "t2UASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1787 = t2UASX
+ { 1788, 6, 1, 88, "t2UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #1788 = t2UBFX
+ { 1789, 5, 1, 88, "t2UDIV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1789 = t2UDIV
+ { 1790, 5, 1, 128, "t2UHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1790 = t2UHADD16
+ { 1791, 5, 1, 128, "t2UHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1791 = t2UHADD8
+ { 1792, 5, 1, 128, "t2UHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1792 = t2UHASX
+ { 1793, 5, 1, 128, "t2UHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1793 = t2UHSAX
+ { 1794, 5, 1, 128, "t2UHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1794 = t2UHSUB16
+ { 1795, 5, 1, 128, "t2UHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1795 = t2UHSUB8
+ { 1796, 6, 2, 110, "t2UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1796 = t2UMAAL
+ { 1797, 6, 2, 110, "t2UMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1797 = t2UMLAL
+ { 1798, 6, 2, 117, "t2UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1798 = t2UMULL
+ { 1799, 5, 1, 128, "t2UQADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1799 = t2UQADD16
+ { 1800, 5, 1, 128, "t2UQADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1800 = t2UQADD8
+ { 1801, 5, 1, 128, "t2UQASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1801 = t2UQASX
+ { 1802, 5, 1, 128, "t2UQSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1802 = t2UQSAX
+ { 1803, 5, 1, 128, "t2UQSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1803 = t2UQSUB16
+ { 1804, 5, 1, 128, "t2UQSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1804 = t2UQSUB8
+ { 1805, 5, 1, 128, "t2USAD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1805 = t2USAD8
+ { 1806, 6, 1, 128, "t2USADA8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1806 = t2USADA8
+ { 1807, 5, 1, 128, "t2USAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo52 }, // Inst #1807 = t2USAT16
+ { 1808, 6, 1, 128, "t2USATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #1808 = t2USATasr
+ { 1809, 6, 1, 128, "t2USATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #1809 = t2USATlsl
+ { 1810, 5, 1, 128, "t2USAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1810 = t2USAX
+ { 1811, 5, 1, 128, "t2USUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1811 = t2USUB16
+ { 1812, 5, 1, 128, "t2USUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1812 = t2USUB8
+ { 1813, 5, 1, 89, "t2UXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1813 = t2UXTAB16rr
+ { 1814, 6, 1, 91, "t2UXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1814 = t2UXTAB16rr_rot
+ { 1815, 5, 1, 89, "t2UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1815 = t2UXTABrr
+ { 1816, 6, 1, 91, "t2UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1816 = t2UXTABrr_rot
+ { 1817, 5, 1, 89, "t2UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1817 = t2UXTAHrr
+ { 1818, 6, 1, 91, "t2UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1818 = t2UXTAHrr_rot
+ { 1819, 4, 1, 125, "t2UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1819 = t2UXTB16r
+ { 1820, 5, 1, 126, "t2UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1820 = t2UXTB16r_rot
+ { 1821, 4, 1, 125, "t2UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1821 = t2UXTBr
+ { 1822, 5, 1, 126, "t2UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1822 = t2UXTBr_rot
+ { 1823, 4, 1, 125, "t2UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1823 = t2UXTHr
+ { 1824, 5, 1, 126, "t2UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1824 = t2UXTHr_rot
+ { 1825, 2, 0, 128, "t2WFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1825 = t2WFE
+ { 1826, 2, 0, 128, "t2WFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1826 = t2WFI
+ { 1827, 2, 0, 128, "t2YIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1827 = t2YIELD
+ { 1828, 6, 2, 89, "tADC", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo156 }, // Inst #1828 = tADC
+ { 1829, 5, 1, 89, "tADDhirr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 }, // Inst #1829 = tADDhirr
+ { 1830, 6, 2, 88, "tADDi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1830 = tADDi3
+ { 1831, 6, 2, 88, "tADDi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 }, // Inst #1831 = tADDi8
+ { 1832, 2, 1, 88, "tADDrPCi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1832 = tADDrPCi
+ { 1833, 3, 1, 89, "tADDrSP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 }, // Inst #1833 = tADDrSP
+ { 1834, 3, 1, 88, "tADDrSPi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo161 }, // Inst #1834 = tADDrSPi
+ { 1835, 6, 2, 89, "tADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1835 = tADDrr
+ { 1836, 3, 1, 88, "tADDspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1836 = tADDspi
+ { 1837, 3, 1, 89, "tADDspr", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 }, // Inst #1837 = tADDspr
+ { 1838, 3, 1, 128, "tADDspr_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo3 }, // Inst #1838 = tADDspr_
+ { 1839, 1, 0, 128, "tADJCALLSTACKDOWN", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo14 }, // Inst #1839 = tADJCALLSTACKDOWN
+ { 1840, 2, 0, 128, "tADJCALLSTACKUP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo148 }, // Inst #1840 = tADJCALLSTACKUP
+ { 1841, 6, 2, 89, "tAND", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1841 = tAND
+ { 1842, 3, 1, 128, "tANDsp", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, ImplicitList1, Barriers1, OperandInfo164 }, // Inst #1842 = tANDsp
+ { 1843, 6, 2, 113, "tASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1843 = tASRri
+ { 1844, 6, 2, 114, "tASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1844 = tASRrr
+ { 1845, 1, 0, 0, "tB", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1845 = tB
+ { 1846, 6, 2, 89, "tBIC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1846 = tBIC
+ { 1847, 1, 0, 128, "tBKPT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1847 = tBKPT
+ { 1848, 1, 0, 0, "tBL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1848 = tBL
+ { 1849, 1, 0, 0, "tBLXi", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1849 = tBLXi
+ { 1850, 1, 0, 0, "tBLXi_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1850 = tBLXi_r9
+ { 1851, 1, 0, 0, "tBLXr", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #1851 = tBLXr
+ { 1852, 1, 0, 0, "tBLXr_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #1852 = tBLXr_r9
+ { 1853, 1, 0, 0, "tBLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1853 = tBLr9
+ { 1854, 1, 0, 0, "tBRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #1854 = tBRIND
+ { 1855, 3, 0, 0, "tBR_JTr", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo165 }, // Inst #1855 = tBR_JTr
+ { 1856, 1, 0, 0, "tBX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo20 }, // Inst #1856 = tBX
+ { 1857, 0, 0, 0, "tBX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1857 = tBX_RET
+ { 1858, 1, 0, 0, "tBX_RET_vararg", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #1858 = tBX_RET_vararg
+ { 1859, 1, 0, 0, "tBXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo20 }, // Inst #1859 = tBXr9
+ { 1860, 3, 0, 0, "tBcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1860 = tBcc
+ { 1861, 1, 0, 0, "tBfar", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, ImplicitList8, NULL, OperandInfo14 }, // Inst #1861 = tBfar
+ { 1862, 2, 0, 0, "tCBNZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1862 = tCBNZ
+ { 1863, 2, 0, 0, "tCBZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1863 = tCBZ
+ { 1864, 4, 0, 98, "tCMNz", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 }, // Inst #1864 = tCMNz
+ { 1865, 4, 0, 98, "tCMPhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1865 = tCMPhir
+ { 1866, 4, 0, 97, "tCMPi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo167 }, // Inst #1866 = tCMPi8
+ { 1867, 4, 0, 98, "tCMPr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 }, // Inst #1867 = tCMPr
+ { 1868, 4, 0, 98, "tCMPzhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1868 = tCMPzhir
+ { 1869, 4, 0, 97, "tCMPzi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo167 }, // Inst #1869 = tCMPzi8
+ { 1870, 4, 0, 98, "tCMPzr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 }, // Inst #1870 = tCMPzr
+ { 1871, 1, 0, 128, "tCPS", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1871 = tCPS
+ { 1872, 6, 2, 89, "tEOR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1872 = tEOR
+ { 1873, 2, 0, 128, "tInt_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList9, Barriers4, OperandInfo168 }, // Inst #1873 = tInt_eh_sjlj_setjmp
+ { 1874, 5, 0, 103, "tLDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1874 = tLDM
+ { 1875, 6, 1, 104, "tLDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1875 = tLDR
+ { 1876, 6, 1, 104, "tLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1876 = tLDRB
+ { 1877, 6, 1, 104, "tLDRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1877 = tLDRBi
+ { 1878, 6, 1, 104, "tLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1878 = tLDRH
+ { 1879, 6, 1, 104, "tLDRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1879 = tLDRHi
+ { 1880, 5, 1, 104, "tLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo170 }, // Inst #1880 = tLDRSB
+ { 1881, 5, 1, 104, "tLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo170 }, // Inst #1881 = tLDRSH
+ { 1882, 4, 1, 101, "tLDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 }, // Inst #1882 = tLDRcp
+ { 1883, 6, 1, 104, "tLDRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1883 = tLDRi
+ { 1884, 4, 1, 101, "tLDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 }, // Inst #1884 = tLDRpci
+ { 1885, 3, 1, 128, "tLDRpci_pic", 0|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1885 = tLDRpci_pic
+ { 1886, 5, 1, 101, "tLDRspi", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 }, // Inst #1886 = tLDRspi
+ { 1887, 4, 1, 88, "tLEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 }, // Inst #1887 = tLEApcrel
+ { 1888, 5, 1, 88, "tLEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo172 }, // Inst #1888 = tLEApcrelJT
+ { 1889, 6, 2, 113, "tLSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1889 = tLSLri
+ { 1890, 6, 2, 114, "tLSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1890 = tLSLrr
+ { 1891, 6, 2, 113, "tLSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1891 = tLSRri
+ { 1892, 6, 2, 114, "tLSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1892 = tLSRrr
+ { 1893, 5, 1, 93, "tMOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo173 }, // Inst #1893 = tMOVCCi
+ { 1894, 5, 1, 94, "tMOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 }, // Inst #1894 = tMOVCCr
+ { 1895, 5, 1, 128, "tMOVCCr_pseudo", 0|(1<<TID::Predicable)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo170 }, // Inst #1895 = tMOVCCr_pseudo
+ { 1896, 2, 1, 112, "tMOVSr", 0, 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo168 }, // Inst #1896 = tMOVSr
+ { 1897, 2, 1, 112, "tMOVgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1897 = tMOVgpr2gpr
+ { 1898, 2, 1, 112, "tMOVgpr2tgpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo174 }, // Inst #1898 = tMOVgpr2tgpr
+ { 1899, 5, 2, 111, "tMOVi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo175 }, // Inst #1899 = tMOVi8
+ { 1900, 2, 1, 112, "tMOVr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo168 }, // Inst #1900 = tMOVr
+ { 1901, 2, 1, 112, "tMOVtgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1901 = tMOVtgpr2gpr
+ { 1902, 6, 2, 116, "tMUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1902 = tMUL
+ { 1903, 5, 2, 112, "tMVN", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo176 }, // Inst #1903 = tMVN
+ { 1904, 2, 0, 128, "tNOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1904 = tNOP
+ { 1905, 6, 2, 89, "tORR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1905 = tORR
+ { 1906, 3, 1, 89, "tPICADD", 0|(1<<TID::NotDuplicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1906 = tPICADD
+ { 1907, 3, 0, 0, "tPOP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo177 }, // Inst #1907 = tPOP
+ { 1908, 3, 0, 0, "tPOP_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo177 }, // Inst #1908 = tPOP_RET
+ { 1909, 3, 0, 0, "tPUSH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo177 }, // Inst #1909 = tPUSH
+ { 1910, 4, 1, 125, "tREV", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1910 = tREV
+ { 1911, 4, 1, 125, "tREV16", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1911 = tREV16
+ { 1912, 4, 1, 125, "tREVSH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1912 = tREVSH
+ { 1913, 6, 2, 114, "tROR", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1913 = tROR
+ { 1914, 5, 2, 88, "tRSB", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo176 }, // Inst #1914 = tRSB
+ { 1915, 5, 1, 101, "tRestore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 }, // Inst #1915 = tRestore
+ { 1916, 6, 2, 89, "tSBC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo156 }, // Inst #1916 = tSBC
+ { 1917, 0, 0, 128, "tSETENDBE", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1917 = tSETENDBE
+ { 1918, 0, 0, 128, "tSETENDLE", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1918 = tSETENDLE
+ { 1919, 2, 0, 128, "tSEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1919 = tSEV
+ { 1920, 5, 0, 120, "tSTM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1920 = tSTM
+ { 1921, 6, 0, 121, "tSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1921 = tSTR
+ { 1922, 6, 0, 121, "tSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1922 = tSTRB
+ { 1923, 6, 0, 121, "tSTRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1923 = tSTRBi
+ { 1924, 6, 0, 121, "tSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1924 = tSTRH
+ { 1925, 6, 0, 121, "tSTRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1925 = tSTRHi
+ { 1926, 6, 0, 121, "tSTRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1926 = tSTRi
+ { 1927, 5, 0, 118, "tSTRspi", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 }, // Inst #1927 = tSTRspi
+ { 1928, 6, 2, 88, "tSUBi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1928 = tSUBi3
+ { 1929, 6, 2, 88, "tSUBi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 }, // Inst #1929 = tSUBi8
+ { 1930, 6, 2, 89, "tSUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1930 = tSUBrr
+ { 1931, 3, 1, 88, "tSUBspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1931 = tSUBspi
+ { 1932, 3, 1, 128, "tSUBspi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1932 = tSUBspi_
+ { 1933, 3, 0, 0, "tSVC", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1933 = tSVC
+ { 1934, 4, 1, 125, "tSXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1934 = tSXTB
+ { 1935, 4, 1, 125, "tSXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1935 = tSXTH
+ { 1936, 5, 0, 118, "tSpill", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 }, // Inst #1936 = tSpill
+ { 1937, 0, 0, 0, "tTPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList10, NULL, 0 }, // Inst #1937 = tTPsoft
+ { 1938, 0, 0, 0, "tTRAP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1938 = tTRAP
+ { 1939, 4, 0, 98, "tTST", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 }, // Inst #1939 = tTST
+ { 1940, 4, 1, 125, "tUXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1940 = tUXTB
+ { 1941, 4, 1, 125, "tUXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1941 = tUXTH
+ { 1942, 2, 0, 128, "tWFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1942 = tWFE
+ { 1943, 2, 0, 128, "tWFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1943 = tWFI
+ { 1944, 2, 0, 128, "tYIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1944 = tYIELD
};
} // End llvm namespace
diff --git a/libclamav/c++/ARMGenInstrNames.inc b/libclamav/c++/ARMGenInstrNames.inc
index 223aa5c..4f6ccea 100644
--- a/libclamav/c++/ARMGenInstrNames.inc
+++ b/libclamav/c++/ARMGenInstrNames.inc
@@ -65,1563 +65,1897 @@ namespace ARM {
ATOMIC_SWAP_I8 = 52,
B = 53,
BFC = 54,
- BICri = 55,
- BICrr = 56,
- BICrs = 57,
- BKPT = 58,
- BL = 59,
- BLX = 60,
- BLXr9 = 61,
- BL_pred = 62,
- BLr9 = 63,
- BLr9_pred = 64,
- BRIND = 65,
- BR_JTadd = 66,
- BR_JTm = 67,
- BR_JTr = 68,
- BX = 69,
- BXJ = 70,
- BX_RET = 71,
- BXr9 = 72,
- Bcc = 73,
- CDP = 74,
- CDP2 = 75,
- CLZ = 76,
- CMNzri = 77,
- CMNzrr = 78,
- CMNzrs = 79,
- CMPri = 80,
- CMPrr = 81,
- CMPrs = 82,
- CMPzri = 83,
- CMPzrr = 84,
- CMPzrs = 85,
- CONSTPOOL_ENTRY = 86,
- CPS = 87,
- DBG = 88,
- EORri = 89,
- EORrr = 90,
- EORrs = 91,
- FCONSTD = 92,
- FCONSTS = 93,
- FMSTAT = 94,
- Int_MemBarrierV6 = 95,
- Int_MemBarrierV7 = 96,
- Int_SyncBarrierV6 = 97,
- Int_SyncBarrierV7 = 98,
- Int_eh_sjlj_setjmp = 99,
- LDM = 100,
- LDM_RET = 101,
- LDR = 102,
- LDRB = 103,
- LDRBT = 104,
- LDRB_POST = 105,
- LDRB_PRE = 106,
- LDRD = 107,
- LDREX = 108,
- LDREXB = 109,
- LDREXD = 110,
- LDREXH = 111,
- LDRH = 112,
- LDRH_POST = 113,
- LDRH_PRE = 114,
- LDRSB = 115,
- LDRSB_POST = 116,
- LDRSB_PRE = 117,
- LDRSH = 118,
- LDRSH_POST = 119,
- LDRSH_PRE = 120,
- LDRT = 121,
- LDR_POST = 122,
- LDR_PRE = 123,
- LDRcp = 124,
- LEApcrel = 125,
- LEApcrelJT = 126,
- MCR = 127,
- MCR2 = 128,
- MCRR = 129,
- MCRR2 = 130,
- MLA = 131,
- MLS = 132,
- MOVCCi = 133,
- MOVCCr = 134,
- MOVCCs = 135,
- MOVTi16 = 136,
- MOVi = 137,
- MOVi16 = 138,
- MOVi2pieces = 139,
- MOVi32imm = 140,
- MOVr = 141,
- MOVrx = 142,
- MOVs = 143,
- MOVsra_flag = 144,
- MOVsrl_flag = 145,
- MRC = 146,
- MRC2 = 147,
- MRRC = 148,
- MRRC2 = 149,
- MRS = 150,
- MRSsys = 151,
- MSR = 152,
- MSRsys = 153,
- MUL = 154,
- MVNi = 155,
- MVNr = 156,
- MVNs = 157,
- NOP = 158,
- ORRri = 159,
- ORRrr = 160,
- ORRrs = 161,
- PICADD = 162,
- PICLDR = 163,
- PICLDRB = 164,
- PICLDRH = 165,
- PICLDRSB = 166,
- PICLDRSH = 167,
- PICSTR = 168,
- PICSTRB = 169,
- PICSTRH = 170,
- PKHBT = 171,
- PKHTB = 172,
- QADD = 173,
- QADD16 = 174,
- QADD8 = 175,
- QASX = 176,
- QDADD = 177,
- QDSUB = 178,
- QSAX = 179,
- QSUB = 180,
- QSUB16 = 181,
- QSUB8 = 182,
- RBIT = 183,
- REV = 184,
- REV16 = 185,
- REVSH = 186,
- RSBSri = 187,
- RSBSrs = 188,
- RSBri = 189,
- RSBrs = 190,
- RSCSri = 191,
- RSCSrs = 192,
- RSCri = 193,
- RSCrs = 194,
- SBCSSri = 195,
- SBCSSrr = 196,
- SBCSSrs = 197,
- SBCri = 198,
- SBCrr = 199,
- SBCrs = 200,
- SBFX = 201,
- SETENDBE = 202,
- SETENDLE = 203,
- SEV = 204,
- SMLABB = 205,
- SMLABT = 206,
- SMLAL = 207,
- SMLALBB = 208,
- SMLALBT = 209,
- SMLALTB = 210,
- SMLALTT = 211,
- SMLATB = 212,
- SMLATT = 213,
- SMLAWB = 214,
- SMLAWT = 215,
- SMMLA = 216,
- SMMLS = 217,
- SMMUL = 218,
- SMULBB = 219,
- SMULBT = 220,
- SMULL = 221,
- SMULTB = 222,
- SMULTT = 223,
- SMULWB = 224,
- SMULWT = 225,
- STM = 226,
- STR = 227,
- STRB = 228,
- STRBT = 229,
- STRB_POST = 230,
- STRB_PRE = 231,
- STRD = 232,
- STREX = 233,
- STREXB = 234,
- STREXD = 235,
- STREXH = 236,
- STRH = 237,
- STRH_POST = 238,
- STRH_PRE = 239,
- STRT = 240,
- STR_POST = 241,
- STR_PRE = 242,
- SUBSri = 243,
- SUBSrr = 244,
- SUBSrs = 245,
- SUBri = 246,
- SUBrr = 247,
- SUBrs = 248,
- SVC = 249,
- SWP = 250,
- SWPB = 251,
- SXTABrr = 252,
- SXTABrr_rot = 253,
- SXTAHrr = 254,
- SXTAHrr_rot = 255,
- SXTBr = 256,
- SXTBr_rot = 257,
- SXTHr = 258,
- SXTHr_rot = 259,
- TEQri = 260,
- TEQrr = 261,
- TEQrs = 262,
- TPsoft = 263,
- TRAP = 264,
- TSTri = 265,
- TSTrr = 266,
- TSTrs = 267,
- UBFX = 268,
- UMAAL = 269,
- UMLAL = 270,
- UMULL = 271,
- UQADD16 = 272,
- UQADD8 = 273,
- UQASX = 274,
- UQSAX = 275,
- UQSUB16 = 276,
- UQSUB8 = 277,
- UXTABrr = 278,
- UXTABrr_rot = 279,
- UXTAHrr = 280,
- UXTAHrr_rot = 281,
- UXTB16r = 282,
- UXTB16r_rot = 283,
- UXTBr = 284,
- UXTBr_rot = 285,
- UXTHr = 286,
- UXTHr_rot = 287,
- VABALsv2i64 = 288,
- VABALsv4i32 = 289,
- VABALsv8i16 = 290,
- VABALuv2i64 = 291,
- VABALuv4i32 = 292,
- VABALuv8i16 = 293,
- VABAsv16i8 = 294,
- VABAsv2i32 = 295,
- VABAsv4i16 = 296,
- VABAsv4i32 = 297,
- VABAsv8i16 = 298,
- VABAsv8i8 = 299,
- VABAuv16i8 = 300,
- VABAuv2i32 = 301,
- VABAuv4i16 = 302,
- VABAuv4i32 = 303,
- VABAuv8i16 = 304,
- VABAuv8i8 = 305,
- VABDLsv2i64 = 306,
- VABDLsv4i32 = 307,
- VABDLsv8i16 = 308,
- VABDLuv2i64 = 309,
- VABDLuv4i32 = 310,
- VABDLuv8i16 = 311,
- VABDfd = 312,
- VABDfq = 313,
- VABDsv16i8 = 314,
- VABDsv2i32 = 315,
- VABDsv4i16 = 316,
- VABDsv4i32 = 317,
- VABDsv8i16 = 318,
- VABDsv8i8 = 319,
- VABDuv16i8 = 320,
- VABDuv2i32 = 321,
- VABDuv4i16 = 322,
- VABDuv4i32 = 323,
- VABDuv8i16 = 324,
- VABDuv8i8 = 325,
- VABSD = 326,
- VABSS = 327,
- VABSfd = 328,
- VABSfd_sfp = 329,
- VABSfq = 330,
- VABSv16i8 = 331,
- VABSv2i32 = 332,
- VABSv4i16 = 333,
- VABSv4i32 = 334,
- VABSv8i16 = 335,
- VABSv8i8 = 336,
- VACGEd = 337,
- VACGEq = 338,
- VACGTd = 339,
- VACGTq = 340,
- VADDD = 341,
- VADDHNv2i32 = 342,
- VADDHNv4i16 = 343,
- VADDHNv8i8 = 344,
- VADDLsv2i64 = 345,
- VADDLsv4i32 = 346,
- VADDLsv8i16 = 347,
- VADDLuv2i64 = 348,
- VADDLuv4i32 = 349,
- VADDLuv8i16 = 350,
- VADDS = 351,
- VADDWsv2i64 = 352,
- VADDWsv4i32 = 353,
- VADDWsv8i16 = 354,
- VADDWuv2i64 = 355,
- VADDWuv4i32 = 356,
- VADDWuv8i16 = 357,
- VADDfd = 358,
- VADDfd_sfp = 359,
- VADDfq = 360,
- VADDv16i8 = 361,
- VADDv1i64 = 362,
- VADDv2i32 = 363,
- VADDv2i64 = 364,
- VADDv4i16 = 365,
- VADDv4i32 = 366,
- VADDv8i16 = 367,
- VADDv8i8 = 368,
- VANDd = 369,
- VANDq = 370,
- VBICd = 371,
- VBICq = 372,
- VBIFd = 373,
- VBIFq = 374,
- VBITd = 375,
- VBITq = 376,
- VBSLd = 377,
- VBSLq = 378,
- VCEQfd = 379,
- VCEQfq = 380,
- VCEQv16i8 = 381,
- VCEQv2i32 = 382,
- VCEQv4i16 = 383,
- VCEQv4i32 = 384,
- VCEQv8i16 = 385,
- VCEQv8i8 = 386,
- VCGEfd = 387,
- VCGEfq = 388,
- VCGEsv16i8 = 389,
- VCGEsv2i32 = 390,
- VCGEsv4i16 = 391,
- VCGEsv4i32 = 392,
- VCGEsv8i16 = 393,
- VCGEsv8i8 = 394,
- VCGEuv16i8 = 395,
- VCGEuv2i32 = 396,
- VCGEuv4i16 = 397,
- VCGEuv4i32 = 398,
- VCGEuv8i16 = 399,
- VCGEuv8i8 = 400,
- VCGTfd = 401,
- VCGTfq = 402,
- VCGTsv16i8 = 403,
- VCGTsv2i32 = 404,
- VCGTsv4i16 = 405,
- VCGTsv4i32 = 406,
- VCGTsv8i16 = 407,
- VCGTsv8i8 = 408,
- VCGTuv16i8 = 409,
- VCGTuv2i32 = 410,
- VCGTuv4i16 = 411,
- VCGTuv4i32 = 412,
- VCGTuv8i16 = 413,
- VCGTuv8i8 = 414,
- VCLSv16i8 = 415,
- VCLSv2i32 = 416,
- VCLSv4i16 = 417,
- VCLSv4i32 = 418,
- VCLSv8i16 = 419,
- VCLSv8i8 = 420,
- VCLZv16i8 = 421,
- VCLZv2i32 = 422,
- VCLZv4i16 = 423,
- VCLZv4i32 = 424,
- VCLZv8i16 = 425,
- VCLZv8i8 = 426,
- VCMPD = 427,
- VCMPED = 428,
- VCMPES = 429,
- VCMPEZD = 430,
- VCMPEZS = 431,
- VCMPS = 432,
- VCMPZD = 433,
- VCMPZS = 434,
- VCNTd = 435,
- VCNTq = 436,
- VCVTBHS = 437,
- VCVTBSH = 438,
- VCVTDS = 439,
- VCVTSD = 440,
- VCVTTHS = 441,
- VCVTTSH = 442,
- VCVTf2sd = 443,
- VCVTf2sd_sfp = 444,
- VCVTf2sq = 445,
- VCVTf2ud = 446,
- VCVTf2ud_sfp = 447,
- VCVTf2uq = 448,
- VCVTf2xsd = 449,
- VCVTf2xsq = 450,
- VCVTf2xud = 451,
- VCVTf2xuq = 452,
- VCVTs2fd = 453,
- VCVTs2fd_sfp = 454,
- VCVTs2fq = 455,
- VCVTu2fd = 456,
- VCVTu2fd_sfp = 457,
- VCVTu2fq = 458,
- VCVTxs2fd = 459,
- VCVTxs2fq = 460,
- VCVTxu2fd = 461,
- VCVTxu2fq = 462,
- VDIVD = 463,
- VDIVS = 464,
- VDUP16d = 465,
- VDUP16q = 466,
- VDUP32d = 467,
- VDUP32q = 468,
- VDUP8d = 469,
- VDUP8q = 470,
- VDUPLN16d = 471,
- VDUPLN16q = 472,
- VDUPLN32d = 473,
- VDUPLN32q = 474,
- VDUPLN8d = 475,
- VDUPLN8q = 476,
- VDUPLNfd = 477,
- VDUPLNfq = 478,
- VDUPfd = 479,
- VDUPfdf = 480,
- VDUPfq = 481,
- VDUPfqf = 482,
- VEORd = 483,
- VEORq = 484,
- VEXTd16 = 485,
- VEXTd32 = 486,
- VEXTd8 = 487,
- VEXTdf = 488,
- VEXTq16 = 489,
- VEXTq32 = 490,
- VEXTq8 = 491,
- VEXTqf = 492,
- VGETLNi32 = 493,
- VGETLNs16 = 494,
- VGETLNs8 = 495,
- VGETLNu16 = 496,
- VGETLNu8 = 497,
- VHADDsv16i8 = 498,
- VHADDsv2i32 = 499,
- VHADDsv4i16 = 500,
- VHADDsv4i32 = 501,
- VHADDsv8i16 = 502,
- VHADDsv8i8 = 503,
- VHADDuv16i8 = 504,
- VHADDuv2i32 = 505,
- VHADDuv4i16 = 506,
- VHADDuv4i32 = 507,
- VHADDuv8i16 = 508,
- VHADDuv8i8 = 509,
- VHSUBsv16i8 = 510,
- VHSUBsv2i32 = 511,
- VHSUBsv4i16 = 512,
- VHSUBsv4i32 = 513,
- VHSUBsv8i16 = 514,
- VHSUBsv8i8 = 515,
- VHSUBuv16i8 = 516,
- VHSUBuv2i32 = 517,
- VHSUBuv4i16 = 518,
- VHSUBuv4i32 = 519,
- VHSUBuv8i16 = 520,
- VHSUBuv8i8 = 521,
- VLD1d16 = 522,
- VLD1d32 = 523,
- VLD1d64 = 524,
- VLD1d8 = 525,
- VLD1df = 526,
- VLD1q16 = 527,
- VLD1q32 = 528,
- VLD1q64 = 529,
- VLD1q8 = 530,
- VLD1qf = 531,
- VLD2LNd16 = 532,
- VLD2LNd32 = 533,
- VLD2LNd8 = 534,
- VLD2LNq16a = 535,
- VLD2LNq16b = 536,
- VLD2LNq32a = 537,
- VLD2LNq32b = 538,
- VLD2d16 = 539,
- VLD2d32 = 540,
- VLD2d64 = 541,
- VLD2d8 = 542,
- VLD2q16 = 543,
- VLD2q32 = 544,
- VLD2q8 = 545,
- VLD3LNd16 = 546,
- VLD3LNd32 = 547,
- VLD3LNd8 = 548,
- VLD3LNq16a = 549,
- VLD3LNq16b = 550,
- VLD3LNq32a = 551,
- VLD3LNq32b = 552,
- VLD3d16 = 553,
- VLD3d32 = 554,
- VLD3d64 = 555,
- VLD3d8 = 556,
- VLD3q16a = 557,
- VLD3q16b = 558,
- VLD3q32a = 559,
- VLD3q32b = 560,
- VLD3q8a = 561,
- VLD3q8b = 562,
- VLD4LNd16 = 563,
- VLD4LNd32 = 564,
- VLD4LNd8 = 565,
- VLD4LNq16a = 566,
- VLD4LNq16b = 567,
- VLD4LNq32a = 568,
- VLD4LNq32b = 569,
- VLD4d16 = 570,
- VLD4d32 = 571,
- VLD4d64 = 572,
- VLD4d8 = 573,
- VLD4q16a = 574,
- VLD4q16b = 575,
- VLD4q32a = 576,
- VLD4q32b = 577,
- VLD4q8a = 578,
- VLD4q8b = 579,
- VLDMD = 580,
- VLDMS = 581,
- VLDRD = 582,
- VLDRQ = 583,
- VLDRS = 584,
- VMAXfd = 585,
- VMAXfq = 586,
- VMAXsv16i8 = 587,
- VMAXsv2i32 = 588,
- VMAXsv4i16 = 589,
- VMAXsv4i32 = 590,
- VMAXsv8i16 = 591,
- VMAXsv8i8 = 592,
- VMAXuv16i8 = 593,
- VMAXuv2i32 = 594,
- VMAXuv4i16 = 595,
- VMAXuv4i32 = 596,
- VMAXuv8i16 = 597,
- VMAXuv8i8 = 598,
- VMINfd = 599,
- VMINfq = 600,
- VMINsv16i8 = 601,
- VMINsv2i32 = 602,
- VMINsv4i16 = 603,
- VMINsv4i32 = 604,
- VMINsv8i16 = 605,
- VMINsv8i8 = 606,
- VMINuv16i8 = 607,
- VMINuv2i32 = 608,
- VMINuv4i16 = 609,
- VMINuv4i32 = 610,
- VMINuv8i16 = 611,
- VMINuv8i8 = 612,
- VMLAD = 613,
- VMLALslsv2i32 = 614,
- VMLALslsv4i16 = 615,
- VMLALsluv2i32 = 616,
- VMLALsluv4i16 = 617,
- VMLALsv2i64 = 618,
- VMLALsv4i32 = 619,
- VMLALsv8i16 = 620,
- VMLALuv2i64 = 621,
- VMLALuv4i32 = 622,
- VMLALuv8i16 = 623,
- VMLAS = 624,
- VMLAfd = 625,
- VMLAfq = 626,
- VMLAslfd = 627,
- VMLAslfq = 628,
- VMLAslv2i32 = 629,
- VMLAslv4i16 = 630,
- VMLAslv4i32 = 631,
- VMLAslv8i16 = 632,
- VMLAv16i8 = 633,
- VMLAv2i32 = 634,
- VMLAv4i16 = 635,
- VMLAv4i32 = 636,
- VMLAv8i16 = 637,
- VMLAv8i8 = 638,
- VMLSD = 639,
- VMLSLslsv2i32 = 640,
- VMLSLslsv4i16 = 641,
- VMLSLsluv2i32 = 642,
- VMLSLsluv4i16 = 643,
- VMLSLsv2i64 = 644,
- VMLSLsv4i32 = 645,
- VMLSLsv8i16 = 646,
- VMLSLuv2i64 = 647,
- VMLSLuv4i32 = 648,
- VMLSLuv8i16 = 649,
- VMLSS = 650,
- VMLSfd = 651,
- VMLSfq = 652,
- VMLSslfd = 653,
- VMLSslfq = 654,
- VMLSslv2i32 = 655,
- VMLSslv4i16 = 656,
- VMLSslv4i32 = 657,
- VMLSslv8i16 = 658,
- VMLSv16i8 = 659,
- VMLSv2i32 = 660,
- VMLSv4i16 = 661,
- VMLSv4i32 = 662,
- VMLSv8i16 = 663,
- VMLSv8i8 = 664,
- VMOVD = 665,
- VMOVDRR = 666,
- VMOVDcc = 667,
- VMOVDneon = 668,
- VMOVLsv2i64 = 669,
- VMOVLsv4i32 = 670,
- VMOVLsv8i16 = 671,
- VMOVLuv2i64 = 672,
- VMOVLuv4i32 = 673,
- VMOVLuv8i16 = 674,
- VMOVNv2i32 = 675,
- VMOVNv4i16 = 676,
- VMOVNv8i8 = 677,
- VMOVQ = 678,
- VMOVRRD = 679,
- VMOVRRS = 680,
- VMOVRS = 681,
- VMOVS = 682,
- VMOVSR = 683,
- VMOVSRR = 684,
- VMOVScc = 685,
- VMOVv16i8 = 686,
- VMOVv1i64 = 687,
- VMOVv2i32 = 688,
- VMOVv2i64 = 689,
- VMOVv4i16 = 690,
- VMOVv4i32 = 691,
- VMOVv8i16 = 692,
- VMOVv8i8 = 693,
- VMRS = 694,
- VMSR = 695,
- VMULD = 696,
- VMULLp = 697,
- VMULLslsv2i32 = 698,
- VMULLslsv4i16 = 699,
- VMULLsluv2i32 = 700,
- VMULLsluv4i16 = 701,
- VMULLsv2i64 = 702,
- VMULLsv4i32 = 703,
- VMULLsv8i16 = 704,
- VMULLuv2i64 = 705,
- VMULLuv4i32 = 706,
- VMULLuv8i16 = 707,
- VMULS = 708,
- VMULfd = 709,
- VMULfd_sfp = 710,
- VMULfq = 711,
- VMULpd = 712,
- VMULpq = 713,
- VMULslfd = 714,
- VMULslfq = 715,
- VMULslv2i32 = 716,
- VMULslv4i16 = 717,
- VMULslv4i32 = 718,
- VMULslv8i16 = 719,
- VMULv16i8 = 720,
- VMULv2i32 = 721,
- VMULv4i16 = 722,
- VMULv4i32 = 723,
- VMULv8i16 = 724,
- VMULv8i8 = 725,
- VMVNd = 726,
- VMVNq = 727,
- VNEGD = 728,
- VNEGDcc = 729,
- VNEGS = 730,
- VNEGScc = 731,
- VNEGf32d = 732,
- VNEGf32d_sfp = 733,
- VNEGf32q = 734,
- VNEGs16d = 735,
- VNEGs16q = 736,
- VNEGs32d = 737,
- VNEGs32q = 738,
- VNEGs8d = 739,
- VNEGs8q = 740,
- VNMLAD = 741,
- VNMLAS = 742,
- VNMLSD = 743,
- VNMLSS = 744,
- VNMULD = 745,
- VNMULS = 746,
- VORNd = 747,
- VORNq = 748,
- VORRd = 749,
- VORRq = 750,
- VPADALsv16i8 = 751,
- VPADALsv2i32 = 752,
- VPADALsv4i16 = 753,
- VPADALsv4i32 = 754,
- VPADALsv8i16 = 755,
- VPADALsv8i8 = 756,
- VPADALuv16i8 = 757,
- VPADALuv2i32 = 758,
- VPADALuv4i16 = 759,
- VPADALuv4i32 = 760,
- VPADALuv8i16 = 761,
- VPADALuv8i8 = 762,
- VPADDLsv16i8 = 763,
- VPADDLsv2i32 = 764,
- VPADDLsv4i16 = 765,
- VPADDLsv4i32 = 766,
- VPADDLsv8i16 = 767,
- VPADDLsv8i8 = 768,
- VPADDLuv16i8 = 769,
- VPADDLuv2i32 = 770,
- VPADDLuv4i16 = 771,
- VPADDLuv4i32 = 772,
- VPADDLuv8i16 = 773,
- VPADDLuv8i8 = 774,
- VPADDf = 775,
- VPADDi16 = 776,
- VPADDi32 = 777,
- VPADDi8 = 778,
- VPMAXf = 779,
- VPMAXs16 = 780,
- VPMAXs32 = 781,
- VPMAXs8 = 782,
- VPMAXu16 = 783,
- VPMAXu32 = 784,
- VPMAXu8 = 785,
- VPMINf = 786,
- VPMINs16 = 787,
- VPMINs32 = 788,
- VPMINs8 = 789,
- VPMINu16 = 790,
- VPMINu32 = 791,
- VPMINu8 = 792,
- VQABSv16i8 = 793,
- VQABSv2i32 = 794,
- VQABSv4i16 = 795,
- VQABSv4i32 = 796,
- VQABSv8i16 = 797,
- VQABSv8i8 = 798,
- VQADDsv16i8 = 799,
- VQADDsv1i64 = 800,
- VQADDsv2i32 = 801,
- VQADDsv2i64 = 802,
- VQADDsv4i16 = 803,
- VQADDsv4i32 = 804,
- VQADDsv8i16 = 805,
- VQADDsv8i8 = 806,
- VQADDuv16i8 = 807,
- VQADDuv1i64 = 808,
- VQADDuv2i32 = 809,
- VQADDuv2i64 = 810,
- VQADDuv4i16 = 811,
- VQADDuv4i32 = 812,
- VQADDuv8i16 = 813,
- VQADDuv8i8 = 814,
- VQDMLALslv2i32 = 815,
- VQDMLALslv4i16 = 816,
- VQDMLALv2i64 = 817,
- VQDMLALv4i32 = 818,
- VQDMLSLslv2i32 = 819,
- VQDMLSLslv4i16 = 820,
- VQDMLSLv2i64 = 821,
- VQDMLSLv4i32 = 822,
- VQDMULHslv2i32 = 823,
- VQDMULHslv4i16 = 824,
- VQDMULHslv4i32 = 825,
- VQDMULHslv8i16 = 826,
- VQDMULHv2i32 = 827,
- VQDMULHv4i16 = 828,
- VQDMULHv4i32 = 829,
- VQDMULHv8i16 = 830,
- VQDMULLslv2i32 = 831,
- VQDMULLslv4i16 = 832,
- VQDMULLv2i64 = 833,
- VQDMULLv4i32 = 834,
- VQMOVNsuv2i32 = 835,
- VQMOVNsuv4i16 = 836,
- VQMOVNsuv8i8 = 837,
- VQMOVNsv2i32 = 838,
- VQMOVNsv4i16 = 839,
- VQMOVNsv8i8 = 840,
- VQMOVNuv2i32 = 841,
- VQMOVNuv4i16 = 842,
- VQMOVNuv8i8 = 843,
- VQNEGv16i8 = 844,
- VQNEGv2i32 = 845,
- VQNEGv4i16 = 846,
- VQNEGv4i32 = 847,
- VQNEGv8i16 = 848,
- VQNEGv8i8 = 849,
- VQRDMULHslv2i32 = 850,
- VQRDMULHslv4i16 = 851,
- VQRDMULHslv4i32 = 852,
- VQRDMULHslv8i16 = 853,
- VQRDMULHv2i32 = 854,
- VQRDMULHv4i16 = 855,
- VQRDMULHv4i32 = 856,
- VQRDMULHv8i16 = 857,
- VQRSHLsv16i8 = 858,
- VQRSHLsv1i64 = 859,
- VQRSHLsv2i32 = 860,
- VQRSHLsv2i64 = 861,
- VQRSHLsv4i16 = 862,
- VQRSHLsv4i32 = 863,
- VQRSHLsv8i16 = 864,
- VQRSHLsv8i8 = 865,
- VQRSHLuv16i8 = 866,
- VQRSHLuv1i64 = 867,
- VQRSHLuv2i32 = 868,
- VQRSHLuv2i64 = 869,
- VQRSHLuv4i16 = 870,
- VQRSHLuv4i32 = 871,
- VQRSHLuv8i16 = 872,
- VQRSHLuv8i8 = 873,
- VQRSHRNsv2i32 = 874,
- VQRSHRNsv4i16 = 875,
- VQRSHRNsv8i8 = 876,
- VQRSHRNuv2i32 = 877,
- VQRSHRNuv4i16 = 878,
- VQRSHRNuv8i8 = 879,
- VQRSHRUNv2i32 = 880,
- VQRSHRUNv4i16 = 881,
- VQRSHRUNv8i8 = 882,
- VQSHLsiv16i8 = 883,
- VQSHLsiv1i64 = 884,
- VQSHLsiv2i32 = 885,
- VQSHLsiv2i64 = 886,
- VQSHLsiv4i16 = 887,
- VQSHLsiv4i32 = 888,
- VQSHLsiv8i16 = 889,
- VQSHLsiv8i8 = 890,
- VQSHLsuv16i8 = 891,
- VQSHLsuv1i64 = 892,
- VQSHLsuv2i32 = 893,
- VQSHLsuv2i64 = 894,
- VQSHLsuv4i16 = 895,
- VQSHLsuv4i32 = 896,
- VQSHLsuv8i16 = 897,
- VQSHLsuv8i8 = 898,
- VQSHLsv16i8 = 899,
- VQSHLsv1i64 = 900,
- VQSHLsv2i32 = 901,
- VQSHLsv2i64 = 902,
- VQSHLsv4i16 = 903,
- VQSHLsv4i32 = 904,
- VQSHLsv8i16 = 905,
- VQSHLsv8i8 = 906,
- VQSHLuiv16i8 = 907,
- VQSHLuiv1i64 = 908,
- VQSHLuiv2i32 = 909,
- VQSHLuiv2i64 = 910,
- VQSHLuiv4i16 = 911,
- VQSHLuiv4i32 = 912,
- VQSHLuiv8i16 = 913,
- VQSHLuiv8i8 = 914,
- VQSHLuv16i8 = 915,
- VQSHLuv1i64 = 916,
- VQSHLuv2i32 = 917,
- VQSHLuv2i64 = 918,
- VQSHLuv4i16 = 919,
- VQSHLuv4i32 = 920,
- VQSHLuv8i16 = 921,
- VQSHLuv8i8 = 922,
- VQSHRNsv2i32 = 923,
- VQSHRNsv4i16 = 924,
- VQSHRNsv8i8 = 925,
- VQSHRNuv2i32 = 926,
- VQSHRNuv4i16 = 927,
- VQSHRNuv8i8 = 928,
- VQSHRUNv2i32 = 929,
- VQSHRUNv4i16 = 930,
- VQSHRUNv8i8 = 931,
- VQSUBsv16i8 = 932,
- VQSUBsv1i64 = 933,
- VQSUBsv2i32 = 934,
- VQSUBsv2i64 = 935,
- VQSUBsv4i16 = 936,
- VQSUBsv4i32 = 937,
- VQSUBsv8i16 = 938,
- VQSUBsv8i8 = 939,
- VQSUBuv16i8 = 940,
- VQSUBuv1i64 = 941,
- VQSUBuv2i32 = 942,
- VQSUBuv2i64 = 943,
- VQSUBuv4i16 = 944,
- VQSUBuv4i32 = 945,
- VQSUBuv8i16 = 946,
- VQSUBuv8i8 = 947,
- VRADDHNv2i32 = 948,
- VRADDHNv4i16 = 949,
- VRADDHNv8i8 = 950,
- VRECPEd = 951,
- VRECPEfd = 952,
- VRECPEfq = 953,
- VRECPEq = 954,
- VRECPSfd = 955,
- VRECPSfq = 956,
- VREV16d8 = 957,
- VREV16q8 = 958,
- VREV32d16 = 959,
- VREV32d8 = 960,
- VREV32q16 = 961,
- VREV32q8 = 962,
- VREV64d16 = 963,
- VREV64d32 = 964,
- VREV64d8 = 965,
- VREV64df = 966,
- VREV64q16 = 967,
- VREV64q32 = 968,
- VREV64q8 = 969,
- VREV64qf = 970,
- VRHADDsv16i8 = 971,
- VRHADDsv2i32 = 972,
- VRHADDsv4i16 = 973,
- VRHADDsv4i32 = 974,
- VRHADDsv8i16 = 975,
- VRHADDsv8i8 = 976,
- VRHADDuv16i8 = 977,
- VRHADDuv2i32 = 978,
- VRHADDuv4i16 = 979,
- VRHADDuv4i32 = 980,
- VRHADDuv8i16 = 981,
- VRHADDuv8i8 = 982,
- VRSHLsv16i8 = 983,
- VRSHLsv1i64 = 984,
- VRSHLsv2i32 = 985,
- VRSHLsv2i64 = 986,
- VRSHLsv4i16 = 987,
- VRSHLsv4i32 = 988,
- VRSHLsv8i16 = 989,
- VRSHLsv8i8 = 990,
- VRSHLuv16i8 = 991,
- VRSHLuv1i64 = 992,
- VRSHLuv2i32 = 993,
- VRSHLuv2i64 = 994,
- VRSHLuv4i16 = 995,
- VRSHLuv4i32 = 996,
- VRSHLuv8i16 = 997,
- VRSHLuv8i8 = 998,
- VRSHRNv2i32 = 999,
- VRSHRNv4i16 = 1000,
- VRSHRNv8i8 = 1001,
- VRSHRsv16i8 = 1002,
- VRSHRsv1i64 = 1003,
- VRSHRsv2i32 = 1004,
- VRSHRsv2i64 = 1005,
- VRSHRsv4i16 = 1006,
- VRSHRsv4i32 = 1007,
- VRSHRsv8i16 = 1008,
- VRSHRsv8i8 = 1009,
- VRSHRuv16i8 = 1010,
- VRSHRuv1i64 = 1011,
- VRSHRuv2i32 = 1012,
- VRSHRuv2i64 = 1013,
- VRSHRuv4i16 = 1014,
- VRSHRuv4i32 = 1015,
- VRSHRuv8i16 = 1016,
- VRSHRuv8i8 = 1017,
- VRSQRTEd = 1018,
- VRSQRTEfd = 1019,
- VRSQRTEfq = 1020,
- VRSQRTEq = 1021,
- VRSQRTSfd = 1022,
- VRSQRTSfq = 1023,
- VRSRAsv16i8 = 1024,
- VRSRAsv1i64 = 1025,
- VRSRAsv2i32 = 1026,
- VRSRAsv2i64 = 1027,
- VRSRAsv4i16 = 1028,
- VRSRAsv4i32 = 1029,
- VRSRAsv8i16 = 1030,
- VRSRAsv8i8 = 1031,
- VRSRAuv16i8 = 1032,
- VRSRAuv1i64 = 1033,
- VRSRAuv2i32 = 1034,
- VRSRAuv2i64 = 1035,
- VRSRAuv4i16 = 1036,
- VRSRAuv4i32 = 1037,
- VRSRAuv8i16 = 1038,
- VRSRAuv8i8 = 1039,
- VRSUBHNv2i32 = 1040,
- VRSUBHNv4i16 = 1041,
- VRSUBHNv8i8 = 1042,
- VSETLNi16 = 1043,
- VSETLNi32 = 1044,
- VSETLNi8 = 1045,
- VSHLLi16 = 1046,
- VSHLLi32 = 1047,
- VSHLLi8 = 1048,
- VSHLLsv2i64 = 1049,
- VSHLLsv4i32 = 1050,
- VSHLLsv8i16 = 1051,
- VSHLLuv2i64 = 1052,
- VSHLLuv4i32 = 1053,
- VSHLLuv8i16 = 1054,
- VSHLiv16i8 = 1055,
- VSHLiv1i64 = 1056,
- VSHLiv2i32 = 1057,
- VSHLiv2i64 = 1058,
- VSHLiv4i16 = 1059,
- VSHLiv4i32 = 1060,
- VSHLiv8i16 = 1061,
- VSHLiv8i8 = 1062,
- VSHLsv16i8 = 1063,
- VSHLsv1i64 = 1064,
- VSHLsv2i32 = 1065,
- VSHLsv2i64 = 1066,
- VSHLsv4i16 = 1067,
- VSHLsv4i32 = 1068,
- VSHLsv8i16 = 1069,
- VSHLsv8i8 = 1070,
- VSHLuv16i8 = 1071,
- VSHLuv1i64 = 1072,
- VSHLuv2i32 = 1073,
- VSHLuv2i64 = 1074,
- VSHLuv4i16 = 1075,
- VSHLuv4i32 = 1076,
- VSHLuv8i16 = 1077,
- VSHLuv8i8 = 1078,
- VSHRNv2i32 = 1079,
- VSHRNv4i16 = 1080,
- VSHRNv8i8 = 1081,
- VSHRsv16i8 = 1082,
- VSHRsv1i64 = 1083,
- VSHRsv2i32 = 1084,
- VSHRsv2i64 = 1085,
- VSHRsv4i16 = 1086,
- VSHRsv4i32 = 1087,
- VSHRsv8i16 = 1088,
- VSHRsv8i8 = 1089,
- VSHRuv16i8 = 1090,
- VSHRuv1i64 = 1091,
- VSHRuv2i32 = 1092,
- VSHRuv2i64 = 1093,
- VSHRuv4i16 = 1094,
- VSHRuv4i32 = 1095,
- VSHRuv8i16 = 1096,
- VSHRuv8i8 = 1097,
- VSHTOD = 1098,
- VSHTOS = 1099,
- VSITOD = 1100,
- VSITOS = 1101,
- VSLIv16i8 = 1102,
- VSLIv1i64 = 1103,
- VSLIv2i32 = 1104,
- VSLIv2i64 = 1105,
- VSLIv4i16 = 1106,
- VSLIv4i32 = 1107,
- VSLIv8i16 = 1108,
- VSLIv8i8 = 1109,
- VSLTOD = 1110,
- VSLTOS = 1111,
- VSQRTD = 1112,
- VSQRTS = 1113,
- VSRAsv16i8 = 1114,
- VSRAsv1i64 = 1115,
- VSRAsv2i32 = 1116,
- VSRAsv2i64 = 1117,
- VSRAsv4i16 = 1118,
- VSRAsv4i32 = 1119,
- VSRAsv8i16 = 1120,
- VSRAsv8i8 = 1121,
- VSRAuv16i8 = 1122,
- VSRAuv1i64 = 1123,
- VSRAuv2i32 = 1124,
- VSRAuv2i64 = 1125,
- VSRAuv4i16 = 1126,
- VSRAuv4i32 = 1127,
- VSRAuv8i16 = 1128,
- VSRAuv8i8 = 1129,
- VSRIv16i8 = 1130,
- VSRIv1i64 = 1131,
- VSRIv2i32 = 1132,
- VSRIv2i64 = 1133,
- VSRIv4i16 = 1134,
- VSRIv4i32 = 1135,
- VSRIv8i16 = 1136,
- VSRIv8i8 = 1137,
- VST1d16 = 1138,
- VST1d32 = 1139,
- VST1d64 = 1140,
- VST1d8 = 1141,
- VST1df = 1142,
- VST1q16 = 1143,
- VST1q32 = 1144,
- VST1q64 = 1145,
- VST1q8 = 1146,
- VST1qf = 1147,
- VST2LNd16 = 1148,
- VST2LNd32 = 1149,
- VST2LNd8 = 1150,
- VST2LNq16a = 1151,
- VST2LNq16b = 1152,
- VST2LNq32a = 1153,
- VST2LNq32b = 1154,
- VST2d16 = 1155,
- VST2d32 = 1156,
- VST2d64 = 1157,
- VST2d8 = 1158,
- VST2q16 = 1159,
- VST2q32 = 1160,
- VST2q8 = 1161,
- VST3LNd16 = 1162,
- VST3LNd32 = 1163,
- VST3LNd8 = 1164,
- VST3LNq16a = 1165,
- VST3LNq16b = 1166,
- VST3LNq32a = 1167,
- VST3LNq32b = 1168,
- VST3d16 = 1169,
- VST3d32 = 1170,
- VST3d64 = 1171,
- VST3d8 = 1172,
- VST3q16a = 1173,
- VST3q16b = 1174,
- VST3q32a = 1175,
- VST3q32b = 1176,
- VST3q8a = 1177,
- VST3q8b = 1178,
- VST4LNd16 = 1179,
- VST4LNd32 = 1180,
- VST4LNd8 = 1181,
- VST4LNq16a = 1182,
- VST4LNq16b = 1183,
- VST4LNq32a = 1184,
- VST4LNq32b = 1185,
- VST4d16 = 1186,
- VST4d32 = 1187,
- VST4d64 = 1188,
- VST4d8 = 1189,
- VST4q16a = 1190,
- VST4q16b = 1191,
- VST4q32a = 1192,
- VST4q32b = 1193,
- VST4q8a = 1194,
- VST4q8b = 1195,
- VSTMD = 1196,
- VSTMS = 1197,
- VSTRD = 1198,
- VSTRQ = 1199,
- VSTRS = 1200,
- VSUBD = 1201,
- VSUBHNv2i32 = 1202,
- VSUBHNv4i16 = 1203,
- VSUBHNv8i8 = 1204,
- VSUBLsv2i64 = 1205,
- VSUBLsv4i32 = 1206,
- VSUBLsv8i16 = 1207,
- VSUBLuv2i64 = 1208,
- VSUBLuv4i32 = 1209,
- VSUBLuv8i16 = 1210,
- VSUBS = 1211,
- VSUBWsv2i64 = 1212,
- VSUBWsv4i32 = 1213,
- VSUBWsv8i16 = 1214,
- VSUBWuv2i64 = 1215,
- VSUBWuv4i32 = 1216,
- VSUBWuv8i16 = 1217,
- VSUBfd = 1218,
- VSUBfd_sfp = 1219,
- VSUBfq = 1220,
- VSUBv16i8 = 1221,
- VSUBv1i64 = 1222,
- VSUBv2i32 = 1223,
- VSUBv2i64 = 1224,
- VSUBv4i16 = 1225,
- VSUBv4i32 = 1226,
- VSUBv8i16 = 1227,
- VSUBv8i8 = 1228,
- VTBL1 = 1229,
- VTBL2 = 1230,
- VTBL3 = 1231,
- VTBL4 = 1232,
- VTBX1 = 1233,
- VTBX2 = 1234,
- VTBX3 = 1235,
- VTBX4 = 1236,
- VTOSHD = 1237,
- VTOSHS = 1238,
- VTOSIRD = 1239,
- VTOSIRS = 1240,
- VTOSIZD = 1241,
- VTOSIZS = 1242,
- VTOSLD = 1243,
- VTOSLS = 1244,
- VTOUHD = 1245,
- VTOUHS = 1246,
- VTOUIRD = 1247,
- VTOUIRS = 1248,
- VTOUIZD = 1249,
- VTOUIZS = 1250,
- VTOULD = 1251,
- VTOULS = 1252,
- VTRNd16 = 1253,
- VTRNd32 = 1254,
- VTRNd8 = 1255,
- VTRNq16 = 1256,
- VTRNq32 = 1257,
- VTRNq8 = 1258,
- VTSTv16i8 = 1259,
- VTSTv2i32 = 1260,
- VTSTv4i16 = 1261,
- VTSTv4i32 = 1262,
- VTSTv8i16 = 1263,
- VTSTv8i8 = 1264,
- VUHTOD = 1265,
- VUHTOS = 1266,
- VUITOD = 1267,
- VUITOS = 1268,
- VULTOD = 1269,
- VULTOS = 1270,
- VUZPd16 = 1271,
- VUZPd32 = 1272,
- VUZPd8 = 1273,
- VUZPq16 = 1274,
- VUZPq32 = 1275,
- VUZPq8 = 1276,
- VZIPd16 = 1277,
- VZIPd32 = 1278,
- VZIPd8 = 1279,
- VZIPq16 = 1280,
- VZIPq32 = 1281,
- VZIPq8 = 1282,
- WFE = 1283,
- WFI = 1284,
- YIELD = 1285,
- t2ADCSri = 1286,
- t2ADCSrr = 1287,
- t2ADCSrs = 1288,
- t2ADCri = 1289,
- t2ADCrr = 1290,
- t2ADCrs = 1291,
- t2ADDSri = 1292,
- t2ADDSrr = 1293,
- t2ADDSrs = 1294,
- t2ADDrSPi = 1295,
- t2ADDrSPi12 = 1296,
- t2ADDrSPs = 1297,
- t2ADDri = 1298,
- t2ADDri12 = 1299,
- t2ADDrr = 1300,
- t2ADDrs = 1301,
- t2ANDri = 1302,
- t2ANDrr = 1303,
- t2ANDrs = 1304,
- t2ASRri = 1305,
- t2ASRrr = 1306,
- t2B = 1307,
- t2BFC = 1308,
- t2BFI = 1309,
- t2BICri = 1310,
- t2BICrr = 1311,
- t2BICrs = 1312,
- t2BR_JT = 1313,
- t2Bcc = 1314,
- t2CLZ = 1315,
- t2CMNzri = 1316,
- t2CMNzrr = 1317,
- t2CMNzrs = 1318,
- t2CMPri = 1319,
- t2CMPrr = 1320,
- t2CMPrs = 1321,
- t2CMPzri = 1322,
- t2CMPzrr = 1323,
- t2CMPzrs = 1324,
- t2EORri = 1325,
- t2EORrr = 1326,
- t2EORrs = 1327,
- t2IT = 1328,
- t2Int_MemBarrierV7 = 1329,
- t2Int_SyncBarrierV7 = 1330,
- t2Int_eh_sjlj_setjmp = 1331,
- t2LDM = 1332,
- t2LDM_RET = 1333,
- t2LDRB_POST = 1334,
- t2LDRB_PRE = 1335,
- t2LDRBi12 = 1336,
- t2LDRBi8 = 1337,
- t2LDRBpci = 1338,
- t2LDRBs = 1339,
- t2LDRDi8 = 1340,
- t2LDRDpci = 1341,
- t2LDREX = 1342,
- t2LDREXB = 1343,
- t2LDREXD = 1344,
- t2LDREXH = 1345,
- t2LDRH_POST = 1346,
- t2LDRH_PRE = 1347,
- t2LDRHi12 = 1348,
- t2LDRHi8 = 1349,
- t2LDRHpci = 1350,
- t2LDRHs = 1351,
- t2LDRSB_POST = 1352,
- t2LDRSB_PRE = 1353,
- t2LDRSBi12 = 1354,
- t2LDRSBi8 = 1355,
- t2LDRSBpci = 1356,
- t2LDRSBs = 1357,
- t2LDRSH_POST = 1358,
- t2LDRSH_PRE = 1359,
- t2LDRSHi12 = 1360,
- t2LDRSHi8 = 1361,
- t2LDRSHpci = 1362,
- t2LDRSHs = 1363,
- t2LDR_POST = 1364,
- t2LDR_PRE = 1365,
- t2LDRi12 = 1366,
- t2LDRi8 = 1367,
- t2LDRpci = 1368,
- t2LDRpci_pic = 1369,
- t2LDRs = 1370,
- t2LEApcrel = 1371,
- t2LEApcrelJT = 1372,
- t2LSLri = 1373,
- t2LSLrr = 1374,
- t2LSRri = 1375,
- t2LSRrr = 1376,
- t2MLA = 1377,
- t2MLS = 1378,
- t2MOVCCasr = 1379,
- t2MOVCCi = 1380,
- t2MOVCClsl = 1381,
- t2MOVCClsr = 1382,
- t2MOVCCr = 1383,
- t2MOVCCror = 1384,
- t2MOVTi16 = 1385,
- t2MOVi = 1386,
- t2MOVi16 = 1387,
- t2MOVi32imm = 1388,
- t2MOVr = 1389,
- t2MOVrx = 1390,
- t2MOVsra_flag = 1391,
- t2MOVsrl_flag = 1392,
- t2MUL = 1393,
- t2MVNi = 1394,
- t2MVNr = 1395,
- t2MVNs = 1396,
- t2ORNri = 1397,
- t2ORNrr = 1398,
- t2ORNrs = 1399,
- t2ORRri = 1400,
- t2ORRrr = 1401,
- t2ORRrs = 1402,
- t2PKHBT = 1403,
- t2PKHTB = 1404,
- t2RBIT = 1405,
- t2REV = 1406,
- t2REV16 = 1407,
- t2REVSH = 1408,
- t2RORri = 1409,
- t2RORrr = 1410,
- t2RSBSri = 1411,
- t2RSBSrs = 1412,
- t2RSBri = 1413,
- t2RSBrs = 1414,
- t2SBCSri = 1415,
- t2SBCSrr = 1416,
- t2SBCSrs = 1417,
- t2SBCri = 1418,
- t2SBCrr = 1419,
- t2SBCrs = 1420,
- t2SBFX = 1421,
- t2SMLABB = 1422,
- t2SMLABT = 1423,
- t2SMLAL = 1424,
- t2SMLATB = 1425,
- t2SMLATT = 1426,
- t2SMLAWB = 1427,
- t2SMLAWT = 1428,
- t2SMMLA = 1429,
- t2SMMLS = 1430,
- t2SMMUL = 1431,
- t2SMULBB = 1432,
- t2SMULBT = 1433,
- t2SMULL = 1434,
- t2SMULTB = 1435,
- t2SMULTT = 1436,
- t2SMULWB = 1437,
- t2SMULWT = 1438,
- t2STM = 1439,
- t2STRB_POST = 1440,
- t2STRB_PRE = 1441,
- t2STRBi12 = 1442,
- t2STRBi8 = 1443,
- t2STRBs = 1444,
- t2STRDi8 = 1445,
- t2STREX = 1446,
- t2STREXB = 1447,
- t2STREXD = 1448,
- t2STREXH = 1449,
- t2STRH_POST = 1450,
- t2STRH_PRE = 1451,
- t2STRHi12 = 1452,
- t2STRHi8 = 1453,
- t2STRHs = 1454,
- t2STR_POST = 1455,
- t2STR_PRE = 1456,
- t2STRi12 = 1457,
- t2STRi8 = 1458,
- t2STRs = 1459,
- t2SUBSri = 1460,
- t2SUBSrr = 1461,
- t2SUBSrs = 1462,
- t2SUBrSPi = 1463,
- t2SUBrSPi12 = 1464,
- t2SUBrSPi12_ = 1465,
- t2SUBrSPi_ = 1466,
- t2SUBrSPs = 1467,
- t2SUBrSPs_ = 1468,
- t2SUBri = 1469,
- t2SUBri12 = 1470,
- t2SUBrr = 1471,
- t2SUBrs = 1472,
- t2SXTABrr = 1473,
- t2SXTABrr_rot = 1474,
- t2SXTAHrr = 1475,
- t2SXTAHrr_rot = 1476,
- t2SXTBr = 1477,
- t2SXTBr_rot = 1478,
- t2SXTHr = 1479,
- t2SXTHr_rot = 1480,
- t2TBB = 1481,
- t2TBH = 1482,
- t2TEQri = 1483,
- t2TEQrr = 1484,
- t2TEQrs = 1485,
- t2TPsoft = 1486,
- t2TSTri = 1487,
- t2TSTrr = 1488,
- t2TSTrs = 1489,
- t2UBFX = 1490,
- t2UMAAL = 1491,
- t2UMLAL = 1492,
- t2UMULL = 1493,
- t2UXTABrr = 1494,
- t2UXTABrr_rot = 1495,
- t2UXTAHrr = 1496,
- t2UXTAHrr_rot = 1497,
- t2UXTB16r = 1498,
- t2UXTB16r_rot = 1499,
- t2UXTBr = 1500,
- t2UXTBr_rot = 1501,
- t2UXTHr = 1502,
- t2UXTHr_rot = 1503,
- tADC = 1504,
- tADDhirr = 1505,
- tADDi3 = 1506,
- tADDi8 = 1507,
- tADDrPCi = 1508,
- tADDrSP = 1509,
- tADDrSPi = 1510,
- tADDrr = 1511,
- tADDspi = 1512,
- tADDspr = 1513,
- tADDspr_ = 1514,
- tADJCALLSTACKDOWN = 1515,
- tADJCALLSTACKUP = 1516,
- tAND = 1517,
- tANDsp = 1518,
- tASRri = 1519,
- tASRrr = 1520,
- tB = 1521,
- tBIC = 1522,
- tBKPT = 1523,
- tBL = 1524,
- tBLXi = 1525,
- tBLXi_r9 = 1526,
- tBLXr = 1527,
- tBLXr_r9 = 1528,
- tBLr9 = 1529,
- tBRIND = 1530,
- tBR_JTr = 1531,
- tBX = 1532,
- tBX_RET = 1533,
- tBX_RET_vararg = 1534,
- tBXr9 = 1535,
- tBcc = 1536,
- tBfar = 1537,
- tCBNZ = 1538,
- tCBZ = 1539,
- tCMNz = 1540,
- tCMPhir = 1541,
- tCMPi8 = 1542,
- tCMPr = 1543,
- tCMPzhir = 1544,
- tCMPzi8 = 1545,
- tCMPzr = 1546,
- tEOR = 1547,
- tInt_eh_sjlj_setjmp = 1548,
- tLDM = 1549,
- tLDR = 1550,
- tLDRB = 1551,
- tLDRBi = 1552,
- tLDRH = 1553,
- tLDRHi = 1554,
- tLDRSB = 1555,
- tLDRSH = 1556,
- tLDRcp = 1557,
- tLDRi = 1558,
- tLDRpci = 1559,
- tLDRpci_pic = 1560,
- tLDRspi = 1561,
- tLEApcrel = 1562,
- tLEApcrelJT = 1563,
- tLSLri = 1564,
- tLSLrr = 1565,
- tLSRri = 1566,
- tLSRrr = 1567,
- tMOVCCi = 1568,
- tMOVCCr = 1569,
- tMOVCCr_pseudo = 1570,
- tMOVSr = 1571,
- tMOVgpr2gpr = 1572,
- tMOVgpr2tgpr = 1573,
- tMOVi8 = 1574,
- tMOVr = 1575,
- tMOVtgpr2gpr = 1576,
- tMUL = 1577,
- tMVN = 1578,
- tORR = 1579,
- tPICADD = 1580,
- tPOP = 1581,
- tPOP_RET = 1582,
- tPUSH = 1583,
- tREV = 1584,
- tREV16 = 1585,
- tREVSH = 1586,
- tROR = 1587,
- tRSB = 1588,
- tRestore = 1589,
- tSBC = 1590,
- tSTM = 1591,
- tSTR = 1592,
- tSTRB = 1593,
- tSTRBi = 1594,
- tSTRH = 1595,
- tSTRHi = 1596,
- tSTRi = 1597,
- tSTRspi = 1598,
- tSUBi3 = 1599,
- tSUBi8 = 1600,
- tSUBrr = 1601,
- tSUBspi = 1602,
- tSUBspi_ = 1603,
- tSXTB = 1604,
- tSXTH = 1605,
- tSpill = 1606,
- tTPsoft = 1607,
- tTST = 1608,
- tUXTB = 1609,
- tUXTH = 1610,
- INSTRUCTION_LIST_END = 1611
+ BFI = 55,
+ BICri = 56,
+ BICrr = 57,
+ BICrs = 58,
+ BKPT = 59,
+ BL = 60,
+ BLX = 61,
+ BLXr9 = 62,
+ BL_pred = 63,
+ BLr9 = 64,
+ BLr9_pred = 65,
+ BRIND = 66,
+ BR_JTadd = 67,
+ BR_JTm = 68,
+ BR_JTr = 69,
+ BX = 70,
+ BXJ = 71,
+ BX_RET = 72,
+ BXr9 = 73,
+ Bcc = 74,
+ CDP = 75,
+ CDP2 = 76,
+ CLREX = 77,
+ CLZ = 78,
+ CMNzri = 79,
+ CMNzrr = 80,
+ CMNzrs = 81,
+ CMPri = 82,
+ CMPrr = 83,
+ CMPrs = 84,
+ CMPzri = 85,
+ CMPzrr = 86,
+ CMPzrs = 87,
+ CONSTPOOL_ENTRY = 88,
+ CPS = 89,
+ DBG = 90,
+ DMBish = 91,
+ DMBishst = 92,
+ DMBnsh = 93,
+ DMBnshst = 94,
+ DMBosh = 95,
+ DMBoshst = 96,
+ DMBst = 97,
+ DSBish = 98,
+ DSBishst = 99,
+ DSBnsh = 100,
+ DSBnshst = 101,
+ DSBosh = 102,
+ DSBoshst = 103,
+ DSBst = 104,
+ EORri = 105,
+ EORrr = 106,
+ EORrs = 107,
+ FCONSTD = 108,
+ FCONSTS = 109,
+ FMSTAT = 110,
+ ISBsy = 111,
+ Int_MemBarrierV6 = 112,
+ Int_MemBarrierV7 = 113,
+ Int_SyncBarrierV6 = 114,
+ Int_SyncBarrierV7 = 115,
+ Int_eh_sjlj_setjmp = 116,
+ LDC2L_OFFSET = 117,
+ LDC2L_OPTION = 118,
+ LDC2L_POST = 119,
+ LDC2L_PRE = 120,
+ LDC2_OFFSET = 121,
+ LDC2_OPTION = 122,
+ LDC2_POST = 123,
+ LDC2_PRE = 124,
+ LDCL_OFFSET = 125,
+ LDCL_OPTION = 126,
+ LDCL_POST = 127,
+ LDCL_PRE = 128,
+ LDC_OFFSET = 129,
+ LDC_OPTION = 130,
+ LDC_POST = 131,
+ LDC_PRE = 132,
+ LDM = 133,
+ LDM_RET = 134,
+ LDR = 135,
+ LDRB = 136,
+ LDRBT = 137,
+ LDRB_POST = 138,
+ LDRB_PRE = 139,
+ LDRD = 140,
+ LDRD_POST = 141,
+ LDRD_PRE = 142,
+ LDREX = 143,
+ LDREXB = 144,
+ LDREXD = 145,
+ LDREXH = 146,
+ LDRH = 147,
+ LDRHT = 148,
+ LDRH_POST = 149,
+ LDRH_PRE = 150,
+ LDRSB = 151,
+ LDRSBT = 152,
+ LDRSB_POST = 153,
+ LDRSB_PRE = 154,
+ LDRSH = 155,
+ LDRSHT = 156,
+ LDRSH_POST = 157,
+ LDRSH_PRE = 158,
+ LDRT = 159,
+ LDR_POST = 160,
+ LDR_PRE = 161,
+ LDRcp = 162,
+ LEApcrel = 163,
+ LEApcrelJT = 164,
+ MCR = 165,
+ MCR2 = 166,
+ MCRR = 167,
+ MCRR2 = 168,
+ MLA = 169,
+ MLS = 170,
+ MOVCCi = 171,
+ MOVCCr = 172,
+ MOVCCs = 173,
+ MOVTi16 = 174,
+ MOVi = 175,
+ MOVi16 = 176,
+ MOVi2pieces = 177,
+ MOVi32imm = 178,
+ MOVr = 179,
+ MOVrx = 180,
+ MOVs = 181,
+ MOVsra_flag = 182,
+ MOVsrl_flag = 183,
+ MRC = 184,
+ MRC2 = 185,
+ MRRC = 186,
+ MRRC2 = 187,
+ MRS = 188,
+ MRSsys = 189,
+ MSR = 190,
+ MSRi = 191,
+ MSRsys = 192,
+ MSRsysi = 193,
+ MUL = 194,
+ MVNi = 195,
+ MVNr = 196,
+ MVNs = 197,
+ NOP = 198,
+ ORRri = 199,
+ ORRrr = 200,
+ ORRrs = 201,
+ PICADD = 202,
+ PICLDR = 203,
+ PICLDRB = 204,
+ PICLDRH = 205,
+ PICLDRSB = 206,
+ PICLDRSH = 207,
+ PICSTR = 208,
+ PICSTRB = 209,
+ PICSTRH = 210,
+ PKHBT = 211,
+ PKHTB = 212,
+ PLDWi = 213,
+ PLDWr = 214,
+ PLDi = 215,
+ PLDr = 216,
+ PLIi = 217,
+ PLIr = 218,
+ QADD = 219,
+ QADD16 = 220,
+ QADD8 = 221,
+ QASX = 222,
+ QDADD = 223,
+ QDSUB = 224,
+ QSAX = 225,
+ QSUB = 226,
+ QSUB16 = 227,
+ QSUB8 = 228,
+ RBIT = 229,
+ REV = 230,
+ REV16 = 231,
+ REVSH = 232,
+ RFE = 233,
+ RFEW = 234,
+ RSBSri = 235,
+ RSBSrs = 236,
+ RSBri = 237,
+ RSBrs = 238,
+ RSCSri = 239,
+ RSCSrs = 240,
+ RSCri = 241,
+ RSCrs = 242,
+ SADD16 = 243,
+ SADD8 = 244,
+ SASX = 245,
+ SBCSSri = 246,
+ SBCSSrr = 247,
+ SBCSSrs = 248,
+ SBCri = 249,
+ SBCrr = 250,
+ SBCrs = 251,
+ SBFX = 252,
+ SEL = 253,
+ SETENDBE = 254,
+ SETENDLE = 255,
+ SEV = 256,
+ SHADD16 = 257,
+ SHADD8 = 258,
+ SHASX = 259,
+ SHSAX = 260,
+ SHSUB16 = 261,
+ SHSUB8 = 262,
+ SMC = 263,
+ SMLABB = 264,
+ SMLABT = 265,
+ SMLAD = 266,
+ SMLADX = 267,
+ SMLAL = 268,
+ SMLALBB = 269,
+ SMLALBT = 270,
+ SMLALD = 271,
+ SMLALDX = 272,
+ SMLALTB = 273,
+ SMLALTT = 274,
+ SMLATB = 275,
+ SMLATT = 276,
+ SMLAWB = 277,
+ SMLAWT = 278,
+ SMLSD = 279,
+ SMLSDX = 280,
+ SMLSLD = 281,
+ SMLSLDX = 282,
+ SMMLA = 283,
+ SMMLAR = 284,
+ SMMLS = 285,
+ SMMLSR = 286,
+ SMMUL = 287,
+ SMMULR = 288,
+ SMUAD = 289,
+ SMUADX = 290,
+ SMULBB = 291,
+ SMULBT = 292,
+ SMULL = 293,
+ SMULTB = 294,
+ SMULTT = 295,
+ SMULWB = 296,
+ SMULWT = 297,
+ SMUSD = 298,
+ SMUSDX = 299,
+ SRS = 300,
+ SRSW = 301,
+ SSAT16 = 302,
+ SSATasr = 303,
+ SSATlsl = 304,
+ SSAX = 305,
+ SSUB16 = 306,
+ SSUB8 = 307,
+ STC2L_OFFSET = 308,
+ STC2L_OPTION = 309,
+ STC2L_POST = 310,
+ STC2L_PRE = 311,
+ STC2_OFFSET = 312,
+ STC2_OPTION = 313,
+ STC2_POST = 314,
+ STC2_PRE = 315,
+ STCL_OFFSET = 316,
+ STCL_OPTION = 317,
+ STCL_POST = 318,
+ STCL_PRE = 319,
+ STC_OFFSET = 320,
+ STC_OPTION = 321,
+ STC_POST = 322,
+ STC_PRE = 323,
+ STM = 324,
+ STR = 325,
+ STRB = 326,
+ STRBT = 327,
+ STRB_POST = 328,
+ STRB_PRE = 329,
+ STRD = 330,
+ STRD_POST = 331,
+ STRD_PRE = 332,
+ STREX = 333,
+ STREXB = 334,
+ STREXD = 335,
+ STREXH = 336,
+ STRH = 337,
+ STRHT = 338,
+ STRH_POST = 339,
+ STRH_PRE = 340,
+ STRT = 341,
+ STR_POST = 342,
+ STR_PRE = 343,
+ SUBSri = 344,
+ SUBSrr = 345,
+ SUBSrs = 346,
+ SUBri = 347,
+ SUBrr = 348,
+ SUBrs = 349,
+ SVC = 350,
+ SWP = 351,
+ SWPB = 352,
+ SXTAB16rr = 353,
+ SXTAB16rr_rot = 354,
+ SXTABrr = 355,
+ SXTABrr_rot = 356,
+ SXTAHrr = 357,
+ SXTAHrr_rot = 358,
+ SXTB16r = 359,
+ SXTB16r_rot = 360,
+ SXTBr = 361,
+ SXTBr_rot = 362,
+ SXTHr = 363,
+ SXTHr_rot = 364,
+ TEQri = 365,
+ TEQrr = 366,
+ TEQrs = 367,
+ TPsoft = 368,
+ TRAP = 369,
+ TSTri = 370,
+ TSTrr = 371,
+ TSTrs = 372,
+ UADD16 = 373,
+ UADD8 = 374,
+ UASX = 375,
+ UBFX = 376,
+ UHADD16 = 377,
+ UHADD8 = 378,
+ UHASX = 379,
+ UHSAX = 380,
+ UHSUB16 = 381,
+ UHSUB8 = 382,
+ UMAAL = 383,
+ UMLAL = 384,
+ UMULL = 385,
+ UQADD16 = 386,
+ UQADD8 = 387,
+ UQASX = 388,
+ UQSAX = 389,
+ UQSUB16 = 390,
+ UQSUB8 = 391,
+ USAD8 = 392,
+ USADA8 = 393,
+ USAT16 = 394,
+ USATasr = 395,
+ USATlsl = 396,
+ USAX = 397,
+ USUB16 = 398,
+ USUB8 = 399,
+ UXTAB16rr = 400,
+ UXTAB16rr_rot = 401,
+ UXTABrr = 402,
+ UXTABrr_rot = 403,
+ UXTAHrr = 404,
+ UXTAHrr_rot = 405,
+ UXTB16r = 406,
+ UXTB16r_rot = 407,
+ UXTBr = 408,
+ UXTBr_rot = 409,
+ UXTHr = 410,
+ UXTHr_rot = 411,
+ VABALsv2i64 = 412,
+ VABALsv4i32 = 413,
+ VABALsv8i16 = 414,
+ VABALuv2i64 = 415,
+ VABALuv4i32 = 416,
+ VABALuv8i16 = 417,
+ VABAsv16i8 = 418,
+ VABAsv2i32 = 419,
+ VABAsv4i16 = 420,
+ VABAsv4i32 = 421,
+ VABAsv8i16 = 422,
+ VABAsv8i8 = 423,
+ VABAuv16i8 = 424,
+ VABAuv2i32 = 425,
+ VABAuv4i16 = 426,
+ VABAuv4i32 = 427,
+ VABAuv8i16 = 428,
+ VABAuv8i8 = 429,
+ VABDLsv2i64 = 430,
+ VABDLsv4i32 = 431,
+ VABDLsv8i16 = 432,
+ VABDLuv2i64 = 433,
+ VABDLuv4i32 = 434,
+ VABDLuv8i16 = 435,
+ VABDfd = 436,
+ VABDfq = 437,
+ VABDsv16i8 = 438,
+ VABDsv2i32 = 439,
+ VABDsv4i16 = 440,
+ VABDsv4i32 = 441,
+ VABDsv8i16 = 442,
+ VABDsv8i8 = 443,
+ VABDuv16i8 = 444,
+ VABDuv2i32 = 445,
+ VABDuv4i16 = 446,
+ VABDuv4i32 = 447,
+ VABDuv8i16 = 448,
+ VABDuv8i8 = 449,
+ VABSD = 450,
+ VABSS = 451,
+ VABSfd = 452,
+ VABSfd_sfp = 453,
+ VABSfq = 454,
+ VABSv16i8 = 455,
+ VABSv2i32 = 456,
+ VABSv4i16 = 457,
+ VABSv4i32 = 458,
+ VABSv8i16 = 459,
+ VABSv8i8 = 460,
+ VACGEd = 461,
+ VACGEq = 462,
+ VACGTd = 463,
+ VACGTq = 464,
+ VADDD = 465,
+ VADDHNv2i32 = 466,
+ VADDHNv4i16 = 467,
+ VADDHNv8i8 = 468,
+ VADDLsv2i64 = 469,
+ VADDLsv4i32 = 470,
+ VADDLsv8i16 = 471,
+ VADDLuv2i64 = 472,
+ VADDLuv4i32 = 473,
+ VADDLuv8i16 = 474,
+ VADDS = 475,
+ VADDWsv2i64 = 476,
+ VADDWsv4i32 = 477,
+ VADDWsv8i16 = 478,
+ VADDWuv2i64 = 479,
+ VADDWuv4i32 = 480,
+ VADDWuv8i16 = 481,
+ VADDfd = 482,
+ VADDfd_sfp = 483,
+ VADDfq = 484,
+ VADDv16i8 = 485,
+ VADDv1i64 = 486,
+ VADDv2i32 = 487,
+ VADDv2i64 = 488,
+ VADDv4i16 = 489,
+ VADDv4i32 = 490,
+ VADDv8i16 = 491,
+ VADDv8i8 = 492,
+ VANDd = 493,
+ VANDq = 494,
+ VBICd = 495,
+ VBICq = 496,
+ VBIFd = 497,
+ VBIFq = 498,
+ VBITd = 499,
+ VBITq = 500,
+ VBSLd = 501,
+ VBSLq = 502,
+ VCEQfd = 503,
+ VCEQfq = 504,
+ VCEQv16i8 = 505,
+ VCEQv2i32 = 506,
+ VCEQv4i16 = 507,
+ VCEQv4i32 = 508,
+ VCEQv8i16 = 509,
+ VCEQv8i8 = 510,
+ VCEQzv16i8 = 511,
+ VCEQzv2f32 = 512,
+ VCEQzv2i32 = 513,
+ VCEQzv4f32 = 514,
+ VCEQzv4i16 = 515,
+ VCEQzv4i32 = 516,
+ VCEQzv8i16 = 517,
+ VCEQzv8i8 = 518,
+ VCGEfd = 519,
+ VCGEfq = 520,
+ VCGEsv16i8 = 521,
+ VCGEsv2i32 = 522,
+ VCGEsv4i16 = 523,
+ VCGEsv4i32 = 524,
+ VCGEsv8i16 = 525,
+ VCGEsv8i8 = 526,
+ VCGEuv16i8 = 527,
+ VCGEuv2i32 = 528,
+ VCGEuv4i16 = 529,
+ VCGEuv4i32 = 530,
+ VCGEuv8i16 = 531,
+ VCGEuv8i8 = 532,
+ VCGEzv16i8 = 533,
+ VCGEzv2f32 = 534,
+ VCGEzv2i32 = 535,
+ VCGEzv4f32 = 536,
+ VCGEzv4i16 = 537,
+ VCGEzv4i32 = 538,
+ VCGEzv8i16 = 539,
+ VCGEzv8i8 = 540,
+ VCGTfd = 541,
+ VCGTfq = 542,
+ VCGTsv16i8 = 543,
+ VCGTsv2i32 = 544,
+ VCGTsv4i16 = 545,
+ VCGTsv4i32 = 546,
+ VCGTsv8i16 = 547,
+ VCGTsv8i8 = 548,
+ VCGTuv16i8 = 549,
+ VCGTuv2i32 = 550,
+ VCGTuv4i16 = 551,
+ VCGTuv4i32 = 552,
+ VCGTuv8i16 = 553,
+ VCGTuv8i8 = 554,
+ VCGTzv16i8 = 555,
+ VCGTzv2f32 = 556,
+ VCGTzv2i32 = 557,
+ VCGTzv4f32 = 558,
+ VCGTzv4i16 = 559,
+ VCGTzv4i32 = 560,
+ VCGTzv8i16 = 561,
+ VCGTzv8i8 = 562,
+ VCLEzv16i8 = 563,
+ VCLEzv2f32 = 564,
+ VCLEzv2i32 = 565,
+ VCLEzv4f32 = 566,
+ VCLEzv4i16 = 567,
+ VCLEzv4i32 = 568,
+ VCLEzv8i16 = 569,
+ VCLEzv8i8 = 570,
+ VCLSv16i8 = 571,
+ VCLSv2i32 = 572,
+ VCLSv4i16 = 573,
+ VCLSv4i32 = 574,
+ VCLSv8i16 = 575,
+ VCLSv8i8 = 576,
+ VCLTzv16i8 = 577,
+ VCLTzv2f32 = 578,
+ VCLTzv2i32 = 579,
+ VCLTzv4f32 = 580,
+ VCLTzv4i16 = 581,
+ VCLTzv4i32 = 582,
+ VCLTzv8i16 = 583,
+ VCLTzv8i8 = 584,
+ VCLZv16i8 = 585,
+ VCLZv2i32 = 586,
+ VCLZv4i16 = 587,
+ VCLZv4i32 = 588,
+ VCLZv8i16 = 589,
+ VCLZv8i8 = 590,
+ VCMPD = 591,
+ VCMPED = 592,
+ VCMPES = 593,
+ VCMPEZD = 594,
+ VCMPEZS = 595,
+ VCMPS = 596,
+ VCMPZD = 597,
+ VCMPZS = 598,
+ VCNTd = 599,
+ VCNTq = 600,
+ VCVTBHS = 601,
+ VCVTBSH = 602,
+ VCVTDS = 603,
+ VCVTSD = 604,
+ VCVTTHS = 605,
+ VCVTTSH = 606,
+ VCVTf2sd = 607,
+ VCVTf2sd_sfp = 608,
+ VCVTf2sq = 609,
+ VCVTf2ud = 610,
+ VCVTf2ud_sfp = 611,
+ VCVTf2uq = 612,
+ VCVTf2xsd = 613,
+ VCVTf2xsq = 614,
+ VCVTf2xud = 615,
+ VCVTf2xuq = 616,
+ VCVTs2fd = 617,
+ VCVTs2fd_sfp = 618,
+ VCVTs2fq = 619,
+ VCVTu2fd = 620,
+ VCVTu2fd_sfp = 621,
+ VCVTu2fq = 622,
+ VCVTxs2fd = 623,
+ VCVTxs2fq = 624,
+ VCVTxu2fd = 625,
+ VCVTxu2fq = 626,
+ VDIVD = 627,
+ VDIVS = 628,
+ VDUP16d = 629,
+ VDUP16q = 630,
+ VDUP32d = 631,
+ VDUP32q = 632,
+ VDUP8d = 633,
+ VDUP8q = 634,
+ VDUPLN16d = 635,
+ VDUPLN16q = 636,
+ VDUPLN32d = 637,
+ VDUPLN32q = 638,
+ VDUPLN8d = 639,
+ VDUPLN8q = 640,
+ VDUPLNfd = 641,
+ VDUPLNfq = 642,
+ VDUPfd = 643,
+ VDUPfdf = 644,
+ VDUPfq = 645,
+ VDUPfqf = 646,
+ VEORd = 647,
+ VEORq = 648,
+ VEXTd16 = 649,
+ VEXTd32 = 650,
+ VEXTd8 = 651,
+ VEXTdf = 652,
+ VEXTq16 = 653,
+ VEXTq32 = 654,
+ VEXTq8 = 655,
+ VEXTqf = 656,
+ VGETLNi32 = 657,
+ VGETLNs16 = 658,
+ VGETLNs8 = 659,
+ VGETLNu16 = 660,
+ VGETLNu8 = 661,
+ VHADDsv16i8 = 662,
+ VHADDsv2i32 = 663,
+ VHADDsv4i16 = 664,
+ VHADDsv4i32 = 665,
+ VHADDsv8i16 = 666,
+ VHADDsv8i8 = 667,
+ VHADDuv16i8 = 668,
+ VHADDuv2i32 = 669,
+ VHADDuv4i16 = 670,
+ VHADDuv4i32 = 671,
+ VHADDuv8i16 = 672,
+ VHADDuv8i8 = 673,
+ VHSUBsv16i8 = 674,
+ VHSUBsv2i32 = 675,
+ VHSUBsv4i16 = 676,
+ VHSUBsv4i32 = 677,
+ VHSUBsv8i16 = 678,
+ VHSUBsv8i8 = 679,
+ VHSUBuv16i8 = 680,
+ VHSUBuv2i32 = 681,
+ VHSUBuv4i16 = 682,
+ VHSUBuv4i32 = 683,
+ VHSUBuv8i16 = 684,
+ VHSUBuv8i8 = 685,
+ VLD1d16 = 686,
+ VLD1d16Q = 687,
+ VLD1d16T = 688,
+ VLD1d32 = 689,
+ VLD1d32Q = 690,
+ VLD1d32T = 691,
+ VLD1d64 = 692,
+ VLD1d8 = 693,
+ VLD1d8Q = 694,
+ VLD1d8T = 695,
+ VLD1df = 696,
+ VLD1q16 = 697,
+ VLD1q32 = 698,
+ VLD1q64 = 699,
+ VLD1q8 = 700,
+ VLD1qf = 701,
+ VLD2LNd16 = 702,
+ VLD2LNd32 = 703,
+ VLD2LNd8 = 704,
+ VLD2LNq16a = 705,
+ VLD2LNq16b = 706,
+ VLD2LNq32a = 707,
+ VLD2LNq32b = 708,
+ VLD2d16 = 709,
+ VLD2d16D = 710,
+ VLD2d32 = 711,
+ VLD2d32D = 712,
+ VLD2d64 = 713,
+ VLD2d8 = 714,
+ VLD2d8D = 715,
+ VLD2q16 = 716,
+ VLD2q32 = 717,
+ VLD2q8 = 718,
+ VLD3LNd16 = 719,
+ VLD3LNd32 = 720,
+ VLD3LNd8 = 721,
+ VLD3LNq16a = 722,
+ VLD3LNq16b = 723,
+ VLD3LNq32a = 724,
+ VLD3LNq32b = 725,
+ VLD3d16 = 726,
+ VLD3d32 = 727,
+ VLD3d64 = 728,
+ VLD3d8 = 729,
+ VLD3q16a = 730,
+ VLD3q16b = 731,
+ VLD3q32a = 732,
+ VLD3q32b = 733,
+ VLD3q8a = 734,
+ VLD3q8b = 735,
+ VLD4LNd16 = 736,
+ VLD4LNd32 = 737,
+ VLD4LNd8 = 738,
+ VLD4LNq16a = 739,
+ VLD4LNq16b = 740,
+ VLD4LNq32a = 741,
+ VLD4LNq32b = 742,
+ VLD4d16 = 743,
+ VLD4d32 = 744,
+ VLD4d64 = 745,
+ VLD4d8 = 746,
+ VLD4q16a = 747,
+ VLD4q16b = 748,
+ VLD4q32a = 749,
+ VLD4q32b = 750,
+ VLD4q8a = 751,
+ VLD4q8b = 752,
+ VLDMD = 753,
+ VLDMS = 754,
+ VLDRD = 755,
+ VLDRQ = 756,
+ VLDRS = 757,
+ VMAXfd = 758,
+ VMAXfd_sfp = 759,
+ VMAXfq = 760,
+ VMAXsv16i8 = 761,
+ VMAXsv2i32 = 762,
+ VMAXsv4i16 = 763,
+ VMAXsv4i32 = 764,
+ VMAXsv8i16 = 765,
+ VMAXsv8i8 = 766,
+ VMAXuv16i8 = 767,
+ VMAXuv2i32 = 768,
+ VMAXuv4i16 = 769,
+ VMAXuv4i32 = 770,
+ VMAXuv8i16 = 771,
+ VMAXuv8i8 = 772,
+ VMINfd = 773,
+ VMINfd_sfp = 774,
+ VMINfq = 775,
+ VMINsv16i8 = 776,
+ VMINsv2i32 = 777,
+ VMINsv4i16 = 778,
+ VMINsv4i32 = 779,
+ VMINsv8i16 = 780,
+ VMINsv8i8 = 781,
+ VMINuv16i8 = 782,
+ VMINuv2i32 = 783,
+ VMINuv4i16 = 784,
+ VMINuv4i32 = 785,
+ VMINuv8i16 = 786,
+ VMINuv8i8 = 787,
+ VMLAD = 788,
+ VMLALslsv2i32 = 789,
+ VMLALslsv4i16 = 790,
+ VMLALsluv2i32 = 791,
+ VMLALsluv4i16 = 792,
+ VMLALsv2i64 = 793,
+ VMLALsv4i32 = 794,
+ VMLALsv8i16 = 795,
+ VMLALuv2i64 = 796,
+ VMLALuv4i32 = 797,
+ VMLALuv8i16 = 798,
+ VMLAS = 799,
+ VMLAfd = 800,
+ VMLAfq = 801,
+ VMLAslfd = 802,
+ VMLAslfq = 803,
+ VMLAslv2i32 = 804,
+ VMLAslv4i16 = 805,
+ VMLAslv4i32 = 806,
+ VMLAslv8i16 = 807,
+ VMLAv16i8 = 808,
+ VMLAv2i32 = 809,
+ VMLAv4i16 = 810,
+ VMLAv4i32 = 811,
+ VMLAv8i16 = 812,
+ VMLAv8i8 = 813,
+ VMLSD = 814,
+ VMLSLslsv2i32 = 815,
+ VMLSLslsv4i16 = 816,
+ VMLSLsluv2i32 = 817,
+ VMLSLsluv4i16 = 818,
+ VMLSLsv2i64 = 819,
+ VMLSLsv4i32 = 820,
+ VMLSLsv8i16 = 821,
+ VMLSLuv2i64 = 822,
+ VMLSLuv4i32 = 823,
+ VMLSLuv8i16 = 824,
+ VMLSS = 825,
+ VMLSfd = 826,
+ VMLSfq = 827,
+ VMLSslfd = 828,
+ VMLSslfq = 829,
+ VMLSslv2i32 = 830,
+ VMLSslv4i16 = 831,
+ VMLSslv4i32 = 832,
+ VMLSslv8i16 = 833,
+ VMLSv16i8 = 834,
+ VMLSv2i32 = 835,
+ VMLSv4i16 = 836,
+ VMLSv4i32 = 837,
+ VMLSv8i16 = 838,
+ VMLSv8i8 = 839,
+ VMOVD = 840,
+ VMOVDRR = 841,
+ VMOVDcc = 842,
+ VMOVDneon = 843,
+ VMOVLsv2i64 = 844,
+ VMOVLsv4i32 = 845,
+ VMOVLsv8i16 = 846,
+ VMOVLuv2i64 = 847,
+ VMOVLuv4i32 = 848,
+ VMOVLuv8i16 = 849,
+ VMOVNv2i32 = 850,
+ VMOVNv4i16 = 851,
+ VMOVNv8i8 = 852,
+ VMOVQ = 853,
+ VMOVRRD = 854,
+ VMOVRRS = 855,
+ VMOVRS = 856,
+ VMOVS = 857,
+ VMOVSR = 858,
+ VMOVSRR = 859,
+ VMOVScc = 860,
+ VMOVv16i8 = 861,
+ VMOVv1i64 = 862,
+ VMOVv2i32 = 863,
+ VMOVv2i64 = 864,
+ VMOVv4i16 = 865,
+ VMOVv4i32 = 866,
+ VMOVv8i16 = 867,
+ VMOVv8i8 = 868,
+ VMRS = 869,
+ VMSR = 870,
+ VMULD = 871,
+ VMULLp = 872,
+ VMULLslsv2i32 = 873,
+ VMULLslsv4i16 = 874,
+ VMULLsluv2i32 = 875,
+ VMULLsluv4i16 = 876,
+ VMULLsv2i64 = 877,
+ VMULLsv4i32 = 878,
+ VMULLsv8i16 = 879,
+ VMULLuv2i64 = 880,
+ VMULLuv4i32 = 881,
+ VMULLuv8i16 = 882,
+ VMULS = 883,
+ VMULfd = 884,
+ VMULfd_sfp = 885,
+ VMULfq = 886,
+ VMULpd = 887,
+ VMULpq = 888,
+ VMULslfd = 889,
+ VMULslfq = 890,
+ VMULslv2i32 = 891,
+ VMULslv4i16 = 892,
+ VMULslv4i32 = 893,
+ VMULslv8i16 = 894,
+ VMULv16i8 = 895,
+ VMULv2i32 = 896,
+ VMULv4i16 = 897,
+ VMULv4i32 = 898,
+ VMULv8i16 = 899,
+ VMULv8i8 = 900,
+ VMVNd = 901,
+ VMVNq = 902,
+ VNEGD = 903,
+ VNEGDcc = 904,
+ VNEGS = 905,
+ VNEGScc = 906,
+ VNEGf32q = 907,
+ VNEGfd = 908,
+ VNEGfd_sfp = 909,
+ VNEGs16d = 910,
+ VNEGs16q = 911,
+ VNEGs32d = 912,
+ VNEGs32q = 913,
+ VNEGs8d = 914,
+ VNEGs8q = 915,
+ VNMLAD = 916,
+ VNMLAS = 917,
+ VNMLSD = 918,
+ VNMLSS = 919,
+ VNMULD = 920,
+ VNMULS = 921,
+ VORNd = 922,
+ VORNq = 923,
+ VORRd = 924,
+ VORRq = 925,
+ VPADALsv16i8 = 926,
+ VPADALsv2i32 = 927,
+ VPADALsv4i16 = 928,
+ VPADALsv4i32 = 929,
+ VPADALsv8i16 = 930,
+ VPADALsv8i8 = 931,
+ VPADALuv16i8 = 932,
+ VPADALuv2i32 = 933,
+ VPADALuv4i16 = 934,
+ VPADALuv4i32 = 935,
+ VPADALuv8i16 = 936,
+ VPADALuv8i8 = 937,
+ VPADDLsv16i8 = 938,
+ VPADDLsv2i32 = 939,
+ VPADDLsv4i16 = 940,
+ VPADDLsv4i32 = 941,
+ VPADDLsv8i16 = 942,
+ VPADDLsv8i8 = 943,
+ VPADDLuv16i8 = 944,
+ VPADDLuv2i32 = 945,
+ VPADDLuv4i16 = 946,
+ VPADDLuv4i32 = 947,
+ VPADDLuv8i16 = 948,
+ VPADDLuv8i8 = 949,
+ VPADDf = 950,
+ VPADDi16 = 951,
+ VPADDi32 = 952,
+ VPADDi8 = 953,
+ VPMAXf = 954,
+ VPMAXs16 = 955,
+ VPMAXs32 = 956,
+ VPMAXs8 = 957,
+ VPMAXu16 = 958,
+ VPMAXu32 = 959,
+ VPMAXu8 = 960,
+ VPMINf = 961,
+ VPMINs16 = 962,
+ VPMINs32 = 963,
+ VPMINs8 = 964,
+ VPMINu16 = 965,
+ VPMINu32 = 966,
+ VPMINu8 = 967,
+ VQABSv16i8 = 968,
+ VQABSv2i32 = 969,
+ VQABSv4i16 = 970,
+ VQABSv4i32 = 971,
+ VQABSv8i16 = 972,
+ VQABSv8i8 = 973,
+ VQADDsv16i8 = 974,
+ VQADDsv1i64 = 975,
+ VQADDsv2i32 = 976,
+ VQADDsv2i64 = 977,
+ VQADDsv4i16 = 978,
+ VQADDsv4i32 = 979,
+ VQADDsv8i16 = 980,
+ VQADDsv8i8 = 981,
+ VQADDuv16i8 = 982,
+ VQADDuv1i64 = 983,
+ VQADDuv2i32 = 984,
+ VQADDuv2i64 = 985,
+ VQADDuv4i16 = 986,
+ VQADDuv4i32 = 987,
+ VQADDuv8i16 = 988,
+ VQADDuv8i8 = 989,
+ VQDMLALslv2i32 = 990,
+ VQDMLALslv4i16 = 991,
+ VQDMLALv2i64 = 992,
+ VQDMLALv4i32 = 993,
+ VQDMLSLslv2i32 = 994,
+ VQDMLSLslv4i16 = 995,
+ VQDMLSLv2i64 = 996,
+ VQDMLSLv4i32 = 997,
+ VQDMULHslv2i32 = 998,
+ VQDMULHslv4i16 = 999,
+ VQDMULHslv4i32 = 1000,
+ VQDMULHslv8i16 = 1001,
+ VQDMULHv2i32 = 1002,
+ VQDMULHv4i16 = 1003,
+ VQDMULHv4i32 = 1004,
+ VQDMULHv8i16 = 1005,
+ VQDMULLslv2i32 = 1006,
+ VQDMULLslv4i16 = 1007,
+ VQDMULLv2i64 = 1008,
+ VQDMULLv4i32 = 1009,
+ VQMOVNsuv2i32 = 1010,
+ VQMOVNsuv4i16 = 1011,
+ VQMOVNsuv8i8 = 1012,
+ VQMOVNsv2i32 = 1013,
+ VQMOVNsv4i16 = 1014,
+ VQMOVNsv8i8 = 1015,
+ VQMOVNuv2i32 = 1016,
+ VQMOVNuv4i16 = 1017,
+ VQMOVNuv8i8 = 1018,
+ VQNEGv16i8 = 1019,
+ VQNEGv2i32 = 1020,
+ VQNEGv4i16 = 1021,
+ VQNEGv4i32 = 1022,
+ VQNEGv8i16 = 1023,
+ VQNEGv8i8 = 1024,
+ VQRDMULHslv2i32 = 1025,
+ VQRDMULHslv4i16 = 1026,
+ VQRDMULHslv4i32 = 1027,
+ VQRDMULHslv8i16 = 1028,
+ VQRDMULHv2i32 = 1029,
+ VQRDMULHv4i16 = 1030,
+ VQRDMULHv4i32 = 1031,
+ VQRDMULHv8i16 = 1032,
+ VQRSHLsv16i8 = 1033,
+ VQRSHLsv1i64 = 1034,
+ VQRSHLsv2i32 = 1035,
+ VQRSHLsv2i64 = 1036,
+ VQRSHLsv4i16 = 1037,
+ VQRSHLsv4i32 = 1038,
+ VQRSHLsv8i16 = 1039,
+ VQRSHLsv8i8 = 1040,
+ VQRSHLuv16i8 = 1041,
+ VQRSHLuv1i64 = 1042,
+ VQRSHLuv2i32 = 1043,
+ VQRSHLuv2i64 = 1044,
+ VQRSHLuv4i16 = 1045,
+ VQRSHLuv4i32 = 1046,
+ VQRSHLuv8i16 = 1047,
+ VQRSHLuv8i8 = 1048,
+ VQRSHRNsv2i32 = 1049,
+ VQRSHRNsv4i16 = 1050,
+ VQRSHRNsv8i8 = 1051,
+ VQRSHRNuv2i32 = 1052,
+ VQRSHRNuv4i16 = 1053,
+ VQRSHRNuv8i8 = 1054,
+ VQRSHRUNv2i32 = 1055,
+ VQRSHRUNv4i16 = 1056,
+ VQRSHRUNv8i8 = 1057,
+ VQSHLsiv16i8 = 1058,
+ VQSHLsiv1i64 = 1059,
+ VQSHLsiv2i32 = 1060,
+ VQSHLsiv2i64 = 1061,
+ VQSHLsiv4i16 = 1062,
+ VQSHLsiv4i32 = 1063,
+ VQSHLsiv8i16 = 1064,
+ VQSHLsiv8i8 = 1065,
+ VQSHLsuv16i8 = 1066,
+ VQSHLsuv1i64 = 1067,
+ VQSHLsuv2i32 = 1068,
+ VQSHLsuv2i64 = 1069,
+ VQSHLsuv4i16 = 1070,
+ VQSHLsuv4i32 = 1071,
+ VQSHLsuv8i16 = 1072,
+ VQSHLsuv8i8 = 1073,
+ VQSHLsv16i8 = 1074,
+ VQSHLsv1i64 = 1075,
+ VQSHLsv2i32 = 1076,
+ VQSHLsv2i64 = 1077,
+ VQSHLsv4i16 = 1078,
+ VQSHLsv4i32 = 1079,
+ VQSHLsv8i16 = 1080,
+ VQSHLsv8i8 = 1081,
+ VQSHLuiv16i8 = 1082,
+ VQSHLuiv1i64 = 1083,
+ VQSHLuiv2i32 = 1084,
+ VQSHLuiv2i64 = 1085,
+ VQSHLuiv4i16 = 1086,
+ VQSHLuiv4i32 = 1087,
+ VQSHLuiv8i16 = 1088,
+ VQSHLuiv8i8 = 1089,
+ VQSHLuv16i8 = 1090,
+ VQSHLuv1i64 = 1091,
+ VQSHLuv2i32 = 1092,
+ VQSHLuv2i64 = 1093,
+ VQSHLuv4i16 = 1094,
+ VQSHLuv4i32 = 1095,
+ VQSHLuv8i16 = 1096,
+ VQSHLuv8i8 = 1097,
+ VQSHRNsv2i32 = 1098,
+ VQSHRNsv4i16 = 1099,
+ VQSHRNsv8i8 = 1100,
+ VQSHRNuv2i32 = 1101,
+ VQSHRNuv4i16 = 1102,
+ VQSHRNuv8i8 = 1103,
+ VQSHRUNv2i32 = 1104,
+ VQSHRUNv4i16 = 1105,
+ VQSHRUNv8i8 = 1106,
+ VQSUBsv16i8 = 1107,
+ VQSUBsv1i64 = 1108,
+ VQSUBsv2i32 = 1109,
+ VQSUBsv2i64 = 1110,
+ VQSUBsv4i16 = 1111,
+ VQSUBsv4i32 = 1112,
+ VQSUBsv8i16 = 1113,
+ VQSUBsv8i8 = 1114,
+ VQSUBuv16i8 = 1115,
+ VQSUBuv1i64 = 1116,
+ VQSUBuv2i32 = 1117,
+ VQSUBuv2i64 = 1118,
+ VQSUBuv4i16 = 1119,
+ VQSUBuv4i32 = 1120,
+ VQSUBuv8i16 = 1121,
+ VQSUBuv8i8 = 1122,
+ VRADDHNv2i32 = 1123,
+ VRADDHNv4i16 = 1124,
+ VRADDHNv8i8 = 1125,
+ VRECPEd = 1126,
+ VRECPEfd = 1127,
+ VRECPEfq = 1128,
+ VRECPEq = 1129,
+ VRECPSfd = 1130,
+ VRECPSfq = 1131,
+ VREV16d8 = 1132,
+ VREV16q8 = 1133,
+ VREV32d16 = 1134,
+ VREV32d8 = 1135,
+ VREV32q16 = 1136,
+ VREV32q8 = 1137,
+ VREV64d16 = 1138,
+ VREV64d32 = 1139,
+ VREV64d8 = 1140,
+ VREV64df = 1141,
+ VREV64q16 = 1142,
+ VREV64q32 = 1143,
+ VREV64q8 = 1144,
+ VREV64qf = 1145,
+ VRHADDsv16i8 = 1146,
+ VRHADDsv2i32 = 1147,
+ VRHADDsv4i16 = 1148,
+ VRHADDsv4i32 = 1149,
+ VRHADDsv8i16 = 1150,
+ VRHADDsv8i8 = 1151,
+ VRHADDuv16i8 = 1152,
+ VRHADDuv2i32 = 1153,
+ VRHADDuv4i16 = 1154,
+ VRHADDuv4i32 = 1155,
+ VRHADDuv8i16 = 1156,
+ VRHADDuv8i8 = 1157,
+ VRSHLsv16i8 = 1158,
+ VRSHLsv1i64 = 1159,
+ VRSHLsv2i32 = 1160,
+ VRSHLsv2i64 = 1161,
+ VRSHLsv4i16 = 1162,
+ VRSHLsv4i32 = 1163,
+ VRSHLsv8i16 = 1164,
+ VRSHLsv8i8 = 1165,
+ VRSHLuv16i8 = 1166,
+ VRSHLuv1i64 = 1167,
+ VRSHLuv2i32 = 1168,
+ VRSHLuv2i64 = 1169,
+ VRSHLuv4i16 = 1170,
+ VRSHLuv4i32 = 1171,
+ VRSHLuv8i16 = 1172,
+ VRSHLuv8i8 = 1173,
+ VRSHRNv2i32 = 1174,
+ VRSHRNv4i16 = 1175,
+ VRSHRNv8i8 = 1176,
+ VRSHRsv16i8 = 1177,
+ VRSHRsv1i64 = 1178,
+ VRSHRsv2i32 = 1179,
+ VRSHRsv2i64 = 1180,
+ VRSHRsv4i16 = 1181,
+ VRSHRsv4i32 = 1182,
+ VRSHRsv8i16 = 1183,
+ VRSHRsv8i8 = 1184,
+ VRSHRuv16i8 = 1185,
+ VRSHRuv1i64 = 1186,
+ VRSHRuv2i32 = 1187,
+ VRSHRuv2i64 = 1188,
+ VRSHRuv4i16 = 1189,
+ VRSHRuv4i32 = 1190,
+ VRSHRuv8i16 = 1191,
+ VRSHRuv8i8 = 1192,
+ VRSQRTEd = 1193,
+ VRSQRTEfd = 1194,
+ VRSQRTEfq = 1195,
+ VRSQRTEq = 1196,
+ VRSQRTSfd = 1197,
+ VRSQRTSfq = 1198,
+ VRSRAsv16i8 = 1199,
+ VRSRAsv1i64 = 1200,
+ VRSRAsv2i32 = 1201,
+ VRSRAsv2i64 = 1202,
+ VRSRAsv4i16 = 1203,
+ VRSRAsv4i32 = 1204,
+ VRSRAsv8i16 = 1205,
+ VRSRAsv8i8 = 1206,
+ VRSRAuv16i8 = 1207,
+ VRSRAuv1i64 = 1208,
+ VRSRAuv2i32 = 1209,
+ VRSRAuv2i64 = 1210,
+ VRSRAuv4i16 = 1211,
+ VRSRAuv4i32 = 1212,
+ VRSRAuv8i16 = 1213,
+ VRSRAuv8i8 = 1214,
+ VRSUBHNv2i32 = 1215,
+ VRSUBHNv4i16 = 1216,
+ VRSUBHNv8i8 = 1217,
+ VSETLNi16 = 1218,
+ VSETLNi32 = 1219,
+ VSETLNi8 = 1220,
+ VSHLLi16 = 1221,
+ VSHLLi32 = 1222,
+ VSHLLi8 = 1223,
+ VSHLLsv2i64 = 1224,
+ VSHLLsv4i32 = 1225,
+ VSHLLsv8i16 = 1226,
+ VSHLLuv2i64 = 1227,
+ VSHLLuv4i32 = 1228,
+ VSHLLuv8i16 = 1229,
+ VSHLiv16i8 = 1230,
+ VSHLiv1i64 = 1231,
+ VSHLiv2i32 = 1232,
+ VSHLiv2i64 = 1233,
+ VSHLiv4i16 = 1234,
+ VSHLiv4i32 = 1235,
+ VSHLiv8i16 = 1236,
+ VSHLiv8i8 = 1237,
+ VSHLsv16i8 = 1238,
+ VSHLsv1i64 = 1239,
+ VSHLsv2i32 = 1240,
+ VSHLsv2i64 = 1241,
+ VSHLsv4i16 = 1242,
+ VSHLsv4i32 = 1243,
+ VSHLsv8i16 = 1244,
+ VSHLsv8i8 = 1245,
+ VSHLuv16i8 = 1246,
+ VSHLuv1i64 = 1247,
+ VSHLuv2i32 = 1248,
+ VSHLuv2i64 = 1249,
+ VSHLuv4i16 = 1250,
+ VSHLuv4i32 = 1251,
+ VSHLuv8i16 = 1252,
+ VSHLuv8i8 = 1253,
+ VSHRNv2i32 = 1254,
+ VSHRNv4i16 = 1255,
+ VSHRNv8i8 = 1256,
+ VSHRsv16i8 = 1257,
+ VSHRsv1i64 = 1258,
+ VSHRsv2i32 = 1259,
+ VSHRsv2i64 = 1260,
+ VSHRsv4i16 = 1261,
+ VSHRsv4i32 = 1262,
+ VSHRsv8i16 = 1263,
+ VSHRsv8i8 = 1264,
+ VSHRuv16i8 = 1265,
+ VSHRuv1i64 = 1266,
+ VSHRuv2i32 = 1267,
+ VSHRuv2i64 = 1268,
+ VSHRuv4i16 = 1269,
+ VSHRuv4i32 = 1270,
+ VSHRuv8i16 = 1271,
+ VSHRuv8i8 = 1272,
+ VSHTOD = 1273,
+ VSHTOS = 1274,
+ VSITOD = 1275,
+ VSITOS = 1276,
+ VSLIv16i8 = 1277,
+ VSLIv1i64 = 1278,
+ VSLIv2i32 = 1279,
+ VSLIv2i64 = 1280,
+ VSLIv4i16 = 1281,
+ VSLIv4i32 = 1282,
+ VSLIv8i16 = 1283,
+ VSLIv8i8 = 1284,
+ VSLTOD = 1285,
+ VSLTOS = 1286,
+ VSQRTD = 1287,
+ VSQRTS = 1288,
+ VSRAsv16i8 = 1289,
+ VSRAsv1i64 = 1290,
+ VSRAsv2i32 = 1291,
+ VSRAsv2i64 = 1292,
+ VSRAsv4i16 = 1293,
+ VSRAsv4i32 = 1294,
+ VSRAsv8i16 = 1295,
+ VSRAsv8i8 = 1296,
+ VSRAuv16i8 = 1297,
+ VSRAuv1i64 = 1298,
+ VSRAuv2i32 = 1299,
+ VSRAuv2i64 = 1300,
+ VSRAuv4i16 = 1301,
+ VSRAuv4i32 = 1302,
+ VSRAuv8i16 = 1303,
+ VSRAuv8i8 = 1304,
+ VSRIv16i8 = 1305,
+ VSRIv1i64 = 1306,
+ VSRIv2i32 = 1307,
+ VSRIv2i64 = 1308,
+ VSRIv4i16 = 1309,
+ VSRIv4i32 = 1310,
+ VSRIv8i16 = 1311,
+ VSRIv8i8 = 1312,
+ VST1d16 = 1313,
+ VST1d16Q = 1314,
+ VST1d16T = 1315,
+ VST1d32 = 1316,
+ VST1d32Q = 1317,
+ VST1d32T = 1318,
+ VST1d64 = 1319,
+ VST1d8 = 1320,
+ VST1d8Q = 1321,
+ VST1d8T = 1322,
+ VST1df = 1323,
+ VST1q16 = 1324,
+ VST1q32 = 1325,
+ VST1q64 = 1326,
+ VST1q8 = 1327,
+ VST1qf = 1328,
+ VST2LNd16 = 1329,
+ VST2LNd32 = 1330,
+ VST2LNd8 = 1331,
+ VST2LNq16a = 1332,
+ VST2LNq16b = 1333,
+ VST2LNq32a = 1334,
+ VST2LNq32b = 1335,
+ VST2d16 = 1336,
+ VST2d16D = 1337,
+ VST2d32 = 1338,
+ VST2d32D = 1339,
+ VST2d64 = 1340,
+ VST2d8 = 1341,
+ VST2d8D = 1342,
+ VST2q16 = 1343,
+ VST2q32 = 1344,
+ VST2q8 = 1345,
+ VST3LNd16 = 1346,
+ VST3LNd32 = 1347,
+ VST3LNd8 = 1348,
+ VST3LNq16a = 1349,
+ VST3LNq16b = 1350,
+ VST3LNq32a = 1351,
+ VST3LNq32b = 1352,
+ VST3d16 = 1353,
+ VST3d32 = 1354,
+ VST3d64 = 1355,
+ VST3d8 = 1356,
+ VST3q16a = 1357,
+ VST3q16b = 1358,
+ VST3q32a = 1359,
+ VST3q32b = 1360,
+ VST3q8a = 1361,
+ VST3q8b = 1362,
+ VST4LNd16 = 1363,
+ VST4LNd32 = 1364,
+ VST4LNd8 = 1365,
+ VST4LNq16a = 1366,
+ VST4LNq16b = 1367,
+ VST4LNq32a = 1368,
+ VST4LNq32b = 1369,
+ VST4d16 = 1370,
+ VST4d32 = 1371,
+ VST4d64 = 1372,
+ VST4d8 = 1373,
+ VST4q16a = 1374,
+ VST4q16b = 1375,
+ VST4q32a = 1376,
+ VST4q32b = 1377,
+ VST4q8a = 1378,
+ VST4q8b = 1379,
+ VSTMD = 1380,
+ VSTMS = 1381,
+ VSTRD = 1382,
+ VSTRQ = 1383,
+ VSTRS = 1384,
+ VSUBD = 1385,
+ VSUBHNv2i32 = 1386,
+ VSUBHNv4i16 = 1387,
+ VSUBHNv8i8 = 1388,
+ VSUBLsv2i64 = 1389,
+ VSUBLsv4i32 = 1390,
+ VSUBLsv8i16 = 1391,
+ VSUBLuv2i64 = 1392,
+ VSUBLuv4i32 = 1393,
+ VSUBLuv8i16 = 1394,
+ VSUBS = 1395,
+ VSUBWsv2i64 = 1396,
+ VSUBWsv4i32 = 1397,
+ VSUBWsv8i16 = 1398,
+ VSUBWuv2i64 = 1399,
+ VSUBWuv4i32 = 1400,
+ VSUBWuv8i16 = 1401,
+ VSUBfd = 1402,
+ VSUBfd_sfp = 1403,
+ VSUBfq = 1404,
+ VSUBv16i8 = 1405,
+ VSUBv1i64 = 1406,
+ VSUBv2i32 = 1407,
+ VSUBv2i64 = 1408,
+ VSUBv4i16 = 1409,
+ VSUBv4i32 = 1410,
+ VSUBv8i16 = 1411,
+ VSUBv8i8 = 1412,
+ VSWPd = 1413,
+ VSWPq = 1414,
+ VTBL1 = 1415,
+ VTBL2 = 1416,
+ VTBL3 = 1417,
+ VTBL4 = 1418,
+ VTBX1 = 1419,
+ VTBX2 = 1420,
+ VTBX3 = 1421,
+ VTBX4 = 1422,
+ VTOSHD = 1423,
+ VTOSHS = 1424,
+ VTOSIRD = 1425,
+ VTOSIRS = 1426,
+ VTOSIZD = 1427,
+ VTOSIZS = 1428,
+ VTOSLD = 1429,
+ VTOSLS = 1430,
+ VTOUHD = 1431,
+ VTOUHS = 1432,
+ VTOUIRD = 1433,
+ VTOUIRS = 1434,
+ VTOUIZD = 1435,
+ VTOUIZS = 1436,
+ VTOULD = 1437,
+ VTOULS = 1438,
+ VTRNd16 = 1439,
+ VTRNd32 = 1440,
+ VTRNd8 = 1441,
+ VTRNq16 = 1442,
+ VTRNq32 = 1443,
+ VTRNq8 = 1444,
+ VTSTv16i8 = 1445,
+ VTSTv2i32 = 1446,
+ VTSTv4i16 = 1447,
+ VTSTv4i32 = 1448,
+ VTSTv8i16 = 1449,
+ VTSTv8i8 = 1450,
+ VUHTOD = 1451,
+ VUHTOS = 1452,
+ VUITOD = 1453,
+ VUITOS = 1454,
+ VULTOD = 1455,
+ VULTOS = 1456,
+ VUZPd16 = 1457,
+ VUZPd32 = 1458,
+ VUZPd8 = 1459,
+ VUZPq16 = 1460,
+ VUZPq32 = 1461,
+ VUZPq8 = 1462,
+ VZIPd16 = 1463,
+ VZIPd32 = 1464,
+ VZIPd8 = 1465,
+ VZIPq16 = 1466,
+ VZIPq32 = 1467,
+ VZIPq8 = 1468,
+ WFE = 1469,
+ WFI = 1470,
+ YIELD = 1471,
+ t2ADCSri = 1472,
+ t2ADCSrr = 1473,
+ t2ADCSrs = 1474,
+ t2ADCri = 1475,
+ t2ADCrr = 1476,
+ t2ADCrs = 1477,
+ t2ADDSri = 1478,
+ t2ADDSrr = 1479,
+ t2ADDSrs = 1480,
+ t2ADDrSPi = 1481,
+ t2ADDrSPi12 = 1482,
+ t2ADDrSPs = 1483,
+ t2ADDri = 1484,
+ t2ADDri12 = 1485,
+ t2ADDrr = 1486,
+ t2ADDrs = 1487,
+ t2ANDri = 1488,
+ t2ANDrr = 1489,
+ t2ANDrs = 1490,
+ t2ASRri = 1491,
+ t2ASRrr = 1492,
+ t2B = 1493,
+ t2BFC = 1494,
+ t2BFI = 1495,
+ t2BICri = 1496,
+ t2BICrr = 1497,
+ t2BICrs = 1498,
+ t2BR_JT = 1499,
+ t2BXJ = 1500,
+ t2Bcc = 1501,
+ t2CLREX = 1502,
+ t2CLZ = 1503,
+ t2CMNzri = 1504,
+ t2CMNzrr = 1505,
+ t2CMNzrs = 1506,
+ t2CMPri = 1507,
+ t2CMPrr = 1508,
+ t2CMPrs = 1509,
+ t2CMPzri = 1510,
+ t2CMPzrr = 1511,
+ t2CMPzrs = 1512,
+ t2CPS = 1513,
+ t2DBG = 1514,
+ t2DMBish = 1515,
+ t2DMBishst = 1516,
+ t2DMBnsh = 1517,
+ t2DMBnshst = 1518,
+ t2DMBosh = 1519,
+ t2DMBoshst = 1520,
+ t2DMBst = 1521,
+ t2DSBish = 1522,
+ t2DSBishst = 1523,
+ t2DSBnsh = 1524,
+ t2DSBnshst = 1525,
+ t2DSBosh = 1526,
+ t2DSBoshst = 1527,
+ t2DSBst = 1528,
+ t2EORri = 1529,
+ t2EORrr = 1530,
+ t2EORrs = 1531,
+ t2ISBsy = 1532,
+ t2IT = 1533,
+ t2Int_MemBarrierV7 = 1534,
+ t2Int_SyncBarrierV7 = 1535,
+ t2Int_eh_sjlj_setjmp = 1536,
+ t2LDM = 1537,
+ t2LDM_RET = 1538,
+ t2LDRBT = 1539,
+ t2LDRB_POST = 1540,
+ t2LDRB_PRE = 1541,
+ t2LDRBi12 = 1542,
+ t2LDRBi8 = 1543,
+ t2LDRBpci = 1544,
+ t2LDRBs = 1545,
+ t2LDRDi8 = 1546,
+ t2LDRDpci = 1547,
+ t2LDREX = 1548,
+ t2LDREXB = 1549,
+ t2LDREXD = 1550,
+ t2LDREXH = 1551,
+ t2LDRHT = 1552,
+ t2LDRH_POST = 1553,
+ t2LDRH_PRE = 1554,
+ t2LDRHi12 = 1555,
+ t2LDRHi8 = 1556,
+ t2LDRHpci = 1557,
+ t2LDRHs = 1558,
+ t2LDRSBT = 1559,
+ t2LDRSB_POST = 1560,
+ t2LDRSB_PRE = 1561,
+ t2LDRSBi12 = 1562,
+ t2LDRSBi8 = 1563,
+ t2LDRSBpci = 1564,
+ t2LDRSBs = 1565,
+ t2LDRSHT = 1566,
+ t2LDRSH_POST = 1567,
+ t2LDRSH_PRE = 1568,
+ t2LDRSHi12 = 1569,
+ t2LDRSHi8 = 1570,
+ t2LDRSHpci = 1571,
+ t2LDRSHs = 1572,
+ t2LDRT = 1573,
+ t2LDR_POST = 1574,
+ t2LDR_PRE = 1575,
+ t2LDRi12 = 1576,
+ t2LDRi8 = 1577,
+ t2LDRpci = 1578,
+ t2LDRpci_pic = 1579,
+ t2LDRs = 1580,
+ t2LEApcrel = 1581,
+ t2LEApcrelJT = 1582,
+ t2LSLri = 1583,
+ t2LSLrr = 1584,
+ t2LSRri = 1585,
+ t2LSRrr = 1586,
+ t2MLA = 1587,
+ t2MLS = 1588,
+ t2MOVCCasr = 1589,
+ t2MOVCCi = 1590,
+ t2MOVCClsl = 1591,
+ t2MOVCClsr = 1592,
+ t2MOVCCr = 1593,
+ t2MOVCCror = 1594,
+ t2MOVTi16 = 1595,
+ t2MOVi = 1596,
+ t2MOVi16 = 1597,
+ t2MOVi32imm = 1598,
+ t2MOVr = 1599,
+ t2MOVrx = 1600,
+ t2MOVsra_flag = 1601,
+ t2MOVsrl_flag = 1602,
+ t2MRS = 1603,
+ t2MRSsys = 1604,
+ t2MSR = 1605,
+ t2MSRsys = 1606,
+ t2MUL = 1607,
+ t2MVNi = 1608,
+ t2MVNr = 1609,
+ t2MVNs = 1610,
+ t2NOP = 1611,
+ t2ORNri = 1612,
+ t2ORNrr = 1613,
+ t2ORNrs = 1614,
+ t2ORRri = 1615,
+ t2ORRrr = 1616,
+ t2ORRrs = 1617,
+ t2PKHBT = 1618,
+ t2PKHTB = 1619,
+ t2PLDWi12 = 1620,
+ t2PLDWi8 = 1621,
+ t2PLDWpci = 1622,
+ t2PLDWr = 1623,
+ t2PLDWs = 1624,
+ t2PLDi12 = 1625,
+ t2PLDi8 = 1626,
+ t2PLDpci = 1627,
+ t2PLDr = 1628,
+ t2PLDs = 1629,
+ t2PLIi12 = 1630,
+ t2PLIi8 = 1631,
+ t2PLIpci = 1632,
+ t2PLIr = 1633,
+ t2PLIs = 1634,
+ t2QADD = 1635,
+ t2QADD16 = 1636,
+ t2QADD8 = 1637,
+ t2QASX = 1638,
+ t2QDADD = 1639,
+ t2QDSUB = 1640,
+ t2QSAX = 1641,
+ t2QSUB = 1642,
+ t2QSUB16 = 1643,
+ t2QSUB8 = 1644,
+ t2RBIT = 1645,
+ t2REV = 1646,
+ t2REV16 = 1647,
+ t2REVSH = 1648,
+ t2RFEDB = 1649,
+ t2RFEDBW = 1650,
+ t2RFEIA = 1651,
+ t2RFEIAW = 1652,
+ t2RORri = 1653,
+ t2RORrr = 1654,
+ t2RSBSri = 1655,
+ t2RSBSrs = 1656,
+ t2RSBri = 1657,
+ t2RSBrs = 1658,
+ t2SADD16 = 1659,
+ t2SADD8 = 1660,
+ t2SASX = 1661,
+ t2SBCSri = 1662,
+ t2SBCSrr = 1663,
+ t2SBCSrs = 1664,
+ t2SBCri = 1665,
+ t2SBCrr = 1666,
+ t2SBCrs = 1667,
+ t2SBFX = 1668,
+ t2SDIV = 1669,
+ t2SEL = 1670,
+ t2SEV = 1671,
+ t2SHADD16 = 1672,
+ t2SHADD8 = 1673,
+ t2SHASX = 1674,
+ t2SHSAX = 1675,
+ t2SHSUB16 = 1676,
+ t2SHSUB8 = 1677,
+ t2SMC = 1678,
+ t2SMLABB = 1679,
+ t2SMLABT = 1680,
+ t2SMLAD = 1681,
+ t2SMLADX = 1682,
+ t2SMLAL = 1683,
+ t2SMLALBB = 1684,
+ t2SMLALBT = 1685,
+ t2SMLALD = 1686,
+ t2SMLALDX = 1687,
+ t2SMLALTB = 1688,
+ t2SMLALTT = 1689,
+ t2SMLATB = 1690,
+ t2SMLATT = 1691,
+ t2SMLAWB = 1692,
+ t2SMLAWT = 1693,
+ t2SMLSD = 1694,
+ t2SMLSDX = 1695,
+ t2SMLSLD = 1696,
+ t2SMLSLDX = 1697,
+ t2SMMLA = 1698,
+ t2SMMLAR = 1699,
+ t2SMMLS = 1700,
+ t2SMMLSR = 1701,
+ t2SMMUL = 1702,
+ t2SMMULR = 1703,
+ t2SMUAD = 1704,
+ t2SMUADX = 1705,
+ t2SMULBB = 1706,
+ t2SMULBT = 1707,
+ t2SMULL = 1708,
+ t2SMULTB = 1709,
+ t2SMULTT = 1710,
+ t2SMULWB = 1711,
+ t2SMULWT = 1712,
+ t2SMUSD = 1713,
+ t2SMUSDX = 1714,
+ t2SRSDB = 1715,
+ t2SRSDBW = 1716,
+ t2SRSIA = 1717,
+ t2SRSIAW = 1718,
+ t2SSAT16 = 1719,
+ t2SSATasr = 1720,
+ t2SSATlsl = 1721,
+ t2SSAX = 1722,
+ t2SSUB16 = 1723,
+ t2SSUB8 = 1724,
+ t2STM = 1725,
+ t2STRBT = 1726,
+ t2STRB_POST = 1727,
+ t2STRB_PRE = 1728,
+ t2STRBi12 = 1729,
+ t2STRBi8 = 1730,
+ t2STRBs = 1731,
+ t2STRDi8 = 1732,
+ t2STREX = 1733,
+ t2STREXB = 1734,
+ t2STREXD = 1735,
+ t2STREXH = 1736,
+ t2STRHT = 1737,
+ t2STRH_POST = 1738,
+ t2STRH_PRE = 1739,
+ t2STRHi12 = 1740,
+ t2STRHi8 = 1741,
+ t2STRHs = 1742,
+ t2STRT = 1743,
+ t2STR_POST = 1744,
+ t2STR_PRE = 1745,
+ t2STRi12 = 1746,
+ t2STRi8 = 1747,
+ t2STRs = 1748,
+ t2SUBSri = 1749,
+ t2SUBSrr = 1750,
+ t2SUBSrs = 1751,
+ t2SUBrSPi = 1752,
+ t2SUBrSPi12 = 1753,
+ t2SUBrSPi12_ = 1754,
+ t2SUBrSPi_ = 1755,
+ t2SUBrSPs = 1756,
+ t2SUBrSPs_ = 1757,
+ t2SUBri = 1758,
+ t2SUBri12 = 1759,
+ t2SUBrr = 1760,
+ t2SUBrs = 1761,
+ t2SXTAB16rr = 1762,
+ t2SXTAB16rr_rot = 1763,
+ t2SXTABrr = 1764,
+ t2SXTABrr_rot = 1765,
+ t2SXTAHrr = 1766,
+ t2SXTAHrr_rot = 1767,
+ t2SXTB16r = 1768,
+ t2SXTB16r_rot = 1769,
+ t2SXTBr = 1770,
+ t2SXTBr_rot = 1771,
+ t2SXTHr = 1772,
+ t2SXTHr_rot = 1773,
+ t2TBB = 1774,
+ t2TBBgen = 1775,
+ t2TBH = 1776,
+ t2TBHgen = 1777,
+ t2TEQri = 1778,
+ t2TEQrr = 1779,
+ t2TEQrs = 1780,
+ t2TPsoft = 1781,
+ t2TSTri = 1782,
+ t2TSTrr = 1783,
+ t2TSTrs = 1784,
+ t2UADD16 = 1785,
+ t2UADD8 = 1786,
+ t2UASX = 1787,
+ t2UBFX = 1788,
+ t2UDIV = 1789,
+ t2UHADD16 = 1790,
+ t2UHADD8 = 1791,
+ t2UHASX = 1792,
+ t2UHSAX = 1793,
+ t2UHSUB16 = 1794,
+ t2UHSUB8 = 1795,
+ t2UMAAL = 1796,
+ t2UMLAL = 1797,
+ t2UMULL = 1798,
+ t2UQADD16 = 1799,
+ t2UQADD8 = 1800,
+ t2UQASX = 1801,
+ t2UQSAX = 1802,
+ t2UQSUB16 = 1803,
+ t2UQSUB8 = 1804,
+ t2USAD8 = 1805,
+ t2USADA8 = 1806,
+ t2USAT16 = 1807,
+ t2USATasr = 1808,
+ t2USATlsl = 1809,
+ t2USAX = 1810,
+ t2USUB16 = 1811,
+ t2USUB8 = 1812,
+ t2UXTAB16rr = 1813,
+ t2UXTAB16rr_rot = 1814,
+ t2UXTABrr = 1815,
+ t2UXTABrr_rot = 1816,
+ t2UXTAHrr = 1817,
+ t2UXTAHrr_rot = 1818,
+ t2UXTB16r = 1819,
+ t2UXTB16r_rot = 1820,
+ t2UXTBr = 1821,
+ t2UXTBr_rot = 1822,
+ t2UXTHr = 1823,
+ t2UXTHr_rot = 1824,
+ t2WFE = 1825,
+ t2WFI = 1826,
+ t2YIELD = 1827,
+ tADC = 1828,
+ tADDhirr = 1829,
+ tADDi3 = 1830,
+ tADDi8 = 1831,
+ tADDrPCi = 1832,
+ tADDrSP = 1833,
+ tADDrSPi = 1834,
+ tADDrr = 1835,
+ tADDspi = 1836,
+ tADDspr = 1837,
+ tADDspr_ = 1838,
+ tADJCALLSTACKDOWN = 1839,
+ tADJCALLSTACKUP = 1840,
+ tAND = 1841,
+ tANDsp = 1842,
+ tASRri = 1843,
+ tASRrr = 1844,
+ tB = 1845,
+ tBIC = 1846,
+ tBKPT = 1847,
+ tBL = 1848,
+ tBLXi = 1849,
+ tBLXi_r9 = 1850,
+ tBLXr = 1851,
+ tBLXr_r9 = 1852,
+ tBLr9 = 1853,
+ tBRIND = 1854,
+ tBR_JTr = 1855,
+ tBX = 1856,
+ tBX_RET = 1857,
+ tBX_RET_vararg = 1858,
+ tBXr9 = 1859,
+ tBcc = 1860,
+ tBfar = 1861,
+ tCBNZ = 1862,
+ tCBZ = 1863,
+ tCMNz = 1864,
+ tCMPhir = 1865,
+ tCMPi8 = 1866,
+ tCMPr = 1867,
+ tCMPzhir = 1868,
+ tCMPzi8 = 1869,
+ tCMPzr = 1870,
+ tCPS = 1871,
+ tEOR = 1872,
+ tInt_eh_sjlj_setjmp = 1873,
+ tLDM = 1874,
+ tLDR = 1875,
+ tLDRB = 1876,
+ tLDRBi = 1877,
+ tLDRH = 1878,
+ tLDRHi = 1879,
+ tLDRSB = 1880,
+ tLDRSH = 1881,
+ tLDRcp = 1882,
+ tLDRi = 1883,
+ tLDRpci = 1884,
+ tLDRpci_pic = 1885,
+ tLDRspi = 1886,
+ tLEApcrel = 1887,
+ tLEApcrelJT = 1888,
+ tLSLri = 1889,
+ tLSLrr = 1890,
+ tLSRri = 1891,
+ tLSRrr = 1892,
+ tMOVCCi = 1893,
+ tMOVCCr = 1894,
+ tMOVCCr_pseudo = 1895,
+ tMOVSr = 1896,
+ tMOVgpr2gpr = 1897,
+ tMOVgpr2tgpr = 1898,
+ tMOVi8 = 1899,
+ tMOVr = 1900,
+ tMOVtgpr2gpr = 1901,
+ tMUL = 1902,
+ tMVN = 1903,
+ tNOP = 1904,
+ tORR = 1905,
+ tPICADD = 1906,
+ tPOP = 1907,
+ tPOP_RET = 1908,
+ tPUSH = 1909,
+ tREV = 1910,
+ tREV16 = 1911,
+ tREVSH = 1912,
+ tROR = 1913,
+ tRSB = 1914,
+ tRestore = 1915,
+ tSBC = 1916,
+ tSETENDBE = 1917,
+ tSETENDLE = 1918,
+ tSEV = 1919,
+ tSTM = 1920,
+ tSTR = 1921,
+ tSTRB = 1922,
+ tSTRBi = 1923,
+ tSTRH = 1924,
+ tSTRHi = 1925,
+ tSTRi = 1926,
+ tSTRspi = 1927,
+ tSUBi3 = 1928,
+ tSUBi8 = 1929,
+ tSUBrr = 1930,
+ tSUBspi = 1931,
+ tSUBspi_ = 1932,
+ tSVC = 1933,
+ tSXTB = 1934,
+ tSXTH = 1935,
+ tSpill = 1936,
+ tTPsoft = 1937,
+ tTRAP = 1938,
+ tTST = 1939,
+ tUXTB = 1940,
+ tUXTH = 1941,
+ tWFE = 1942,
+ tWFI = 1943,
+ tYIELD = 1944,
+ INSTRUCTION_LIST_END = 1945
};
}
} // End llvm namespace
diff --git a/libclamav/c++/Makefile.am b/libclamav/c++/Makefile.am
index 132a4e4..e939a29 100644
--- a/libclamav/c++/Makefile.am
+++ b/libclamav/c++/Makefile.am
@@ -169,6 +169,7 @@ tblgen_SOURCES=\
llvm/utils/TableGen/DAGISelMatcher.cpp\
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp\
llvm/utils/TableGen/DAGISelMatcherGen.cpp\
+ llvm/utils/TableGen/DAGISelMatcherOpt.cpp\
llvm/utils/TableGen/DisassemblerEmitter.cpp\
llvm/utils/TableGen/EDEmitter.cpp\
llvm/utils/TableGen/FastISelEmitter.cpp\
@@ -251,7 +252,7 @@ tblgen_SOURCES=\
TBLGEN=$(top_builddir)/tblgen
TBLGEN_V=$(AM_V_GEN)$(TBLGEN)
-TBLGEN_FLAGS=-I$(top_srcdir)/llvm/include -I$(top_srcdir)/llvm/lib/Target
+TBLGEN_FLAGS=-I$(top_srcdir)/llvm/include -I$(top_srcdir)/llvm/lib/Target -omit-comments
llvm/include/llvm/Intrinsics.gen: llvm/include/llvm/Intrinsics.td $(TBLGEN)
$(TBLGEN_V) $(TBLGEN_FLAGS) -gen-intrinsic -o $@ $<
@@ -365,11 +366,12 @@ endif
if BUILD_X86
libllvmx86codegen_la_CPPFLAGS=$(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/X86
libllvmx86codegen_la_SOURCES=\
- llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/MC/MCAsmInfoCOFF.cpp\
llvm/lib/MC/MCCodeEmitter.cpp\
+ llvm/lib/MC/TargetAsmBackend.cpp\
llvm/lib/Target/TargetELFWriterInfo.cpp\
llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp\
+ llvm/lib/Target/X86/X86AsmBackend.cpp\
llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp\
llvm/lib/Target/X86/X86CodeEmitter.cpp\
llvm/lib/Target/X86/X86ELFWriterInfo.cpp\
@@ -474,7 +476,6 @@ libllvmjit_la_SOURCES=\
llvm/lib/MC/MCExpr.cpp\
llvm/lib/MC/MCSection.cpp\
llvm/lib/MC/MCSectionELF.cpp\
- llvm/lib/MC/MCSectionMachO.cpp\
llvm/lib/MC/MCSymbol.cpp\
llvm/lib/Support/APFloat.cpp\
llvm/lib/Support/APInt.cpp\
@@ -578,9 +579,11 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/LiveStackAnalysis.cpp\
llvm/lib/CodeGen/LiveVariables.cpp\
llvm/lib/CodeGen/LowerSubregs.cpp\
+ llvm/lib/CodeGen/MachineCSE.cpp\
llvm/lib/CodeGen/MachineDominators.cpp\
llvm/lib/CodeGen/MachineLICM.cpp\
llvm/lib/CodeGen/MachineLoopInfo.cpp\
+ llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/CodeGen/MachinePassRegistry.cpp\
llvm/lib/CodeGen/MachineSSAUpdater.cpp\
llvm/lib/CodeGen/MachineSink.cpp\
@@ -630,6 +633,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/StackSlotColoring.cpp\
llvm/lib/CodeGen/StrongPHIElimination.cpp\
llvm/lib/CodeGen/TailDuplication.cpp\
+ llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp\
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp\
llvm/lib/CodeGen/UnreachableBlockElim.cpp\
llvm/lib/CodeGen/VirtRegMap.cpp\
@@ -640,6 +644,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/MC/MCInst.cpp\
llvm/lib/MC/MCMachOStreamer.cpp\
llvm/lib/MC/MCNullStreamer.cpp\
+ llvm/lib/MC/MCSectionMachO.cpp\
llvm/lib/MC/MCStreamer.cpp\
llvm/lib/Target/TargetFrameInfo.cpp\
llvm/lib/Target/TargetSubtarget.cpp\
@@ -806,7 +811,6 @@ libllvmfullcodegen_la_SOURCES=\
llvm/lib/CodeGen/GCMetadataPrinter.cpp\
llvm/lib/CodeGen/IfConversion.cpp\
llvm/lib/CodeGen/IntrinsicLowering.cpp\
- llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/CodeGen/OcamlGC.cpp\
llvm/lib/CodeGen/RegAllocLocal.cpp\
llvm/lib/CodeGen/RegAllocPBQP.cpp\
diff --git a/libclamav/c++/Makefile.in b/libclamav/c++/Makefile.in
index a0c9574..5fd2f34 100644
--- a/libclamav/c++/Makefile.in
+++ b/libclamav/c++/Makefile.in
@@ -231,8 +231,9 @@ am_libllvmcodegen_la_OBJECTS = AliasSetTracker.lo ConstantFolding.lo \
DwarfEHPrepare.lo ExactHazardRecognizer.lo GCMetadata.lo \
GCStrategy.lo LLVMTargetMachine.lo LatencyPriorityQueue.lo \
LiveInterval.lo LiveIntervalAnalysis.lo LiveStackAnalysis.lo \
- LiveVariables.lo LowerSubregs.lo MachineDominators.lo \
- MachineLICM.lo MachineLoopInfo.lo MachinePassRegistry.lo \
+ LiveVariables.lo LowerSubregs.lo MachineCSE.lo \
+ MachineDominators.lo MachineLICM.lo MachineLoopInfo.lo \
+ MachineModuleInfoImpls.lo MachinePassRegistry.lo \
MachineSSAUpdater.lo MachineSink.lo MachineVerifier.lo \
OptimizeExts.lo OptimizePHIs.lo PHIElimination.lo Passes.lo \
PostRASchedulerList.lo PreAllocSplitting.lo \
@@ -251,22 +252,23 @@ am_libllvmcodegen_la_OBJECTS = AliasSetTracker.lo ConstantFolding.lo \
SimpleRegisterCoalescing.lo SjLjEHPrepare.lo SlotIndexes.lo \
Spiller.lo StackProtector.lo StackSlotColoring.lo \
StrongPHIElimination.lo TailDuplication.lo \
- TwoAddressInstructionPass.lo UnreachableBlockElim.lo \
- VirtRegMap.lo VirtRegRewriter.lo MCAsmInfoDarwin.lo \
- MCAsmStreamer.lo MCAssembler.lo MCInst.lo MCMachOStreamer.lo \
- MCNullStreamer.lo MCStreamer.lo TargetFrameInfo.lo \
- TargetSubtarget.lo CodeGenPrepare.lo GEPSplitter.lo GVN.lo \
- LoopStrengthReduce.lo AddrModeMatcher.lo BasicBlockUtils.lo \
- BreakCriticalEdges.lo DemoteRegToStack.lo LCSSA.lo Local.lo \
- LoopSimplify.lo LowerInvoke.lo LowerSwitch.lo Mem2Reg.lo \
+ TargetLoweringObjectFileImpl.lo TwoAddressInstructionPass.lo \
+ UnreachableBlockElim.lo VirtRegMap.lo VirtRegRewriter.lo \
+ MCAsmInfoDarwin.lo MCAsmStreamer.lo MCAssembler.lo MCInst.lo \
+ MCMachOStreamer.lo MCNullStreamer.lo MCSectionMachO.lo \
+ MCStreamer.lo TargetFrameInfo.lo TargetSubtarget.lo \
+ CodeGenPrepare.lo GEPSplitter.lo GVN.lo LoopStrengthReduce.lo \
+ AddrModeMatcher.lo BasicBlockUtils.lo BreakCriticalEdges.lo \
+ DemoteRegToStack.lo LCSSA.lo Local.lo LoopSimplify.lo \
+ LowerInvoke.lo LowerSwitch.lo Mem2Reg.lo \
PromoteMemoryToRegister.lo SSAUpdater.lo SimplifyCFG.lo \
UnifyFunctionExitNodes.lo
libllvmcodegen_la_OBJECTS = $(am_libllvmcodegen_la_OBJECTS)
libllvmfullcodegen_la_LIBADD =
am_libllvmfullcodegen_la_OBJECTS = GCMetadataPrinter.lo \
- IfConversion.lo IntrinsicLowering.lo MachineModuleInfoImpls.lo \
- OcamlGC.lo RegAllocLocal.lo RegAllocPBQP.lo ShadowStackGC.lo \
- Execution.lo ExternalFunctions.lo Interpreter.lo Target.lo \
+ IfConversion.lo IntrinsicLowering.lo OcamlGC.lo \
+ RegAllocLocal.lo RegAllocPBQP.lo ShadowStackGC.lo Execution.lo \
+ ExternalFunctions.lo Interpreter.lo Target.lo \
TargetAsmLexer.lo TargetELFWriterInfo.lo \
TargetIntrinsicInfo.lo
libllvmfullcodegen_la_OBJECTS = $(am_libllvmfullcodegen_la_OBJECTS)
@@ -286,14 +288,13 @@ am_libllvmjit_la_OBJECTS = AliasAnalysis.lo BasicAliasAnalysis.lo \
JITDebugRegisterer.lo JITDwarfEmitter.lo JITEmitter.lo \
JITMemoryManager.lo OProfileJITEventListener.lo \
TargetSelect.lo MCAsmInfo.lo MCContext.lo MCExpr.lo \
- MCSection.lo MCSectionELF.lo MCSectionMachO.lo MCSymbol.lo \
- APFloat.lo APInt.lo Allocator.lo CommandLine.lo \
- ConstantRange.lo Debug.lo Dwarf.lo ErrorHandling.lo \
- FoldingSet.lo FormattedStream.lo GraphWriter.lo \
- ManagedStatic.lo MemoryBuffer.lo PrettyStackTrace.lo \
- SmallPtrSet.lo SmallVector.lo SourceMgr.lo Statistic.lo \
- StringExtras.lo StringMap.lo StringPool.lo StringRef.lo \
- TargetRegistry.lo Timer.lo Triple.lo Twine.lo \
+ MCSection.lo MCSectionELF.lo MCSymbol.lo APFloat.lo APInt.lo \
+ Allocator.lo CommandLine.lo ConstantRange.lo Debug.lo Dwarf.lo \
+ ErrorHandling.lo FoldingSet.lo FormattedStream.lo \
+ GraphWriter.lo ManagedStatic.lo MemoryBuffer.lo \
+ PrettyStackTrace.lo SmallPtrSet.lo SmallVector.lo SourceMgr.lo \
+ Statistic.lo StringExtras.lo StringMap.lo StringPool.lo \
+ StringRef.lo TargetRegistry.lo Timer.lo Triple.lo Twine.lo \
circular_raw_ostream.lo raw_ostream.lo Mangler.lo \
SubtargetFeature.lo TargetData.lo TargetInstrInfo.lo \
TargetLoweringObjectFile.lo TargetMachine.lo \
@@ -363,11 +364,11 @@ libllvmsystem_la_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CXX \
$(AM_CXXFLAGS) $(CXXFLAGS) $(libllvmsystem_la_LDFLAGS) \
$(LDFLAGS) -o $@
libllvmx86codegen_la_LIBADD =
-am__libllvmx86codegen_la_SOURCES_DIST = \
- llvm/lib/CodeGen/MachineModuleInfoImpls.cpp \
- llvm/lib/MC/MCAsmInfoCOFF.cpp llvm/lib/MC/MCCodeEmitter.cpp \
+am__libllvmx86codegen_la_SOURCES_DIST = llvm/lib/MC/MCAsmInfoCOFF.cpp \
+ llvm/lib/MC/MCCodeEmitter.cpp llvm/lib/MC/TargetAsmBackend.cpp \
llvm/lib/Target/TargetELFWriterInfo.cpp \
llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp \
+ llvm/lib/Target/X86/X86AsmBackend.cpp \
llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp \
llvm/lib/Target/X86/X86CodeEmitter.cpp \
llvm/lib/Target/X86/X86ELFWriterInfo.cpp \
@@ -385,11 +386,13 @@ am__libllvmx86codegen_la_SOURCES_DIST = \
llvm/lib/Target/X86/X86Subtarget.cpp \
llvm/lib/Target/X86/X86TargetMachine.cpp \
llvm/lib/Target/X86/X86TargetObjectFile.cpp
- at BUILD_X86_TRUE@am_libllvmx86codegen_la_OBJECTS = libllvmx86codegen_la-MachineModuleInfoImpls.lo \
+ at BUILD_X86_TRUE@am_libllvmx86codegen_la_OBJECTS = \
@BUILD_X86_TRUE@ libllvmx86codegen_la-MCAsmInfoCOFF.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-MCCodeEmitter.lo \
+ at BUILD_X86_TRUE@ libllvmx86codegen_la-TargetAsmBackend.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-TargetELFWriterInfo.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86TargetInfo.lo \
+ at BUILD_X86_TRUE@ libllvmx86codegen_la-X86AsmBackend.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86COFFMachineModuleInfo.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86CodeEmitter.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86ELFWriterInfo.lo \
@@ -517,6 +520,7 @@ am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
llvm/utils/TableGen/DAGISelMatcher.cpp \
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp \
llvm/utils/TableGen/DAGISelMatcherGen.cpp \
+ llvm/utils/TableGen/DAGISelMatcherOpt.cpp \
llvm/utils/TableGen/DisassemblerEmitter.cpp \
llvm/utils/TableGen/EDEmitter.cpp \
llvm/utils/TableGen/FastISelEmitter.cpp \
@@ -589,6 +593,7 @@ am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
@MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcher.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcherEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcherGen.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcherOpt.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DisassemblerEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-EDEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-FastISelEmitter.$(OBJEXT) \
@@ -1031,6 +1036,7 @@ libllvmsupport_la_SOURCES = \
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcher.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcherEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcherGen.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcherOpt.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DisassemblerEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/EDEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/FastISelEmitter.cpp\
@@ -1113,7 +1119,7 @@ libllvmsupport_la_SOURCES = \
@MAINTAINER_MODE_TRUE at TBLGEN = $(top_builddir)/tblgen
@MAINTAINER_MODE_TRUE at TBLGEN_V = $(AM_V_GEN)$(TBLGEN)
- at MAINTAINER_MODE_TRUE@TBLGEN_FLAGS = -I$(top_srcdir)/llvm/include -I$(top_srcdir)/llvm/lib/Target
+ at MAINTAINER_MODE_TRUE@TBLGEN_FLAGS = -I$(top_srcdir)/llvm/include -I$(top_srcdir)/llvm/lib/Target -omit-comments
# X86 Target
@MAINTAINER_MODE_TRUE at TBLGEN_FLAGS_X86 = $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/X86
@@ -1125,11 +1131,12 @@ libllvmsupport_la_SOURCES = \
@MAINTAINER_MODE_TRUE at TBLGEN_FLAGS_ARM = $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/ARM
@BUILD_X86_TRUE at libllvmx86codegen_la_CPPFLAGS = $(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/X86
@BUILD_X86_TRUE at libllvmx86codegen_la_SOURCES = \
- at BUILD_X86_TRUE@ llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
@BUILD_X86_TRUE@ llvm/lib/MC/MCAsmInfoCOFF.cpp\
@BUILD_X86_TRUE@ llvm/lib/MC/MCCodeEmitter.cpp\
+ at BUILD_X86_TRUE@ llvm/lib/MC/TargetAsmBackend.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/TargetELFWriterInfo.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp\
+ at BUILD_X86_TRUE@ llvm/lib/Target/X86/X86AsmBackend.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86CodeEmitter.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86ELFWriterInfo.cpp\
@@ -1228,7 +1235,6 @@ libllvmjit_la_SOURCES = \
llvm/lib/MC/MCExpr.cpp\
llvm/lib/MC/MCSection.cpp\
llvm/lib/MC/MCSectionELF.cpp\
- llvm/lib/MC/MCSectionMachO.cpp\
llvm/lib/MC/MCSymbol.cpp\
llvm/lib/Support/APFloat.cpp\
llvm/lib/Support/APInt.cpp\
@@ -1332,9 +1338,11 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/LiveStackAnalysis.cpp\
llvm/lib/CodeGen/LiveVariables.cpp\
llvm/lib/CodeGen/LowerSubregs.cpp\
+ llvm/lib/CodeGen/MachineCSE.cpp\
llvm/lib/CodeGen/MachineDominators.cpp\
llvm/lib/CodeGen/MachineLICM.cpp\
llvm/lib/CodeGen/MachineLoopInfo.cpp\
+ llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/CodeGen/MachinePassRegistry.cpp\
llvm/lib/CodeGen/MachineSSAUpdater.cpp\
llvm/lib/CodeGen/MachineSink.cpp\
@@ -1384,6 +1392,7 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/StackSlotColoring.cpp\
llvm/lib/CodeGen/StrongPHIElimination.cpp\
llvm/lib/CodeGen/TailDuplication.cpp\
+ llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp\
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp\
llvm/lib/CodeGen/UnreachableBlockElim.cpp\
llvm/lib/CodeGen/VirtRegMap.cpp\
@@ -1394,6 +1403,7 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/MC/MCInst.cpp\
llvm/lib/MC/MCMachOStreamer.cpp\
llvm/lib/MC/MCNullStreamer.cpp\
+ llvm/lib/MC/MCSectionMachO.cpp\
llvm/lib/MC/MCStreamer.cpp\
llvm/lib/Target/TargetFrameInfo.cpp\
llvm/lib/Target/TargetSubtarget.cpp\
@@ -1536,7 +1546,6 @@ libllvmfullcodegen_la_SOURCES = \
llvm/lib/CodeGen/GCMetadataPrinter.cpp\
llvm/lib/CodeGen/IfConversion.cpp\
llvm/lib/CodeGen/IntrinsicLowering.cpp\
- llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/CodeGen/OcamlGC.cpp\
llvm/lib/CodeGen/RegAllocLocal.cpp\
llvm/lib/CodeGen/RegAllocPBQP.cpp\
@@ -1877,6 +1886,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCStreamer.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCSymbol.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachineBasicBlock.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachineCSE.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachineDominators.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachineFunction.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachineFunctionAnalysis.Plo at am__quote@
@@ -1982,6 +1992,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetIntrinsicInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetLowering.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetLoweringObjectFile.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetLoweringObjectFileImpl.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetMachine.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetRegisterInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetRegistry.Plo at am__quote@
@@ -2070,8 +2081,9 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmpowerpccodegen_la-PowerPCTargetInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-MCAsmInfoCOFF.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-MCCodeEmitter.Plo at am__quote@
- at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-MachineModuleInfoImpls.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-TargetAsmBackend.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-TargetELFWriterInfo.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-X86AsmBackend.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-X86COFFMachineModuleInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-X86CodeEmitter.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-X86ELFWriterInfo.Plo at am__quote@
@@ -2155,6 +2167,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DAGISelMatcher.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DAGISelMatcherEmitter.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DAGISelMatcherGen.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DAGISelMatcherOpt.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Debug.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DeltaAlgorithm.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Disassembler.Po at am__quote@
@@ -3131,6 +3144,14 @@ LowerSubregs.lo: llvm/lib/CodeGen/LowerSubregs.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o LowerSubregs.lo `test -f 'llvm/lib/CodeGen/LowerSubregs.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/LowerSubregs.cpp
+MachineCSE.lo: llvm/lib/CodeGen/MachineCSE.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachineCSE.lo -MD -MP -MF $(DEPDIR)/MachineCSE.Tpo -c -o MachineCSE.lo `test -f 'llvm/lib/CodeGen/MachineCSE.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineCSE.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachineCSE.Tpo $(DEPDIR)/MachineCSE.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/MachineCSE.cpp' object='MachineCSE.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MachineCSE.lo `test -f 'llvm/lib/CodeGen/MachineCSE.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineCSE.cpp
+
MachineDominators.lo: llvm/lib/CodeGen/MachineDominators.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachineDominators.lo -MD -MP -MF $(DEPDIR)/MachineDominators.Tpo -c -o MachineDominators.lo `test -f 'llvm/lib/CodeGen/MachineDominators.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineDominators.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachineDominators.Tpo $(DEPDIR)/MachineDominators.Plo
@@ -3155,6 +3176,14 @@ MachineLoopInfo.lo: llvm/lib/CodeGen/MachineLoopInfo.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MachineLoopInfo.lo `test -f 'llvm/lib/CodeGen/MachineLoopInfo.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineLoopInfo.cpp
+MachineModuleInfoImpls.lo: llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachineModuleInfoImpls.lo -MD -MP -MF $(DEPDIR)/MachineModuleInfoImpls.Tpo -c -o MachineModuleInfoImpls.lo `test -f 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachineModuleInfoImpls.Tpo $(DEPDIR)/MachineModuleInfoImpls.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' object='MachineModuleInfoImpls.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MachineModuleInfoImpls.lo `test -f 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
+
MachinePassRegistry.lo: llvm/lib/CodeGen/MachinePassRegistry.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachinePassRegistry.lo -MD -MP -MF $(DEPDIR)/MachinePassRegistry.Tpo -c -o MachinePassRegistry.lo `test -f 'llvm/lib/CodeGen/MachinePassRegistry.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachinePassRegistry.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachinePassRegistry.Tpo $(DEPDIR)/MachinePassRegistry.Plo
@@ -3547,6 +3576,14 @@ TailDuplication.lo: llvm/lib/CodeGen/TailDuplication.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o TailDuplication.lo `test -f 'llvm/lib/CodeGen/TailDuplication.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/TailDuplication.cpp
+TargetLoweringObjectFileImpl.lo: llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT TargetLoweringObjectFileImpl.lo -MD -MP -MF $(DEPDIR)/TargetLoweringObjectFileImpl.Tpo -c -o TargetLoweringObjectFileImpl.lo `test -f 'llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/TargetLoweringObjectFileImpl.Tpo $(DEPDIR)/TargetLoweringObjectFileImpl.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp' object='TargetLoweringObjectFileImpl.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o TargetLoweringObjectFileImpl.lo `test -f 'llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+
TwoAddressInstructionPass.lo: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT TwoAddressInstructionPass.lo -MD -MP -MF $(DEPDIR)/TwoAddressInstructionPass.Tpo -c -o TwoAddressInstructionPass.lo `test -f 'llvm/lib/CodeGen/TwoAddressInstructionPass.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/TwoAddressInstructionPass.Tpo $(DEPDIR)/TwoAddressInstructionPass.Plo
@@ -3627,6 +3664,14 @@ MCNullStreamer.lo: llvm/lib/MC/MCNullStreamer.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MCNullStreamer.lo `test -f 'llvm/lib/MC/MCNullStreamer.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCNullStreamer.cpp
+MCSectionMachO.lo: llvm/lib/MC/MCSectionMachO.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MCSectionMachO.lo -MD -MP -MF $(DEPDIR)/MCSectionMachO.Tpo -c -o MCSectionMachO.lo `test -f 'llvm/lib/MC/MCSectionMachO.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCSectionMachO.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MCSectionMachO.Tpo $(DEPDIR)/MCSectionMachO.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/MC/MCSectionMachO.cpp' object='MCSectionMachO.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MCSectionMachO.lo `test -f 'llvm/lib/MC/MCSectionMachO.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCSectionMachO.cpp
+
MCStreamer.lo: llvm/lib/MC/MCStreamer.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MCStreamer.lo -MD -MP -MF $(DEPDIR)/MCStreamer.Tpo -c -o MCStreamer.lo `test -f 'llvm/lib/MC/MCStreamer.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCStreamer.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MCStreamer.Tpo $(DEPDIR)/MCStreamer.Plo
@@ -3819,14 +3864,6 @@ IntrinsicLowering.lo: llvm/lib/CodeGen/IntrinsicLowering.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o IntrinsicLowering.lo `test -f 'llvm/lib/CodeGen/IntrinsicLowering.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/IntrinsicLowering.cpp
-MachineModuleInfoImpls.lo: llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachineModuleInfoImpls.lo -MD -MP -MF $(DEPDIR)/MachineModuleInfoImpls.Tpo -c -o MachineModuleInfoImpls.lo `test -f 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachineModuleInfoImpls.Tpo $(DEPDIR)/MachineModuleInfoImpls.Plo
- at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' object='MachineModuleInfoImpls.lo' libtool=yes @AMDEPBACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MachineModuleInfoImpls.lo `test -f 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
-
OcamlGC.lo: llvm/lib/CodeGen/OcamlGC.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT OcamlGC.lo -MD -MP -MF $(DEPDIR)/OcamlGC.Tpo -c -o OcamlGC.lo `test -f 'llvm/lib/CodeGen/OcamlGC.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/OcamlGC.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/OcamlGC.Tpo $(DEPDIR)/OcamlGC.Plo
@@ -4179,14 +4216,6 @@ MCSectionELF.lo: llvm/lib/MC/MCSectionELF.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MCSectionELF.lo `test -f 'llvm/lib/MC/MCSectionELF.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCSectionELF.cpp
-MCSectionMachO.lo: llvm/lib/MC/MCSectionMachO.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MCSectionMachO.lo -MD -MP -MF $(DEPDIR)/MCSectionMachO.Tpo -c -o MCSectionMachO.lo `test -f 'llvm/lib/MC/MCSectionMachO.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCSectionMachO.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MCSectionMachO.Tpo $(DEPDIR)/MCSectionMachO.Plo
- at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/MC/MCSectionMachO.cpp' object='MCSectionMachO.lo' libtool=yes @AMDEPBACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MCSectionMachO.lo `test -f 'llvm/lib/MC/MCSectionMachO.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCSectionMachO.cpp
-
MCSymbol.lo: llvm/lib/MC/MCSymbol.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MCSymbol.lo -MD -MP -MF $(DEPDIR)/MCSymbol.Tpo -c -o MCSymbol.lo `test -f 'llvm/lib/MC/MCSymbol.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCSymbol.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MCSymbol.Tpo $(DEPDIR)/MCSymbol.Plo
@@ -5043,14 +5072,6 @@ TimeValue.lo: llvm/lib/System/TimeValue.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o TimeValue.lo `test -f 'llvm/lib/System/TimeValue.cpp' || echo '$(srcdir)/'`llvm/lib/System/TimeValue.cpp
-libllvmx86codegen_la-MachineModuleInfoImpls.lo: llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-MachineModuleInfoImpls.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-MachineModuleInfoImpls.Tpo -c -o libllvmx86codegen_la-MachineModuleInfoImpls.lo `test -f 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libllvmx86codegen_la-MachineModuleInfoImpls.Tpo $(DEPDIR)/libllvmx86codegen_la-MachineModuleInfoImpls.Plo
- at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' object='libllvmx86codegen_la-MachineModuleInfoImpls.lo' libtool=yes @AMDEPBACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o libllvmx86codegen_la-MachineModuleInfoImpls.lo `test -f 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
-
libllvmx86codegen_la-MCAsmInfoCOFF.lo: llvm/lib/MC/MCAsmInfoCOFF.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-MCAsmInfoCOFF.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-MCAsmInfoCOFF.Tpo -c -o libllvmx86codegen_la-MCAsmInfoCOFF.lo `test -f 'llvm/lib/MC/MCAsmInfoCOFF.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCAsmInfoCOFF.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libllvmx86codegen_la-MCAsmInfoCOFF.Tpo $(DEPDIR)/libllvmx86codegen_la-MCAsmInfoCOFF.Plo
@@ -5067,6 +5088,14 @@ libllvmx86codegen_la-MCCodeEmitter.lo: llvm/lib/MC/MCCodeEmitter.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o libllvmx86codegen_la-MCCodeEmitter.lo `test -f 'llvm/lib/MC/MCCodeEmitter.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCCodeEmitter.cpp
+libllvmx86codegen_la-TargetAsmBackend.lo: llvm/lib/MC/TargetAsmBackend.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-TargetAsmBackend.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-TargetAsmBackend.Tpo -c -o libllvmx86codegen_la-TargetAsmBackend.lo `test -f 'llvm/lib/MC/TargetAsmBackend.cpp' || echo '$(srcdir)/'`llvm/lib/MC/TargetAsmBackend.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libllvmx86codegen_la-TargetAsmBackend.Tpo $(DEPDIR)/libllvmx86codegen_la-TargetAsmBackend.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/MC/TargetAsmBackend.cpp' object='libllvmx86codegen_la-TargetAsmBackend.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o libllvmx86codegen_la-TargetAsmBackend.lo `test -f 'llvm/lib/MC/TargetAsmBackend.cpp' || echo '$(srcdir)/'`llvm/lib/MC/TargetAsmBackend.cpp
+
libllvmx86codegen_la-TargetELFWriterInfo.lo: llvm/lib/Target/TargetELFWriterInfo.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-TargetELFWriterInfo.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-TargetELFWriterInfo.Tpo -c -o libllvmx86codegen_la-TargetELFWriterInfo.lo `test -f 'llvm/lib/Target/TargetELFWriterInfo.cpp' || echo '$(srcdir)/'`llvm/lib/Target/TargetELFWriterInfo.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libllvmx86codegen_la-TargetELFWriterInfo.Tpo $(DEPDIR)/libllvmx86codegen_la-TargetELFWriterInfo.Plo
@@ -5083,6 +5112,14 @@ libllvmx86codegen_la-X86TargetInfo.lo: llvm/lib/Target/X86/TargetInfo/X86TargetI
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o libllvmx86codegen_la-X86TargetInfo.lo `test -f 'llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp' || echo '$(srcdir)/'`llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp
+libllvmx86codegen_la-X86AsmBackend.lo: llvm/lib/Target/X86/X86AsmBackend.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-X86AsmBackend.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-X86AsmBackend.Tpo -c -o libllvmx86codegen_la-X86AsmBackend.lo `test -f 'llvm/lib/Target/X86/X86AsmBackend.cpp' || echo '$(srcdir)/'`llvm/lib/Target/X86/X86AsmBackend.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libllvmx86codegen_la-X86AsmBackend.Tpo $(DEPDIR)/libllvmx86codegen_la-X86AsmBackend.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Target/X86/X86AsmBackend.cpp' object='libllvmx86codegen_la-X86AsmBackend.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o libllvmx86codegen_la-X86AsmBackend.lo `test -f 'llvm/lib/Target/X86/X86AsmBackend.cpp' || echo '$(srcdir)/'`llvm/lib/Target/X86/X86AsmBackend.cpp
+
libllvmx86codegen_la-X86COFFMachineModuleInfo.lo: llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-X86COFFMachineModuleInfo.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-X86COFFMachineModuleInfo.Tpo -c -o libllvmx86codegen_la-X86COFFMachineModuleInfo.lo `test -f 'llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp' || echo '$(srcdir)/'`llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libllvmx86codegen_la-X86COFFMachineModuleInfo.Tpo $(DEPDIR)/libllvmx86codegen_la-X86COFFMachineModuleInfo.Plo
@@ -6035,6 +6072,22 @@ tblgen-DAGISelMatcherGen.obj: llvm/utils/TableGen/DAGISelMatcherGen.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelMatcherGen.obj `if test -f 'llvm/utils/TableGen/DAGISelMatcherGen.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelMatcherGen.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelMatcherGen.cpp'; fi`
+tblgen-DAGISelMatcherOpt.o: llvm/utils/TableGen/DAGISelMatcherOpt.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelMatcherOpt.o -MD -MP -MF $(DEPDIR)/tblgen-DAGISelMatcherOpt.Tpo -c -o tblgen-DAGISelMatcherOpt.o `test -f 'llvm/utils/TableGen/DAGISelMatcherOpt.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelMatcherOpt.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelMatcherOpt.Tpo $(DEPDIR)/tblgen-DAGISelMatcherOpt.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelMatcherOpt.cpp' object='tblgen-DAGISelMatcherOpt.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelMatcherOpt.o `test -f 'llvm/utils/TableGen/DAGISelMatcherOpt.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelMatcherOpt.cpp
+
+tblgen-DAGISelMatcherOpt.obj: llvm/utils/TableGen/DAGISelMatcherOpt.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelMatcherOpt.obj -MD -MP -MF $(DEPDIR)/tblgen-DAGISelMatcherOpt.Tpo -c -o tblgen-DAGISelMatcherOpt.obj `if test -f 'llvm/utils/TableGen/DAGISelMatcherOpt.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelMatcherOpt.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelMatcherOpt.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelMatcherOpt.Tpo $(DEPDIR)/tblgen-DAGISelMatcherOpt.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelMatcherOpt.cpp' object='tblgen-DAGISelMatcherOpt.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelMatcherOpt.obj `if test -f 'llvm/utils/TableGen/DAGISelMatcherOpt.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelMatcherOpt.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelMatcherOpt.cpp'; fi`
+
tblgen-DisassemblerEmitter.o: llvm/utils/TableGen/DisassemblerEmitter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DisassemblerEmitter.o -MD -MP -MF $(DEPDIR)/tblgen-DisassemblerEmitter.Tpo -c -o tblgen-DisassemblerEmitter.o `test -f 'llvm/utils/TableGen/DisassemblerEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DisassemblerEmitter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DisassemblerEmitter.Tpo $(DEPDIR)/tblgen-DisassemblerEmitter.Po
diff --git a/libclamav/c++/PPCGenAsmWriter.inc b/libclamav/c++/PPCGenAsmWriter.inc
index 142ebe1..fa1d206 100644
--- a/libclamav/c++/PPCGenAsmWriter.inc
+++ b/libclamav/c++/PPCGenAsmWriter.inc
@@ -157,8 +157,7 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
268435860U, // FDIVS
268435867U, // FMADD
268435874U, // FMADDS
- 268468650U, // FMRD
- 268468650U, // FMRS
+ 268468650U, // FMR
268468650U, // FMRSD
268435887U, // FMSUB
268435894U, // FMSUBS
@@ -338,7 +337,6 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
270009560U, // STWBRX
270009568U, // STWCX
3409970408U, // STWU
- 3409970408U, // STWU8
268436718U, // STWUX
270009589U, // STWX
270009589U, // STWX8
@@ -663,7 +661,7 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 12:
- // MTFSF, STBU, STBU8, STDU, STFDU, STFSU, STHU, STHU8, STWU, STWU8
+ // MTFSF, STBU, STBU8, STDU, STFDU, STFSU, STHU, STHU8, STWU
printOperand(MI, 1);
O << ", ";
break;
@@ -915,7 +913,7 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 45:
- // STBU, STBU8, STFDU, STFSU, STHU, STHU8, STWU, STWU8
+ // STBU, STBU8, STFDU, STFSU, STHU, STHU8, STWU
printSymbolLo(MI, 2);
O << '(';
printOperand(MI, 3);
@@ -1405,7 +1403,7 @@ const char *PPCAsmPrinter::getRegisterName(unsigned RegNo) {
/// from the instruction set description. This returns the enum name of the
/// specified instruction.
const char *PPCAsmPrinter::getInstructionName(unsigned Opcode) {
- assert(Opcode < 521 && "Invalid instruction number!");
+ assert(Opcode < 519 && "Invalid instruction number!");
static const unsigned InstAsmOffset[] = {
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 135,
@@ -1418,34 +1416,34 @@ const char *PPCAsmPrinter::getInstructionName(unsigned Opcode) {
1138, 1143, 1149, 1154, 1159, 1164, 1170, 1175, 1182, 1187, 1193, 1198, 1204, 1209,
1215, 1219, 1226, 1230, 1236, 1242, 1250, 1257, 1266, 1271, 1278, 1287, 1297, 1301,
1306, 1312, 1319, 1325, 1332, 1338, 1347, 1359, 1365, 1371, 1376, 1382, 1390, 1396,
- 1403, 1410, 1417, 1424, 1429, 1435, 1441, 1448, 1453, 1458, 1464, 1470, 1477, 1482,
- 1488, 1495, 1502, 1508, 1514, 1521, 1529, 1536, 1544, 1549, 1555, 1561, 1567, 1574,
- 1579, 1585, 1588, 1592, 1597, 1602, 1608, 1613, 1619, 1622, 1628, 1632, 1636, 1647,
- 1653, 1667, 1671, 1676, 1681, 1685, 1690, 1695, 1699, 1704, 1709, 1715, 1720, 1726,
- 1732, 1736, 1741, 1746, 1752, 1757, 1763, 1766, 1770, 1774, 1779, 1785, 1791, 1797,
- 1802, 1807, 1811, 1816, 1820, 1826, 1831, 1837, 1841, 1846, 1851, 1857, 1862, 1868,
- 1873, 1878, 1884, 1891, 1896, 1901, 1907, 1914, 1923, 1930, 1936, 1942, 1949, 1956,
- 1963, 1969, 1974, 1980, 1989, 1996, 2002, 2009, 2015, 2022, 2028, 2034, 2040, 2051,
- 2063, 2068, 2074, 2078, 2083, 2087, 2091, 2096, 2099, 2106, 2110, 2117, 2121, 2126,
- 2130, 2135, 2140, 2146, 2152, 2159, 2166, 2173, 2180, 2187, 2195, 2201, 2214, 2227,
- 2240, 2253, 2268, 2272, 2276, 2285, 2290, 2296, 2301, 2307, 2311, 2315, 2319, 2324,
- 2329, 2335, 2340, 2346, 2350, 2356, 2361, 2367, 2372, 2380, 2387, 2392, 2398, 2404,
- 2411, 2416, 2422, 2428, 2432, 2437, 2444, 2449, 2455, 2460, 2466, 2473, 2480, 2487,
- 2492, 2498, 2502, 2507, 2514, 2520, 2525, 2531, 2537, 2542, 2548, 2553, 2559, 2565,
- 2572, 2578, 2585, 2592, 2600, 2607, 2615, 2622, 2630, 2635, 2641, 2648, 2655, 2663,
- 2672, 2682, 2693, 2705, 2716, 2728, 2739, 2751, 2756, 2770, 2778, 2785, 2793, 2801,
- 2809, 2817, 2825, 2833, 2841, 2849, 2857, 2862, 2868, 2875, 2882, 2889, 2896, 2903,
- 2910, 2916, 2922, 2930, 2939, 2948, 2958, 2967, 2977, 2986, 2996, 3005, 3015, 3024,
- 3034, 3043, 3053, 3062, 3072, 3081, 3091, 3100, 3110, 3119, 3129, 3138, 3148, 3157,
- 3167, 3174, 3181, 3190, 3198, 3206, 3213, 3220, 3227, 3234, 3241, 3248, 3255, 3265,
- 3276, 3283, 3290, 3297, 3304, 3311, 3318, 3325, 3335, 3342, 3349, 3356, 3363, 3370,
- 3377, 3386, 3395, 3404, 3413, 3422, 3431, 3439, 3447, 3455, 3463, 3471, 3479, 3487,
- 3495, 3504, 3509, 3513, 3519, 3525, 3533, 3541, 3549, 3557, 3565, 3573, 3581, 3589,
- 3595, 3601, 3607, 3613, 3619, 3624, 3629, 3634, 3644, 3649, 3653, 3658, 3665, 3670,
- 3675, 3680, 3687, 3694, 3703, 3712, 3721, 3728, 3732, 3738, 3744, 3750, 3755, 3760,
- 3765, 3770, 3778, 3785, 3793, 3801, 3809, 3817, 3825, 3833, 3841, 3849, 3857, 3866,
- 3875, 3884, 3893, 3901, 3909, 3917, 3925, 3933, 3941, 3949, 3954, 3961, 3965, 3970,
- 3975, 3981, 3987, 0
+ 1403, 1410, 1417, 1424, 1429, 1435, 1441, 1448, 1452, 1458, 1464, 1471, 1476, 1482,
+ 1489, 1496, 1502, 1508, 1515, 1523, 1530, 1538, 1543, 1549, 1555, 1561, 1568, 1573,
+ 1579, 1582, 1586, 1591, 1596, 1602, 1607, 1613, 1616, 1622, 1626, 1630, 1641, 1647,
+ 1661, 1665, 1670, 1675, 1679, 1684, 1689, 1693, 1698, 1703, 1709, 1714, 1720, 1726,
+ 1730, 1735, 1740, 1746, 1751, 1757, 1760, 1764, 1768, 1773, 1779, 1785, 1791, 1796,
+ 1801, 1805, 1810, 1814, 1820, 1825, 1831, 1835, 1840, 1845, 1851, 1856, 1862, 1867,
+ 1872, 1878, 1885, 1890, 1895, 1901, 1908, 1917, 1924, 1930, 1936, 1943, 1950, 1957,
+ 1963, 1968, 1974, 1983, 1990, 1996, 2003, 2009, 2016, 2022, 2028, 2034, 2045, 2057,
+ 2062, 2068, 2072, 2077, 2081, 2085, 2090, 2093, 2100, 2104, 2111, 2115, 2120, 2124,
+ 2129, 2134, 2140, 2146, 2153, 2160, 2167, 2174, 2181, 2189, 2195, 2208, 2221, 2234,
+ 2247, 2262, 2266, 2270, 2279, 2284, 2290, 2295, 2301, 2305, 2309, 2313, 2318, 2323,
+ 2329, 2334, 2340, 2344, 2350, 2355, 2361, 2366, 2374, 2381, 2386, 2392, 2398, 2405,
+ 2410, 2416, 2422, 2426, 2431, 2438, 2443, 2449, 2454, 2460, 2467, 2474, 2481, 2486,
+ 2492, 2496, 2501, 2508, 2514, 2519, 2525, 2530, 2536, 2541, 2547, 2553, 2560, 2566,
+ 2573, 2580, 2588, 2595, 2603, 2610, 2618, 2623, 2629, 2636, 2643, 2651, 2660, 2670,
+ 2681, 2693, 2704, 2716, 2727, 2739, 2744, 2758, 2766, 2773, 2781, 2789, 2797, 2805,
+ 2813, 2821, 2829, 2837, 2845, 2850, 2856, 2863, 2870, 2877, 2884, 2891, 2898, 2904,
+ 2910, 2918, 2927, 2936, 2946, 2955, 2965, 2974, 2984, 2993, 3003, 3012, 3022, 3031,
+ 3041, 3050, 3060, 3069, 3079, 3088, 3098, 3107, 3117, 3126, 3136, 3145, 3155, 3162,
+ 3169, 3178, 3186, 3194, 3201, 3208, 3215, 3222, 3229, 3236, 3243, 3253, 3264, 3271,
+ 3278, 3285, 3292, 3299, 3306, 3313, 3323, 3330, 3337, 3344, 3351, 3358, 3365, 3374,
+ 3383, 3392, 3401, 3410, 3419, 3427, 3435, 3443, 3451, 3459, 3467, 3475, 3483, 3492,
+ 3497, 3501, 3507, 3513, 3521, 3529, 3537, 3545, 3553, 3561, 3569, 3577, 3583, 3589,
+ 3595, 3601, 3607, 3612, 3617, 3622, 3632, 3637, 3641, 3646, 3653, 3658, 3663, 3668,
+ 3675, 3682, 3691, 3700, 3709, 3716, 3720, 3726, 3732, 3738, 3743, 3748, 3753, 3758,
+ 3766, 3773, 3781, 3789, 3797, 3805, 3813, 3821, 3829, 3837, 3845, 3854, 3863, 3872,
+ 3881, 3889, 3897, 3905, 3913, 3921, 3929, 3937, 3942, 3949, 3953, 3958, 3963, 3969,
+ 3975, 0
};
const char *Strs =
@@ -1475,58 +1473,58 @@ const char *PPCAsmPrinter::getInstructionName(unsigned Opcode) {
"NALLOC\000DYNALLOC8\000EQV\000EQV8\000EXTSB\000EXTSB8\000EXTSH\000EXTSH"
"8\000EXTSW\000EXTSW_32\000EXTSW_32_64\000FABSD\000FABSS\000FADD\000FADD"
"S\000FADDrtz\000FCFID\000FCMPUD\000FCMPUS\000FCTIDZ\000FCTIWZ\000FDIV\000"
- "FDIVS\000FMADD\000FMADDS\000FMRD\000FMRS\000FMRSD\000FMSUB\000FMSUBS\000"
- "FMUL\000FMULS\000FNABSD\000FNABSS\000FNEGD\000FNEGS\000FNMADD\000FNMADD"
- "S\000FNMSUB\000FNMSUBS\000FRSP\000FSELD\000FSELS\000FSQRT\000FSQRTS\000"
- "FSUB\000FSUBS\000LA\000LBZ\000LBZ8\000LBZU\000LBZU8\000LBZX\000LBZX8\000"
- "LD\000LDARX\000LDU\000LDX\000LDinto_toc\000LDtoc\000LDtoc_restore\000LF"
- "D\000LFDU\000LFDX\000LFS\000LFSU\000LFSX\000LHA\000LHA8\000LHAU\000LHAU"
- "8\000LHAX\000LHAX8\000LHBRX\000LHZ\000LHZ8\000LHZU\000LHZU8\000LHZX\000"
- "LHZX8\000LI\000LI8\000LIS\000LIS8\000LVEBX\000LVEHX\000LVEWX\000LVSL\000"
- "LVSR\000LVX\000LVXL\000LWA\000LWARX\000LWAX\000LWBRX\000LWZ\000LWZ8\000"
- "LWZU\000LWZU8\000LWZX\000LWZX8\000MCRF\000MFCR\000MFCTR\000MFCTR8\000MF"
- "FS\000MFLR\000MFLR8\000MFOCRF\000MFVRSAVE\000MFVSCR\000MTCRF\000MTCTR\000"
- "MTCTR8\000MTFSB0\000MTFSB1\000MTFSF\000MTLR\000MTLR8\000MTVRSAVE\000MTV"
- "SCR\000MULHD\000MULHDU\000MULHW\000MULHWU\000MULLD\000MULLI\000MULLW\000"
- "MovePCtoLR\000MovePCtoLR8\000NAND\000NAND8\000NEG\000NEG8\000NOP\000NOR"
- "\000NOR8\000OR\000OR4To8\000OR8\000OR8To4\000ORC\000ORC8\000ORI\000ORI8"
- "\000ORIS\000ORIS8\000RLDCL\000RLDICL\000RLDICR\000RLDIMI\000RLWIMI\000R"
- "LWINM\000RLWINMo\000RLWNM\000SELECT_CC_F4\000SELECT_CC_F8\000SELECT_CC_"
- "I4\000SELECT_CC_I8\000SELECT_CC_VRRC\000SLD\000SLW\000SPILL_CR\000SRAD\000"
- "SRADI\000SRAW\000SRAWI\000SRD\000SRW\000STB\000STB8\000STBU\000STBU8\000"
- "STBX\000STBX8\000STD\000STDCX\000STDU\000STDUX\000STDX\000STDX_32\000ST"
- "D_32\000STFD\000STFDU\000STFDX\000STFIWX\000STFS\000STFSU\000STFSX\000S"
- "TH\000STH8\000STHBRX\000STHU\000STHU8\000STHX\000STHX8\000STVEBX\000STV"
- "EHX\000STVEWX\000STVX\000STVXL\000STW\000STW8\000STWBRX\000STWCX\000STW"
- "U\000STWU8\000STWUX\000STWX\000STWX8\000SUBF\000SUBF8\000SUBFC\000SUBFC"
- "8\000SUBFE\000SUBFE8\000SUBFIC\000SUBFIC8\000SUBFME\000SUBFME8\000SUBFZ"
- "E\000SUBFZE8\000SYNC\000TAILB\000TAILB8\000TAILBA\000TAILBA8\000TAILBCT"
- "R\000TAILBCTR8\000TCRETURNai\000TCRETURNai8\000TCRETURNdi\000TCRETURNdi"
- "8\000TCRETURNri\000TCRETURNri8\000TRAP\000UPDATE_VRSAVE\000VADDCUW\000V"
- "ADDFP\000VADDSBS\000VADDSHS\000VADDSWS\000VADDUBM\000VADDUBS\000VADDUHM"
- "\000VADDUHS\000VADDUWM\000VADDUWS\000VAND\000VANDC\000VAVGSB\000VAVGSH\000"
- "VAVGSW\000VAVGUB\000VAVGUH\000VAVGUW\000VCFSX\000VCFUX\000VCMPBFP\000VC"
- "MPBFPo\000VCMPEQFP\000VCMPEQFPo\000VCMPEQUB\000VCMPEQUBo\000VCMPEQUH\000"
- "VCMPEQUHo\000VCMPEQUW\000VCMPEQUWo\000VCMPGEFP\000VCMPGEFPo\000VCMPGTFP"
- "\000VCMPGTFPo\000VCMPGTSB\000VCMPGTSBo\000VCMPGTSH\000VCMPGTSHo\000VCMP"
- "GTSW\000VCMPGTSWo\000VCMPGTUB\000VCMPGTUBo\000VCMPGTUH\000VCMPGTUHo\000"
- "VCMPGTUW\000VCMPGTUWo\000VCTSXS\000VCTUXS\000VEXPTEFP\000VLOGEFP\000VMA"
- "DDFP\000VMAXFP\000VMAXSB\000VMAXSH\000VMAXSW\000VMAXUB\000VMAXUH\000VMA"
- "XUW\000VMHADDSHS\000VMHRADDSHS\000VMINFP\000VMINSB\000VMINSH\000VMINSW\000"
- "VMINUB\000VMINUH\000VMINUW\000VMLADDUHM\000VMRGHB\000VMRGHH\000VMRGHW\000"
- "VMRGLB\000VMRGLH\000VMRGLW\000VMSUMMBM\000VMSUMSHM\000VMSUMSHS\000VMSUM"
- "UBM\000VMSUMUHM\000VMSUMUHS\000VMULESB\000VMULESH\000VMULEUB\000VMULEUH"
- "\000VMULOSB\000VMULOSH\000VMULOUB\000VMULOUH\000VNMSUBFP\000VNOR\000VOR"
- "\000VPERM\000VPKPX\000VPKSHSS\000VPKSHUS\000VPKSWSS\000VPKSWUS\000VPKUH"
- "UM\000VPKUHUS\000VPKUWUM\000VPKUWUS\000VREFP\000VRFIM\000VRFIN\000VRFIP"
- "\000VRFIZ\000VRLB\000VRLH\000VRLW\000VRSQRTEFP\000VSEL\000VSL\000VSLB\000"
- "VSLDOI\000VSLH\000VSLO\000VSLW\000VSPLTB\000VSPLTH\000VSPLTISB\000VSPLT"
- "ISH\000VSPLTISW\000VSPLTW\000VSR\000VSRAB\000VSRAH\000VSRAW\000VSRB\000"
- "VSRH\000VSRO\000VSRW\000VSUBCUW\000VSUBFP\000VSUBSBS\000VSUBSHS\000VSUB"
- "SWS\000VSUBUBM\000VSUBUBS\000VSUBUHM\000VSUBUHS\000VSUBUWM\000VSUBUWS\000"
- "VSUM2SWS\000VSUM4SBS\000VSUM4SHS\000VSUM4UBS\000VSUMSWS\000VUPKHPX\000V"
- "UPKHSB\000VUPKHSH\000VUPKLPX\000VUPKLSB\000VUPKLSH\000VXOR\000V_SET0\000"
- "XOR\000XOR8\000XORI\000XORI8\000XORIS\000XORIS8\000";
+ "FDIVS\000FMADD\000FMADDS\000FMR\000FMRSD\000FMSUB\000FMSUBS\000FMUL\000"
+ "FMULS\000FNABSD\000FNABSS\000FNEGD\000FNEGS\000FNMADD\000FNMADDS\000FNM"
+ "SUB\000FNMSUBS\000FRSP\000FSELD\000FSELS\000FSQRT\000FSQRTS\000FSUB\000"
+ "FSUBS\000LA\000LBZ\000LBZ8\000LBZU\000LBZU8\000LBZX\000LBZX8\000LD\000L"
+ "DARX\000LDU\000LDX\000LDinto_toc\000LDtoc\000LDtoc_restore\000LFD\000LF"
+ "DU\000LFDX\000LFS\000LFSU\000LFSX\000LHA\000LHA8\000LHAU\000LHAU8\000LH"
+ "AX\000LHAX8\000LHBRX\000LHZ\000LHZ8\000LHZU\000LHZU8\000LHZX\000LHZX8\000"
+ "LI\000LI8\000LIS\000LIS8\000LVEBX\000LVEHX\000LVEWX\000LVSL\000LVSR\000"
+ "LVX\000LVXL\000LWA\000LWARX\000LWAX\000LWBRX\000LWZ\000LWZ8\000LWZU\000"
+ "LWZU8\000LWZX\000LWZX8\000MCRF\000MFCR\000MFCTR\000MFCTR8\000MFFS\000MF"
+ "LR\000MFLR8\000MFOCRF\000MFVRSAVE\000MFVSCR\000MTCRF\000MTCTR\000MTCTR8"
+ "\000MTFSB0\000MTFSB1\000MTFSF\000MTLR\000MTLR8\000MTVRSAVE\000MTVSCR\000"
+ "MULHD\000MULHDU\000MULHW\000MULHWU\000MULLD\000MULLI\000MULLW\000MovePC"
+ "toLR\000MovePCtoLR8\000NAND\000NAND8\000NEG\000NEG8\000NOP\000NOR\000NO"
+ "R8\000OR\000OR4To8\000OR8\000OR8To4\000ORC\000ORC8\000ORI\000ORI8\000OR"
+ "IS\000ORIS8\000RLDCL\000RLDICL\000RLDICR\000RLDIMI\000RLWIMI\000RLWINM\000"
+ "RLWINMo\000RLWNM\000SELECT_CC_F4\000SELECT_CC_F8\000SELECT_CC_I4\000SEL"
+ "ECT_CC_I8\000SELECT_CC_VRRC\000SLD\000SLW\000SPILL_CR\000SRAD\000SRADI\000"
+ "SRAW\000SRAWI\000SRD\000SRW\000STB\000STB8\000STBU\000STBU8\000STBX\000"
+ "STBX8\000STD\000STDCX\000STDU\000STDUX\000STDX\000STDX_32\000STD_32\000"
+ "STFD\000STFDU\000STFDX\000STFIWX\000STFS\000STFSU\000STFSX\000STH\000ST"
+ "H8\000STHBRX\000STHU\000STHU8\000STHX\000STHX8\000STVEBX\000STVEHX\000S"
+ "TVEWX\000STVX\000STVXL\000STW\000STW8\000STWBRX\000STWCX\000STWU\000STW"
+ "UX\000STWX\000STWX8\000SUBF\000SUBF8\000SUBFC\000SUBFC8\000SUBFE\000SUB"
+ "FE8\000SUBFIC\000SUBFIC8\000SUBFME\000SUBFME8\000SUBFZE\000SUBFZE8\000S"
+ "YNC\000TAILB\000TAILB8\000TAILBA\000TAILBA8\000TAILBCTR\000TAILBCTR8\000"
+ "TCRETURNai\000TCRETURNai8\000TCRETURNdi\000TCRETURNdi8\000TCRETURNri\000"
+ "TCRETURNri8\000TRAP\000UPDATE_VRSAVE\000VADDCUW\000VADDFP\000VADDSBS\000"
+ "VADDSHS\000VADDSWS\000VADDUBM\000VADDUBS\000VADDUHM\000VADDUHS\000VADDU"
+ "WM\000VADDUWS\000VAND\000VANDC\000VAVGSB\000VAVGSH\000VAVGSW\000VAVGUB\000"
+ "VAVGUH\000VAVGUW\000VCFSX\000VCFUX\000VCMPBFP\000VCMPBFPo\000VCMPEQFP\000"
+ "VCMPEQFPo\000VCMPEQUB\000VCMPEQUBo\000VCMPEQUH\000VCMPEQUHo\000VCMPEQUW"
+ "\000VCMPEQUWo\000VCMPGEFP\000VCMPGEFPo\000VCMPGTFP\000VCMPGTFPo\000VCMP"
+ "GTSB\000VCMPGTSBo\000VCMPGTSH\000VCMPGTSHo\000VCMPGTSW\000VCMPGTSWo\000"
+ "VCMPGTUB\000VCMPGTUBo\000VCMPGTUH\000VCMPGTUHo\000VCMPGTUW\000VCMPGTUWo"
+ "\000VCTSXS\000VCTUXS\000VEXPTEFP\000VLOGEFP\000VMADDFP\000VMAXFP\000VMA"
+ "XSB\000VMAXSH\000VMAXSW\000VMAXUB\000VMAXUH\000VMAXUW\000VMHADDSHS\000V"
+ "MHRADDSHS\000VMINFP\000VMINSB\000VMINSH\000VMINSW\000VMINUB\000VMINUH\000"
+ "VMINUW\000VMLADDUHM\000VMRGHB\000VMRGHH\000VMRGHW\000VMRGLB\000VMRGLH\000"
+ "VMRGLW\000VMSUMMBM\000VMSUMSHM\000VMSUMSHS\000VMSUMUBM\000VMSUMUHM\000V"
+ "MSUMUHS\000VMULESB\000VMULESH\000VMULEUB\000VMULEUH\000VMULOSB\000VMULO"
+ "SH\000VMULOUB\000VMULOUH\000VNMSUBFP\000VNOR\000VOR\000VPERM\000VPKPX\000"
+ "VPKSHSS\000VPKSHUS\000VPKSWSS\000VPKSWUS\000VPKUHUM\000VPKUHUS\000VPKUW"
+ "UM\000VPKUWUS\000VREFP\000VRFIM\000VRFIN\000VRFIP\000VRFIZ\000VRLB\000V"
+ "RLH\000VRLW\000VRSQRTEFP\000VSEL\000VSL\000VSLB\000VSLDOI\000VSLH\000VS"
+ "LO\000VSLW\000VSPLTB\000VSPLTH\000VSPLTISB\000VSPLTISH\000VSPLTISW\000V"
+ "SPLTW\000VSR\000VSRAB\000VSRAH\000VSRAW\000VSRB\000VSRH\000VSRO\000VSRW"
+ "\000VSUBCUW\000VSUBFP\000VSUBSBS\000VSUBSHS\000VSUBSWS\000VSUBUBM\000VS"
+ "UBUBS\000VSUBUHM\000VSUBUHS\000VSUBUWM\000VSUBUWS\000VSUM2SWS\000VSUM4S"
+ "BS\000VSUM4SHS\000VSUM4UBS\000VSUMSWS\000VUPKHPX\000VUPKHSB\000VUPKHSH\000"
+ "VUPKLPX\000VUPKLSB\000VUPKLSH\000VXOR\000V_SET0\000XOR\000XOR8\000XORI\000"
+ "XORI8\000XORIS\000XORIS8\000";
return Strs+InstAsmOffset[Opcode];
}
diff --git a/libclamav/c++/PPCGenCallingConv.inc b/libclamav/c++/PPCGenCallingConv.inc
index da7d05e..21aaed2 100644
--- a/libclamav/c++/PPCGenCallingConv.inc
+++ b/libclamav/c++/PPCGenCallingConv.inc
@@ -75,14 +75,12 @@ static bool CC_PPC_SVR4_Common(unsigned ValNo, EVT ValVT,
}
if (LocVT == MVT::i32) {
- if (!ArgFlags.isInReg()) {
- static const unsigned RegList1[] = {
- PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
- };
- if (unsigned Reg = State.AllocateReg(RegList1, 8)) {
- State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
- return false;
- }
+ static const unsigned RegList1[] = {
+ PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 8)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
}
}
diff --git a/libclamav/c++/PPCGenCodeEmitter.inc b/libclamav/c++/PPCGenCodeEmitter.inc
index ebb9db1..8283292 100644
--- a/libclamav/c++/PPCGenCodeEmitter.inc
+++ b/libclamav/c++/PPCGenCodeEmitter.inc
@@ -155,8 +155,7 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
3959423012U, // FDIVS
4227858490U, // FMADD
3959423034U, // FMADDS
- 4227858576U, // FMRD
- 4227858576U, // FMRS
+ 4227858576U, // FMR
4227858576U, // FMRSD
4227858488U, // FMSUB
3959423032U, // FMSUBS
@@ -336,7 +335,6 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
2080376108U, // STWBRX
2080375085U, // STWCX
2483027968U, // STWU
- 2483027968U, // STWU8
2080375150U, // STWUX
2080375086U, // STWX
2080375086U, // STWX8
@@ -772,8 +770,7 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::STFSU:
case PPC::STHU:
case PPC::STHU8:
- case PPC::STWU:
- case PPC::STWU8: {
+ case PPC::STWU: {
// op: A
op = getMachineOpValue(MI, MI.getOperand(1));
Value |= (op & 31U) << 21;
@@ -1155,8 +1152,7 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::FCFID:
case PPC::FCTIDZ:
case PPC::FCTIWZ:
- case PPC::FMRD:
- case PPC::FMRS:
+ case PPC::FMR:
case PPC::FMRSD:
case PPC::FNABSD:
case PPC::FNABSS:
diff --git a/libclamav/c++/PPCGenDAGISel.inc b/libclamav/c++/PPCGenDAGISel.inc
index 4a898f2..88fcf32 100644
--- a/libclamav/c++/PPCGenDAGISel.inc
+++ b/libclamav/c++/PPCGenDAGISel.inc
@@ -9,462 +9,334 @@
// *** NOTE: This file is #included into the middle of the target
// *** instruction selector class. These functions are really methods.
-// Include standard, target-independent definitions and methods used
-// by the instruction selector.
-#include "llvm/CodeGen/DAGISelHeader.h"
-
-
-// Node transformations.
-inline SDValue Transform_HA16(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // Transformation function: shift the immediate value down into the low bits.
- signed int Val = N->getZExtValue();
- return getI32Imm((Val - (signed short)Val) >> 16);
-
-}
-inline SDValue Transform_HI16(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // Transformation function: shift the immediate value down into the low bits.
- return getI32Imm((unsigned)N->getZExtValue() >> 16);
-
-}
-inline SDValue Transform_HI32_48(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // Transformation function: shift the immediate value down into the low bits.
- return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
-
-}
-inline SDValue Transform_HI48_64(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // Transformation function: shift the immediate value down into the low bits.
- return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
-
-}
-inline SDValue Transform_LO16(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // Transformation function: get the low 16 bits.
- return getI32Imm((unsigned short)N->getZExtValue());
-
-}
-inline SDValue Transform_MB(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // Transformation function: get the start bit of a mask
- unsigned mb = 0, me;
- (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
- return getI32Imm(mb);
-
-}
-inline SDValue Transform_ME(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // Transformation function: get the end bit of a mask
- unsigned mb, me = 0;
- (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
- return getI32Imm(me);
-
-}
-inline SDValue Transform_SHL32(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // Transformation function: 31 - imm
- return getI32Imm(31 - N->getZExtValue());
-
-}
-inline SDValue Transform_SHL64(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // Transformation function: 63 - imm
- return getI32Imm(63 - N->getZExtValue());
-
-}
-inline SDValue Transform_SRL32(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // Transformation function: 32 - imm
- return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
-
-}
-inline SDValue Transform_SRL64(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // Transformation function: 64 - imm
- return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
-
-}
-inline SDValue Transform_VSLDOI_get_imm(SDNode *N) {
-
- return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
-
-}
-inline SDValue Transform_VSLDOI_unary_get_imm(SDNode *N) {
-
- return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
-
-}
-inline SDValue Transform_VSPLTB_get_imm(SDNode *N) {
-
- return getI32Imm(PPC::getVSPLTImmediate(N, 1));
-
-}
-inline SDValue Transform_VSPLTH_get_imm(SDNode *N) {
-
- return getI32Imm(PPC::getVSPLTImmediate(N, 2));
-
-}
-inline SDValue Transform_VSPLTISB_get_imm(SDNode *N) {
-
- return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
-
-}
-inline SDValue Transform_VSPLTISH_get_imm(SDNode *N) {
-
- return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
-
-}
-inline SDValue Transform_VSPLTISW_get_imm(SDNode *N) {
-
- return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
-
-}
-inline SDValue Transform_VSPLTW_get_imm(SDNode *N) {
-
- return getI32Imm(PPC::getVSPLTImmediate(N, 4));
-
-}
// Predicate functions.
-inline bool Predicate_V_immneg0(SDNode *N) {
+inline bool Predicate_V_immneg0(SDNode *N) const {
return PPC::isAllNegativeZeroVector(N);
}
-inline bool Predicate_atomic_cmp_swap_16(SDNode *N) {
+inline bool Predicate_atomic_cmp_swap_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_cmp_swap_32(SDNode *N) {
+inline bool Predicate_atomic_cmp_swap_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_cmp_swap_64(SDNode *N) {
+inline bool Predicate_atomic_cmp_swap_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_cmp_swap_8(SDNode *N) {
+inline bool Predicate_atomic_cmp_swap_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_add_16(SDNode *N) {
+inline bool Predicate_atomic_load_add_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_add_32(SDNode *N) {
+inline bool Predicate_atomic_load_add_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_add_64(SDNode *N) {
+inline bool Predicate_atomic_load_add_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_add_8(SDNode *N) {
+inline bool Predicate_atomic_load_add_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_and_16(SDNode *N) {
+inline bool Predicate_atomic_load_and_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_and_32(SDNode *N) {
+inline bool Predicate_atomic_load_and_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_and_64(SDNode *N) {
+inline bool Predicate_atomic_load_and_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_and_8(SDNode *N) {
+inline bool Predicate_atomic_load_and_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_max_16(SDNode *N) {
+inline bool Predicate_atomic_load_max_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_max_32(SDNode *N) {
+inline bool Predicate_atomic_load_max_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_max_64(SDNode *N) {
+inline bool Predicate_atomic_load_max_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_max_8(SDNode *N) {
+inline bool Predicate_atomic_load_max_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_min_16(SDNode *N) {
+inline bool Predicate_atomic_load_min_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_min_32(SDNode *N) {
+inline bool Predicate_atomic_load_min_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_min_64(SDNode *N) {
+inline bool Predicate_atomic_load_min_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_min_8(SDNode *N) {
+inline bool Predicate_atomic_load_min_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_nand_16(SDNode *N) {
+inline bool Predicate_atomic_load_nand_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_nand_32(SDNode *N) {
+inline bool Predicate_atomic_load_nand_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_nand_64(SDNode *N) {
+inline bool Predicate_atomic_load_nand_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_nand_8(SDNode *N) {
+inline bool Predicate_atomic_load_nand_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_or_16(SDNode *N) {
+inline bool Predicate_atomic_load_or_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_or_32(SDNode *N) {
+inline bool Predicate_atomic_load_or_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_or_64(SDNode *N) {
+inline bool Predicate_atomic_load_or_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_or_8(SDNode *N) {
+inline bool Predicate_atomic_load_or_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_sub_16(SDNode *N) {
+inline bool Predicate_atomic_load_sub_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_sub_32(SDNode *N) {
+inline bool Predicate_atomic_load_sub_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_sub_64(SDNode *N) {
+inline bool Predicate_atomic_load_sub_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_sub_8(SDNode *N) {
+inline bool Predicate_atomic_load_sub_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_umax_16(SDNode *N) {
+inline bool Predicate_atomic_load_umax_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_umax_32(SDNode *N) {
+inline bool Predicate_atomic_load_umax_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_umax_64(SDNode *N) {
+inline bool Predicate_atomic_load_umax_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_umax_8(SDNode *N) {
+inline bool Predicate_atomic_load_umax_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_umin_16(SDNode *N) {
+inline bool Predicate_atomic_load_umin_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_umin_32(SDNode *N) {
+inline bool Predicate_atomic_load_umin_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_umin_64(SDNode *N) {
+inline bool Predicate_atomic_load_umin_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_umin_8(SDNode *N) {
+inline bool Predicate_atomic_load_umin_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_xor_16(SDNode *N) {
+inline bool Predicate_atomic_load_xor_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_xor_32(SDNode *N) {
+inline bool Predicate_atomic_load_xor_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_xor_64(SDNode *N) {
+inline bool Predicate_atomic_load_xor_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_xor_8(SDNode *N) {
+inline bool Predicate_atomic_load_xor_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_swap_16(SDNode *N) {
+inline bool Predicate_atomic_swap_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_swap_32(SDNode *N) {
+inline bool Predicate_atomic_swap_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_swap_64(SDNode *N) {
+inline bool Predicate_atomic_swap_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_swap_8(SDNode *N) {
+inline bool Predicate_atomic_swap_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_cvtff(SDNode *N) {
+inline bool Predicate_cvtff(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
}
-inline bool Predicate_cvtfs(SDNode *N) {
+inline bool Predicate_cvtfs(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
}
-inline bool Predicate_cvtfu(SDNode *N) {
+inline bool Predicate_cvtfu(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
}
-inline bool Predicate_cvtsf(SDNode *N) {
+inline bool Predicate_cvtsf(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
}
-inline bool Predicate_cvtss(SDNode *N) {
+inline bool Predicate_cvtss(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
}
-inline bool Predicate_cvtsu(SDNode *N) {
+inline bool Predicate_cvtsu(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
}
-inline bool Predicate_cvtuf(SDNode *N) {
+inline bool Predicate_cvtuf(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
}
-inline bool Predicate_cvtus(SDNode *N) {
+inline bool Predicate_cvtus(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
}
-inline bool Predicate_cvtuu(SDNode *N) {
+inline bool Predicate_cvtuu(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
}
-inline bool Predicate_extload(SDNode *N) {
+inline bool Predicate_extload(SDNode *N) const {
return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
}
-inline bool Predicate_extloadf32(SDNode *N) {
+inline bool Predicate_extloadf32(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
}
-inline bool Predicate_extloadf64(SDNode *N) {
+inline bool Predicate_extloadf64(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
}
-inline bool Predicate_extloadi1(SDNode *N) {
+inline bool Predicate_extloadi1(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_extloadi16(SDNode *N) {
+inline bool Predicate_extloadi16(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_extloadi32(SDNode *N) {
+inline bool Predicate_extloadi32(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_extloadi8(SDNode *N) {
+inline bool Predicate_extloadi8(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_imm16ShiftedSExt(SDNode *inN) {
+inline bool Predicate_imm16ShiftedSExt(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
// imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
@@ -477,7 +349,7 @@ inline bool Predicate_imm16ShiftedSExt(SDNode *inN) {
return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
}
-inline bool Predicate_imm16ShiftedZExt(SDNode *inN) {
+inline bool Predicate_imm16ShiftedZExt(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
// imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
@@ -485,31 +357,27 @@ inline bool Predicate_imm16ShiftedZExt(SDNode *inN) {
return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
}
-inline bool Predicate_immAllOnes(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
- return N->isAllOnesValue();
-}
-inline bool Predicate_immAllOnesV(SDNode *N) {
+inline bool Predicate_immAllOnesV(SDNode *N) const {
return ISD::isBuildVectorAllOnes(N);
}
-inline bool Predicate_immAllOnesV_bc(SDNode *N) {
+inline bool Predicate_immAllOnesV_bc(SDNode *N) const {
return ISD::isBuildVectorAllOnes(N);
}
-inline bool Predicate_immAllZerosV(SDNode *N) {
+inline bool Predicate_immAllZerosV(SDNode *N) const {
return ISD::isBuildVectorAllZeros(N);
}
-inline bool Predicate_immAllZerosV_bc(SDNode *N) {
+inline bool Predicate_immAllZerosV_bc(SDNode *N) const {
return ISD::isBuildVectorAllZeros(N);
}
-inline bool Predicate_immSExt16(SDNode *inN) {
+inline bool Predicate_immSExt16(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
@@ -520,7 +388,7 @@ inline bool Predicate_immSExt16(SDNode *inN) {
return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
}
-inline bool Predicate_immZExt16(SDNode *inN) {
+inline bool Predicate_immZExt16(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
// immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
@@ -528,22 +396,22 @@ inline bool Predicate_immZExt16(SDNode *inN) {
return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
}
-inline bool Predicate_istore(SDNode *N) {
+inline bool Predicate_istore(SDNode *N) const {
return !cast<StoreSDNode>(N)->isTruncatingStore();
}
-inline bool Predicate_itruncstore(SDNode *N) {
+inline bool Predicate_itruncstore(SDNode *N) const {
return cast<StoreSDNode>(N)->isTruncatingStore();
}
-inline bool Predicate_load(SDNode *N) {
+inline bool Predicate_load(SDNode *N) const {
return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
}
-inline bool Predicate_maskimm32(SDNode *inN) {
+inline bool Predicate_maskimm32(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
// maskImm predicate - True if immediate is a run of ones.
@@ -554,9092 +422,5860 @@ inline bool Predicate_maskimm32(SDNode *inN) {
return false;
}
-inline bool Predicate_post_store(SDNode *N) {
+inline bool Predicate_post_store(SDNode *N) const {
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::POST_INC || AM == ISD::POST_DEC;
}
-inline bool Predicate_post_truncst(SDNode *N) {
+inline bool Predicate_post_truncst(SDNode *N) const {
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::POST_INC || AM == ISD::POST_DEC;
}
-inline bool Predicate_post_truncstf32(SDNode *N) {
+inline bool Predicate_post_truncstf32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}
-inline bool Predicate_post_truncsti1(SDNode *N) {
+inline bool Predicate_post_truncsti1(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_post_truncsti16(SDNode *N) {
+inline bool Predicate_post_truncsti16(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_post_truncsti32(SDNode *N) {
+inline bool Predicate_post_truncsti32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_post_truncsti8(SDNode *N) {
+inline bool Predicate_post_truncsti8(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_pre_store(SDNode *N) {
+inline bool Predicate_pre_store(SDNode *N) const {
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
}
-inline bool Predicate_pre_truncst(SDNode *N) {
+inline bool Predicate_pre_truncst(SDNode *N) const {
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
}
-inline bool Predicate_pre_truncstf32(SDNode *N) {
+inline bool Predicate_pre_truncstf32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}
-inline bool Predicate_pre_truncsti1(SDNode *N) {
+inline bool Predicate_pre_truncsti1(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_pre_truncsti16(SDNode *N) {
+inline bool Predicate_pre_truncsti16(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_pre_truncsti32(SDNode *N) {
+inline bool Predicate_pre_truncsti32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_pre_truncsti8(SDNode *N) {
+inline bool Predicate_pre_truncsti8(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_sextload(SDNode *N) {
+inline bool Predicate_sextload(SDNode *N) const {
return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
}
-inline bool Predicate_sextloadi1(SDNode *N) {
+inline bool Predicate_sextloadi1(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_sextloadi16(SDNode *N) {
+inline bool Predicate_sextloadi16(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_sextloadi32(SDNode *N) {
+inline bool Predicate_sextloadi32(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_sextloadi8(SDNode *N) {
+inline bool Predicate_sextloadi8(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_store(SDNode *N) {
+inline bool Predicate_store(SDNode *N) const {
return !cast<StoreSDNode>(N)->isTruncatingStore();
}
-inline bool Predicate_truncstore(SDNode *N) {
+inline bool Predicate_truncstore(SDNode *N) const {
return cast<StoreSDNode>(N)->isTruncatingStore();
}
-inline bool Predicate_truncstoref32(SDNode *N) {
+inline bool Predicate_truncstoref32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}
-inline bool Predicate_truncstoref64(SDNode *N) {
+inline bool Predicate_truncstoref64(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
}
-inline bool Predicate_truncstorei16(SDNode *N) {
+inline bool Predicate_truncstorei16(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_truncstorei32(SDNode *N) {
+inline bool Predicate_truncstorei32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_truncstorei8(SDNode *N) {
+inline bool Predicate_truncstorei8(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_unindexedload(SDNode *N) {
+inline bool Predicate_unindexedload(SDNode *N) const {
return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}
-inline bool Predicate_unindexedstore(SDNode *N) {
+inline bool Predicate_unindexedstore(SDNode *N) const {
return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}
-inline bool Predicate_vecspltisb(SDNode *N) {
+inline bool Predicate_vecspltisb(SDNode *N) const {
return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
}
-inline bool Predicate_vecspltish(SDNode *N) {
+inline bool Predicate_vecspltish(SDNode *N) const {
return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
}
-inline bool Predicate_vecspltisw(SDNode *N) {
+inline bool Predicate_vecspltisw(SDNode *N) const {
return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
}
-inline bool Predicate_vmrghb_shuffle(SDNode *N) {
+inline bool Predicate_vmrghb_shuffle(SDNode *N) const {
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
}
-inline bool Predicate_vmrghb_unary_shuffle(SDNode *N) {
+inline bool Predicate_vmrghb_unary_shuffle(SDNode *N) const {
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
}
-inline bool Predicate_vmrghh_shuffle(SDNode *N) {
+inline bool Predicate_vmrghh_shuffle(SDNode *N) const {
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
}
-inline bool Predicate_vmrghh_unary_shuffle(SDNode *N) {
+inline bool Predicate_vmrghh_unary_shuffle(SDNode *N) const {
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
}
-inline bool Predicate_vmrghw_shuffle(SDNode *N) {
+inline bool Predicate_vmrghw_shuffle(SDNode *N) const {
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
}
-inline bool Predicate_vmrghw_unary_shuffle(SDNode *N) {
+inline bool Predicate_vmrghw_unary_shuffle(SDNode *N) const {
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
}
-inline bool Predicate_vmrglb_shuffle(SDNode *N) {
+inline bool Predicate_vmrglb_shuffle(SDNode *N) const {
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
}
-inline bool Predicate_vmrglb_unary_shuffle(SDNode *N) {
+inline bool Predicate_vmrglb_unary_shuffle(SDNode *N) const {
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
}
-inline bool Predicate_vmrglh_shuffle(SDNode *N) {
+inline bool Predicate_vmrglh_shuffle(SDNode *N) const {
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
}
-inline bool Predicate_vmrglh_unary_shuffle(SDNode *N) {
+inline bool Predicate_vmrglh_unary_shuffle(SDNode *N) const {
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
}
-inline bool Predicate_vmrglw_shuffle(SDNode *N) {
+inline bool Predicate_vmrglw_shuffle(SDNode *N) const {
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
}
-inline bool Predicate_vmrglw_unary_shuffle(SDNode *N) {
+inline bool Predicate_vmrglw_unary_shuffle(SDNode *N) const {
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
}
-inline bool Predicate_vpkuhum_shuffle(SDNode *N) {
+inline bool Predicate_vpkuhum_shuffle(SDNode *N) const {
return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
}
-inline bool Predicate_vpkuhum_unary_shuffle(SDNode *N) {
+inline bool Predicate_vpkuhum_unary_shuffle(SDNode *N) const {
return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
}
-inline bool Predicate_vpkuwum_shuffle(SDNode *N) {
+inline bool Predicate_vpkuwum_shuffle(SDNode *N) const {
return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
}
-inline bool Predicate_vpkuwum_unary_shuffle(SDNode *N) {
+inline bool Predicate_vpkuwum_unary_shuffle(SDNode *N) const {
return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
}
-inline bool Predicate_vsldoi_shuffle(SDNode *N) {
+inline bool Predicate_vsldoi_shuffle(SDNode *N) const {
return PPC::isVSLDOIShuffleMask(N, false) != -1;
}
-inline bool Predicate_vsldoi_unary_shuffle(SDNode *N) {
+inline bool Predicate_vsldoi_unary_shuffle(SDNode *N) const {
return PPC::isVSLDOIShuffleMask(N, true) != -1;
}
-inline bool Predicate_vspltb_shuffle(SDNode *N) {
+inline bool Predicate_vspltb_shuffle(SDNode *N) const {
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
}
-inline bool Predicate_vsplth_shuffle(SDNode *N) {
+inline bool Predicate_vsplth_shuffle(SDNode *N) const {
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
}
-inline bool Predicate_vspltw_shuffle(SDNode *N) {
+inline bool Predicate_vspltw_shuffle(SDNode *N) const {
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
}
-inline bool Predicate_vtFP(SDNode *inN) {
+inline bool Predicate_vtFP(SDNode *inN) const {
VTSDNode *N = cast<VTSDNode>(inN);
return N->getVT().isFloatingPoint();
}
-inline bool Predicate_vtInt(SDNode *inN) {
+inline bool Predicate_vtInt(SDNode *inN) const {
VTSDNode *N = cast<VTSDNode>(inN);
return N->getVT().isInteger();
}
-inline bool Predicate_zextload(SDNode *N) {
+inline bool Predicate_zextload(SDNode *N) const {
return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
}
-inline bool Predicate_zextloadi1(SDNode *N) {
+inline bool Predicate_zextloadi1(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_zextloadi16(SDNode *N) {
+inline bool Predicate_zextloadi16(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_zextloadi32(SDNode *N) {
+inline bool Predicate_zextloadi32(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_zextloadi8(SDNode *N) {
+inline bool Predicate_zextloadi8(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}
-DISABLE_INLINE SDNode *Emit_0(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_1(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_HI16(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_2(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N10);
-}
-DISABLE_INLINE SDNode *Emit_3(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1);
-}
-DISABLE_INLINE SDNode *Emit_4(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_LO16(Tmp1.getNode());
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
- SDValue Tmp4 = Transform_HA16(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp3, Tmp4);
-}
-DISABLE_INLINE SDNode *Emit_5(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N00);
-}
-SDNode *Select_ISD_ADD_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:i32 GPRC:i32:$rA, (PPClo:i32 (tglobaladdr:i32):$sym, 0:i32))
- // Emits: (LA:i32 GPRC:i32:$rA, (tglobaladdr:i32):$sym)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == PPCISD::Lo) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_2(N, PPC::LA, MVT::i32);
- return Result;
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == PPCISD::Hi) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (add:i32 GPRC:i32:$in, (PPChi:i32 (tglobaladdr:i32):$g, 0:i32))
- // Emits: (ADDIS:i32 GPRC:i32:$in, (tglobaladdr:i32):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_2(N, PPC::ADDIS, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i32 GPRC:i32:$in, (PPChi:i32 (tconstpool:i32):$g, 0:i32))
- // Emits: (ADDIS:i32 GPRC:i32:$in, (tconstpool:i32):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_2(N, PPC::ADDIS, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i32 GPRC:i32:$in, (PPChi:i32 (tjumptable:i32):$g, 0:i32))
- // Emits: (ADDIS:i32 GPRC:i32:$in, (tjumptable:i32):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_2(N, PPC::ADDIS, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i32 GPRC:i32:$in, (PPChi:i32 (tblockaddress:i32):$g, 0:i32))
- // Emits: (ADDIS:i32 GPRC:i32:$in, (tblockaddress:i32):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_2(N, PPC::ADDIS, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:i32 (PPClo:i32 (tglobaladdr:i32):$sym, 0:i32), GPRC:i32:$rA)
- // Emits: (LA:i32 GPRC:i32:$rA, (tglobaladdr:i32):$sym)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == PPCISD::Lo) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_5(N, PPC::LA, MVT::i32);
- return Result;
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == PPCISD::Hi) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (PPChi:i32 (tglobaladdr:i32):$g, 0:i32), GPRC:i32:$in)
- // Emits: (ADDIS:i32 GPRC:i32:$in, (tglobaladdr:i32):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_5(N, PPC::ADDIS, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i32 (PPChi:i32 (tconstpool:i32):$g, 0:i32), GPRC:i32:$in)
- // Emits: (ADDIS:i32 GPRC:i32:$in, (tconstpool:i32):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_5(N, PPC::ADDIS, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i32 (PPChi:i32 (tjumptable:i32):$g, 0:i32), GPRC:i32:$in)
- // Emits: (ADDIS:i32 GPRC:i32:$in, (tjumptable:i32):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_5(N, PPC::ADDIS, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i32 (PPChi:i32 (tblockaddress:i32):$g, 0:i32), GPRC:i32:$in)
- // Emits: (ADDIS:i32 GPRC:i32:$in, (tblockaddress:i32):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_5(N, PPC::ADDIS, MVT::i32);
- return Result;
- }
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (add:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_immSExt16>>:$imm)
- // Emits: (ADDI:i32 GPRC:i32:$rA, (imm:i32):$imm)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_immSExt16(N1.getNode())) {
- SDNode *Result = Emit_0(N, PPC::ADDI, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_imm16ShiftedSExt>><<X:HI16>>:$imm)
- // Emits: (ADDIS:i32 GPRC:i32:$rA, (HI16:i32 (imm:i32):$imm))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm16ShiftedSExt(N1.getNode())) {
- SDNode *Result = Emit_1(N, PPC::ADDIS, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GPRC:i32:$in, (imm:i32):$imm)
- // Emits: (ADDIS:i32 (ADDI:i32 GPRC:i32:$in, (LO16:i32 (imm:i32):$imm)), (HA16:i32 (imm:i32):$imm))
- // Pattern complexity = 6 cost = 2 size = 0
- SDNode *Result = Emit_4(N, PPC::ADDI, PPC::ADDIS, MVT::i32, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (add:i32 GPRC:i32:$rA, GPRC:i32:$rB)
- // Emits: (ADD4:i32 GPRC:i32:$rA, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::ADD4, MVT::i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_6(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_7(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- SDValue Tmp2 = Transform_HI16(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
-}
-SDNode *Select_ISD_ADD_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == PPCISD::Hi) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (add:i64 G8RC:i64:$in, (PPChi:i64 (tglobaladdr:i64):$g, 0:i64))
- // Emits: (ADDIS8:i64 G8RC:i64:$in, (tglobaladdr:i64):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_2(N, PPC::ADDIS8, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i64 G8RC:i64:$in, (PPChi:i64 (tconstpool:i64):$g, 0:i64))
- // Emits: (ADDIS8:i64 G8RC:i64:$in, (tconstpool:i64):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_2(N, PPC::ADDIS8, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i64 G8RC:i64:$in, (PPChi:i64 (tjumptable:i64):$g, 0:i64))
- // Emits: (ADDIS8:i64 G8RC:i64:$in, (tjumptable:i64):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_2(N, PPC::ADDIS8, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i64 G8RC:i64:$in, (PPChi:i64 (tblockaddress:i64):$g, 0:i64))
- // Emits: (ADDIS8:i64 G8RC:i64:$in, (tblockaddress:i64):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_2(N, PPC::ADDIS8, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == PPCISD::Hi) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:i64 (PPChi:i64 (tglobaladdr:i64):$g, 0:i64), G8RC:i64:$in)
- // Emits: (ADDIS8:i64 G8RC:i64:$in, (tglobaladdr:i64):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_5(N, PPC::ADDIS8, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i64 (PPChi:i64 (tconstpool:i64):$g, 0:i64), G8RC:i64:$in)
- // Emits: (ADDIS8:i64 G8RC:i64:$in, (tconstpool:i64):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_5(N, PPC::ADDIS8, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i64 (PPChi:i64 (tjumptable:i64):$g, 0:i64), G8RC:i64:$in)
- // Emits: (ADDIS8:i64 G8RC:i64:$in, (tjumptable:i64):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_5(N, PPC::ADDIS8, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i64 (PPChi:i64 (tblockaddress:i64):$g, 0:i64), G8RC:i64:$in)
- // Emits: (ADDIS8:i64 G8RC:i64:$in, (tblockaddress:i64):$g)
- // Pattern complexity = 14 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_5(N, PPC::ADDIS8, MVT::i64);
- return Result;
- }
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (add:i64 G8RC:i64:$rA, (imm:i64)<<P:Predicate_immSExt16>>:$imm)
- // Emits: (ADDI8:i64 G8RC:i64:$rA, (imm:i64):$imm)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_immSExt16(N1.getNode())) {
- SDNode *Result = Emit_6(N, PPC::ADDI8, MVT::i64);
- return Result;
- }
-
- // Pattern: (add:i64 G8RC:i64:$rA, (imm:i64)<<P:Predicate_imm16ShiftedSExt>><<X:HI16>>:$imm)
- // Emits: (ADDIS8:i64 G8RC:i64:$rA, (HI16:i64 (imm:i64):$imm))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm16ShiftedSExt(N1.getNode())) {
- SDNode *Result = Emit_7(N, PPC::ADDIS8, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i64 G8RC:i64:$rA, G8RC:i64:$rB)
- // Emits: (ADD8:i64 G8RC:i64:$rA, G8RC:i64:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::ADD8, MVT::i64);
- return Result;
-}
-
-SDNode *Select_ISD_ADD_v16i8(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::VADDUBM, MVT::v16i8);
- return Result;
-}
-
-SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::VADDUHM, MVT::v8i16);
- return Result;
-}
-
-SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::VADDUWM, MVT::v4i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_8(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_9(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, N1);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_ADDC_i32(SDNode *N) {
-
- // Pattern: (addc:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_immSExt16>>:$imm)
- // Emits: (ADDIC:i32 GPRC:i32:$rA, (imm:i32):$imm)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immSExt16(N1.getNode())) {
- SDNode *Result = Emit_8(N, PPC::ADDIC, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (addc:i32 GPRC:i32:$rA, GPRC:i32:$rB)
- // Emits: (ADDC:i32 GPRC:i32:$rA, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_9(N, PPC::ADDC, MVT::i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_10(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_ADDC_i64(SDNode *N) {
-
- // Pattern: (addc:i64 G8RC:i64:$rA, (imm:i64)<<P:Predicate_immSExt16>>:$imm)
- // Emits: (ADDIC8:i64 G8RC:i64:$rA, (imm:i64):$imm)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immSExt16(N1.getNode())) {
- SDNode *Result = Emit_10(N, PPC::ADDIC8, MVT::i64);
- return Result;
- }
- }
-
- // Pattern: (addc:i64 G8RC:i64:$rA, G8RC:i64:$rB)
- // Emits: (ADDC8:i64 G8RC:i64:$rA, G8RC:i64:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_9(N, PPC::ADDC8, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_11(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, N1, InFlag);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_12(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, InFlag);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_ADDE_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (adde:i32 GPRC:i32:$rA, 0:i32)
- // Emits: (ADDZE:i32 GPRC:i32:$rA)
- // Pattern complexity = 8 cost = 1 size = 0
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_12(N, PPC::ADDZE, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (adde:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_immAllOnes>>)
- // Emits: (ADDME:i32 GPRC:i32:$rA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_12(N, PPC::ADDME, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 GPRC:i32:$rA, GPRC:i32:$rB)
- // Emits: (ADDE:i32 GPRC:i32:$rA, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_11(N, PPC::ADDE, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_ADDE_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (adde:i64 G8RC:i64:$rA, 0:i64)
- // Emits: (ADDZE8:i64 G8RC:i64:$rA)
- // Pattern complexity = 8 cost = 1 size = 0
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_12(N, PPC::ADDZE8, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (adde:i64 G8RC:i64:$rA, (imm:i64)<<P:Predicate_immAllOnes>>)
- // Emits: (ADDME8:i64 G8RC:i64:$rA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_12(N, PPC::ADDME8, MVT::i64);
- return Result;
- }
- }
-
- // Pattern: (adde:i64 G8RC:i64:$rA, G8RC:i64:$rB)
- // Emits: (ADDE8:i64 G8RC:i64:$rA, G8RC:i64:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_11(N, PPC::ADDE8, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_13(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_LO16(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_14(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp3 = Transform_MB(Tmp2.getNode());
- SDValue Tmp4 = Transform_ME(Tmp2.getNode());
- SDValue Ops0[] = { N00, N01, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ISD_AND_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:i32 GPRC:i32:$rS, (xor:i32 GPRC:i32:$rB, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (ANDC:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_2(N, PPC::ANDC, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i32 (rotl:i32 GPRC:i32:$in, GPRC:i32:$sh), (imm:i32)<<P:Predicate_maskimm32>>:$imm)
- // Emits: (RLWNM:i32 GPRC:i32:$in, GPRC:i32:$sh, (MB:i32 (imm:i32)<<P:Predicate_maskimm32>>:$imm), (ME:i32 (imm:i32)<<P:Predicate_maskimm32>>:$imm))
- // Pattern complexity = 10 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::ROTL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_maskimm32(N1.getNode()) &&
- N01.getValueType() == MVT::i32) {
- SDNode *Result = Emit_14(N, PPC::RLWNM, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (and:i32 (xor:i32 GPRC:i32:$rB, (imm:i32)<<P:Predicate_immAllOnes>>), GPRC:i32:$rS)
- // Emits: (ANDC:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_5(N, PPC::ANDC, MVT::i32);
- return Result;
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (and:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
- // Emits: (ANDIo:i32 GPRC:i32:$src1, (LO16:i32 (imm:i32):$src2))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_immZExt16(N1.getNode())) {
- SDNode *Result = Emit_13(N, PPC::ANDIo, MVT::i32);
- return Result;
- }
-
- // Pattern: (and:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_imm16ShiftedZExt>><<X:HI16>>:$src2)
- // Emits: (ANDISo:i32 GPRC:i32:$src1, (HI16:i32 (imm:i32):$src2))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm16ShiftedZExt(N1.getNode())) {
- SDNode *Result = Emit_1(N, PPC::ANDISo, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Emits: (AND:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::AND, MVT::i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_15(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- SDValue Tmp2 = Transform_LO16(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
-}
-SDNode *Select_ISD_AND_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:i64 G8RC:i64:$rS, (xor:i64 G8RC:i64:$rB, (imm:i64)<<P:Predicate_immAllOnes>>))
- // Emits: (ANDC8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_2(N, PPC::ANDC8, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i64 (xor:i64 G8RC:i64:$rB, (imm:i64)<<P:Predicate_immAllOnes>>), G8RC:i64:$rS)
- // Emits: (ANDC8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_5(N, PPC::ANDC8, MVT::i64);
- return Result;
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (and:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
- // Emits: (ANDIo8:i64 G8RC:i64:$src1, (LO16:i32 (imm:i64):$src2))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_immZExt16(N1.getNode())) {
- SDNode *Result = Emit_15(N, PPC::ANDIo8, MVT::i64);
- return Result;
- }
-
- // Pattern: (and:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_imm16ShiftedZExt>><<X:HI16>>:$src2)
- // Emits: (ANDISo8:i64 G8RC:i64:$src1, (HI16:i32 (imm:i64):$src2))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm16ShiftedZExt(N1.getNode())) {
- SDNode *Result = Emit_7(N, PPC::ANDISo8, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Emits: (AND8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::AND8, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_16(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N11);
-}
-DISABLE_INLINE SDNode *Emit_17(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N01);
-}
-SDNode *Select_ISD_AND_v4i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- {
- SDValue N11 = N1.getNode()->getOperand(1);
-
- // Pattern: (and:v4i32 VRRC:v4i32:$vA, (xor:v4i32 VRRC:v4i32:$vB, (build_vector:v4i32)<<P:Predicate_immAllOnesV>>))
- // Emits: (VANDC:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N11.getNode())) {
- SDNode *Result = Emit_2(N, PPC::VANDC, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (and:v4i32 VRRC:v4i32:$A, (xor:v4i32 VRRC:v4i32:$B, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>))
- // Emits: (VANDC:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N11.getNode())) {
- SDNode *Result = Emit_2(N, PPC::VANDC, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (and:v4i32 VRRC:v4i32:$vA, (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, VRRC:v4i32:$vB))
- // Emits: (VANDC:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N10.getNode())) {
- SDNode *Result = Emit_16(N, PPC::VANDC, MVT::v4i32);
- return Result;
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (and:v4i32 (xor:v4i32 VRRC:v4i32:$vB, (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VRRC:v4i32:$vA)
- // Emits: (VANDC:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N01.getNode())) {
- SDNode *Result = Emit_5(N, PPC::VANDC, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (and:v4i32 (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, VRRC:v4i32:$vB), VRRC:v4i32:$vA)
- // Emits: (VANDC:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N00.getNode())) {
- SDNode *Result = Emit_17(N, PPC::VANDC, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (and:v4i32 VRRC:v4i32:$A, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, VRRC:v4i32:$B))
- // Emits: (VANDC:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N10.getNode())) {
- SDNode *Result = Emit_16(N, PPC::VANDC, MVT::v4i32);
- return Result;
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (and:v4i32 (xor:v4i32 VRRC:v4i32:$B, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), VRRC:v4i32:$A)
- // Emits: (VANDC:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N01.getNode())) {
- SDNode *Result = Emit_5(N, PPC::VANDC, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, VRRC:v4i32:$B), VRRC:v4i32:$A)
- // Emits: (VANDC:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N00.getNode())) {
- SDNode *Result = Emit_17(N, PPC::VANDC, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VAND:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::VAND, MVT::v4i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_18(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N0);
-}
-SDNode *Select_ISD_ANY_EXTEND_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_18(N, PPC::OR4To8, MVT::i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_19(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, N2, N3, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 5);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_cmp_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)<<P:Predicate_atomic_cmp_swap_8>>
- // Emits: (ATOMIC_CMP_SWAP_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_cmp_swap_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_19(N, PPC::ATOMIC_CMP_SWAP_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_cmp_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)<<P:Predicate_atomic_cmp_swap_16>>
- // Emits: (ATOMIC_CMP_SWAP_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_cmp_swap_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_19(N, PPC::ATOMIC_CMP_SWAP_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_cmp_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)<<P:Predicate_atomic_cmp_swap_32>>
- // Emits: (ATOMIC_CMP_SWAP_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_cmp_swap_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_19(N, PPC::ATOMIC_CMP_SWAP_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_CMP_SWAP_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_cmp_swap_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_19(N, PPC::ATOMIC_CMP_SWAP_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_20(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, N2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 4);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_load_add:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_add_8>>
- // Emits: (ATOMIC_LOAD_ADD_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_add_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_ADD_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_add:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_add_16>>
- // Emits: (ATOMIC_LOAD_ADD_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_add_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_ADD_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_add:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_add_32>>
- // Emits: (ATOMIC_LOAD_ADD_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_add_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_ADD_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_add_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_ADD_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_load_and:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_and_8>>
- // Emits: (ATOMIC_LOAD_AND_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_and_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_AND_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_and:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_and_16>>
- // Emits: (ATOMIC_LOAD_AND_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_and_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_AND_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_and:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_and_32>>
- // Emits: (ATOMIC_LOAD_AND_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_and_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_AND_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_and_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_AND_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_load_nand:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_nand_8>>
- // Emits: (ATOMIC_LOAD_NAND_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_nand_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_NAND_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_nand:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_nand_16>>
- // Emits: (ATOMIC_LOAD_NAND_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_nand_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_NAND_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_nand:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_nand_32>>
- // Emits: (ATOMIC_LOAD_NAND_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_nand_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_NAND_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_nand_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_NAND_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_load_or:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_or_8>>
- // Emits: (ATOMIC_LOAD_OR_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_or_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_OR_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_or:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_or_16>>
- // Emits: (ATOMIC_LOAD_OR_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_or_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_OR_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_or:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_or_32>>
- // Emits: (ATOMIC_LOAD_OR_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_or_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_OR_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_or_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_OR_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_load_sub:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_sub_8>>
- // Emits: (ATOMIC_LOAD_SUB_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_sub_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_SUB_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_sub:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_sub_16>>
- // Emits: (ATOMIC_LOAD_SUB_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_sub_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_SUB_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_sub:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_sub_32>>
- // Emits: (ATOMIC_LOAD_SUB_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_sub_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_SUB_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_SUB_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_sub_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_SUB_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_load_xor:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_xor_8>>
- // Emits: (ATOMIC_LOAD_XOR_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_xor_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_XOR_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_xor:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_xor_16>>
- // Emits: (ATOMIC_LOAD_XOR_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_xor_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_XOR_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_load_xor:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_xor_32>>
- // Emits: (ATOMIC_LOAD_XOR_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_xor_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_XOR_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_xor_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_LOAD_XOR_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_SWAP_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
-
- // Pattern: (atomic_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)<<P:Predicate_atomic_swap_8>>
- // Emits: (ATOMIC_SWAP_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_swap_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_SWAP_I8, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)<<P:Predicate_atomic_swap_16>>
- // Emits: (ATOMIC_SWAP_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_swap_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_SWAP_I16, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (atomic_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)<<P:Predicate_atomic_swap_32>>
- // Emits: (ATOMIC_SWAP_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)
- // Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_swap_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_SWAP_I32, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_SWAP_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_swap_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_20(N, PPC::ATOMIC_SWAP_I64, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_21(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- ReplaceUses(SDValue(N, 0), N0);
- return NULL;
-}
-SDNode *Select_ISD_BIT_CONVERT_v16i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v16i8 VRRC:v8i16:$src)
- // Emits: VRRC:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_21(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v16i8 VRRC:v4i32:$src)
- // Emits: VRRC:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_21(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v16i8 VRRC:v4f32:$src)
- // Emits: VRRC:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_21(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v8i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v8i16 VRRC:v16i8:$src)
- // Emits: VRRC:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_21(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i16 VRRC:v4i32:$src)
- // Emits: VRRC:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_21(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i16 VRRC:v4f32:$src)
- // Emits: VRRC:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_21(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v4i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v4i32 VRRC:v16i8:$src)
- // Emits: VRRC:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_21(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i32 VRRC:v8i16:$src)
- // Emits: VRRC:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_21(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i32 VRRC:v4f32:$src)
- // Emits: VRRC:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_21(N);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v4f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v4f32 VRRC:v16i8:$src)
- // Emits: VRRC:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_21(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4f32 VRRC:v8i16:$src)
- // Emits: VRRC:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_21(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4f32 VRRC:v4i32:$src)
- // Emits: VRRC:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_21(N);
- return Result;
- }
+// The main instruction selector code.
+SDNode *SelectCode(SDNode *N) {
+ // Opcodes are emitted as 2 bytes, TARGET_OPCODE handles this.
+ #define TARGET_OPCODE(X) X & 255, unsigned(X) >> 8
+ static const unsigned char MatcherTable[] = {
+ OPC_SwitchOpcode , 37, ISD::MEMBARRIER,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveChild, 4,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SYNC), 0|OPFL_Chain,
+ 0, 0,
+ 114|128,4, ISD::INTRINSIC_VOID,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_Scope, 19,
+ OPC_CheckInteger, 80|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DCBA), 0|OPFL_Chain,
+ 0, 2, 2, 3,
+ 19,
+ OPC_CheckInteger, 81|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DCBF), 0|OPFL_Chain,
+ 0, 2, 2, 3,
+ 19,
+ OPC_CheckInteger, 82|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DCBI), 0|OPFL_Chain,
+ 0, 2, 2, 3,
+ 19,
+ OPC_CheckInteger, 83|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DCBST), 0|OPFL_Chain,
+ 0, 2, 2, 3,
+ 19,
+ OPC_CheckInteger, 84|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DCBT), 0|OPFL_Chain,
+ 0, 2, 2, 3,
+ 19,
+ OPC_CheckInteger, 85|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DCBTST), 0|OPFL_Chain,
+ 0, 2, 2, 3,
+ 19,
+ OPC_CheckInteger, 86|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DCBZ), 0|OPFL_Chain,
+ 0, 2, 2, 3,
+ 19,
+ OPC_CheckInteger, 87|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DCBZL), 0|OPFL_Chain,
+ 0, 2, 2, 3,
+ 21,
+ OPC_CheckInteger, 76|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STVEBX), 0|OPFL_Chain,
+ 0, 3, 1, 3, 4,
+ 21,
+ OPC_CheckInteger, 77|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STVEHX), 0|OPFL_Chain,
+ 0, 3, 1, 3, 4,
+ 21,
+ OPC_CheckInteger, 78|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STVEWX), 0|OPFL_Chain,
+ 0, 3, 1, 3, 4,
+ 21,
+ OPC_CheckInteger, 79|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STVX), 0|OPFL_Chain,
+ 0, 3, 1, 3, 4,
+ 21,
+ OPC_CheckInteger, 80|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STVXL), 0|OPFL_Chain,
+ 0, 3, 1, 3, 4,
+ 34,
+ OPC_CheckInteger, 61|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DSS), 0|OPFL_Chain,
+ 0, 4, 2, 3, 4, 5,
+ 63,
+ OPC_CheckInteger, 63|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_Scope, 27,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_MoveChild, 4,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DST), 0|OPFL_Chain,
+ 0, 4, 4, 5, 1, 2,
+ 27,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_MoveChild, 4,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DST64), 0|OPFL_Chain,
+ 0, 4, 4, 5, 1, 2,
+ 0,
+ 63,
+ OPC_CheckInteger, 66|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_Scope, 27,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_MoveChild, 4,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DSTT), 0|OPFL_Chain,
+ 0, 4, 4, 5, 1, 2,
+ 27,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_MoveChild, 4,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DSTT64), 0|OPFL_Chain,
+ 0, 4, 4, 5, 1, 2,
+ 0,
+ 63,
+ OPC_CheckInteger, 64|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_Scope, 27,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_MoveChild, 4,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DSTST), 0|OPFL_Chain,
+ 0, 4, 4, 5, 1, 2,
+ 27,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_MoveChild, 4,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DSTST64), 0|OPFL_Chain,
+ 0, 4, 4, 5, 1, 2,
+ 0,
+ 63,
+ OPC_CheckInteger, 65|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_Scope, 27,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_MoveChild, 4,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DSTSTT), 0|OPFL_Chain,
+ 0, 4, 4, 5, 1, 2,
+ 27,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_MoveChild, 4,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DSTSTT64), 0|OPFL_Chain,
+ 0, 4, 4, 5, 1, 2,
+ 0,
+ 13,
+ OPC_CheckInteger, 88|128,2,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SYNC), 0|OPFL_Chain,
+ 0, 0,
+ 15,
+ OPC_CheckInteger, 75|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MTVSCR), 0|OPFL_Chain,
+ 0, 1, 1,
+ 29,
+ OPC_CheckInteger, 62|128,1,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DSSALL), 0|OPFL_Chain,
+ 0, 4, 1, 2, 3, 4,
+ 0,
+ 125, ISD::INTRINSIC_W_CHAIN,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_Scope, 20,
+ OPC_CheckInteger, 67|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LVEBX), 0|OPFL_Chain,
+ 1, MVT::v16i8, 2, 2, 3,
+ 20,
+ OPC_CheckInteger, 68|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LVEHX), 0|OPFL_Chain,
+ 1, MVT::v8i16, 2, 2, 3,
+ 20,
+ OPC_CheckInteger, 69|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LVEWX), 0|OPFL_Chain,
+ 1, MVT::v4i32, 2, 2, 3,
+ 20,
+ OPC_CheckInteger, 72|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LVX), 0|OPFL_Chain,
+ 1, MVT::v4i32, 2, 2, 3,
+ 20,
+ OPC_CheckInteger, 73|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LVXL), 0|OPFL_Chain,
+ 1, MVT::v4i32, 2, 2, 3,
+ 14,
+ OPC_CheckInteger, 74|128,1,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MFVSCR), 0|OPFL_Chain,
+ 1, MVT::v8i16, 0,
+ 0,
+ 18|128,13, ISD::INTRINSIC_WO_CHAIN,
+ OPC_MoveChild, 0,
+ OPC_Scope, 17,
+ OPC_CheckInteger, 70|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LVSL), 0,
+ 1, MVT::v16i8, 2, 1, 2,
+ 17,
+ OPC_CheckInteger, 71|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LVSR), 0,
+ 1, MVT::v16i8, 2, 1, 2,
+ 22,
+ OPC_CheckInteger, 94|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCFSX), 0,
+ 1, MVT::v4f32, 2, 2, 0,
+ 22,
+ OPC_CheckInteger, 95|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCFUX), 0,
+ 1, MVT::v4f32, 2, 2, 0,
+ 22,
+ OPC_CheckInteger, 122|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCTSXS), 0,
+ 1, MVT::v4i32, 2, 2, 0,
+ 22,
+ OPC_CheckInteger, 123|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCTUXS), 0,
+ 1, MVT::v4i32, 2, 2, 0,
+ 17,
+ OPC_CheckInteger, 6|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMHADDSHS), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 17,
+ OPC_CheckInteger, 7|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMHRADDSHS), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 17,
+ OPC_CheckInteger, 15|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMLADDUHM), 0,
+ 1, MVT::v8i16, 3, 0, 1, 2,
+ 17,
+ OPC_CheckInteger, 31|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPERM), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 17,
+ OPC_CheckInteger, 48|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSEL), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 15,
+ OPC_CheckInteger, 81|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VADDCUW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 82|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VADDSBS), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 83|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VADDSHS), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 84|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VADDSWS), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 85|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VADDUBS), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 86|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VADDUHS), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 87|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VADDUWS), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 13,
+ OPC_CheckInteger, 124|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VEXPTEFP), 0,
+ 1, MVT::v4f32, 1, 0,
+ 13,
+ OPC_CheckInteger, 125|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VLOGEFP), 0,
+ 1, MVT::v4f32, 1, 0,
+ 15,
+ OPC_CheckInteger, 88|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VAVGSB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 89|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VAVGSH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 90|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VAVGSW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 91|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VAVGUB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 92|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VAVGUH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 93|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VAVGUW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 127|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMAXFP), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 0|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMAXSB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 1|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMAXSH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 2|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMAXSW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 3|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMAXUB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 4|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMAXUH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 5|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMAXUW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 8|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMINFP), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 9|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMINSB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 10|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMINSH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 11|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMINSW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 12|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMINUB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 13|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMINUH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 14|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMINUW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 17,
+ OPC_CheckInteger, 16|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMSUMMBM), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 17,
+ OPC_CheckInteger, 17|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMSUMSHM), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 17,
+ OPC_CheckInteger, 18|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMSUMSHS), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 17,
+ OPC_CheckInteger, 19|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMSUMUBM), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 17,
+ OPC_CheckInteger, 20|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMSUMUHM), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 17,
+ OPC_CheckInteger, 21|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMSUMUHS), 0,
+ 1, MVT::v4i32, 3, 0, 1, 2,
+ 15,
+ OPC_CheckInteger, 22|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMULESB), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 23|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMULESH), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 24|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMULEUB), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 25|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMULEUH), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 26|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMULOSB), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 27|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMULOSH), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 28|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMULOUB), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 29|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMULOUH), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 13,
+ OPC_CheckInteger, 39|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VREFP), 0,
+ 1, MVT::v4f32, 1, 0,
+ 13,
+ OPC_CheckInteger, 40|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VRFIM), 0,
+ 1, MVT::v4f32, 1, 0,
+ 13,
+ OPC_CheckInteger, 41|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VRFIN), 0,
+ 1, MVT::v4f32, 1, 0,
+ 13,
+ OPC_CheckInteger, 42|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VRFIP), 0,
+ 1, MVT::v4f32, 1, 0,
+ 13,
+ OPC_CheckInteger, 43|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VRFIZ), 0,
+ 1, MVT::v4f32, 1, 0,
+ 13,
+ OPC_CheckInteger, 47|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VRSQRTEFP), 0,
+ 1, MVT::v4f32, 1, 0,
+ 15,
+ OPC_CheckInteger, 62|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUBCUW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 63|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUBSBS), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 64|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUBSHS), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 65|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUBSWS), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 66|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUBUBS), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 67|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUBUHS), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 68|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUBUWS), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 73|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUMSWS), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 69|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUM2SWS), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 70|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUM4SBS), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 71|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUM4SHS), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 72|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUM4UBS), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 44|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VRLB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 45|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VRLH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 46|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VRLW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 49|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSL), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 52|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSLO), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 50|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSLB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 51|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSLH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 53|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSLW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 54|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSR), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 60|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRO), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 55|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRAB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 56|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRAH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 57|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRAW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 58|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 59|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 61|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 32|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKPX), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 33|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKSHSS), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 34|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKSHUS), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 35|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKSWSS), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 36|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKSWUS), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 37|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUHUS), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 38|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUWUS), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 13,
+ OPC_CheckInteger, 74|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VUPKHPX), 0,
+ 1, MVT::v4i32, 1, 0,
+ 13,
+ OPC_CheckInteger, 75|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VUPKHSB), 0,
+ 1, MVT::v8i16, 1, 0,
+ 13,
+ OPC_CheckInteger, 76|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VUPKHSH), 0,
+ 1, MVT::v4i32, 1, 0,
+ 13,
+ OPC_CheckInteger, 77|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VUPKLPX), 0,
+ 1, MVT::v4i32, 1, 0,
+ 13,
+ OPC_CheckInteger, 78|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VUPKLSB), 0,
+ 1, MVT::v8i16, 1, 0,
+ 13,
+ OPC_CheckInteger, 79|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VUPKLSH), 0,
+ 1, MVT::v4i32, 1, 0,
+ 17,
+ OPC_CheckInteger, 126|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMADDFP), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 17,
+ OPC_CheckInteger, 30|128,2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VNMSUBFP), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 0,
+ 17|128,4, ISD::ADD,
+ OPC_Scope, 42|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 23, PPCISD::Lo,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LA), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9|128,1, PPCISD::Hi,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 31, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 31, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 31, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 31, ISD::TargetBlockAddress,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 0,
+ 46|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 24, PPCISD::Lo,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LA), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 13|128,1, PPCISD::Hi,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 32, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS8), 0,
+ 1, MVT::i64, 2, 1, 0,
+ 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 0,
+ 32, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS8), 0,
+ 1, MVT::i64, 2, 1, 0,
+ 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 0,
+ 32, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS8), 0,
+ 1, MVT::i64, 2, 1, 0,
+ 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 0,
+ 32, ISD::TargetBlockAddress,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS8), 0,
+ 1, MVT::i64, 2, 1, 0,
+ 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 0,
+ 0,
+ 0,
+ 49|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 112,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 16,
+ OPC_CheckPredicate, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDI), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 19,
+ OPC_CheckPredicate, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS), 0,
+ 1, MVT::i32, 2, 0, 3,
+ 16,
+ OPC_CheckPredicate, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDI8), 0,
+ 1, MVT::i64, 2, 0, 2,
+ 19,
+ OPC_CheckPredicate, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS8), 0,
+ 1, MVT::i64, 2, 0, 3,
+ 31,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_EmitNode, TARGET_OPCODE(PPC::ADDI), 0,
+ 1, MVT::i32, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 2, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIS), 0,
+ 1, MVT::i32, 2, 4, 6,
+ 0,
+ 11,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADD4), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VADDUBM), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VADDUHM), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VADDUWM), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADD8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 12|128,8, ISD::LOAD,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 3,
+ OPC_CheckPredicate, 4,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 24,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHA), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 24,
+ OPC_CheckPredicate, 3,
+ OPC_CheckPredicate, 7,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZ), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 58,
+ OPC_CheckPredicate, 8,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 15, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWZ), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 15, MVT::f32,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LFS), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 2, 2, 3,
+ 15, MVT::f64,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LFD), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 2, 2, 3,
+ 0,
+ 24,
+ OPC_CheckPredicate, 3,
+ OPC_CheckPredicate, 4,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 24,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHAX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 24,
+ OPC_CheckPredicate, 3,
+ OPC_CheckPredicate, 7,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 58,
+ OPC_CheckPredicate, 8,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 15, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWZX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 15, MVT::f32,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LFSX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 2, 2, 3,
+ 15, MVT::f64,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LFDX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 2, 2, 3,
+ 0,
+ 43,
+ OPC_CheckPredicate, 3,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 0,
+ 2|128,1,
+ OPC_CheckPredicate, 10,
+ OPC_Scope, 41,
+ OPC_CheckPredicate, 11,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 0,
+ 41,
+ OPC_CheckPredicate, 12,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 0,
+ 41,
+ OPC_CheckPredicate, 13,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZ), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 2, 2, 3,
+ 0,
+ 0,
+ 22,
+ OPC_CheckPredicate, 8,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LVX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 2, 2, 3,
+ 96,
+ OPC_CheckPredicate, 5,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHA8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 22,
+ OPC_CheckPredicate, 14,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWA), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 22,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHAX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 22,
+ OPC_CheckPredicate, 14,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWAX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 14|128,1,
+ OPC_CheckPredicate, 3,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 4,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 22,
+ OPC_CheckPredicate, 7,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZ8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 22,
+ OPC_CheckPredicate, 15,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWZ8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 22,
+ OPC_CheckPredicate, 4,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 22,
+ OPC_CheckPredicate, 7,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 22,
+ OPC_CheckPredicate, 15,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWZX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 41,
+ OPC_CheckPredicate, 8,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LDX), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 43,
+ OPC_CheckPredicate, 3,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 108|128,1,
+ OPC_CheckPredicate, 10,
+ OPC_Scope, 41,
+ OPC_CheckPredicate, 11,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 41,
+ OPC_CheckPredicate, 12,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 41,
+ OPC_CheckPredicate, 13,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZ8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 41,
+ OPC_CheckPredicate, 16,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWZ8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWZX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 63,
+ OPC_CheckPredicate, 17,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_Scope, 26,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitNode, TARGET_OPCODE(PPC::LFS), 0|OPFL_Chain,
+ 1, MVT::f32, 2, 2, 3,
+ OPC_EmitNode, TARGET_OPCODE(PPC::FMRSD), 0|OPFL_MemRefs,
+ 1, MVT::f64, 1, 4,
+ OPC_CompleteMatch, 1, 5,
+
+ 26,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitNode, TARGET_OPCODE(PPC::LFSX), 0|OPFL_Chain,
+ 1, MVT::f32, 2, 2, 3,
+ OPC_EmitNode, TARGET_OPCODE(PPC::FMRSD), 0|OPFL_MemRefs,
+ 1, MVT::f64, 1, 4,
+ OPC_CompleteMatch, 1, 5,
+
+ 0,
+ 0,
+ 0,
+ 35|128,5, ISD::STORE,
+ OPC_Scope, 68|128,3,
+ OPC_CheckPredicate, 18,
+ OPC_Scope, 52,
+ OPC_CheckPredicate, 19,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 20,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STB), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 23,
+ OPC_CheckPredicate, 21,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STH), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 0,
+ 64,
+ OPC_CheckPredicate, 22,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 18,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STW), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 18,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFS), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 18,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFD), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 0,
+ 52,
+ OPC_CheckPredicate, 19,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 20,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STBX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 23,
+ OPC_CheckPredicate, 21,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 0,
+ 83,
+ OPC_CheckPredicate, 22,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 18,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STWX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 18,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFSX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 18,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFDX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 18,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STVX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 0,
+ 20|128,1,
+ OPC_CheckPredicate, 19,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 20,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STB8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 23,
+ OPC_CheckPredicate, 21,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STH8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 23,
+ OPC_CheckPredicate, 23,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STW8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 23,
+ OPC_CheckPredicate, 20,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STBX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 23,
+ OPC_CheckPredicate, 21,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 23,
+ OPC_CheckPredicate, 23,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STWX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 0,
+ 42,
+ OPC_CheckPredicate, 22,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STD), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STDX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 0,
+ 0,
+ 58,
+ OPC_CheckPredicate, 24,
+ OPC_CheckPredicate, 25,
+ OPC_Scope, 25,
+ OPC_CheckPredicate, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STBU), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 25,
+ OPC_CheckPredicate, 27,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHU), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 0,
+ 72,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPredicate, 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 20,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STWU), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 20,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFSU), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 20,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFDU), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 0,
+ 58,
+ OPC_CheckPredicate, 24,
+ OPC_CheckPredicate, 25,
+ OPC_Scope, 25,
+ OPC_CheckPredicate, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STBU8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 25,
+ OPC_CheckPredicate, 27,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHU8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 0,
+ 27,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPredicate, 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STDU), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 0,
+ 26|128,1, ISD::FSUB,
+ OPC_Scope, 72,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 30, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 30,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::FSUB,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VNMSUBFP), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 34, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 12, MVT::f64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FMSUB), 0,
+ 1, MVT::f64, 3, 0, 1, 2,
+ 12, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FMSUBS), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 0,
+ 0,
+ 78,
+ OPC_RecordChild0,
+ OPC_Scope, 37,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::f64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FNMSUB), 0,
+ 1, MVT::f64, 3, 1, 2, 0,
+ 12, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FNMSUBS), 0,
+ 1, MVT::f32, 3, 1, 2, 0,
+ 0,
+ 36,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FSUB), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 9, MVT::f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FSUBS), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 9, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUBFP), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 0,
+ 0,
+ 102, ISD::ATOMIC_LOAD_ADD,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_ADD_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_ADD_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 33,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_ADD_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 34,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_ADD_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 3, 3, 4, 2,
+ 0,
+ 102, ISD::ATOMIC_LOAD_SUB,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 35,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_SUB_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 36,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_SUB_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 37,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_SUB_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 38,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_SUB_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 3, 3, 4, 2,
+ 0,
+ 102, ISD::ATOMIC_LOAD_AND,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 39,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_AND_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 40,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_AND_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 41,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_AND_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 42,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_AND_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 3, 3, 4, 2,
+ 0,
+ 102, ISD::ATOMIC_LOAD_OR,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 43,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_OR_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 44,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_OR_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 45,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_OR_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 46,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_OR_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 3, 3, 4, 2,
+ 0,
+ 102, ISD::ATOMIC_LOAD_XOR,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 47,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_XOR_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 48,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_XOR_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_XOR_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 50,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_XOR_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 3, 3, 4, 2,
+ 0,
+ 102, ISD::ATOMIC_LOAD_NAND,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 51,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_NAND_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 52,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_NAND_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 53,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_NAND_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 54,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_NAND_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 3, 3, 4, 2,
+ 0,
+ 110, ISD::ATOMIC_CMP_SWAP,
+ OPC_Scope, 26,
+ OPC_CheckPredicate, 55,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_CMP_SWAP_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 4, 5, 2, 3,
+ 26,
+ OPC_CheckPredicate, 56,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_CMP_SWAP_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 4, 5, 2, 3,
+ 26,
+ OPC_CheckPredicate, 57,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_CMP_SWAP_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 4, 5, 2, 3,
+ 26,
+ OPC_CheckPredicate, 58,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_CMP_SWAP_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 4, 4, 5, 2, 3,
+ 0,
+ 102, ISD::ATOMIC_SWAP,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 59,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_SWAP_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 60,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_SWAP_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 61,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_SWAP_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 24,
+ OPC_CheckPredicate, 62,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_SWAP_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 3, 3, 4, 2,
+ 0,
+ 52, PPCISD::DYNALLOC,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 23,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::iPTR,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DYNALLOC), 0|OPFL_Chain,
+ 1, MVT::i32, 3, 1, 3, 4,
+ 23,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::iPTR,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DYNALLOC8), 0|OPFL_Chain,
+ 1, MVT::i64, 3, 1, 3, 4,
+ 0,
+ 38, PPCISD::LARX,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 15, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWARX), 0|OPFL_Chain,
+ 1, MVT::i32, 2, 2, 3,
+ 15, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LDARX), 0|OPFL_Chain,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 42, PPCISD::STCX,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 18,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STWCX), 0|OPFL_Chain,
+ 0, 3, 1, 3, 4,
+ 18,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STDCX), 0|OPFL_Chain,
+ 0, 3, 1, 3, 4,
+ 0,
+ 44, PPCISD::LBRX,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_Scope, 18,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHBRX), 0|OPFL_Chain,
+ 1, MVT::i32, 2, 2, 3,
+ 18,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWBRX), 0|OPFL_Chain,
+ 1, MVT::i32, 2, 2, 3,
+ 0,
+ 45, PPCISD::STBRX,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 3,
+ OPC_Scope, 18,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHBRX), 0|OPFL_Chain,
+ 0, 3, 1, 3, 4,
+ 18,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STWBRX), 0|OPFL_Chain,
+ 0, 3, 1, 3, 4,
+ 0,
+ 18, PPCISD::STFIWX,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFIWX), 0|OPFL_Chain,
+ 0, 3, 1, 3, 4,
+ 41, PPCISD::LOAD,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::iPTR,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LD), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LDX), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 39, PPCISD::STD_32,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STD_32), 0|OPFL_Chain,
+ 0, 3, 1, 3, 4,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STDX_32), 0|OPFL_Chain,
+ 0, 3, 1, 3, 4,
+ 0,
+ 127|128,4, ISD::XOR,
+ OPC_Scope, 36|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 41, ISD::AND,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::NAND), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::NAND8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 41, ISD::OR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::NOR), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::NOR8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 72, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_Scope, 40,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EQV), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EQV8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 27,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EQV), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 32,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EQV), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 32,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EQV8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 32,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EQV8), 0,
+ 1, MVT::i64, 2, 1, 0,
+ 91,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 39, ISD::OR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 14, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 63,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VNOR), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 14, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VNOR), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 21, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 63,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VNOR), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 21, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::OR,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VNOR), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 34|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 25,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::NOR), 0,
+ 1, MVT::i32, 2, 0, 0,
+ 47,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 19,
+ OPC_CheckPredicate, 65,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::XORI), 0,
+ 1, MVT::i32, 2, 0, 3,
+ 19,
+ OPC_CheckPredicate, 66,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::XORIS), 0,
+ 1, MVT::i32, 2, 0, 3,
+ 0,
+ 36,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 14, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 63,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VNOR), 0,
+ 1, MVT::v4i32, 2, 0, 0,
+ 14, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VNOR), 0,
+ 1, MVT::v4i32, 2, 0, 0,
+ 0,
+ 47,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 19,
+ OPC_CheckPredicate, 65,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::XORI8), 0,
+ 1, MVT::i64, 2, 0, 3,
+ 19,
+ OPC_CheckPredicate, 66,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::XORIS8), 0,
+ 1, MVT::i64, 2, 0, 3,
+ 0,
+ 0,
+ 38,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 15, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 63,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VNOR), 0,
+ 1, MVT::v4i32, 2, 0, 0,
+ 15, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VNOR), 0,
+ 1, MVT::v4i32, 2, 0, 0,
+ 0,
+ 76,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_EmitNode, TARGET_OPCODE(PPC::XORI), 0,
+ 1, MVT::i32, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::XORIS), 0,
+ 1, MVT::i32, 2, 4, 6,
+ 11,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::XOR), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VXOR), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::XOR8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 75|128,3, ISD::AND,
+ OPC_Scope, 45,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ANDC), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ANDC8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 85,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 41, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ANDC), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ANDC8), 0,
+ 1, MVT::i64, 2, 1, 0,
+ 0,
+ 36, ISD::ROTL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 3, 3,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 4, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::RLWNM), 0,
+ 1, MVT::i32, 4, 0, 1, 4, 6,
+ 0,
+ 68,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 39,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 15, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 63,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VANDC), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VANDC), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 20,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 63,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VANDC), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 50,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 21,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 63,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VANDC), 0,
+ 1, MVT::v4i32, 2, 1, 0,
+ 21,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 63,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VANDC), 0,
+ 1, MVT::v4i32, 2, 1, 0,
+ 0,
+ 25,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VANDC), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 50,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 21,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VANDC), 0,
+ 1, MVT::v4i32, 2, 1, 0,
+ 21,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VANDC), 0,
+ 1, MVT::v4i32, 2, 1, 0,
+ 0,
+ 127,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 86,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 19,
+ OPC_CheckPredicate, 65,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ANDIo), 0,
+ 1, MVT::i32, 2, 0, 3,
+ 19,
+ OPC_CheckPredicate, 66,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ANDISo), 0,
+ 1, MVT::i32, 2, 0, 3,
+ 19,
+ OPC_CheckPredicate, 65,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ANDIo8), 0,
+ 1, MVT::i64, 2, 0, 3,
+ 19,
+ OPC_CheckPredicate, 66,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ANDISo8), 0,
+ 1, MVT::i64, 2, 0, 3,
+ 0,
+ 11,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::AND), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VAND), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::AND8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 127|128,1, ISD::OR,
+ OPC_Scope, 45,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ORC), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ORC8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 45,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ORC), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ORC8), 0,
+ 1, MVT::i64, 2, 1, 0,
+ 0,
+ 31|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 118,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 19,
+ OPC_CheckPredicate, 65,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ORI), 0,
+ 1, MVT::i32, 2, 0, 3,
+ 19,
+ OPC_CheckPredicate, 66,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ORIS), 0,
+ 1, MVT::i32, 2, 0, 3,
+ 19,
+ OPC_CheckPredicate, 65,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ORI8), 0,
+ 1, MVT::i64, 2, 0, 3,
+ 19,
+ OPC_CheckPredicate, 66,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ORIS8), 0,
+ 1, MVT::i64, 2, 0, 3,
+ 31,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 1, 2,
+ OPC_EmitNode, TARGET_OPCODE(PPC::ORI), 0,
+ 1, MVT::i32, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 0, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ORIS), 0,
+ 1, MVT::i32, 2, 4, 6,
+ 0,
+ 11,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::OR), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VOR), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::OR8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 125, PPCISD::Hi,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 28, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 28, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 28, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 28, ISD::TargetBlockAddress,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 125, PPCISD::Lo,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 28, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 28, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 28, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 28, ISD::TargetBlockAddress,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 25, ISD::CALLSEQ_END,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TargetConstant,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::TargetConstant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADJCALLSTACKUP), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 2, 1, 2,
+ 75|128,1, PPCISD::TC_RETURN,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_Scope, 24|128,1,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 50, ISD::Constant,
+ OPC_SwitchType , 22, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::TCRETURNai), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 3, 4,
+ 22, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::TCRETURNai8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 3, 4,
+ 0,
+ 46, ISD::TargetGlobalAddress,
+ OPC_SwitchType , 20, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::TCRETURNdi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 1, 3,
+ 20, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::TCRETURNdi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 1, 3,
+ 0,
+ 46, ISD::TargetExternalSymbol,
+ OPC_SwitchType , 20, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::TCRETURNdi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 1, 3,
+ 20, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::TCRETURNdi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 1, 3,
+ 0,
+ 0,
+ 21,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::TCRETURNri), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 1, 3,
+ 21,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::TCRETURNri8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 1, 3,
+ 0,
+ 55|128,1, ISD::FNEG,
+ OPC_Scope, 27|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 82, ISD::FADD,
+ OPC_Scope, 39,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::f64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FNMADD), 0,
+ 1, MVT::f64, 3, 0, 1, 2,
+ 12, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FNMADDS), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 0,
+ 39,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::f64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FNMADD), 0,
+ 1, MVT::f64, 3, 1, 2, 0,
+ 12, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FNMADDS), 0,
+ 1, MVT::f32, 3, 1, 2, 0,
+ 0,
+ 0,
+ 39, ISD::FSUB,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::f64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FNMSUB), 0,
+ 1, MVT::f64, 3, 0, 1, 2,
+ 12, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FNMSUBS), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 0,
+ 24, ISD::FABS,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FNABSS), 0,
+ 1, MVT::f32, 1, 0,
+ 8, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FNABSD), 0,
+ 1, MVT::f64, 1, 0,
+ 0,
+ 0,
+ 23,
+ OPC_RecordChild0,
+ OPC_SwitchType , 8, MVT::f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FNEGS), 0,
+ 1, MVT::f32, 1, 0,
+ 8, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FNEGD), 0,
+ 1, MVT::f64, 1, 0,
+ 0,
+ 0,
+ 116, ISD::SUB,
+ OPC_Scope, 28,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::NEG), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::NEG8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 84,
+ OPC_RecordChild0,
+ OPC_Scope, 21,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBFIC), 0,
+ 1, MVT::i32, 2, 1, 2,
+ 58,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBF), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 9, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUBUBM), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 9, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUBUHM), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 9, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSUBUWM), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBF8), 0,
+ 1, MVT::i64, 2, 1, 0,
+ 0,
+ 0,
+ 0,
+ 96, ISD::ADDE,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_Scope, 65,
+ OPC_MoveChild, 1,
+ OPC_Scope, 34,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDME), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDME8), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 25,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDZE), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDZE8), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 25,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDE), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDE8), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 98, ISD::SUBE,
+ OPC_CaptureFlagInput,
+ OPC_Scope, 67,
+ OPC_MoveChild, 0,
+ OPC_Scope, 35,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBFME), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBFME8), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 26,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBFZE), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBFZE8), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 26,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBFE), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 1, 0,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBFE8), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 1, 0,
+ 0,
+ 0,
+ 84|128,1, PPCISD::VCMP,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_Scope, 15,
+ OPC_CheckInteger, 70|128,7,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPBFP), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 70|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPEQFP), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 70|128,3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGEFP), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 70|128,5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTFP), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 14,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPEQUB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 6|128,6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTSB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 6|128,4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTUB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 14,
+ OPC_CheckInteger, 70,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPEQUH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 70|128,6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTSH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 70|128,4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTUH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 6|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPEQUW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 6|128,7,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTSW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 6|128,5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTUW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 84|128,1, PPCISD::VCMPo,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_Scope, 15,
+ OPC_CheckInteger, 70|128,7,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPBFPo), 0|OPFL_FlagOutput,
+ 1, MVT::v4f32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 70|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPEQFPo), 0|OPFL_FlagOutput,
+ 1, MVT::v4f32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 70|128,3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGEFPo), 0|OPFL_FlagOutput,
+ 1, MVT::v4f32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 70|128,5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTFPo), 0|OPFL_FlagOutput,
+ 1, MVT::v4f32, 2, 0, 1,
+ 14,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPEQUBo), 0|OPFL_FlagOutput,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 6|128,6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTSBo), 0|OPFL_FlagOutput,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 6|128,4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTUBo), 0|OPFL_FlagOutput,
+ 1, MVT::v16i8, 2, 0, 1,
+ 14,
+ OPC_CheckInteger, 70,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPEQUHo), 0|OPFL_FlagOutput,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 70|128,6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTSHo), 0|OPFL_FlagOutput,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 70|128,4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTUHo), 0|OPFL_FlagOutput,
+ 1, MVT::v8i16, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 6|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPEQUWo), 0|OPFL_FlagOutput,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 6|128,7,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTSWo), 0|OPFL_FlagOutput,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckInteger, 6|128,5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VCMPGTUWo), 0|OPFL_FlagOutput,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 64, ISD::ADDC,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 0,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIC), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDIC8), 0|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 11,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDC), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADDC8), 0|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 49, ISD::MUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 20,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MULLI), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 11,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MULLW), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MULLD), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 66, ISD::SUBC,
+ OPC_RecordChild0,
+ OPC_Scope, 36,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 11, MVT::i32,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBFIC), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 1, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBFIC8), 0|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 1, 2,
+ 0,
+ 25,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBFC), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 1, 0,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SUBFC8), 0|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 1, 0,
+ 0,
+ 0,
+ 24|128,3, ISD::VECTOR_SHUFFLE,
+ OPC_Scope, 96,
+ OPC_RecordNode,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 68,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_EmitNodeXForm, 5, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSPLTB), 0,
+ 1, MVT::v16i8, 2, 2, 1,
+ 22,
+ OPC_CheckPredicate, 69,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_EmitNodeXForm, 6, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSPLTH), 0,
+ 1, MVT::v16i8, 2, 2, 1,
+ 22,
+ OPC_CheckPredicate, 70,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_EmitNodeXForm, 7, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSPLTW), 0,
+ 1, MVT::v16i8, 2, 2, 1,
+ 23,
+ OPC_CheckPredicate, 71,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_EmitNodeXForm, 8, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSLDOI), 0,
+ 1, MVT::v16i8, 3, 1, 1, 2,
+ 0,
+ 19,
+ OPC_CheckPredicate, 72,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUWUM), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 19,
+ OPC_CheckPredicate, 73,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUHUM), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 19,
+ OPC_CheckPredicate, 74,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLB), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 19,
+ OPC_CheckPredicate, 75,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLH), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 19,
+ OPC_CheckPredicate, 76,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLW), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 19,
+ OPC_CheckPredicate, 77,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHB), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 19,
+ OPC_CheckPredicate, 78,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHH), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 19,
+ OPC_CheckPredicate, 79,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHW), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 20,
+ OPC_RecordNode,
+ OPC_CheckPredicate, 80,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_EmitNodeXForm, 9, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSLDOI), 0,
+ 1, MVT::v16i8, 3, 1, 2, 3,
+ 15,
+ OPC_CheckPredicate, 81,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckPredicate, 82,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHH), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckPredicate, 83,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHW), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckPredicate, 84,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckPredicate, 85,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLH), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckPredicate, 86,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLW), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckPredicate, 87,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUHUM), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 15,
+ OPC_CheckPredicate, 88,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUWUM), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 17, ISD::CALLSEQ_START,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TargetConstant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ADJCALLSTACKDOWN), 0|OPFL_Chain|OPFL_FlagOutput,
+ 0, 1, 1,
+ 101, PPCISD::CALL_Darwin,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 32, ISD::Constant,
+ OPC_SwitchType , 13, MVT::i32,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BLA_Darwin), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 2,
+ 13, MVT::i64,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BLA8_Darwin), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 2,
+ 0,
+ 28, ISD::TargetGlobalAddress,
+ OPC_SwitchType , 11, MVT::i32,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BL_Darwin), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 11, MVT::i64,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BL8_Darwin), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 28, ISD::TargetExternalSymbol,
+ OPC_SwitchType , 11, MVT::i32,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BL_Darwin), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 11, MVT::i64,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BL8_Darwin), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 0,
+ 101, PPCISD::CALL_SVR4,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 32, ISD::Constant,
+ OPC_SwitchType , 13, MVT::i32,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BLA_SVR4), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 2,
+ 13, MVT::i64,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BLA8_ELF), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 2,
+ 0,
+ 28, ISD::TargetGlobalAddress,
+ OPC_SwitchType , 11, MVT::i32,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BL_SVR4), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 11, MVT::i64,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BL8_ELF), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 28, ISD::TargetExternalSymbol,
+ OPC_SwitchType , 11, MVT::i32,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BL_SVR4), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 11, MVT::i64,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BL8_ELF), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 0,
+ 109, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SRAWI), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SRADI), 0,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 26,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SRAW), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SRAD), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 13,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRAB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 13,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRAH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 13,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRAW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 18, PPCISD::MTFSB0,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MTFSB0), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 1, 1,
+ 18, PPCISD::MTFSB1,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MTFSB1), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 1, 1,
+ 23, PPCISD::MTFSF,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MTFSF), 0|OPFL_FlagInput,
+ 1, MVT::f64, 3, 3, 1, 2,
+ 20|128,1, ISD::FADD,
+ OPC_Scope, 52,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 12, MVT::f64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FMADD), 0,
+ 1, MVT::f64, 3, 0, 1, 2,
+ 12, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FMADDS), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 12, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMADDFP), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 0,
+ 92,
+ OPC_RecordChild0,
+ OPC_Scope, 51,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::f64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FMADD), 0,
+ 1, MVT::f64, 3, 1, 2, 0,
+ 12, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FMADDS), 0,
+ 1, MVT::f32, 3, 1, 2, 0,
+ 12, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMADDFP), 0,
+ 1, MVT::v4f32, 3, 1, 2, 0,
+ 0,
+ 36,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FADD), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 9, MVT::f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FADDS), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 9, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VADDFP), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 0,
+ 0,
+ 125, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 51,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 10, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::RLWINM), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 5,
+ 17, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 11, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::RLDICR), 0,
+ 1, MVT::i64, 3, 0, 2, 4,
+ 0,
+ 26,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SLW), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SLD), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 13,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSLB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 13,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSLH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 13,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSLW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 125, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 51,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 12, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 31,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::RLWINM), 0,
+ 1, MVT::i32, 4, 0, 3, 4, 5,
+ 17, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 13, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::RLDICL), 0,
+ 1, MVT::i64, 3, 0, 3, 4,
+ 0,
+ 26,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SRW), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SRD), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 13,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 13,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRH), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 13,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSRW), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 91, ISD::ROTL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 47,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_SwitchType , 19, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 31,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::RLWINM), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 15, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::RLDICL), 0,
+ 1, MVT::i64, 3, 0, 2, 3,
+ 0,
+ 38,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_SwitchType , 17, MVT::i32,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 31,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::RLWNM), 0,
+ 1, MVT::i32, 4, 0, 1, 2, 3,
+ 13, MVT::i64,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::RLDCL), 0,
+ 1, MVT::i64, 3, 0, 1, 2,
+ 0,
+ 0,
+ 18, PPCISD::TOC_ENTRY,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LDtoc), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 99, ISD::Constant,
+ OPC_RecordNode,
+ OPC_Scope, 14,
+ OPC_CheckPredicate, 0,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI), 0,
+ 1, MVT::i32, 1, 1,
+ 17,
+ OPC_CheckPredicate, 1,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS), 0,
+ 1, MVT::i32, 1, 2,
+ 14,
+ OPC_CheckPredicate, 0,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI8), 0,
+ 1, MVT::i64, 1, 1,
+ 17,
+ OPC_CheckPredicate, 1,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS8), 0,
+ 1, MVT::i64, 1, 2,
+ 29,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 0, 1,
+ OPC_EmitNode, TARGET_OPCODE(PPC::LIS), 0,
+ 1, MVT::i32, 1, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 1, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ORI), 0,
+ 1, MVT::i32, 2, 3, 5,
+ 0,
+ 66, ISD::BUILD_VECTOR,
+ OPC_Scope, 51,
+ OPC_RecordNode,
+ OPC_Scope, 15,
+ OPC_CheckPredicate, 89,
+ OPC_CheckType, MVT::v16i8,
+ OPC_EmitNodeXForm, 14, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSPLTISB), 0,
+ 1, MVT::v16i8, 1, 1,
+ 15,
+ OPC_CheckPredicate, 90,
+ OPC_CheckType, MVT::v8i16,
+ OPC_EmitNodeXForm, 15, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSPLTISH), 0,
+ 1, MVT::v8i16, 1, 1,
+ 15,
+ OPC_CheckPredicate, 91,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitNodeXForm, 16, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSPLTISW), 0,
+ 1, MVT::v4i32, 1, 1,
+ 0,
+ 11,
+ OPC_CheckPredicate, 92,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::V_SET0), 0,
+ 1, MVT::v4i32, 0,
+ 0,
+ 83, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_Scope, 19,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_SwitchType , 3, MVT::v16i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 19,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_SwitchType , 3, MVT::v16i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v8i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 19,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_SwitchType , 3, MVT::v16i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v8i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 19,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_SwitchType , 3, MVT::v8i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 0,
+ 19, PPCISD::RET_FLAG,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 20,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BLR), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 2, 1, 2,
+ 17, ISD::BR,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BasicBlock,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::B), 0|OPFL_Chain,
+ 0, 1, 1,
+ 28, PPCISD::BCTRL_Darwin,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BCTRL_Darwin), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic0,
+ 0, 0,
+ 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BCTRL8_Darwin), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic0,
+ 0, 0,
+ 0,
+ 28, PPCISD::BCTRL_SVR4,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BCTRL_SVR4), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic0,
+ 0, 0,
+ 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::BCTRL8_ELF), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic0,
+ 0, 0,
+ 0,
+ 10, ISD::TRAP,
+ OPC_RecordNode,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::TRAP), 0|OPFL_Chain,
+ 0, 0,
+ 28, PPCISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SLW), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SLD), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 28, PPCISD::SRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SRW), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SRD), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 28, PPCISD::SRA,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SRAW), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::SRAD), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 23, ISD::CTLZ,
+ OPC_RecordChild0,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::CNTLZW), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::CNTLZD), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 75, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_Scope, 13,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSB), 0,
+ 1, MVT::i32, 1, 0,
+ 13,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSH), 0,
+ 1, MVT::i32, 1, 0,
+ 13,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSB8), 0,
+ 1, MVT::i64, 1, 0,
+ 13,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSH8), 0,
+ 1, MVT::i64, 1, 0,
+ 13,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSW), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 11, PPCISD::FCTIWZ,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FCTIWZ), 0,
+ 1, MVT::f64, 1, 0,
+ 13, ISD::FP_ROUND,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_CheckType, MVT::f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FRSP), 0,
+ 1, MVT::f32, 1, 0,
+ 23, ISD::FSQRT,
+ OPC_RecordChild0,
+ OPC_SwitchType , 8, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FSQRT), 0,
+ 1, MVT::f64, 1, 0,
+ 8, MVT::f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FSQRTS), 0,
+ 1, MVT::f32, 1, 0,
+ 0,
+ 13, ISD::FP_EXTEND,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_CheckType, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FMRSD), 0,
+ 1, MVT::f64, 1, 0,
+ 23, ISD::FABS,
+ OPC_RecordChild0,
+ OPC_SwitchType , 8, MVT::f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FABSS), 0,
+ 1, MVT::f32, 1, 0,
+ 8, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FABSD), 0,
+ 1, MVT::f64, 1, 0,
+ 0,
+ 31, PPCISD::MTCTR,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_Scope, 12,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MTCTR), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 1, 1,
+ 12,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MTCTR8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 1, 1,
+ 0,
+ 7, PPCISD::MFFS,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MFFS), 0|OPFL_FlagOutput,
+ 1, MVT::f64, 0,
+ 14, PPCISD::FADDRTZ,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FADDrtz), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::f64, 2, 0, 1,
+ 26, ISD::SDIV,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DIVW), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DIVD), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 26, ISD::UDIV,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DIVWU), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::DIVDU), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 26, ISD::MULHS,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MULHW), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MULHD), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 26, ISD::MULHU,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MULHWU), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::MULHDU), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 29, PPCISD::FSEL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 10, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FSELD), 0,
+ 1, MVT::f64, 3, 0, 1, 2,
+ 10, MVT::f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FSELS), 0,
+ 1, MVT::f32, 3, 0, 1, 2,
+ 0,
+ 26, ISD::FDIV,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FDIV), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 9, MVT::f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FDIVS), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 0,
+ 45, ISD::FMUL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FMUL), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 9, MVT::f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FMULS), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 17, MVT::v4f32,
+ OPC_EmitNode, TARGET_OPCODE(PPC::V_SET0), 0,
+ 1, MVT::v4i32, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMADDFP), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 0,
+ 15, PPCISD::VMADDFP,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMADDFP), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 15, PPCISD::VNMSUBFP,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VNMSUBFP), 0,
+ 1, MVT::v4f32, 3, 0, 1, 2,
+ 15, PPCISD::VPERM,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPERM), 0,
+ 1, MVT::v16i8, 3, 0, 1, 2,
+ 7, PPCISD::NOP,
+ OPC_CaptureFlagInput,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::NOP), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 0,
+ 11, PPCISD::EXTSW_32,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSW_32), 0,
+ 1, MVT::i32, 1, 0,
+ 13, ISD::SIGN_EXTEND,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSW_32_64), 0,
+ 1, MVT::i64, 1, 0,
+ 15, PPCISD::LOAD_TOC,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LDinto_toc), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 1, 1,
+ 11, PPCISD::TOC_RESTORE,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LDtoc_restore), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 0,
+ 11, PPCISD::FCFID,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FCFID), 0,
+ 1, MVT::f64, 1, 0,
+ 11, PPCISD::FCTIDZ,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::FCTIDZ), 0,
+ 1, MVT::f64, 1, 0,
+ 14, ISD::ANY_EXTEND,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::OR4To8), 0,
+ 1, MVT::i64, 2, 0, 0,
+ 14, ISD::TRUNCATE,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::OR8To4), 0,
+ 1, MVT::i32, 2, 0, 0,
+ 30, ISD::ZERO_EXTEND,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitNode, TARGET_OPCODE(PPC::OR4To8), 0,
+ 1, MVT::i64, 2, 0, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitInteger, MVT::i32, 32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::RLDICL), 0,
+ 1, MVT::i64, 3, 1, 2, 3,
+ 0,
+ 0
+ }; // Total Array size is 11495 bytes
+
+ #undef TARGET_OPCODE
+ return SelectCodeCommon(N, MatcherTable,sizeof(MatcherTable));
+}
+
+bool CheckPatternPredicate(unsigned PredNo) const {
+ switch (PredNo) {
+ default: assert(0 && "Invalid predicate in table?");
+ case 0: return (!NoExcessFPPrecision);
+ case 1: return (!PPCSubTarget.isPPC64());
+ case 2: return (PPCSubTarget.isPPC64());
+ }
+}
+
+bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {
+ switch (PredNo) {
+ default: assert(0 && "Invalid predicate in table?");
+ case 0: { // Predicate_immSExt16
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
+ // field. Used by instructions like 'addi'.
+ if (N->getValueType(0) == MVT::i32)
+ return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
+ else
+ return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
-DISABLE_INLINE SDNode *Emit_22(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, N1, Chain);
-}
-SDNode *Select_ISD_BR(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
- SDNode *Result = Emit_22(N, PPC::B);
- return Result;
}
+ case 1: { // Predicate_imm16ShiftedSExt
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
+ // immediate are set. Used by instructions like 'addis'. Identical to
+ // imm16ShiftedZExt in 32-bit mode.
+ if (N->getZExtValue() & 0xFFFF) return false;
+ if (N->getValueType(0) == MVT::i32)
+ return true;
+ // For 64-bit, make sure it is sext right.
+ return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
-DISABLE_INLINE SDNode *Emit_23(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VSPLTISB_get_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1);
-}
-SDNode *Select_ISD_BUILD_VECTOR_v16i8(SDNode *N) {
- if (Predicate_vecspltisb(N)) {
- SDNode *Result = Emit_23(N, PPC::VSPLTISB, MVT::v16i8);
- return Result;
}
+ case 2: { // Predicate_unindexedload
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
-DISABLE_INLINE SDNode *Emit_24(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VSPLTISH_get_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1);
-}
-SDNode *Select_ISD_BUILD_VECTOR_v8i16(SDNode *N) {
- if (Predicate_vecspltish(N)) {
- SDNode *Result = Emit_24(N, PPC::VSPLTISH, MVT::v8i16);
- return Result;
}
+ case 3: { // Predicate_zextload
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_25(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VSPLTISW_get_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_26(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- return CurDAG->SelectNodeTo(N, Opc0, VT0);
-}
-SDNode *Select_ISD_BUILD_VECTOR_v4i32(SDNode *N) {
-
- // Pattern: (build_vector:v4i32)<<P:Predicate_vecspltisw>><<X:VSPLTISW_get_imm>>:$SIMM
- // Emits: (VSPLTISW:v4i32 (VSPLTISW_get_imm:i32 (build_vector:v4i32):$SIMM))
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vecspltisw(N)) {
- SDNode *Result = Emit_25(N, PPC::VSPLTISW, MVT::v4i32);
- return Result;
- }
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
- // Pattern: (build_vector:v4i32)<<P:Predicate_immAllZerosV>>
- // Emits: (V_SET0:v4i32)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_immAllZerosV(N)) {
- SDNode *Result = Emit_26(N, PPC::V_SET0, MVT::v4i32);
- return Result;
}
+ case 4: { // Predicate_zextloadi8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_27(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- SDValue Ops0[] = { N1, N2, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_ISD_CALLSEQ_END(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_27(N, PPC::ADJCALLSTACKUP);
- return Result;
- }
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_28(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, N1, Chain);
- Chain = SDValue(ResNode, 0);
- SDValue InFlag(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_ISD_CALLSEQ_START(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_28(N, PPC::ADJCALLSTACKDOWN);
- return Result;
}
+ case 5: { // Predicate_sextload
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_29(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0);
-}
-SDNode *Select_ISD_CTLZ_i32(SDNode *N) {
- SDNode *Result = Emit_29(N, PPC::CNTLZW, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_CTLZ_i64(SDNode *N) {
- SDNode *Result = Emit_29(N, PPC::CNTLZD, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_30(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0);
-}
-DISABLE_INLINE SDNode *Emit_31(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- SDValue Tmp1 = Transform_HI16(Tmp0.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_32(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- SDValue Tmp1 = Transform_HI16(Tmp0.getNode());
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Tmp1), 0);
- SDValue Tmp3 = Transform_LO16(Tmp0.getNode());
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, Tmp3);
-}
-SDNode *Select_ISD_Constant_i32(SDNode *N) {
-
- // Pattern: (imm:i32)<<P:Predicate_immSExt16>>:$imm
- // Emits: (LI:i32 (imm:i32):$imm)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_immSExt16(N)) {
- SDNode *Result = Emit_30(N, PPC::LI, MVT::i32);
- return Result;
- }
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
- // Pattern: (imm:i32)<<P:Predicate_imm16ShiftedSExt>><<X:HI16>>:$imm
- // Emits: (LIS:i32 (HI16:i32 (imm:i32):$imm))
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_imm16ShiftedSExt(N)) {
- SDNode *Result = Emit_31(N, PPC::LIS, MVT::i32);
- return Result;
}
+ case 6: { // Predicate_sextloadi16
+ SDNode *N = Node;
- // Pattern: (imm:i32):$imm
- // Emits: (ORI:i32 (LIS:i32 (HI16:i32 (imm:i32):$imm)), (LO16:i32 (imm:i32):$imm))
- // Pattern complexity = 3 cost = 2 size = 0
- SDNode *Result = Emit_32(N, PPC::LIS, PPC::ORI, MVT::i32, MVT::i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_33(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i64);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0);
-}
-DISABLE_INLINE SDNode *Emit_34(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i64);
- SDValue Tmp1 = Transform_HI16(Tmp0.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1);
-}
-SDNode *Select_ISD_Constant_i64(SDNode *N) {
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
- // Pattern: (imm:i64)<<P:Predicate_immSExt16>>:$imm
- // Emits: (LI8:i64 (imm:i64):$imm)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_immSExt16(N)) {
- SDNode *Result = Emit_33(N, PPC::LI8, MVT::i64);
- return Result;
}
+ case 7: { // Predicate_zextloadi16
+ SDNode *N = Node;
- // Pattern: (imm:i64)<<P:Predicate_imm16ShiftedSExt>><<X:HI16>>:$imm
- // Emits: (LIS8:i64 (HI16:i64 (imm:i64):$imm))
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_imm16ShiftedSExt(N)) {
- SDNode *Result = Emit_34(N, PPC::LIS8, MVT::i64);
- return Result;
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FABS_f32(SDNode *N) {
- SDNode *Result = Emit_29(N, PPC::FABSS, MVT::f32);
- return Result;
-}
-
-SDNode *Select_ISD_FABS_f64(SDNode *N) {
- SDNode *Result = Emit_29(N, PPC::FABSD, MVT::f64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_35(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N01, N1);
-}
-DISABLE_INLINE SDNode *Emit_36(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N11, N0);
-}
-SDNode *Select_ISD_FADD_f32(SDNode *N) {
- if ((!NoExcessFPPrecision)) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:f32 (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC), F4RC:f32:$FRB)
- // Emits: (FMADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_35(N, PPC::FMADDS, MVT::f32);
- return Result;
- }
-
- // Pattern: (fadd:f32 F4RC:f32:$FRB, (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC))
- // Emits: (FMADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
- // Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_36(N, PPC::FMADDS, MVT::f32);
- return Result;
- }
}
+ case 8: { // Predicate_load
+ SDNode *N = Node;
- // Pattern: (fadd:f32 F4RC:f32:$FRA, F4RC:f32:$FRB)
- // Emits: (FADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::FADDS, MVT::f32);
- return Result;
-}
-
-SDNode *Select_ISD_FADD_f64(SDNode *N) {
- if ((!NoExcessFPPrecision)) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:f64 (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC), F8RC:f64:$FRB)
- // Emits: (FMADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_35(N, PPC::FMADD, MVT::f64);
- return Result;
- }
-
- // Pattern: (fadd:f64 F8RC:f64:$FRB, (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC))
- // Emits: (FMADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
- // Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_36(N, PPC::FMADD, MVT::f64);
- return Result;
- }
- }
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
- // Pattern: (fadd:f64 F8RC:f64:$FRA, F8RC:f64:$FRB)
- // Emits: (FADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::FADD, MVT::f64);
- return Result;
-}
-
-SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
- if ((!NoExcessFPPrecision)) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:v4f32 (fmul:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC), VRRC:v4f32:$vB)
- // Emits: (VMADDFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC, VRRC:v4f32:$vB)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_35(N, PPC::VMADDFP, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (fadd:v4f32 VRRC:v4f32:$vB, (fmul:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC))
- // Emits: (VMADDFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC, VRRC:v4f32:$vB)
- // Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_36(N, PPC::VMADDFP, MVT::v4f32);
- return Result;
- }
}
+ case 9: { // Predicate_zextloadi1
+ SDNode *N = Node;
- // Pattern: (fadd:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Emits: (VADDFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::VADDFP, MVT::v4f32);
- return Result;
-}
-
-SDNode *Select_ISD_FDIV_f32(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::FDIVS, MVT::f32);
- return Result;
-}
-
-SDNode *Select_ISD_FDIV_f64(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::FDIV, MVT::f64);
- return Result;
-}
-
-SDNode *Select_ISD_FMUL_f32(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::FMULS, MVT::f32);
- return Result;
-}
-
-SDNode *Select_ISD_FMUL_f64(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::FMUL, MVT::f64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_37(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, N0, N1, Tmp2);
-}
-SDNode *Select_ISD_FMUL_v4f32(SDNode *N) {
- SDNode *Result = Emit_37(N, PPC::V_SET0, PPC::VMADDFP, MVT::v4i32, MVT::v4f32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_38(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00);
-}
-DISABLE_INLINE SDNode *Emit_39(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N000, N001, N01);
-}
-DISABLE_INLINE SDNode *Emit_40(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N010, N011, N00);
-}
-SDNode *Select_ISD_FNEG_f32(SDNode *N) {
- if ((!NoExcessFPPrecision)) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fneg:f32 (fadd:f32 (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC), F4RC:f32:$FRB))
- // Emits: (FNMADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FADD) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_39(N, PPC::FNMADDS, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (fneg:f32 (fsub:f32 (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC), F4RC:f32:$FRB))
- // Emits: (FNMSUBS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FSUB) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_39(N, PPC::FNMSUBS, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (fneg:f32 (fadd:f32 F4RC:f32:$FRB, (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC)))
- // Emits: (FNMADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FADD) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_40(N, PPC::FNMADDS, MVT::f32);
- return Result;
- }
- }
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
- // Pattern: (fneg:f32 (fabs:f32 F4RC:f32:$frB))
- // Emits: (FNABSS:f32 F4RC:f32:$frB)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::FABS) {
- SDNode *Result = Emit_38(N, PPC::FNABSS, MVT::f32);
- return Result;
- }
}
+ case 10: { // Predicate_extload
+ SDNode *N = Node;
- // Pattern: (fneg:f32 F4RC:f32:$frB)
- // Emits: (FNEGS:f32 F4RC:f32:$frB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_29(N, PPC::FNEGS, MVT::f32);
- return Result;
-}
-
-SDNode *Select_ISD_FNEG_f64(SDNode *N) {
- if ((!NoExcessFPPrecision)) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fneg:f64 (fadd:f64 (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC), F8RC:f64:$FRB))
- // Emits: (FNMADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FADD) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_39(N, PPC::FNMADD, MVT::f64);
- return Result;
- }
- }
-
- // Pattern: (fneg:f64 (fsub:f64 (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC), F8RC:f64:$FRB))
- // Emits: (FNMSUB:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FSUB) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_39(N, PPC::FNMSUB, MVT::f64);
- return Result;
- }
- }
-
- // Pattern: (fneg:f64 (fadd:f64 F8RC:f64:$FRB, (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC)))
- // Emits: (FNMADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FADD) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_40(N, PPC::FNMADD, MVT::f64);
- return Result;
- }
- }
- }
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
- // Pattern: (fneg:f64 (fabs:f64 F8RC:f64:$frB))
- // Emits: (FNABSD:f64 F8RC:f64:$frB)
- // Pattern complexity = 6 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::FABS) {
- SDNode *Result = Emit_38(N, PPC::FNABSD, MVT::f64);
- return Result;
- }
}
+ case 11: { // Predicate_extloadi1
+ SDNode *N = Node;
- // Pattern: (fneg:f64 F8RC:f64:$frB)
- // Emits: (FNEGD:f64 F8RC:f64:$frB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_29(N, PPC::FNEGD, MVT::f64);
- return Result;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
-SDNode *Select_ISD_FP_EXTEND_f64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_29(N, PPC::FMRSD, MVT::f64);
- return Result;
}
+ case 12: { // Predicate_extloadi8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
-SDNode *Select_ISD_FP_ROUND_f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_29(N, PPC::FRSP, MVT::f32);
- return Result;
}
+ case 13: { // Predicate_extloadi16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSQRT_f32(SDNode *N) {
- SDNode *Result = Emit_29(N, PPC::FSQRTS, MVT::f32);
- return Result;
-}
-
-SDNode *Select_ISD_FSQRT_f64(SDNode *N) {
- SDNode *Result = Emit_29(N, PPC::FSQRT, MVT::f64);
- return Result;
-}
-
-SDNode *Select_ISD_FSUB_f32(SDNode *N) {
- if ((!NoExcessFPPrecision)) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fsub:f32 (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC), F4RC:f32:$FRB)
- // Emits: (FMSUBS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_35(N, PPC::FMSUBS, MVT::f32);
- return Result;
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
- // Pattern: (fsub:f32 F4RC:f32:$B, (fmul:f32 F4RC:f32:$A, F4RC:f32:$C))
- // Emits: (FNMSUBS:f32 F4RC:f32:$A, F4RC:f32:$C, F4RC:f32:$B)
- // Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_36(N, PPC::FNMSUBS, MVT::f32);
- return Result;
- }
}
+ case 14: { // Predicate_sextloadi32
+ SDNode *N = Node;
- // Pattern: (fsub:f32 F4RC:f32:$FRA, F4RC:f32:$FRB)
- // Emits: (FSUBS:f32 F4RC:f32:$FRA, F4RC:f32:$FRB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::FSUBS, MVT::f32);
- return Result;
-}
-
-SDNode *Select_ISD_FSUB_f64(SDNode *N) {
- if ((!NoExcessFPPrecision)) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fsub:f64 (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC), F8RC:f64:$FRB)
- // Emits: (FMSUB:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_35(N, PPC::FMSUB, MVT::f64);
- return Result;
- }
-
- // Pattern: (fsub:f64 F8RC:f64:$B, (fmul:f64 F8RC:f64:$A, F8RC:f64:$C))
- // Emits: (FNMSUB:f64 F8RC:f64:$A, F8RC:f64:$C, F8RC:f64:$B)
- // Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_36(N, PPC::FNMSUB, MVT::f64);
- return Result;
- }
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
- // Pattern: (fsub:f64 F8RC:f64:$FRA, F8RC:f64:$FRB)
- // Emits: (FSUB:f64 F8RC:f64:$FRA, F8RC:f64:$FRB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::FSUB, MVT::f64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_41(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N100, N101, N11);
-}
-SDNode *Select_ISD_FSUB_v4f32(SDNode *N) {
-
- // Pattern: (fsub:v4f32 (build_vector:v4f32)<<P:Predicate_V_immneg0>>, (fsub:v4f32 (fmul:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC), VRRC:v4f32:$vB))
- // Emits: (VNMSUBFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC, VRRC:v4f32:$vB)
- // Pattern complexity = 13 cost = 1 size = 0
- if ((!NoExcessFPPrecision)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_V_immneg0(N0.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::FSUB) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::FMUL) {
- SDNode *Result = Emit_41(N, PPC::VNMSUBFP, MVT::v4f32);
- return Result;
- }
- }
- }
}
+ case 15: { // Predicate_zextloadi32
+ SDNode *N = Node;
- // Pattern: (fsub:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Emits: (VSUBFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::VSUBFP, MVT::v4f32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_42(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, CPTmpN2_0, CPTmpN2_1, Chain);
-}
-DISABLE_INLINE SDNode *Emit_43(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
-}
-DISABLE_INLINE SDNode *Emit_44(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, N2, Chain);
-}
-DISABLE_INLINE SDNode *Emit_45(SDNode *N, unsigned Opc0, SDValue &CPTmpN3_0, SDValue &CPTmpN3_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Ops0[] = { N2, CPTmpN3_0, CPTmpN3_1, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_46(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Ops0[] = { Tmp2, Tmp3, Tmp4, Tmp5, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_47(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Ops0[] = { Tmp2, Tmp3, Tmp4, Tmp5, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_48(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N4)->getZExtValue()), MVT::i32);
- SDValue Ops0[] = { Tmp2, Tmp3, N2, N3, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_49(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N4)->getZExtValue()), MVT::i32);
- SDValue Ops0[] = { Tmp2, Tmp3, N2, N3, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 5);
-}
-SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_void:isVoid 336:iPTR, xoaddr:iPTR:$dst)
- // Emits: (DCBA:isVoid xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(336)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_42(N, PPC::DCBA, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 337:iPTR, xoaddr:iPTR:$dst)
- // Emits: (DCBF:isVoid xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(337)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_42(N, PPC::DCBF, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 338:iPTR, xoaddr:iPTR:$dst)
- // Emits: (DCBI:isVoid xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(338)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_42(N, PPC::DCBI, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 339:iPTR, xoaddr:iPTR:$dst)
- // Emits: (DCBST:isVoid xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(339)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_42(N, PPC::DCBST, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 340:iPTR, xoaddr:iPTR:$dst)
- // Emits: (DCBT:isVoid xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(340)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_42(N, PPC::DCBT, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 341:iPTR, xoaddr:iPTR:$dst)
- // Emits: (DCBTST:isVoid xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(341)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_42(N, PPC::DCBTST, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 342:iPTR, xoaddr:iPTR:$dst)
- // Emits: (DCBZ:isVoid xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(342)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_42(N, PPC::DCBZ, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 343:iPTR, xoaddr:iPTR:$dst)
- // Emits: (DCBZL:isVoid xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(343)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_42(N, PPC::DCBZL, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 204:iPTR, VRRC:v16i8:$rS, xoaddr:iPTR:$dst)
- // Emits: (STVEBX:isVoid VRRC:v16i8:$rS, xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(204)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- SDValue CPTmpN3_1;
- if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
- SDNode *Result = Emit_45(N, PPC::STVEBX, CPTmpN3_0, CPTmpN3_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 205:iPTR, VRRC:v8i16:$rS, xoaddr:iPTR:$dst)
- // Emits: (STVEHX:isVoid VRRC:v8i16:$rS, xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(205)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- SDValue CPTmpN3_1;
- if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
- SDNode *Result = Emit_45(N, PPC::STVEHX, CPTmpN3_0, CPTmpN3_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 206:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
- // Emits: (STVEWX:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(206)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- SDValue CPTmpN3_1;
- if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
- SDNode *Result = Emit_45(N, PPC::STVEWX, CPTmpN3_0, CPTmpN3_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 207:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
- // Emits: (STVX:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(207)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- SDValue CPTmpN3_1;
- if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
- SDNode *Result = Emit_45(N, PPC::STVX, CPTmpN3_0, CPTmpN3_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 208:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
- // Emits: (STVXL:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(208)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- SDValue CPTmpN3_1;
- if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
- SDNode *Result = Emit_45(N, PPC::STVXL, CPTmpN3_0, CPTmpN3_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 189:iPTR, (imm:i32):$STRM)
- // Emits: (DSS:isVoid 0:i32, (imm:i32):$STRM, 0:i32, 0:i32)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(189)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_47(N, PPC::DSS);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 191:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
- // Emits: (DST:isVoid 0:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(191)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- if (N4.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_48(N, PPC::DST);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 194:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
- // Emits: (DSTT:isVoid 1:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(194)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- if (N4.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_49(N, PPC::DSTT);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 192:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
- // Emits: (DSTST:isVoid 0:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(192)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- if (N4.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_48(N, PPC::DSTST);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 193:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
- // Emits: (DSTSTT:isVoid 1:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(193)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- if (N4.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_49(N, PPC::DSTSTT);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 191:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
- // Emits: (DST64:isVoid 0:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(191)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- if (N4.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i64) {
- SDNode *Result = Emit_48(N, PPC::DST64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 194:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
- // Emits: (DSTT64:isVoid 1:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(194)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- if (N4.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i64) {
- SDNode *Result = Emit_49(N, PPC::DSTT64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 192:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
- // Emits: (DSTST64:isVoid 0:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(192)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- if (N4.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i64) {
- SDNode *Result = Emit_48(N, PPC::DSTST64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 193:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
- // Emits: (DSTSTT64:isVoid 1:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(193)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- if (N4.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i64) {
- SDNode *Result = Emit_49(N, PPC::DSTSTT64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 344:iPTR)
- // Emits: (SYNC:isVoid)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(344)) {
- SDNode *Result = Emit_43(N, PPC::SYNC);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 203:iPTR, VRRC:v4i32:$vB)
- // Emits: (MTVSCR:isVoid VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(203)) {
- SDNode *Result = Emit_44(N, PPC::MTVSCR);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 190:iPTR)
- // Emits: (DSSALL:isVoid 1:i32, 0:i32, 0:i32, 0:i32)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(190)) {
- SDNode *Result = Emit_46(N, PPC::DSSALL);
- return Result;
- }
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_50(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, CPTmpN1_0, CPTmpN1_1);
-}
-DISABLE_INLINE SDNode *Emit_51(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2);
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v16i8 198:iPTR, xoaddr:iPTR:$src)
- // Emits: (LVSL:v16i8 xoaddr:iPTR:$src)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(198)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_50(N, PPC::LVSL, MVT::v16i8, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 199:iPTR, xoaddr:iPTR:$src)
- // Emits: (LVSR:v16i8 xoaddr:iPTR:$src)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(199)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_50(N, PPC::LVSR, MVT::v16i8, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 210:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VADDSBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(210)) {
- SDNode *Result = Emit_51(N, PPC::VADDSBS, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 213:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VADDUBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(213)) {
- SDNode *Result = Emit_51(N, PPC::VADDUBS, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 216:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VAVGSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(216)) {
- SDNode *Result = Emit_51(N, PPC::VAVGSB, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 219:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VAVGUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(219)) {
- SDNode *Result = Emit_51(N, PPC::VAVGUB, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 256:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VMAXSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(256)) {
- SDNode *Result = Emit_51(N, PPC::VMAXSB, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 259:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VMAXUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(259)) {
- SDNode *Result = Emit_51(N, PPC::VMAXUB, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 265:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VMINSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(265)) {
- SDNode *Result = Emit_51(N, PPC::VMINSB, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 268:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VMINUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(268)) {
- SDNode *Result = Emit_51(N, PPC::VMINUB, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 319:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VSUBSBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(319)) {
- SDNode *Result = Emit_51(N, PPC::VSUBSBS, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 322:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VSUBUBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(322)) {
- SDNode *Result = Emit_51(N, PPC::VSUBUBS, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 300:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VRLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(300)) {
- SDNode *Result = Emit_51(N, PPC::VRLB, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 306:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VSLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(306)) {
- SDNode *Result = Emit_51(N, PPC::VSLB, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 311:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VSRAB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(311)) {
- SDNode *Result = Emit_51(N, PPC::VSRAB, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 314:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VSRB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(314)) {
- SDNode *Result = Emit_51(N, PPC::VSRB, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 289:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VPKSHSS:v16i8 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(289)) {
- SDNode *Result = Emit_51(N, PPC::VPKSHSS, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 290:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VPKSHUS:v16i8 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(290)) {
- SDNode *Result = Emit_51(N, PPC::VPKSHUS, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 291:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VPKSWSS:v16i8 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(291)) {
- SDNode *Result = Emit_51(N, PPC::VPKSWSS, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 293:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VPKUHUS:v16i8 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(293)) {
- SDNode *Result = Emit_51(N, PPC::VPKUHUS, MVT::v16i8);
- return Result;
- }
}
+ case 16: { // Predicate_extloadi32
+ SDNode *N = Node;
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_52(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2, N3);
-}
-DISABLE_INLINE SDNode *Emit_53(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1);
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 262:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
- // Emits: (VMHADDSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(262)) {
- SDNode *Result = Emit_52(N, PPC::VMHADDSHS, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 263:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
- // Emits: (VMHRADDSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(263)) {
- SDNode *Result = Emit_52(N, PPC::VMHRADDSHS, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 271:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
- // Emits: (VMLADDUHM:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(271)) {
- SDNode *Result = Emit_52(N, PPC::VMLADDUHM, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 211:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VADDSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(211)) {
- SDNode *Result = Emit_51(N, PPC::VADDSHS, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 214:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VADDUHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(214)) {
- SDNode *Result = Emit_51(N, PPC::VADDUHS, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 217:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VAVGSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(217)) {
- SDNode *Result = Emit_51(N, PPC::VAVGSH, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 220:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VAVGUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(220)) {
- SDNode *Result = Emit_51(N, PPC::VAVGUH, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 257:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VMAXSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(257)) {
- SDNode *Result = Emit_51(N, PPC::VMAXSH, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 260:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VMAXUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(260)) {
- SDNode *Result = Emit_51(N, PPC::VMAXUH, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 266:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VMINSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(266)) {
- SDNode *Result = Emit_51(N, PPC::VMINSH, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 269:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VMINUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(269)) {
- SDNode *Result = Emit_51(N, PPC::VMINUH, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 278:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VMULESB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(278)) {
- SDNode *Result = Emit_51(N, PPC::VMULESB, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 280:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VMULEUB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(280)) {
- SDNode *Result = Emit_51(N, PPC::VMULEUB, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 282:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VMULOSB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(282)) {
- SDNode *Result = Emit_51(N, PPC::VMULOSB, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 284:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Emits: (VMULOUB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(284)) {
- SDNode *Result = Emit_51(N, PPC::VMULOUB, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 320:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VSUBSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(320)) {
- SDNode *Result = Emit_51(N, PPC::VSUBSHS, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 323:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VSUBUHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(323)) {
- SDNode *Result = Emit_51(N, PPC::VSUBUHS, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 301:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VRLH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(301)) {
- SDNode *Result = Emit_51(N, PPC::VRLH, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 307:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VSLH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(307)) {
- SDNode *Result = Emit_51(N, PPC::VSLH, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 312:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VSRAH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(312)) {
- SDNode *Result = Emit_51(N, PPC::VSRAH, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 315:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VSRH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(315)) {
- SDNode *Result = Emit_51(N, PPC::VSRH, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 288:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VPKPX:v8i16 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(288)) {
- SDNode *Result = Emit_51(N, PPC::VPKPX, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 292:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VPKSWUS:v8i16 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(292)) {
- SDNode *Result = Emit_51(N, PPC::VPKSWUS, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 294:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VPKUWUS:v8i16 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(294)) {
- SDNode *Result = Emit_51(N, PPC::VPKUWUS, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 331:iPTR, VRRC:v16i8:$vB)
- // Emits: (VUPKHSB:v8i16 VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(331)) {
- SDNode *Result = Emit_53(N, PPC::VUPKHSB, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 334:iPTR, VRRC:v16i8:$vB)
- // Emits: (VUPKLSB:v8i16 VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(334)) {
- SDNode *Result = Emit_53(N, PPC::VUPKLSB, MVT::v8i16);
- return Result;
- }
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_54(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp2, N1);
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 250:iPTR, VRRC:v4f32:$vB, (imm:i32):$UIMM)
- // Emits: (VCTSXS:v4i32 (imm:i32):$UIMM, VRRC:v4f32:$vB)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(250)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_54(N, PPC::VCTSXS, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 251:iPTR, VRRC:v4f32:$vB, (imm:i32):$UIMM)
- // Emits: (VCTUXS:v4i32 (imm:i32):$UIMM, VRRC:v4f32:$vB)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(251)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_54(N, PPC::VCTUXS, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 287:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v16i8:$vC)
- // Emits: (VPERM:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v16i8:$vC)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(287)) {
- SDNode *Result = Emit_52(N, PPC::VPERM, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 304:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v4i32:$vC)
- // Emits: (VSEL:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v4i32:$vC)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(304)) {
- SDNode *Result = Emit_52(N, PPC::VSEL, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 209:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VADDCUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(209)) {
- SDNode *Result = Emit_51(N, PPC::VADDCUW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 212:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VADDSWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(212)) {
- SDNode *Result = Emit_51(N, PPC::VADDSWS, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 215:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VADDUWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(215)) {
- SDNode *Result = Emit_51(N, PPC::VADDUWS, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 218:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VAVGSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(218)) {
- SDNode *Result = Emit_51(N, PPC::VAVGSW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 221:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VAVGUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(221)) {
- SDNode *Result = Emit_51(N, PPC::VAVGUW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 258:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VMAXSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(258)) {
- SDNode *Result = Emit_51(N, PPC::VMAXSW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 261:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VMAXUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(261)) {
- SDNode *Result = Emit_51(N, PPC::VMAXUW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 267:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VMINSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(267)) {
- SDNode *Result = Emit_51(N, PPC::VMINSW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 270:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VMINUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(270)) {
- SDNode *Result = Emit_51(N, PPC::VMINUW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 272:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
- // Emits: (VMSUMMBM:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(272)) {
- SDNode *Result = Emit_52(N, PPC::VMSUMMBM, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 273:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
- // Emits: (VMSUMSHM:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(273)) {
- SDNode *Result = Emit_52(N, PPC::VMSUMSHM, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 274:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
- // Emits: (VMSUMSHS:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(274)) {
- SDNode *Result = Emit_52(N, PPC::VMSUMSHS, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 275:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
- // Emits: (VMSUMUBM:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(275)) {
- SDNode *Result = Emit_52(N, PPC::VMSUMUBM, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 276:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
- // Emits: (VMSUMUHM:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(276)) {
- SDNode *Result = Emit_52(N, PPC::VMSUMUHM, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 277:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
- // Emits: (VMSUMUHS:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(277)) {
- SDNode *Result = Emit_52(N, PPC::VMSUMUHS, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 279:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VMULESH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(279)) {
- SDNode *Result = Emit_51(N, PPC::VMULESH, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 281:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VMULEUH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(281)) {
- SDNode *Result = Emit_51(N, PPC::VMULEUH, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 283:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VMULOSH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(283)) {
- SDNode *Result = Emit_51(N, PPC::VMULOSH, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 285:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Emits: (VMULOUH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(285)) {
- SDNode *Result = Emit_51(N, PPC::VMULOUH, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 318:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VSUBCUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(318)) {
- SDNode *Result = Emit_51(N, PPC::VSUBCUW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 321:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VSUBSWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(321)) {
- SDNode *Result = Emit_51(N, PPC::VSUBSWS, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 324:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VSUBUWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(324)) {
- SDNode *Result = Emit_51(N, PPC::VSUBUWS, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 329:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VSUMSWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(329)) {
- SDNode *Result = Emit_51(N, PPC::VSUMSWS, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 325:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VSUM2SWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(325)) {
- SDNode *Result = Emit_51(N, PPC::VSUM2SWS, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 326:iPTR, VRRC:v16i8:$vA, VRRC:v4i32:$vB)
- // Emits: (VSUM4SBS:v4i32 VRRC:v16i8:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(326)) {
- SDNode *Result = Emit_51(N, PPC::VSUM4SBS, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 327:iPTR, VRRC:v8i16:$vA, VRRC:v4i32:$vB)
- // Emits: (VSUM4SHS:v4i32 VRRC:v8i16:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(327)) {
- SDNode *Result = Emit_51(N, PPC::VSUM4SHS, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 328:iPTR, VRRC:v16i8:$vA, VRRC:v4i32:$vB)
- // Emits: (VSUM4UBS:v4i32 VRRC:v16i8:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(328)) {
- SDNode *Result = Emit_51(N, PPC::VSUM4UBS, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 302:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VRLW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(302)) {
- SDNode *Result = Emit_51(N, PPC::VRLW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 305:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VSL:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(305)) {
- SDNode *Result = Emit_51(N, PPC::VSL, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 308:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VSLO:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(308)) {
- SDNode *Result = Emit_51(N, PPC::VSLO, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 309:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VSLW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(309)) {
- SDNode *Result = Emit_51(N, PPC::VSLW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 310:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VSR:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(310)) {
- SDNode *Result = Emit_51(N, PPC::VSR, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 316:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VSRO:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(316)) {
- SDNode *Result = Emit_51(N, PPC::VSRO, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 313:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VSRAW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(313)) {
- SDNode *Result = Emit_51(N, PPC::VSRAW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 317:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VSRW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(317)) {
- SDNode *Result = Emit_51(N, PPC::VSRW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 330:iPTR, VRRC:v8i16:$vB)
- // Emits: (VUPKHPX:v4i32 VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(330)) {
- SDNode *Result = Emit_53(N, PPC::VUPKHPX, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 332:iPTR, VRRC:v8i16:$vB)
- // Emits: (VUPKHSH:v4i32 VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(332)) {
- SDNode *Result = Emit_53(N, PPC::VUPKHSH, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 333:iPTR, VRRC:v8i16:$vB)
- // Emits: (VUPKLPX:v4i32 VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(333)) {
- SDNode *Result = Emit_53(N, PPC::VUPKLPX, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 335:iPTR, VRRC:v8i16:$vB)
- // Emits: (VUPKLSH:v4i32 VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(335)) {
- SDNode *Result = Emit_53(N, PPC::VUPKLSH, MVT::v4i32);
- return Result;
- }
}
+ case 17: { // Predicate_extloadf32
+ SDNode *N = Node;
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 222:iPTR, VRRC:v4i32:$vB, (imm:i32):$UIMM)
- // Emits: (VCFSX:v4f32 (imm:i32):$UIMM, VRRC:v4i32:$vB)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(222)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_54(N, PPC::VCFSX, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 223:iPTR, VRRC:v4i32:$vB, (imm:i32):$UIMM)
- // Emits: (VCFUX:v4f32 (imm:i32):$UIMM, VRRC:v4i32:$vB)
- // Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(223)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_54(N, PPC::VCFUX, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 252:iPTR, VRRC:v4f32:$vB)
- // Emits: (VEXPTEFP:v4f32 VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(252)) {
- SDNode *Result = Emit_53(N, PPC::VEXPTEFP, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 253:iPTR, VRRC:v4f32:$vB)
- // Emits: (VLOGEFP:v4f32 VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(253)) {
- SDNode *Result = Emit_53(N, PPC::VLOGEFP, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 255:iPTR, VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Emits: (VMAXFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(255)) {
- SDNode *Result = Emit_51(N, PPC::VMAXFP, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 264:iPTR, VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Emits: (VMINFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(264)) {
- SDNode *Result = Emit_51(N, PPC::VMINFP, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 295:iPTR, VRRC:v4f32:$vB)
- // Emits: (VREFP:v4f32 VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(295)) {
- SDNode *Result = Emit_53(N, PPC::VREFP, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 296:iPTR, VRRC:v4f32:$vB)
- // Emits: (VRFIM:v4f32 VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(296)) {
- SDNode *Result = Emit_53(N, PPC::VRFIM, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 297:iPTR, VRRC:v4f32:$vB)
- // Emits: (VRFIN:v4f32 VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(297)) {
- SDNode *Result = Emit_53(N, PPC::VRFIN, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 298:iPTR, VRRC:v4f32:$vB)
- // Emits: (VRFIP:v4f32 VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(298)) {
- SDNode *Result = Emit_53(N, PPC::VRFIP, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 299:iPTR, VRRC:v4f32:$vB)
- // Emits: (VRFIZ:v4f32 VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(299)) {
- SDNode *Result = Emit_53(N, PPC::VRFIZ, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 303:iPTR, VRRC:v4f32:$vB)
- // Emits: (VRSQRTEFP:v4f32 VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(303)) {
- SDNode *Result = Emit_53(N, PPC::VRSQRTEFP, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 254:iPTR, VRRC:v4f32:$A, VRRC:v4f32:$B, VRRC:v4f32:$C)
- // Emits: (VMADDFP:v4f32 VRRC:v16i8:$A, VRRC:v16i8:$B, VRRC:v16i8:$C)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(254)) {
- SDNode *Result = Emit_52(N, PPC::VMADDFP, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 286:iPTR, VRRC:v4f32:$A, VRRC:v4f32:$B, VRRC:v4f32:$C)
- // Emits: (VNMSUBFP:v4f32 VRRC:v16i8:$A, VRRC:v16i8:$B, VRRC:v16i8:$C)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(286)) {
- SDNode *Result = Emit_52(N, PPC::VNMSUBFP, MVT::v4f32);
- return Result;
- }
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_55(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, CPTmpN2_0, CPTmpN2_1, Chain);
-}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(195)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_55(N, PPC::LVEBX, MVT::v16i8, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
}
+ case 18: { // Predicate_unindexedstore
+ SDNode *N = Node;
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_56(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Chain);
-}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_w_chain:v8i16 196:iPTR, xoaddr:iPTR:$src)
- // Emits: (LVEHX:v8i16 xoaddr:iPTR:$src)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(196)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_55(N, PPC::LVEHX, MVT::v8i16, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_w_chain:v8i16 202:iPTR)
- // Emits: (MFVSCR:v8i16)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(202)) {
- SDNode *Result = Emit_56(N, PPC::MFVSCR, MVT::v8i16);
- return Result;
- }
- }
+ return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_w_chain:v4i32 197:iPTR, xoaddr:iPTR:$src)
- // Emits: (LVEWX:v4i32 xoaddr:iPTR:$src)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(197)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_55(N, PPC::LVEWX, MVT::v4i32, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_w_chain:v4i32 200:iPTR, xoaddr:iPTR:$src)
- // Emits: (LVX:v4i32 xoaddr:iPTR:$src)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(200)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_55(N, PPC::LVX, MVT::v4i32, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_w_chain:v4i32 201:iPTR, xoaddr:iPTR:$src)
- // Emits: (LVXL:v4i32 xoaddr:iPTR:$src)
- // Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(201)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_55(N, PPC::LVXL, MVT::v4i32, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
}
+ case 19: { // Predicate_truncstore
+ SDNode *N = Node;
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_57(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_LOAD_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (LBZ:i32 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextload(N) &&
- Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (LHA:i32 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_sextload(N) &&
- Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LHA, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (LHZ:i32 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextload(N) &&
- Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LHZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (LWZ:i32 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LWZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (LBZX:i32 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextload(N) &&
- Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (LHAX:i32 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_sextload(N) &&
- Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LHAX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (LHZX:i32 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextload(N) &&
- Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LHZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (LWZX:i32 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LWZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_zextload(N) &&
- Predicate_zextloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (LBZ:i32 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (LBZX:i32 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_extload(N)) {
- if (Predicate_extloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (LBZ:i32 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (LBZX:i32 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_extloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (LBZ:i32 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (LBZX:i32 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_extloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (LHZ:i32 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LHZ, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (LHZX:i32 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LHZX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- }
- }
+ return cast<StoreSDNode>(N)->isTruncatingStore();
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_LOAD_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
- if (Predicate_sextload(N)) {
-
- // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (LHA8:i64 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LHA8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 ixaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>
- // Emits: (LWA:i64 ixaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_sextloadi32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrImmShift(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LWA, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (LHAX8:i64 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LHAX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>
- // Emits: (LWAX:i64 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_sextloadi32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LWAX, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- }
- if (Predicate_zextload(N)) {
-
- // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (LBZ8:i64 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (LHZ8:i64 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LHZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>
- // Emits: (LWZ8:i64 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextloadi32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LWZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (LBZX8:i64 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (LHZX8:i64 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LHZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>
- // Emits: (LWZX8:i64 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextloadi32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LWZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- }
- if (Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i64 ixaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (LD:i64 ixaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImmShift(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LD, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (LDX:i64 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LDX, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_zextload(N) &&
- Predicate_zextloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (LBZ8:i64 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (LBZX8:i64 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_extload(N)) {
- if (Predicate_extloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (LBZ8:i64 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (LBZX8:i64 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_extloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (LBZ8:i64 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (LBZX8:i64 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LBZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_extloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (LHZ8:i64 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LHZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (LHZX8:i64 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LHZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_extloadi32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>
- // Emits: (LWZ8:i64 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LWZ8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>
- // Emits: (LWZX8:i64 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LWZX8, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- }
}
+ case 20: { // Predicate_truncstorei8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_LOAD_f32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:f32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (LFS:f32 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LFS, MVT::f32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:f32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (LFSX:f32 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LFSX, MVT::f32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_58(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain), 0);
- Chain = SDValue(Tmp1.getNode(), 1);
- MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
- MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
- SDNode *ResNode = CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp1);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
- ReplaceUses(SDValue(N, 1), Chain);
- return ResNode;
-}
-SDNode *Select_ISD_LOAD_f64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
- if (Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:f64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (LFD:f64 iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LFD, MVT::f64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:f64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (LFDX:f64 xaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LFDX, MVT::f64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
- if (Predicate_extload(N) &&
- Predicate_extloadf32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (ld:f64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
- // Emits: (FMRSD:f64 (LFS:f32 iaddr:iPTR:$src))
- // Pattern complexity = 13 cost = 2 size = 0
- if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_58(N, PPC::LFS, PPC::FMRSD, MVT::f32, MVT::f64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (ld:f64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
- // Emits: (FMRSD:f64 (LFSX:f32 xaddr:iPTR:$src))
- // Pattern complexity = 13 cost = 2 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_58(N, PPC::LFSX, PPC::FMRSD, MVT::f32, MVT::f64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
}
+ case 21: { // Predicate_truncstorei16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_LOAD_v4i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_57(N, PPC::LVX, MVT::v4i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
- }
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_59(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
-}
-SDNode *Select_ISD_MEMBARRIER(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDValue N4 = N->getOperand(4);
- if (N4.getNode()->getOpcode() == ISD::Constant) {
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_59(N, PPC::SYNC);
- return Result;
- }
- }
- }
- }
}
+ case 22: { // Predicate_store
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_MUL_i32(SDNode *N) {
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
- // Pattern: (mul:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_immSExt16>>:$imm)
- // Emits: (MULLI:i32 GPRC:i32:$rA, (imm:i32):$imm)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immSExt16(N1.getNode())) {
- SDNode *Result = Emit_0(N, PPC::MULLI, MVT::i32);
- return Result;
- }
}
+ case 23: { // Predicate_truncstorei32
+ SDNode *N = Node;
- // Pattern: (mul:i32 GPRC:i32:$rA, GPRC:i32:$rB)
- // Emits: (MULLW:i32 GPRC:i32:$rA, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::MULLW, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_MUL_i64(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::MULLD, MVT::i64);
- return Result;
-}
-
-SDNode *Select_ISD_MULHS_i32(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::MULHW, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_MULHS_i64(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::MULHD, MVT::i64);
- return Result;
-}
-
-SDNode *Select_ISD_MULHU_i32(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::MULHWU, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_MULHU_i64(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::MULHDU, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_60(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_LO16(Tmp1.getNode());
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
- SDValue Tmp4 = Transform_HI16(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp3, Tmp4);
-}
-SDNode *Select_ISD_OR_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (or:i32 GPRC:i32:$rS, (xor:i32 GPRC:i32:$rB, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (ORC:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_2(N, PPC::ORC, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (or:i32 (xor:i32 GPRC:i32:$rB, (imm:i32)<<P:Predicate_immAllOnes>>), GPRC:i32:$rS)
- // Emits: (ORC:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_5(N, PPC::ORC, MVT::i32);
- return Result;
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (or:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
- // Emits: (ORI:i32 GPRC:i32:$src1, (LO16:i32 (imm:i32):$src2))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_immZExt16(N1.getNode())) {
- SDNode *Result = Emit_13(N, PPC::ORI, MVT::i32);
- return Result;
- }
-
- // Pattern: (or:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_imm16ShiftedZExt>><<X:HI16>>:$src2)
- // Emits: (ORIS:i32 GPRC:i32:$src1, (HI16:i32 (imm:i32):$src2))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm16ShiftedZExt(N1.getNode())) {
- SDNode *Result = Emit_1(N, PPC::ORIS, MVT::i32);
- return Result;
- }
-
- // Pattern: (or:i32 GPRC:i32:$in, (imm:i32):$imm)
- // Emits: (ORIS:i32 (ORI:i32 GPRC:i32:$in, (LO16:i32 (imm:i32):$imm)), (HI16:i32 (imm:i32):$imm))
- // Pattern complexity = 6 cost = 2 size = 0
- SDNode *Result = Emit_60(N, PPC::ORI, PPC::ORIS, MVT::i32, MVT::i32);
- return Result;
- }
- }
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
- // Pattern: (or:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Emits: (OR:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::OR, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_OR_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (or:i64 G8RC:i64:$rS, (xor:i64 G8RC:i64:$rB, (imm:i64)<<P:Predicate_immAllOnes>>))
- // Emits: (ORC8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_2(N, PPC::ORC8, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (or:i64 (xor:i64 G8RC:i64:$rB, (imm:i64)<<P:Predicate_immAllOnes>>), G8RC:i64:$rS)
- // Emits: (ORC8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_5(N, PPC::ORC8, MVT::i64);
- return Result;
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (or:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
- // Emits: (ORI8:i64 G8RC:i64:$src1, (LO16:i32 (imm:i64):$src2))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_immZExt16(N1.getNode())) {
- SDNode *Result = Emit_15(N, PPC::ORI8, MVT::i64);
- return Result;
- }
-
- // Pattern: (or:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_imm16ShiftedZExt>><<X:HI16>>:$src2)
- // Emits: (ORIS8:i64 G8RC:i64:$src1, (HI16:i32 (imm:i64):$src2))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm16ShiftedZExt(N1.getNode())) {
- SDNode *Result = Emit_7(N, PPC::ORIS8, MVT::i64);
- return Result;
- }
- }
}
+ case 24: { // Predicate_itruncstore
+ SDNode *N = Node;
- // Pattern: (or:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Emits: (OR8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::OR8, MVT::i64);
- return Result;
-}
-
-SDNode *Select_ISD_OR_v4i32(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::VOR, MVT::v4i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_61(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0x1FULL, MVT::i32);
- SDValue Ops0[] = { N0, N1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_62(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp3 = CurDAG->getTargetConstant(0x1FULL, MVT::i32);
- SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ISD_ROTL_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (rotl:i32 GPRC:i32:$in, (imm:i32):$imm)
- // Emits: (RLWINM:i32 GPRC:i32:$in, (imm:i32):$imm, 0:i32, 31:i32)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_62(N, PPC::RLWINM, MVT::i32);
- return Result;
- }
+ return cast<StoreSDNode>(N)->isTruncatingStore();
- // Pattern: (rotl:i32 GPRC:i32:$in, GPRC:i32:$sh)
- // Emits: (RLWNM:i32 GPRC:i32:$in, GPRC:i32:$sh, 0:i32, 31:i32)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_61(N, PPC::RLWNM, MVT::i32);
- return Result;
}
+ case 25: { // Predicate_pre_truncst
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_63(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_64(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1, Tmp2);
-}
-SDNode *Select_ISD_ROTL_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (rotl:i64 G8RC:i64:$in, (imm:i32):$imm)
- // Emits: (RLDICL:i64 G8RC:i64:$in, (imm:i32):$imm, 0:i32)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_64(N, PPC::RLDICL, MVT::i64);
- return Result;
- }
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
- // Pattern: (rotl:i64 G8RC:i64:$in, GPRC:i32:$sh)
- // Emits: (RLDCL:i64 G8RC:i64:$in, GPRC:i32:$sh, 0:i32)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_63(N, PPC::RLDCL, MVT::i64);
- return Result;
}
+ case 26: { // Predicate_pre_truncsti8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SDIV_i32(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::DIVW, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_SDIV_i64(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::DIVD, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_65(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp3 = Transform_SHL32(Tmp1.getNode());
- SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ISD_SHL_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (shl:i32 GPRC:i32:$in, (imm:i32):$imm)
- // Emits: (RLWINM:i32 GPRC:i32:$in, (imm:i32):$imm, 0:i32, (SHL32:i32 (imm:i32):$imm))
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_65(N, PPC::RLWINM, MVT::i32);
- return Result;
- }
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
- // Pattern: (shl:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Emits: (SLW:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, PPC::SLW, MVT::i32);
- return Result;
}
+ case 27: { // Predicate_pre_truncsti16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_66(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_SHL64(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1, Tmp2);
-}
-SDNode *Select_ISD_SHL_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (shl:i64 G8RC:i64:$in, (imm:i32):$imm)
- // Emits: (RLDICR:i64 G8RC:i64:$in, (imm:i32):$imm, (SHL64:i32 (imm:i32):$imm))
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_66(N, PPC::RLDICR, MVT::i64);
- return Result;
- }
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
- // Pattern: (shl:i64 G8RC:i64:$rS, GPRC:i32:$rB)
- // Emits: (SLD:i64 G8RC:i64:$rS, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, PPC::SLD, MVT::i64);
- return Result;
}
+ case 28: { // Predicate_istore
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
-SDNode *Select_ISD_SHL_v16i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_3(N, PPC::VSLB, MVT::v16i8);
- return Result;
}
+ case 29: { // Predicate_pre_store
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
+ return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
-SDNode *Select_ISD_SHL_v8i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_3(N, PPC::VSLH, MVT::v8i16);
- return Result;
}
+ case 30: { // Predicate_V_immneg0
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return PPC::isAllNegativeZeroVector(N);
-SDNode *Select_ISD_SHL_v4i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_3(N, PPC::VSLW, MVT::v4i32);
- return Result;
}
+ case 31: { // Predicate_atomic_load_add_8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SIGN_EXTEND_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_29(N, PPC::EXTSW_32_64, MVT::i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 32: { // Predicate_atomic_load_add_16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_67(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0);
-}
-SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sext_inreg:i32 GPRC:i32:$rS, i8:Other)
- // Emits: (EXTSB:i32 GPRC:i32:$rS)
- // Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_67(N, PPC::EXTSB, MVT::i32);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 33: { // Predicate_atomic_load_add_32
+ SDNode *N = Node;
- // Pattern: (sext_inreg:i32 GPRC:i32:$rS, i16:Other)
- // Emits: (EXTSH:i32 GPRC:i32:$rS)
- // Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_67(N, PPC::EXTSH, MVT::i32);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 34: { // Predicate_atomic_load_add_64
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sext_inreg:i64 G8RC:i64:$rS, i8:Other)
- // Emits: (EXTSB8:i64 G8RC:i64:$rS)
- // Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_67(N, PPC::EXTSB8, MVT::i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 35: { // Predicate_atomic_load_sub_8
+ SDNode *N = Node;
- // Pattern: (sext_inreg:i64 G8RC:i64:$rS, i16:Other)
- // Emits: (EXTSH8:i64 G8RC:i64:$rS)
- // Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_67(N, PPC::EXTSH8, MVT::i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 36: { // Predicate_atomic_load_sub_16
+ SDNode *N = Node;
- // Pattern: (sext_inreg:i64 G8RC:i64:$rS, i32:Other)
- // Emits: (EXTSW:i64 G8RC:i64:$rS)
- // Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_67(N, PPC::EXTSW, MVT::i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 37: { // Predicate_atomic_load_sub_32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRA_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sra:i32 GPRC:i32:$rS, (imm:i32):$SH)
- // Emits: (SRAWI:i32 GPRC:i32:$rS, (imm:i32):$SH)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_0(N, PPC::SRAWI, MVT::i32);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 38: { // Predicate_atomic_load_sub_64
+ SDNode *N = Node;
- // Pattern: (sra:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Emits: (SRAW:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, PPC::SRAW, MVT::i32);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 39: { // Predicate_atomic_load_and_8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRA_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sra:i64 G8RC:i64:$rS, (imm:i32):$SH)
- // Emits: (SRADI:i64 G8RC:i64:$rS, (imm:i32):$SH)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_0(N, PPC::SRADI, MVT::i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 40: { // Predicate_atomic_load_and_16
+ SDNode *N = Node;
- // Pattern: (sra:i64 G8RC:i64:$rS, GPRC:i32:$rB)
- // Emits: (SRAD:i64 G8RC:i64:$rS, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, PPC::SRAD, MVT::i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 41: { // Predicate_atomic_load_and_32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRA_v16i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_3(N, PPC::VSRAB, MVT::v16i8);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 42: { // Predicate_atomic_load_and_64
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRA_v8i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_3(N, PPC::VSRAH, MVT::v8i16);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 43: { // Predicate_atomic_load_or_8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRA_v4i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_3(N, PPC::VSRAW, MVT::v4i32);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 44: { // Predicate_atomic_load_or_16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_68(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_SRL32(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0x1FULL, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp1, Tmp3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_ISD_SRL_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (srl:i32 GPRC:i32:$in, (imm:i32):$imm)
- // Emits: (RLWINM:i32 GPRC:i32:$in, (SRL32:i32 (imm:i32):$imm), (imm:i32):$imm, 31:i32)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_68(N, PPC::RLWINM, MVT::i32);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 45: { // Predicate_atomic_load_or_32
+ SDNode *N = Node;
- // Pattern: (srl:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Emits: (SRW:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, PPC::SRW, MVT::i32);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 46: { // Predicate_atomic_load_or_64
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_69(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_SRL64(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2, Tmp1);
-}
-SDNode *Select_ISD_SRL_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (srl:i64 G8RC:i64:$in, (imm:i32):$imm)
- // Emits: (RLDICL:i64 G8RC:i64:$in, (SRL64:i32 (imm:i32):$imm), (imm:i32):$imm)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_69(N, PPC::RLDICL, MVT::i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 47: { // Predicate_atomic_load_xor_8
+ SDNode *N = Node;
- // Pattern: (srl:i64 G8RC:i64:$rS, GPRC:i32:$rB)
- // Emits: (SRD:i64 G8RC:i64:$rS, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, PPC::SRD, MVT::i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 48: { // Predicate_atomic_load_xor_16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRL_v16i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_3(N, PPC::VSRB, MVT::v16i8);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 49: { // Predicate_atomic_load_xor_32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRL_v8i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_3(N, PPC::VSRH, MVT::v8i16);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 50: { // Predicate_atomic_load_xor_64
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRL_v4i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_3(N, PPC::VSRW, MVT::v4i32);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 51: { // Predicate_atomic_load_nand_8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_70(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_STORE(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N)) {
- if (Predicate_truncstore(N)) {
-
- // Pattern: (st:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
- // Emits: (STB:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_70(N, PPC::STB, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (STH:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_70(N, PPC::STH, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
- }
- if (Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1)) {
-
- // Pattern: (st:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (STW:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_70(N, PPC::STW, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
-
- // Pattern: (st:isVoid F4RC:f32:$rS, iaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (STFS:isVoid F4RC:f32:$rS, iaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_70(N, PPC::STFS, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
-
- // Pattern: (st:isVoid F8RC:f64:$rS, iaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (STFD:isVoid F8RC:f64:$rS, iaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_70(N, PPC::STFD, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
- }
- if (Predicate_truncstore(N)) {
-
- // Pattern: (st:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
- // Emits: (STBX:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_70(N, PPC::STBX, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (STHX:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_70(N, PPC::STHX, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
- }
- if (Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1)) {
-
- // Pattern: (st:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (STWX:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_70(N, PPC::STWX, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
-
- // Pattern: (st:isVoid F4RC:f32:$frS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (STFSX:isVoid F4RC:f32:$frS, xaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_70(N, PPC::STFSX, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
-
- // Pattern: (st:isVoid F8RC:f64:$frS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (STFDX:isVoid F8RC:f64:$frS, xaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_70(N, PPC::STFDX, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
- }
- if (Predicate_truncstore(N)) {
-
- // Pattern: (st:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
- // Emits: (STB8:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_70(N, PPC::STB8, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (STH8:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_70(N, PPC::STH8, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>
- // Emits: (STW8:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_70(N, PPC::STW8, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
- // Emits: (STBX8:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_70(N, PPC::STBX8, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (STHX8:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_70(N, PPC::STHX8, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>
- // Emits: (STWX8:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_70(N, PPC::STWX8, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
- }
- if (Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
-
- // Pattern: (st:isVoid G8RC:i64:$rS, ixaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (STD:isVoid G8RC:i64:$rS, ixaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrImmShift(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_70(N, PPC::STD, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
-
- // Pattern: (st:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (STDX:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_70(N, PPC::STDX, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
-
- // Pattern: (st:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (STVX:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
- // Pattern complexity = 13 cost = 1 size = 0
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_70(N, PPC::STVX, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 52: { // Predicate_atomic_load_nand_16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_71(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN3_0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN3_0, N2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 4);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_STORE_iPTR(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_itruncstore(N) &&
- Predicate_pre_truncst(N)) {
-
- // Pattern: (ist:iPTR GPRC:i32:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti8>>
- // Emits: (STBU:iPTR GPRC:i32:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_truncsti8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_71(N, PPC::STBU, MVT::iPTR, CPTmpN3_0);
- return Result;
- }
- }
-
- // Pattern: (ist:iPTR GPRC:i32:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti16>>
- // Emits: (STHU:iPTR GPRC:i32:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_truncsti16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_71(N, PPC::STHU, MVT::iPTR, CPTmpN3_0);
- return Result;
- }
- }
- }
- if (Predicate_istore(N) &&
- Predicate_pre_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- if (SelectAddrImmOffs(N, N3, CPTmpN3_0)) {
-
- // Pattern: (ist:iPTR GPRC:i32:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_istore>><<P:Predicate_pre_store>>
- // Emits: (STWU:iPTR GPRC:i32:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_71(N, PPC::STWU, MVT::iPTR, CPTmpN3_0);
- return Result;
- }
-
- // Pattern: (ist:iPTR F4RC:f32:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_istore>><<P:Predicate_pre_store>>
- // Emits: (STFSU:iPTR F4RC:f32:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_71(N, PPC::STFSU, MVT::iPTR, CPTmpN3_0);
- return Result;
- }
-
- // Pattern: (ist:iPTR F8RC:f64:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_istore>><<P:Predicate_pre_store>>
- // Emits: (STFDU:iPTR F8RC:f64:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_71(N, PPC::STFDU, MVT::iPTR, CPTmpN3_0);
- return Result;
- }
- }
- }
- if (Predicate_itruncstore(N) &&
- Predicate_pre_truncst(N)) {
-
- // Pattern: (ist:iPTR G8RC:i64:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti8>>
- // Emits: (STBU8:iPTR G8RC:i64:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_truncsti8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_71(N, PPC::STBU8, MVT::iPTR, CPTmpN3_0);
- return Result;
- }
- }
-
- // Pattern: (ist:iPTR G8RC:i64:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti16>>
- // Emits: (STHU8:iPTR G8RC:i64:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
- // Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_truncsti16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_71(N, PPC::STHU8, MVT::iPTR, CPTmpN3_0);
- return Result;
- }
- }
- }
- if (Predicate_istore(N) &&
- Predicate_pre_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue CPTmpN3_0;
- if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
- N1.getValueType() == MVT::i64) {
-
- // Pattern: (ist:iPTR G8RC:i64:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_istore>><<P:Predicate_pre_store>>
- // Emits: (STWU8:iPTR G8RC:i64:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDNode *Result = Emit_71(N, PPC::STWU8, MVT::iPTR, CPTmpN3_0);
- return Result;
- }
-
- // Pattern: (ist:iPTR G8RC:i64:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_istore>><<P:Predicate_pre_store>>
- // Emits: (STDU:iPTR G8RC:i64:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
- // Pattern complexity = 10 cost = 1 size = 0
- SDNode *Result = Emit_71(N, PPC::STDU, MVT::iPTR, CPTmpN3_0);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 53: { // Predicate_atomic_load_nand_32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_72(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N0);
-}
-DISABLE_INLINE SDNode *Emit_73(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, Tmp1);
-}
-SDNode *Select_ISD_SUB_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (sub:i32 0:i32, GPRC:i32:$rA)
- // Emits: (NEG:i32 GPRC:i32:$rA)
- // Pattern complexity = 8 cost = 1 size = 0
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_53(N, PPC::NEG, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (sub:i32 (imm:i32)<<P:Predicate_immSExt16>>:$imm, GPRC:i32:$in)
- // Emits: (SUBFIC:i32 GPRC:i32:$in, (imm:i32):$imm)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immSExt16(N0.getNode())) {
- SDNode *Result = Emit_73(N, PPC::SUBFIC, MVT::i32);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 54: { // Predicate_atomic_load_nand_64
+ SDNode *N = Node;
- // Pattern: (sub:i32 GPRC:i32:$rB, GPRC:i32:$rA)
- // Emits: (SUBF:i32 GPRC:i32:$rA, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_72(N, PPC::SUBF, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_SUB_i64(SDNode *N) {
-
- // Pattern: (sub:i64 0:i64, G8RC:i64:$rA)
- // Emits: (NEG8:i64 G8RC:i64:$rA)
- // Pattern complexity = 8 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_53(N, PPC::NEG8, MVT::i64);
- return Result;
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 55: { // Predicate_atomic_cmp_swap_8
+ SDNode *N = Node;
- // Pattern: (sub:i64 G8RC:i64:$rB, G8RC:i64:$rA)
- // Emits: (SUBF8:i64 G8RC:i64:$rA, G8RC:i64:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_72(N, PPC::SUBF8, MVT::i64);
- return Result;
-}
-
-SDNode *Select_ISD_SUB_v16i8(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::VSUBUBM, MVT::v16i8);
- return Result;
-}
-
-SDNode *Select_ISD_SUB_v8i16(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::VSUBUHM, MVT::v8i16);
- return Result;
-}
-
-SDNode *Select_ISD_SUB_v4i32(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::VSUBUWM, MVT::v4i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_74(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, Tmp1);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_75(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, N0);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_SUBC_i32(SDNode *N) {
-
- // Pattern: (subc:i32 (imm:i32)<<P:Predicate_immSExt16>>:$imm, GPRC:i32:$rA)
- // Emits: (SUBFIC:i32 GPRC:i32:$rA, (imm:i32):$imm)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immSExt16(N0.getNode())) {
- SDNode *Result = Emit_74(N, PPC::SUBFIC, MVT::i32);
- return Result;
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
- // Pattern: (subc:i32 GPRC:i32:$rB, GPRC:i32:$rA)
- // Emits: (SUBFC:i32 GPRC:i32:$rA, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_75(N, PPC::SUBFC, MVT::i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_76(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i64);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, Tmp1);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_SUBC_i64(SDNode *N) {
-
- // Pattern: (subc:i64 (imm:i64)<<P:Predicate_immSExt16>>:$imm, G8RC:i64:$rA)
- // Emits: (SUBFIC8:i64 G8RC:i64:$rA, (imm:i64):$imm)
- // Pattern complexity = 7 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immSExt16(N0.getNode())) {
- SDNode *Result = Emit_76(N, PPC::SUBFIC8, MVT::i64);
- return Result;
- }
}
+ case 56: { // Predicate_atomic_cmp_swap_16
+ SDNode *N = Node;
- // Pattern: (subc:i64 G8RC:i64:$rB, G8RC:i64:$rA)
- // Emits: (SUBFC8:i64 G8RC:i64:$rA, G8RC:i64:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_75(N, PPC::SUBFC8, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_77(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, N0, InFlag);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_78(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, InFlag);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_SUBE_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (sube:i32 0:i32, GPRC:i32:$rA)
- // Emits: (SUBFZE:i32 GPRC:i32:$rA)
- // Pattern complexity = 8 cost = 1 size = 0
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_78(N, PPC::SUBFZE, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (sube:i32 (imm:i32)<<P:Predicate_immAllOnes>>, GPRC:i32:$rA)
- // Emits: (SUBFME:i32 GPRC:i32:$rA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N0.getNode())) {
- SDNode *Result = Emit_78(N, PPC::SUBFME, MVT::i32);
- return Result;
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
- // Pattern: (sube:i32 GPRC:i32:$rB, GPRC:i32:$rA)
- // Emits: (SUBFE:i32 GPRC:i32:$rA, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_77(N, PPC::SUBFE, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_SUBE_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (sube:i64 0:i64, G8RC:i64:$rA)
- // Emits: (SUBFZE8:i64 G8RC:i64:$rA)
- // Pattern complexity = 8 cost = 1 size = 0
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_78(N, PPC::SUBFZE8, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (sube:i64 (imm:i64)<<P:Predicate_immAllOnes>>, G8RC:i64:$rA)
- // Emits: (SUBFME8:i64 G8RC:i64:$rA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N0.getNode())) {
- SDNode *Result = Emit_78(N, PPC::SUBFME8, MVT::i64);
- return Result;
- }
}
+ case 57: { // Predicate_atomic_cmp_swap_32
+ SDNode *N = Node;
- // Pattern: (sube:i64 G8RC:i64:$rB, G8RC:i64:$rA)
- // Emits: (SUBFE8:i64 G8RC:i64:$rA, G8RC:i64:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_77(N, PPC::SUBFE8, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_79(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
-}
-SDNode *Select_ISD_TRAP(SDNode *N) {
- SDNode *Result = Emit_79(N, PPC::TRAP);
- return Result;
-}
-
-SDNode *Select_ISD_TRUNCATE_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_18(N, PPC::OR8To4, MVT::i32);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_UDIV_i32(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::DIVWU, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_UDIV_i64(SDNode *N) {
- SDNode *Result = Emit_3(N, PPC::DIVDU, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_80(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = Transform_VSLDOI_get_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_81(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = Transform_VSPLTB_get_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, N0);
-}
-DISABLE_INLINE SDNode *Emit_82(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = Transform_VSPLTH_get_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, N0);
-}
-DISABLE_INLINE SDNode *Emit_83(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = Transform_VSPLTW_get_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, N0);
-}
-DISABLE_INLINE SDNode *Emit_84(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = Transform_VSLDOI_unary_get_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N0, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_85(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N0);
-}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(SDNode *N) {
-
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8))<<P:Predicate_vspltb_shuffle>><<X:VSPLTB_get_imm>>:$UIMM
- // Emits: (VSPLTB:v16i8 (VSPLTB_get_imm:i32 (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8)):$UIMM), VRRC:v16i8:$vB)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vspltb_shuffle(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_81(N, PPC::VSPLTB, MVT::v16i8);
- return Result;
- }
}
+ case 58: { // Predicate_atomic_cmp_swap_64
+ SDNode *N = Node;
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8))<<P:Predicate_vsplth_shuffle>><<X:VSPLTH_get_imm>>:$UIMM
- // Emits: (VSPLTH:v16i8 (VSPLTH_get_imm:i32 (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8)):$UIMM), VRRC:v16i8:$vB)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vsplth_shuffle(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_82(N, PPC::VSPLTH, MVT::v16i8);
- return Result;
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8))<<P:Predicate_vspltw_shuffle>><<X:VSPLTW_get_imm>>:$UIMM
- // Emits: (VSPLTW:v16i8 (VSPLTW_get_imm:i32 (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8)):$UIMM), VRRC:v16i8:$vB)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vspltw_shuffle(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_83(N, PPC::VSPLTW, MVT::v16i8);
- return Result;
- }
}
+ case 59: { // Predicate_atomic_swap_8
+ SDNode *N = Node;
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vsldoi_unary_shuffle>><<X:VSLDOI_unary_get_imm>>:$in
- // Emits: (VSLDOI:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA, (VSLDOI_unary_get_imm:i32 VRRC:i32:$in))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vsldoi_unary_shuffle(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_84(N, PPC::VSLDOI, MVT::v16i8);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 60: { // Predicate_atomic_swap_16
+ SDNode *N = Node;
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vpkuwum_unary_shuffle>>
- // Emits: (VPKUWUM:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vpkuwum_unary_shuffle(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_85(N, PPC::VPKUWUM, MVT::v16i8);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 61: { // Predicate_atomic_swap_32
+ SDNode *N = Node;
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vpkuhum_unary_shuffle>>
- // Emits: (VPKUHUM:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vpkuhum_unary_shuffle(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_85(N, PPC::VPKUHUM, MVT::v16i8);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 62: { // Predicate_atomic_swap_64
+ SDNode *N = Node;
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrglb_unary_shuffle>>
- // Emits: (VMRGLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vmrglb_unary_shuffle(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_85(N, PPC::VMRGLB, MVT::v16i8);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 63: { // Predicate_immAllOnesV
+ SDNode *N = Node;
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrglh_unary_shuffle>>
- // Emits: (VMRGLH:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vmrglh_unary_shuffle(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_85(N, PPC::VMRGLH, MVT::v16i8);
- return Result;
- }
- }
+ return ISD::isBuildVectorAllOnes(N);
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrglw_unary_shuffle>>
- // Emits: (VMRGLW:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vmrglw_unary_shuffle(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_85(N, PPC::VMRGLW, MVT::v16i8);
- return Result;
- }
}
+ case 64: { // Predicate_immAllOnesV_bc
+ SDNode *N = Node;
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrghb_unary_shuffle>>
- // Emits: (VMRGHB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vmrghb_unary_shuffle(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_85(N, PPC::VMRGHB, MVT::v16i8);
- return Result;
- }
- }
+ return ISD::isBuildVectorAllOnes(N);
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrghh_unary_shuffle>>
- // Emits: (VMRGHH:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vmrghh_unary_shuffle(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_85(N, PPC::VMRGHH, MVT::v16i8);
- return Result;
- }
}
+ case 65: { // Predicate_immZExt16
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrghw_unary_shuffle>>
- // Emits: (VMRGHW:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vmrghw_unary_shuffle(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_85(N, PPC::VMRGHW, MVT::v16i8);
- return Result;
- }
- }
+ // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
+ // field. Used by instructions like 'ori'.
+ return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vsldoi_shuffle>><<X:VSLDOI_get_imm>>:$SH
- // Emits: (VSLDOI:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, (VSLDOI_get_imm:i32 (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB):$SH))
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vsldoi_shuffle(N)) {
- SDNode *Result = Emit_80(N, PPC::VSLDOI, MVT::v16i8);
- return Result;
}
+ case 66: { // Predicate_imm16ShiftedZExt
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrghb_shuffle>>
- // Emits: (VMRGHB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vmrghb_shuffle(N)) {
- SDNode *Result = Emit_3(N, PPC::VMRGHB, MVT::v16i8);
- return Result;
- }
+ // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
+ // immediate are set. Used by instructions like 'xoris'.
+ return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrghh_shuffle>>
- // Emits: (VMRGHH:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vmrghh_shuffle(N)) {
- SDNode *Result = Emit_3(N, PPC::VMRGHH, MVT::v16i8);
- return Result;
}
+ case 67: { // Predicate_maskimm32
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrghw_shuffle>>
- // Emits: (VMRGHW:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vmrghw_shuffle(N)) {
- SDNode *Result = Emit_3(N, PPC::VMRGHW, MVT::v16i8);
- return Result;
- }
+ // maskImm predicate - True if immediate is a run of ones.
+ unsigned mb, me;
+ if (N->getValueType(0) == MVT::i32)
+ return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
+ else
+ return false;
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrglb_shuffle>>
- // Emits: (VMRGLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vmrglb_shuffle(N)) {
- SDNode *Result = Emit_3(N, PPC::VMRGLB, MVT::v16i8);
- return Result;
}
+ case 68: { // Predicate_vspltb_shuffle
+ SDNode *N = Node;
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrglh_shuffle>>
- // Emits: (VMRGLH:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vmrglh_shuffle(N)) {
- SDNode *Result = Emit_3(N, PPC::VMRGLH, MVT::v16i8);
- return Result;
- }
+ return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrglw_shuffle>>
- // Emits: (VMRGLW:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vmrglw_shuffle(N)) {
- SDNode *Result = Emit_3(N, PPC::VMRGLW, MVT::v16i8);
- return Result;
}
+ case 69: { // Predicate_vsplth_shuffle
+ SDNode *N = Node;
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vpkuhum_shuffle>>
- // Emits: (VPKUHUM:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vpkuhum_shuffle(N)) {
- SDNode *Result = Emit_3(N, PPC::VPKUHUM, MVT::v16i8);
- return Result;
- }
+ return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
- // Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vpkuwum_shuffle>>
- // Emits: (VPKUWUM:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vpkuwum_shuffle(N)) {
- SDNode *Result = Emit_3(N, PPC::VPKUWUM, MVT::v16i8);
- return Result;
}
+ case 70: { // Predicate_vspltw_shuffle
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_86(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N01);
-}
-DISABLE_INLINE SDNode *Emit_87(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N1);
-}
-DISABLE_INLINE SDNode *Emit_88(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N0);
-}
-SDNode *Select_ISD_XOR_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (xor:i32 (and:i32 GPRC:i32:$rS, GPRC:i32:$rB), (imm:i32)<<P:Predicate_immAllOnes>>)
- // Emits: (NAND:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_86(N, PPC::NAND, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (xor:i32 (or:i32 GPRC:i32:$rS, GPRC:i32:$rB), (imm:i32)<<P:Predicate_immAllOnes>>)
- // Emits: (NOR:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::OR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_86(N, PPC::NOR, MVT::i32);
- return Result;
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
-
- // Pattern: (xor:i32 (xor:i32 GPRC:i32:$rS, GPRC:i32:$rB), (imm:i32)<<P:Predicate_immAllOnes>>)
- // Emits: (EQV:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_86(N, PPC::EQV, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (xor:i32 (xor:i32 GPRC:i32:$rS, (imm:i32)<<P:Predicate_immAllOnes>>), GPRC:i32:$rB)
- // Emits: (EQV:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_87(N, PPC::EQV, MVT::i32);
- return Result;
- }
- }
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (xor:i32 GPRC:i32:$rB, (xor:i32 GPRC:i32:$rS, (imm:i32)<<P:Predicate_immAllOnes>>))
- // Emits: (EQV:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_88(N, PPC::EQV, MVT::i32);
- return Result;
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (xor:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
- // Emits: (XORI:i32 GPRC:i32:$src1, (LO16:i32 (imm:i32):$src2))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_immZExt16(N1.getNode())) {
- SDNode *Result = Emit_13(N, PPC::XORI, MVT::i32);
- return Result;
- }
-
- // Pattern: (xor:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_imm16ShiftedZExt>><<X:HI16>>:$src2)
- // Emits: (XORIS:i32 GPRC:i32:$src1, (HI16:i32 (imm:i32):$src2))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm16ShiftedZExt(N1.getNode())) {
- SDNode *Result = Emit_1(N, PPC::XORIS, MVT::i32);
- return Result;
- }
-
- // Pattern: (xor:i32 GPRC:i32:$in, (imm:i32)<<P:Predicate_immAllOnes>>)
- // Emits: (NOR:i32 GPRC:i32:$in, GPRC:i32:$in)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_85(N, PPC::NOR, MVT::i32);
- return Result;
- }
-
- // Pattern: (xor:i32 GPRC:i32:$in, (imm:i32):$imm)
- // Emits: (XORIS:i32 (XORI:i32 GPRC:i32:$in, (LO16:i32 (imm:i32):$imm)), (HI16:i32 (imm:i32):$imm))
- // Pattern complexity = 6 cost = 2 size = 0
- SDNode *Result = Emit_60(N, PPC::XORI, PPC::XORIS, MVT::i32, MVT::i32);
- return Result;
- }
- }
+ return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
- // Pattern: (xor:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Emits: (XOR:i32 GPRC:i32:$rS, GPRC:i32:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::XOR, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_XOR_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (xor:i64 (and:i64 G8RC:i64:$rS, G8RC:i64:$rB), (imm:i64)<<P:Predicate_immAllOnes>>)
- // Emits: (NAND8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::AND) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_86(N, PPC::NAND8, MVT::i64);
- return Result;
- }
- }
-
- // Pattern: (xor:i64 (or:i64 G8RC:i64:$rS, G8RC:i64:$rB), (imm:i64)<<P:Predicate_immAllOnes>>)
- // Emits: (NOR8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::OR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_86(N, PPC::NOR8, MVT::i64);
- return Result;
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
-
- // Pattern: (xor:i64 (xor:i64 G8RC:i64:$rS, G8RC:i64:$rB), (imm:i64)<<P:Predicate_immAllOnes>>)
- // Emits: (EQV8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_86(N, PPC::EQV8, MVT::i64);
- return Result;
- }
- }
-
- // Pattern: (xor:i64 (xor:i64 G8RC:i64:$rS, (imm:i64)<<P:Predicate_immAllOnes>>), G8RC:i64:$rB)
- // Emits: (EQV8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N01.getNode())) {
- SDNode *Result = Emit_87(N, PPC::EQV8, MVT::i64);
- return Result;
- }
- }
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (xor:i64 G8RC:i64:$rB, (xor:i64 G8RC:i64:$rS, (imm:i64)<<P:Predicate_immAllOnes>>))
- // Emits: (EQV8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDNode *Result = Emit_88(N, PPC::EQV8, MVT::i64);
- return Result;
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (xor:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
- // Emits: (XORI8:i64 G8RC:i64:$src1, (LO16:i32 (imm:i64):$src2))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_immZExt16(N1.getNode())) {
- SDNode *Result = Emit_15(N, PPC::XORI8, MVT::i64);
- return Result;
- }
-
- // Pattern: (xor:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_imm16ShiftedZExt>><<X:HI16>>:$src2)
- // Emits: (XORIS8:i64 G8RC:i64:$src1, (HI16:i32 (imm:i64):$src2))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_imm16ShiftedZExt(N1.getNode())) {
- SDNode *Result = Emit_7(N, PPC::XORIS8, MVT::i64);
- return Result;
- }
- }
}
+ case 71: { // Predicate_vsldoi_unary_shuffle
+ SDNode *N = Node;
- // Pattern: (xor:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Emits: (XOR8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::XOR8, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_89(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N11);
-}
-DISABLE_INLINE SDNode *Emit_90(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N1);
-}
-SDNode *Select_ISD_XOR_v4i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::OR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (xor:v4i32 (or:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB), (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)
- // Emits: (VNOR:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N1.getNode())) {
- SDNode *Result = Emit_86(N, PPC::VNOR, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (xor:v4i32 (or:v4i32 VRRC:v4i32:$A, VRRC:v4i32:$B), (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)
- // Emits: (VNOR:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N1.getNode())) {
- SDNode *Result = Emit_86(N, PPC::VNOR, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, (or:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB))
- // Emits: (VNOR:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N0.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::OR) {
- SDNode *Result = Emit_89(N, PPC::VNOR, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, (or:v4i32 VRRC:v4i32:$A, VRRC:v4i32:$B))
- // Emits: (VNOR:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
- // Pattern complexity = 10 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N0.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::OR) {
- SDNode *Result = Emit_89(N, PPC::VNOR, MVT::v4i32);
- return Result;
- }
- }
- {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (xor:v4i32 VRRC:v4i32:$vA, (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)
- // Emits: (VNOR:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N1.getNode())) {
- SDNode *Result = Emit_85(N, PPC::VNOR, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (xor:v4i32 VRRC:v4i32:$vA, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)
- // Emits: (VNOR:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N1.getNode())) {
- SDNode *Result = Emit_85(N, PPC::VNOR, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, VRRC:v4i32:$vA)
- // Emits: (VNOR:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N0.getNode())) {
- SDNode *Result = Emit_90(N, PPC::VNOR, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, VRRC:v4i32:$vA)
- // Emits: (VNOR:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
- // Pattern complexity = 7 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N0.getNode())) {
- SDNode *Result = Emit_90(N, PPC::VNOR, MVT::v4i32);
- return Result;
- }
- }
+ return PPC::isVSLDOIShuffleMask(N, true) != -1;
- // Pattern: (xor:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Emits: (VXOR:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_3(N, PPC::VXOR, MVT::v4i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_91(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, N0), 0);
- SDValue Tmp3 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0x20ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, Tmp3, Tmp4);
-}
-SDNode *Select_ISD_ZERO_EXTEND_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_91(N, PPC::OR4To8, PPC::RLDICL, MVT::i64, MVT::i64);
- return Result;
}
+ case 72: { // Predicate_vpkuwum_unary_shuffle
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_92(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_PPCISD_BCTRL_Darwin(SDNode *N) {
-
- // Pattern: (PPCbctrl_Darwin:isVoid)
- // Emits: (BCTRL_Darwin:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!PPCSubTarget.isPPC64())) {
- SDNode *Result = Emit_92(N, PPC::BCTRL_Darwin, 0);
- return Result;
- }
+ return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
- // Pattern: (PPCbctrl_Darwin:isVoid)
- // Emits: (BCTRL8_Darwin:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((PPCSubTarget.isPPC64())) {
- SDNode *Result = Emit_92(N, PPC::BCTRL8_Darwin, 0);
- return Result;
}
+ case 73: { // Predicate_vpkuhum_unary_shuffle
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_BCTRL_SVR4(SDNode *N) {
-
- // Pattern: (PPCbctrl_SVR4:isVoid)
- // Emits: (BCTRL_SVR4:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!PPCSubTarget.isPPC64())) {
- SDNode *Result = Emit_92(N, PPC::BCTRL_SVR4, 0);
- return Result;
- }
+ return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
- // Pattern: (PPCbctrl_SVR4:isVoid)
- // Emits: (BCTRL8_ELF:isVoid)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((PPCSubTarget.isPPC64())) {
- SDNode *Result = Emit_92(N, PPC::BCTRL8_ELF, 0);
- return Result;
}
+ case 74: { // Predicate_vmrglb_unary_shuffle
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_93(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(Tmp0);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_94(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(Tmp0);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_95(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(N1);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_PPCISD_CALL_Darwin(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (PPCcall_Darwin:isVoid (imm:i32):$func)
- // Emits: (BLA_Darwin:isVoid (imm:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_93(N, PPC::BLA_Darwin, 1);
- return Result;
- }
-
- // Pattern: (PPCcall_Darwin:isVoid (imm:i64):$func)
- // Emits: (BLA8_Darwin:isVoid (imm:i64):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_94(N, PPC::BLA8_Darwin, 1);
- return Result;
- }
- }
+ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
- // Pattern: (PPCcall_Darwin:isVoid (tglobaladdr:i64):$dst)
- // Emits: (BL8_Darwin:isVoid (tglobaladdr:iPTR):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_95(N, PPC::BL8_Darwin, 1);
- return Result;
}
+ case 75: { // Predicate_vmrglh_unary_shuffle
+ SDNode *N = Node;
- // Pattern: (PPCcall_Darwin:isVoid (texternalsym:i64):$dst)
- // Emits: (BL8_Darwin:isVoid (texternalsym:iPTR):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_95(N, PPC::BL8_Darwin, 1);
- return Result;
- }
+ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
- // Pattern: (PPCcall_Darwin:isVoid (tglobaladdr:i32):$dst)
- // Emits: (BL_Darwin:isVoid (tglobaladdr:iPTR):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_95(N, PPC::BL_Darwin, 1);
- return Result;
}
+ case 76: { // Predicate_vmrglw_unary_shuffle
+ SDNode *N = Node;
- // Pattern: (PPCcall_Darwin:isVoid (texternalsym:i32):$dst)
- // Emits: (BL_Darwin:isVoid (texternalsym:iPTR):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_95(N, PPC::BL_Darwin, 1);
- return Result;
- }
+ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_CALL_SVR4(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (PPCcall_SVR4:isVoid (imm:i32):$func)
- // Emits: (BLA_SVR4:isVoid (imm:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_93(N, PPC::BLA_SVR4, 1);
- return Result;
- }
-
- // Pattern: (PPCcall_SVR4:isVoid (imm:i64):$func)
- // Emits: (BLA8_ELF:isVoid (imm:i64):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_94(N, PPC::BLA8_ELF, 1);
- return Result;
- }
}
+ case 77: { // Predicate_vmrghb_unary_shuffle
+ SDNode *N = Node;
- // Pattern: (PPCcall_SVR4:isVoid (tglobaladdr:i64):$dst)
- // Emits: (BL8_ELF:isVoid (tglobaladdr:iPTR):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_95(N, PPC::BL8_ELF, 1);
- return Result;
- }
+ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
- // Pattern: (PPCcall_SVR4:isVoid (texternalsym:i64):$dst)
- // Emits: (BL8_ELF:isVoid (texternalsym:iPTR):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_95(N, PPC::BL8_ELF, 1);
- return Result;
}
+ case 78: { // Predicate_vmrghh_unary_shuffle
+ SDNode *N = Node;
- // Pattern: (PPCcall_SVR4:isVoid (tglobaladdr:i32):$dst)
- // Emits: (BL_SVR4:isVoid (tglobaladdr:iPTR):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_95(N, PPC::BL_SVR4, 1);
- return Result;
- }
+ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
- // Pattern: (PPCcall_SVR4:isVoid (texternalsym:i32):$dst)
- // Emits: (BL_SVR4:isVoid (texternalsym:iPTR):$dst)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_95(N, PPC::BL_SVR4, 1);
- return Result;
}
+ case 79: { // Predicate_vmrghw_unary_shuffle
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_96(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 4);
-}
-SDNode *Select_PPCISD_DYNALLOC_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_96(N, PPC::DYNALLOC, MVT::i32, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
+ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_DYNALLOC_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i64 &&
- N2.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_96(N, PPC::DYNALLOC8, MVT::i64, CPTmpN2_0, CPTmpN2_1);
- return Result;
}
+ case 80: { // Predicate_vsldoi_shuffle
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_EXTSW_32_i32(SDNode *N) {
- SDNode *Result = Emit_29(N, PPC::EXTSW_32, MVT::i32);
- return Result;
-}
-
-SDNode *Select_PPCISD_FADDRTZ_f64(SDNode *N) {
- SDNode *Result = Emit_11(N, PPC::FADDrtz, MVT::f64);
- return Result;
-}
-
-SDNode *Select_PPCISD_FCFID_f64(SDNode *N) {
- SDNode *Result = Emit_29(N, PPC::FCFID, MVT::f64);
- return Result;
-}
-
-SDNode *Select_PPCISD_FCTIDZ_f64(SDNode *N) {
- SDNode *Result = Emit_29(N, PPC::FCTIDZ, MVT::f64);
- return Result;
-}
-
-SDNode *Select_PPCISD_FCTIWZ_f64(SDNode *N) {
- SDNode *Result = Emit_29(N, PPC::FCTIWZ, MVT::f64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_97(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, N2);
-}
-SDNode *Select_PPCISD_FSEL_f32(SDNode *N) {
- SDNode *Result = Emit_97(N, PPC::FSELS, MVT::f32);
- return Result;
-}
-
-SDNode *Select_PPCISD_FSEL_f64(SDNode *N) {
- SDNode *Result = Emit_97(N, PPC::FSELD, MVT::f64);
- return Result;
-}
-
-SDNode *Select_PPCISD_Hi_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (PPChi:i32 (tglobaladdr:i32):$in, 0:i32)
- // Emits: (LIS:i32 (tglobaladdr:i32):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LIS, MVT::i32);
- return Result;
- }
- }
- }
+ return PPC::isVSLDOIShuffleMask(N, false) != -1;
- // Pattern: (PPChi:i32 (tconstpool:i32):$in, 0:i32)
- // Emits: (LIS:i32 (tconstpool:i32):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LIS, MVT::i32);
- return Result;
- }
- }
}
+ case 81: { // Predicate_vmrghb_shuffle
+ SDNode *N = Node;
- // Pattern: (PPChi:i32 (tjumptable:i32):$in, 0:i32)
- // Emits: (LIS:i32 (tjumptable:i32):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LIS, MVT::i32);
- return Result;
- }
- }
- }
+ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
- // Pattern: (PPChi:i32 (tblockaddress:i32):$in, 0:i32)
- // Emits: (LIS:i32 (tblockaddress:i32):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LIS, MVT::i32);
- return Result;
- }
- }
}
+ case 82: { // Predicate_vmrghh_shuffle
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_Hi_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (PPChi:i64 (tglobaladdr:i64):$in, 0:i64)
- // Emits: (LIS8:i64 (tglobaladdr:i64):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LIS8, MVT::i64);
- return Result;
- }
- }
- }
+ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
- // Pattern: (PPChi:i64 (tconstpool:i64):$in, 0:i64)
- // Emits: (LIS8:i64 (tconstpool:i64):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LIS8, MVT::i64);
- return Result;
- }
- }
}
+ case 83: { // Predicate_vmrghw_shuffle
+ SDNode *N = Node;
- // Pattern: (PPChi:i64 (tjumptable:i64):$in, 0:i64)
- // Emits: (LIS8:i64 (tjumptable:i64):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LIS8, MVT::i64);
- return Result;
- }
- }
- }
+ return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
- // Pattern: (PPChi:i64 (tblockaddress:i64):$in, 0:i64)
- // Emits: (LIS8:i64 (tblockaddress:i64):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LIS8, MVT::i64);
- return Result;
- }
- }
}
+ case 84: { // Predicate_vmrglb_shuffle
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
-DISABLE_INLINE SDNode *Emit_98(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain);
-}
-SDNode *Select_PPCISD_LARX_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_98(N, PPC::LWARX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
}
+ case 85: { // Predicate_vmrglh_shuffle
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_LARX_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDNode *Result = Emit_98(N, PPC::LDARX, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
+ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_99(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain);
-}
-SDNode *Select_PPCISD_LBRX_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDValue N2 = N->getOperand(2);
-
- // Pattern: (PPClbrx:i32 xoaddr:iPTR:$src, i16:Other)
- // Emits: (LHBRX:i32 xoaddr:iPTR:$src)
- // Pattern complexity = 12 cost = 1 size = 0
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_99(N, PPC::LHBRX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
-
- // Pattern: (PPClbrx:i32 xoaddr:iPTR:$src, i32:Other)
- // Emits: (LWBRX:i32 xoaddr:iPTR:$src)
- // Pattern complexity = 12 cost = 1 size = 0
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_99(N, PPC::LWBRX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
}
+ case 86: { // Predicate_vmrglw_shuffle
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
-DISABLE_INLINE SDNode *Emit_100(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
- Chain = SDValue(ResNode, 1);
- InFlag = SDValue(ResNode, 2);
- const SDValue Froms[] = {
- SDValue(N, 2),
- SDValue(N, 1)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_PPCISD_LOAD_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
-
- // Pattern: (PPCload:i64 ixaddr:iPTR:$src)
- // Emits: (LD:i64 ixaddr:iPTR:$src)
- // Pattern complexity = 12 cost = 1 size = 0
- if (SelectAddrImmShift(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_100(N, PPC::LD, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
}
+ case 87: { // Predicate_vpkuhum_shuffle
+ SDNode *N = Node;
- // Pattern: (PPCload:i64 xaddr:iPTR:$src)
- // Emits: (LDX:i64 xaddr:iPTR:$src)
- // Pattern complexity = 12 cost = 1 size = 0
- if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1) &&
- N1.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_100(N, PPC::LDX, MVT::i64, CPTmpN1_0, CPTmpN1_1);
- return Result;
- }
+ return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_101(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, N1, Chain, InFlag);
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_PPCISD_LOAD_TOC(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_101(N, PPC::LDinto_toc);
- return Result;
}
+ case 88: { // Predicate_vpkuwum_shuffle
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_Lo_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (PPClo:i32 (tglobaladdr:i32):$in, 0:i32)
- // Emits: (LI:i32 (tglobaladdr:i32):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LI, MVT::i32);
- return Result;
- }
- }
- }
+ return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
- // Pattern: (PPClo:i32 (tconstpool:i32):$in, 0:i32)
- // Emits: (LI:i32 (tconstpool:i32):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LI, MVT::i32);
- return Result;
- }
- }
}
+ case 89: { // Predicate_vecspltisb
+ SDNode *N = Node;
- // Pattern: (PPClo:i32 (tjumptable:i32):$in, 0:i32)
- // Emits: (LI:i32 (tjumptable:i32):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LI, MVT::i32);
- return Result;
- }
- }
- }
+ return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
- // Pattern: (PPClo:i32 (tblockaddress:i32):$in, 0:i32)
- // Emits: (LI:i32 (tblockaddress:i32):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LI, MVT::i32);
- return Result;
- }
- }
}
+ case 90: { // Predicate_vecspltish
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_Lo_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (PPClo:i64 (tglobaladdr:i64):$in, 0:i64)
- // Emits: (LI8:i64 (tglobaladdr:i64):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LI8, MVT::i64);
- return Result;
- }
- }
- }
+ return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
- // Pattern: (PPClo:i64 (tconstpool:i64):$in, 0:i64)
- // Emits: (LI8:i64 (tconstpool:i64):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LI8, MVT::i64);
- return Result;
- }
- }
}
+ case 91: { // Predicate_vecspltisw
+ SDNode *N = Node;
- // Pattern: (PPClo:i64 (tjumptable:i64):$in, 0:i64)
- // Emits: (LI8:i64 (tjumptable:i64):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LI8, MVT::i64);
- return Result;
- }
- }
- }
+ return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
- // Pattern: (PPClo:i64 (tblockaddress:i64):$in, 0:i64)
- // Emits: (LI8:i64 (tblockaddress:i64):$in)
- // Pattern complexity = 11 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_67(N, PPC::LI8, MVT::i64);
- return Result;
- }
- }
}
+ case 92: { // Predicate_immAllZerosV
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_102(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_PPCISD_MFFS_f64(SDNode *N) {
- SDNode *Result = Emit_102(N, PPC::MFFS, MVT::f64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_103(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- SDValue Ops0[] = { N1, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 3 : 2);
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_PPCISD_MTCTR(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (PPCmtctr:isVoid GPRC:i32:$rS)
- // Emits: (MTCTR:isVoid GPRC:i32:$rS)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_103(N, PPC::MTCTR);
- return Result;
- }
+ return ISD::isBuildVectorAllZeros(N);
- // Pattern: (PPCmtctr:isVoid G8RC:i64:$rS)
- // Emits: (MTCTR8:isVoid G8RC:i64:$rS)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_103(N, PPC::MTCTR8);
- return Result;
}
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_104(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDValue InFlag = N->getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Tmp0, InFlag);
- InFlag = SDValue(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-SDNode *Select_PPCISD_MTFSB0(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_104(N, PPC::MTFSB0);
- return Result;
}
-
- CannotYetSelect(N);
- return NULL;
}
-SDNode *Select_PPCISD_MTFSB1(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_104(N, PPC::MTFSB1);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_105(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDValue InFlag = N->getOperand(3);
- SDValue Ops0[] = { Tmp0, N1, N2, InFlag };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_PPCISD_MTFSF_f64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_105(N, PPC::MTFSF, MVT::f64);
- return Result;
- }
+bool CheckComplexPattern(SDNode *Root, SDValue N,
+ unsigned PatternNo, SmallVectorImpl<SDValue> &Result) {
+ switch (PatternNo) {
+ default: assert(0 && "Invalid pattern # in table?");
+ case 0:
+ Result.resize(Result.size()+2);
+ return SelectAddrIdxOnly(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 1:
+ Result.resize(Result.size()+2);
+ return SelectAddrImm(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 2:
+ Result.resize(Result.size()+2);
+ return SelectAddrIdx(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 3:
+ Result.resize(Result.size()+2);
+ return SelectAddrImmShift(Root, N, Result[Result.size()-2], Result[Result.size()-1]);
+ case 4:
+ Result.resize(Result.size()+1);
+ return SelectAddrImmOffs(Root, N, Result[Result.size()-1]);
}
-
- CannotYetSelect(N);
- return NULL;
}
-DISABLE_INLINE SDNode *Emit_106(SDNode *N, unsigned Opc0) {
- SDValue InFlag = N->getOperand(0);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, InFlag);
- InFlag = SDValue(ResNode, 0);
- ReplaceUses(SDValue(N, 0), InFlag);
- return ResNode;
-}
-SDNode *Select_PPCISD_NOP(SDNode *N) {
- SDNode *Result = Emit_106(N, PPC::NOP);
- return Result;
-}
+SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
+ switch (XFormNo) {
+ default: assert(0 && "Invalid xform # in table?");
+ case 0: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
-DISABLE_INLINE SDNode *Emit_107(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SDValue Tmp0 = CurDAG->getTargetConstant(0x14ULL, MVT::i32);
- SDValue Tmp1 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- SDValue Ops0[] = { Tmp0, Tmp1, Chain, InFlag };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, HasInFlag ? 4 : 3);
-}
-SDNode *Select_PPCISD_RET_FLAG(SDNode *N) {
- SDNode *Result = Emit_107(N, PPC::BLR);
- return Result;
-}
+ // Transformation function: shift the immediate value down into the low bits.
+ return getI32Imm((unsigned)N->getZExtValue() >> 16);
-SDNode *Select_PPCISD_SHL_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, PPC::SLW, MVT::i32);
- return Result;
}
+ case 1: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ // Transformation function: get the low 16 bits.
+ return getI32Imm((unsigned short)N->getZExtValue());
-SDNode *Select_PPCISD_SHL_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, PPC::SLD, MVT::i64);
- return Result;
}
+ case 2: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ // Transformation function: shift the immediate value down into the low bits.
+ signed int Val = N->getZExtValue();
+ return getI32Imm((Val - (signed short)Val) >> 16);
-SDNode *Select_PPCISD_SRA_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, PPC::SRAW, MVT::i32);
- return Result;
}
+ case 3: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ // Transformation function: get the start bit of a mask
+ unsigned mb = 0, me;
+ (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
+ return getI32Imm(mb);
-SDNode *Select_PPCISD_SRA_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, PPC::SRAD, MVT::i64);
- return Result;
}
+ case 4: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ // Transformation function: get the end bit of a mask
+ unsigned mb, me = 0;
+ (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
+ return getI32Imm(me);
-SDNode *Select_PPCISD_SRL_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, PPC::SRW, MVT::i32);
- return Result;
}
+ case 5: {
+ SDNode *N = V.getNode();
- CannotYetSelect(N);
- return NULL;
-}
+ return getI32Imm(PPC::getVSPLTImmediate(N, 1));
-SDNode *Select_PPCISD_SRL_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_3(N, PPC::SRD, MVT::i64);
- return Result;
}
+ case 6: {
+ SDNode *N = V.getNode();
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_108(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
-}
-SDNode *Select_PPCISD_STBRX(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDValue N3 = N->getOperand(3);
-
- // Pattern: (PPCstbrx:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst, i16:Other)
- // Emits: (STHBRX:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
- // Pattern complexity = 12 cost = 1 size = 0
- if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_108(N, PPC::STHBRX, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
-
- // Pattern: (PPCstbrx:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst, i32:Other)
- // Emits: (STWBRX:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
- // Pattern complexity = 12 cost = 1 size = 0
- if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_108(N, PPC::STWBRX, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
- }
+ return getI32Imm(PPC::getVSPLTImmediate(N, 2));
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_109(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
-}
-SDNode *Select_PPCISD_STCX(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
-
- // Pattern: (PPCstcx:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
- // Emits: (STWCX:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_109(N, PPC::STWCX, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
-
- // Pattern: (PPCstcx:isVoid G8RC:i64:$rS, xoaddr:iPTR:$dst)
- // Emits: (STDCX:isVoid G8RC:i64:$rS, xoaddr:iPTR:$dst)
- // Pattern complexity = 12 cost = 1 size = 0
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_109(N, PPC::STDCX, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
}
+ case 7: {
+ SDNode *N = V.getNode();
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_STD_32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
-
- // Pattern: (PPCstd_32:isVoid GPRC:i32:$rT, ixaddr:iPTR:$dst)
- // Emits: (STD_32:isVoid GPRC:i32:$rT, ixaddr:iPTR:$dst)
- // Pattern complexity = 12 cost = 1 size = 0
- if (SelectAddrImmShift(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_109(N, PPC::STD_32, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
+ return getI32Imm(PPC::getVSPLTImmediate(N, 4));
- // Pattern: (PPCstd_32:isVoid GPRC:i32:$rT, xaddr:iPTR:$dst)
- // Emits: (STDX_32:isVoid GPRC:i32:$rT, xaddr:iPTR:$dst)
- // Pattern complexity = 12 cost = 1 size = 0
- if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_109(N, PPC::STDX_32, CPTmpN2_0, CPTmpN2_1);
- return Result;
}
+ case 8: {
+ SDNode *N = V.getNode();
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_STFIWX(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDNode *Result = Emit_109(N, PPC::STFIWX, CPTmpN2_0, CPTmpN2_1);
- return Result;
- }
+ return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_110(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(Tmp0);
- Ops0.push_back(Tmp1);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
-}
-DISABLE_INLINE SDNode *Emit_111(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(Tmp0);
- Ops0.push_back(Tmp1);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
-}
-DISABLE_INLINE SDNode *Emit_112(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(N1);
- Ops0.push_back(Tmp1);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
-}
-SDNode *Select_PPCISD_TC_RETURN(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (PPCtc_return:isVoid (imm:i32):$func, (imm:i32):$offset)
- // Emits: (TCRETURNai:isVoid (imm:i32):$func, (imm:i32):$offset)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_110(N, PPC::TCRETURNai, 2);
- return Result;
- }
-
- // Pattern: (PPCtc_return:isVoid (imm:i64):$func, (imm:i32):$offset)
- // Emits: (TCRETURNai8:isVoid (imm:i64):$func, (imm:i32):$offset)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_111(N, PPC::TCRETURNai8, 2);
- return Result;
- }
- }
}
+ case 9: {
+ SDNode *N = V.getNode();
- // Pattern: (PPCtc_return:isVoid (tglobaladdr:i64):$dst, (imm:i32):$imm)
- // Emits: (TCRETURNdi8:isVoid (tglobaladdr:iPTR):$dst, (imm:i32):$imm)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_112(N, PPC::TCRETURNdi8, 2);
- return Result;
- }
- }
+ return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
- // Pattern: (PPCtc_return:isVoid (texternalsym:i64):$dst, (imm:i32):$imm)
- // Emits: (TCRETURNdi8:isVoid (texternalsym:iPTR):$dst, (imm:i32):$imm)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_112(N, PPC::TCRETURNdi8, 2);
- return Result;
- }
}
+ case 10: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (PPCtc_return:isVoid (tglobaladdr:i32):$dst, (imm:i32):$imm)
- // Emits: (TCRETURNdi:isVoid (tglobaladdr:iPTR):$dst, (imm:i32):$imm)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_112(N, PPC::TCRETURNdi, 2);
- return Result;
- }
- }
+ // Transformation function: 31 - imm
+ return getI32Imm(31 - N->getZExtValue());
- // Pattern: (PPCtc_return:isVoid (texternalsym:i32):$dst, (imm:i32):$imm)
- // Emits: (TCRETURNdi:isVoid (texternalsym:iPTR):$dst, (imm:i32):$imm)
- // Pattern complexity = 9 cost = 1 size = 0
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_112(N, PPC::TCRETURNdi, 2);
- return Result;
- }
- }
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (PPCtc_return:isVoid CTRRC8:i64:$dst, (imm:i32):$imm)
- // Emits: (TCRETURNri8:isVoid CTRRC8:i64:$dst, (imm:i32):$imm)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_112(N, PPC::TCRETURNri8, 2);
- return Result;
- }
-
- // Pattern: (PPCtc_return:isVoid CTRRC:i32:$dst, (imm:i32):$imm)
- // Emits: (TCRETURNri:isVoid CTRRC:i32:$dst, (imm:i32):$imm)
- // Pattern complexity = 6 cost = 1 size = 0
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_112(N, PPC::TCRETURNri, 2);
- return Result;
- }
}
+ case 11: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
+ // Transformation function: 63 - imm
+ return getI32Imm(63 - N->getZExtValue());
-SDNode *Select_PPCISD_TOC_ENTRY_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_3(N, PPC::LDtoc, MVT::i64);
- return Result;
}
+ case 12: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_113(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue InFlag = N->getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Chain, InFlag);
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_PPCISD_TOC_RESTORE(SDNode *N) {
- SDNode *Result = Emit_113(N, PPC::LDtoc_restore);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_114(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1);
-}
-SDNode *Select_PPCISD_VCMP_v16i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (PPCvcmp:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, 6:i32)
- // Emits: (VCMPEQUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_114(N, PPC::VCMPEQUB, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (PPCvcmp:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, 774:i32)
- // Emits: (VCMPGTSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(774)) {
- SDNode *Result = Emit_114(N, PPC::VCMPGTSB, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (PPCvcmp:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, 518:i32)
- // Emits: (VCMPGTUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(518)) {
- SDNode *Result = Emit_114(N, PPC::VCMPGTUB, MVT::v16i8);
- return Result;
- }
- }
+ // Transformation function: 32 - imm
+ return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_VCMP_v8i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (PPCvcmp:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, 70:i32)
- // Emits: (VCMPEQUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(70)) {
- SDNode *Result = Emit_114(N, PPC::VCMPEQUH, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (PPCvcmp:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, 838:i32)
- // Emits: (VCMPGTSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(838)) {
- SDNode *Result = Emit_114(N, PPC::VCMPGTSH, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (PPCvcmp:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, 582:i32)
- // Emits: (VCMPGTUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(582)) {
- SDNode *Result = Emit_114(N, PPC::VCMPGTUH, MVT::v8i16);
- return Result;
- }
}
+ case 13: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_VCMP_v4i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (PPCvcmp:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, 134:i32)
- // Emits: (VCMPEQUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(134)) {
- SDNode *Result = Emit_114(N, PPC::VCMPEQUW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (PPCvcmp:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, 902:i32)
- // Emits: (VCMPGTSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(902)) {
- SDNode *Result = Emit_114(N, PPC::VCMPGTSW, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (PPCvcmp:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, 646:i32)
- // Emits: (VCMPGTUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(646)) {
- SDNode *Result = Emit_114(N, PPC::VCMPGTUW, MVT::v4i32);
- return Result;
- }
- }
+ // Transformation function: 64 - imm
+ return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_VCMP_v4f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (PPCvcmp:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 966:i32)
- // Emits: (VCMPBFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(966)) {
- SDNode *Result = Emit_114(N, PPC::VCMPBFP, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (PPCvcmp:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 198:i32)
- // Emits: (VCMPEQFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(198)) {
- SDNode *Result = Emit_114(N, PPC::VCMPEQFP, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (PPCvcmp:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 454:i32)
- // Emits: (VCMPGEFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(454)) {
- SDNode *Result = Emit_114(N, PPC::VCMPGEFP, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (PPCvcmp:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 710:i32)
- // Emits: (VCMPGTFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(710)) {
- SDNode *Result = Emit_114(N, PPC::VCMPGTFP, MVT::v4f32);
- return Result;
- }
}
+ case 14: {
+ SDNode *N = V.getNode();
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_115(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, N1);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_PPCISD_VCMPo_v16i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (PPCvcmp_o:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, 6:i32)
- // Emits: (VCMPEQUBo:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_115(N, PPC::VCMPEQUBo, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (PPCvcmp_o:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, 774:i32)
- // Emits: (VCMPGTSBo:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(774)) {
- SDNode *Result = Emit_115(N, PPC::VCMPGTSBo, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (PPCvcmp_o:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, 518:i32)
- // Emits: (VCMPGTUBo:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(518)) {
- SDNode *Result = Emit_115(N, PPC::VCMPGTUBo, MVT::v16i8);
- return Result;
- }
- }
+ return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_VCMPo_v8i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (PPCvcmp_o:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, 70:i32)
- // Emits: (VCMPEQUHo:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(70)) {
- SDNode *Result = Emit_115(N, PPC::VCMPEQUHo, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (PPCvcmp_o:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, 838:i32)
- // Emits: (VCMPGTSHo:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(838)) {
- SDNode *Result = Emit_115(N, PPC::VCMPGTSHo, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (PPCvcmp_o:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, 582:i32)
- // Emits: (VCMPGTUHo:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(582)) {
- SDNode *Result = Emit_115(N, PPC::VCMPGTUHo, MVT::v8i16);
- return Result;
- }
}
+ case 15: {
+ SDNode *N = V.getNode();
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_VCMPo_v4i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (PPCvcmp_o:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, 134:i32)
- // Emits: (VCMPEQUWo:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(134)) {
- SDNode *Result = Emit_115(N, PPC::VCMPEQUWo, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (PPCvcmp_o:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, 902:i32)
- // Emits: (VCMPGTSWo:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(902)) {
- SDNode *Result = Emit_115(N, PPC::VCMPGTSWo, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (PPCvcmp_o:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, 646:i32)
- // Emits: (VCMPGTUWo:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(646)) {
- SDNode *Result = Emit_115(N, PPC::VCMPGTUWo, MVT::v4i32);
- return Result;
- }
- }
+ return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_VCMPo_v4f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (PPCvcmp_o:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 966:i32)
- // Emits: (VCMPBFPo:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(966)) {
- SDNode *Result = Emit_115(N, PPC::VCMPBFPo, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (PPCvcmp_o:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 198:i32)
- // Emits: (VCMPEQFPo:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(198)) {
- SDNode *Result = Emit_115(N, PPC::VCMPEQFPo, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (PPCvcmp_o:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 454:i32)
- // Emits: (VCMPGEFPo:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(454)) {
- SDNode *Result = Emit_115(N, PPC::VCMPGEFPo, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (PPCvcmp_o:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB, 710:i32)
- // Emits: (VCMPGTFPo:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(710)) {
- SDNode *Result = Emit_115(N, PPC::VCMPGTFPo, MVT::v4f32);
- return Result;
- }
}
+ case 16: {
+ SDNode *N = V.getNode();
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_PPCISD_VMADDFP_v4f32(SDNode *N) {
- SDNode *Result = Emit_97(N, PPC::VMADDFP, MVT::v4f32);
- return Result;
-}
-
-SDNode *Select_PPCISD_VNMSUBFP_v4f32(SDNode *N) {
- SDNode *Result = Emit_97(N, PPC::VNMSUBFP, MVT::v4f32);
- return Result;
-}
-
-SDNode *Select_PPCISD_VPERM_v16i8(SDNode *N) {
- SDNode *Result = Emit_97(N, PPC::VPERM, MVT::v16i8);
- return Result;
-}
+ return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
-// The main instruction selector code.
-SDNode *SelectCode(SDNode *N) {
- MVT::SimpleValueType NVT = N->getValueType(0).getSimpleVT().SimpleTy;
- switch (N->getOpcode()) {
- default:
- assert(!N->isMachineOpcode() && "Node already selected!");
- break;
- case ISD::EntryToken: // These nodes remain the same.
- case ISD::BasicBlock:
- case ISD::Register:
- case ISD::HANDLENODE:
- case ISD::TargetConstant:
- case ISD::TargetConstantFP:
- case ISD::TargetConstantPool:
- case ISD::TargetFrameIndex:
- case ISD::TargetExternalSymbol:
- case ISD::TargetBlockAddress:
- case ISD::TargetJumpTable:
- case ISD::TargetGlobalTLSAddress:
- case ISD::TargetGlobalAddress:
- case ISD::TokenFactor:
- case ISD::CopyFromReg:
- case ISD::CopyToReg: {
- return NULL;
- }
- case ISD::AssertSext:
- case ISD::AssertZext: {
- ReplaceUses(SDValue(N, 0), N->getOperand(0));
- return NULL;
- }
- case ISD::INLINEASM: return Select_INLINEASM(N);
- case ISD::EH_LABEL: return Select_EH_LABEL(N);
- case ISD::UNDEF: return Select_UNDEF(N);
- case ISD::ADD: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ADD_i32(N);
- case MVT::i64:
- return Select_ISD_ADD_i64(N);
- case MVT::v16i8:
- return Select_ISD_ADD_v16i8(N);
- case MVT::v8i16:
- return Select_ISD_ADD_v8i16(N);
- case MVT::v4i32:
- return Select_ISD_ADD_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ADDC: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ADDC_i32(N);
- case MVT::i64:
- return Select_ISD_ADDC_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ADDE: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ADDE_i32(N);
- case MVT::i64:
- return Select_ISD_ADDE_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::AND: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_AND_i32(N);
- case MVT::i64:
- return Select_ISD_AND_i64(N);
- case MVT::v4i32:
- return Select_ISD_AND_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ANY_EXTEND: {
- switch (NVT) {
- case MVT::i64:
- return Select_ISD_ANY_EXTEND_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_CMP_SWAP: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_CMP_SWAP_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_CMP_SWAP_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_ADD: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_ADD_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_ADD_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_AND: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_AND_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_AND_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_NAND: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_NAND_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_NAND_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_OR: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_OR_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_OR_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_SUB: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_SUB_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_SUB_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_XOR: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_XOR_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_XOR_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_SWAP: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ATOMIC_SWAP_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_SWAP_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::BIT_CONVERT: {
- switch (NVT) {
- case MVT::v16i8:
- return Select_ISD_BIT_CONVERT_v16i8(N);
- case MVT::v8i16:
- return Select_ISD_BIT_CONVERT_v8i16(N);
- case MVT::v4i32:
- return Select_ISD_BIT_CONVERT_v4i32(N);
- case MVT::v4f32:
- return Select_ISD_BIT_CONVERT_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::BR: {
- return Select_ISD_BR(N);
- break;
- }
- case ISD::BUILD_VECTOR: {
- switch (NVT) {
- case MVT::v16i8:
- return Select_ISD_BUILD_VECTOR_v16i8(N);
- case MVT::v8i16:
- return Select_ISD_BUILD_VECTOR_v8i16(N);
- case MVT::v4i32:
- return Select_ISD_BUILD_VECTOR_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::CALLSEQ_END: {
- return Select_ISD_CALLSEQ_END(N);
- break;
- }
- case ISD::CALLSEQ_START: {
- return Select_ISD_CALLSEQ_START(N);
- break;
- }
- case ISD::CTLZ: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_CTLZ_i32(N);
- case MVT::i64:
- return Select_ISD_CTLZ_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::Constant: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_Constant_i32(N);
- case MVT::i64:
- return Select_ISD_Constant_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FABS: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FABS_f32(N);
- case MVT::f64:
- return Select_ISD_FABS_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FADD: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FADD_f32(N);
- case MVT::f64:
- return Select_ISD_FADD_f64(N);
- case MVT::v4f32:
- return Select_ISD_FADD_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::FDIV: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FDIV_f32(N);
- case MVT::f64:
- return Select_ISD_FDIV_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FMUL: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FMUL_f32(N);
- case MVT::f64:
- return Select_ISD_FMUL_f64(N);
- case MVT::v4f32:
- return Select_ISD_FMUL_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::FNEG: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FNEG_f32(N);
- case MVT::f64:
- return Select_ISD_FNEG_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FP_EXTEND: {
- switch (NVT) {
- case MVT::f64:
- return Select_ISD_FP_EXTEND_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FP_ROUND: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FP_ROUND_f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::FSQRT: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FSQRT_f32(N);
- case MVT::f64:
- return Select_ISD_FSQRT_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FSUB: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FSUB_f32(N);
- case MVT::f64:
- return Select_ISD_FSUB_f64(N);
- case MVT::v4f32:
- return Select_ISD_FSUB_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::INTRINSIC_VOID: {
- return Select_ISD_INTRINSIC_VOID(N);
- break;
- }
- case ISD::INTRINSIC_WO_CHAIN: {
- switch (NVT) {
- case MVT::v16i8:
- return Select_ISD_INTRINSIC_WO_CHAIN_v16i8(N);
- case MVT::v8i16:
- return Select_ISD_INTRINSIC_WO_CHAIN_v8i16(N);
- case MVT::v4i32:
- return Select_ISD_INTRINSIC_WO_CHAIN_v4i32(N);
- case MVT::v4f32:
- return Select_ISD_INTRINSIC_WO_CHAIN_v4f32(N);
- default:
- break;
- }
- break;
- }
- case ISD::INTRINSIC_W_CHAIN: {
- switch (NVT) {
- case MVT::v16i8:
- return Select_ISD_INTRINSIC_W_CHAIN_v16i8(N);
- case MVT::v8i16:
- return Select_ISD_INTRINSIC_W_CHAIN_v8i16(N);
- case MVT::v4i32:
- return Select_ISD_INTRINSIC_W_CHAIN_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::LOAD: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_LOAD_i32(N);
- case MVT::i64:
- return Select_ISD_LOAD_i64(N);
- case MVT::f32:
- return Select_ISD_LOAD_f32(N);
- case MVT::f64:
- return Select_ISD_LOAD_f64(N);
- case MVT::v4i32:
- return Select_ISD_LOAD_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::MEMBARRIER: {
- return Select_ISD_MEMBARRIER(N);
- break;
- }
- case ISD::MUL: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_MUL_i32(N);
- case MVT::i64:
- return Select_ISD_MUL_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::MULHS: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_MULHS_i32(N);
- case MVT::i64:
- return Select_ISD_MULHS_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::MULHU: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_MULHU_i32(N);
- case MVT::i64:
- return Select_ISD_MULHU_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::OR: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_OR_i32(N);
- case MVT::i64:
- return Select_ISD_OR_i64(N);
- case MVT::v4i32:
- return Select_ISD_OR_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ROTL: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ROTL_i32(N);
- case MVT::i64:
- return Select_ISD_ROTL_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SDIV: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SDIV_i32(N);
- case MVT::i64:
- return Select_ISD_SDIV_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SHL: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SHL_i32(N);
- case MVT::i64:
- return Select_ISD_SHL_i64(N);
- case MVT::v16i8:
- return Select_ISD_SHL_v16i8(N);
- case MVT::v8i16:
- return Select_ISD_SHL_v8i16(N);
- case MVT::v4i32:
- return Select_ISD_SHL_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::SIGN_EXTEND: {
- switch (NVT) {
- case MVT::i64:
- return Select_ISD_SIGN_EXTEND_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SIGN_EXTEND_INREG: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SIGN_EXTEND_INREG_i32(N);
- case MVT::i64:
- return Select_ISD_SIGN_EXTEND_INREG_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SRA: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SRA_i32(N);
- case MVT::i64:
- return Select_ISD_SRA_i64(N);
- case MVT::v16i8:
- return Select_ISD_SRA_v16i8(N);
- case MVT::v8i16:
- return Select_ISD_SRA_v8i16(N);
- case MVT::v4i32:
- return Select_ISD_SRA_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::SRL: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SRL_i32(N);
- case MVT::i64:
- return Select_ISD_SRL_i64(N);
- case MVT::v16i8:
- return Select_ISD_SRL_v16i8(N);
- case MVT::v8i16:
- return Select_ISD_SRL_v8i16(N);
- case MVT::v4i32:
- return Select_ISD_SRL_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::STORE: {
- switch (NVT) {
- default:
- if (TLI.getPointerTy() == NVT)
- return Select_ISD_STORE_iPTR(N);
- return Select_ISD_STORE(N);
- break;
- }
- break;
- }
- case ISD::SUB: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SUB_i32(N);
- case MVT::i64:
- return Select_ISD_SUB_i64(N);
- case MVT::v16i8:
- return Select_ISD_SUB_v16i8(N);
- case MVT::v8i16:
- return Select_ISD_SUB_v8i16(N);
- case MVT::v4i32:
- return Select_ISD_SUB_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::SUBC: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SUBC_i32(N);
- case MVT::i64:
- return Select_ISD_SUBC_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SUBE: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SUBE_i32(N);
- case MVT::i64:
- return Select_ISD_SUBE_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::TRAP: {
- return Select_ISD_TRAP(N);
- break;
- }
- case ISD::TRUNCATE: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_TRUNCATE_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::UDIV: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_UDIV_i32(N);
- case MVT::i64:
- return Select_ISD_UDIV_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::VECTOR_SHUFFLE: {
- switch (NVT) {
- case MVT::v16i8:
- return Select_ISD_VECTOR_SHUFFLE_v16i8(N);
- default:
- break;
- }
- break;
- }
- case ISD::XOR: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_XOR_i32(N);
- case MVT::i64:
- return Select_ISD_XOR_i64(N);
- case MVT::v4i32:
- return Select_ISD_XOR_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::ZERO_EXTEND: {
- switch (NVT) {
- case MVT::i64:
- return Select_ISD_ZERO_EXTEND_i64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::BCTRL_Darwin: {
- return Select_PPCISD_BCTRL_Darwin(N);
- break;
- }
- case PPCISD::BCTRL_SVR4: {
- return Select_PPCISD_BCTRL_SVR4(N);
- break;
- }
- case PPCISD::CALL_Darwin: {
- return Select_PPCISD_CALL_Darwin(N);
- break;
- }
- case PPCISD::CALL_SVR4: {
- return Select_PPCISD_CALL_SVR4(N);
- break;
- }
- case PPCISD::DYNALLOC: {
- switch (NVT) {
- case MVT::i32:
- return Select_PPCISD_DYNALLOC_i32(N);
- case MVT::i64:
- return Select_PPCISD_DYNALLOC_i64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::EXTSW_32: {
- switch (NVT) {
- case MVT::i32:
- return Select_PPCISD_EXTSW_32_i32(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::FADDRTZ: {
- switch (NVT) {
- case MVT::f64:
- return Select_PPCISD_FADDRTZ_f64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::FCFID: {
- switch (NVT) {
- case MVT::f64:
- return Select_PPCISD_FCFID_f64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::FCTIDZ: {
- switch (NVT) {
- case MVT::f64:
- return Select_PPCISD_FCTIDZ_f64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::FCTIWZ: {
- switch (NVT) {
- case MVT::f64:
- return Select_PPCISD_FCTIWZ_f64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::FSEL: {
- switch (NVT) {
- case MVT::f32:
- return Select_PPCISD_FSEL_f32(N);
- case MVT::f64:
- return Select_PPCISD_FSEL_f64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::Hi: {
- switch (NVT) {
- case MVT::i32:
- return Select_PPCISD_Hi_i32(N);
- case MVT::i64:
- return Select_PPCISD_Hi_i64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::LARX: {
- switch (NVT) {
- case MVT::i32:
- return Select_PPCISD_LARX_i32(N);
- case MVT::i64:
- return Select_PPCISD_LARX_i64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::LBRX: {
- switch (NVT) {
- case MVT::i32:
- return Select_PPCISD_LBRX_i32(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::LOAD: {
- switch (NVT) {
- case MVT::i64:
- return Select_PPCISD_LOAD_i64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::LOAD_TOC: {
- return Select_PPCISD_LOAD_TOC(N);
- break;
- }
- case PPCISD::Lo: {
- switch (NVT) {
- case MVT::i32:
- return Select_PPCISD_Lo_i32(N);
- case MVT::i64:
- return Select_PPCISD_Lo_i64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::MFFS: {
- switch (NVT) {
- case MVT::f64:
- return Select_PPCISD_MFFS_f64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::MTCTR: {
- return Select_PPCISD_MTCTR(N);
- break;
- }
- case PPCISD::MTFSB0: {
- return Select_PPCISD_MTFSB0(N);
- break;
- }
- case PPCISD::MTFSB1: {
- return Select_PPCISD_MTFSB1(N);
- break;
- }
- case PPCISD::MTFSF: {
- switch (NVT) {
- case MVT::f64:
- return Select_PPCISD_MTFSF_f64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::NOP: {
- return Select_PPCISD_NOP(N);
- break;
- }
- case PPCISD::RET_FLAG: {
- return Select_PPCISD_RET_FLAG(N);
- break;
- }
- case PPCISD::SHL: {
- switch (NVT) {
- case MVT::i32:
- return Select_PPCISD_SHL_i32(N);
- case MVT::i64:
- return Select_PPCISD_SHL_i64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::SRA: {
- switch (NVT) {
- case MVT::i32:
- return Select_PPCISD_SRA_i32(N);
- case MVT::i64:
- return Select_PPCISD_SRA_i64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::SRL: {
- switch (NVT) {
- case MVT::i32:
- return Select_PPCISD_SRL_i32(N);
- case MVT::i64:
- return Select_PPCISD_SRL_i64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::STBRX: {
- return Select_PPCISD_STBRX(N);
- break;
- }
- case PPCISD::STCX: {
- return Select_PPCISD_STCX(N);
- break;
- }
- case PPCISD::STD_32: {
- return Select_PPCISD_STD_32(N);
- break;
- }
- case PPCISD::STFIWX: {
- return Select_PPCISD_STFIWX(N);
- break;
- }
- case PPCISD::TC_RETURN: {
- return Select_PPCISD_TC_RETURN(N);
- break;
- }
- case PPCISD::TOC_ENTRY: {
- switch (NVT) {
- case MVT::i64:
- return Select_PPCISD_TOC_ENTRY_i64(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::TOC_RESTORE: {
- return Select_PPCISD_TOC_RESTORE(N);
- break;
- }
- case PPCISD::VCMP: {
- switch (NVT) {
- case MVT::v16i8:
- return Select_PPCISD_VCMP_v16i8(N);
- case MVT::v8i16:
- return Select_PPCISD_VCMP_v8i16(N);
- case MVT::v4i32:
- return Select_PPCISD_VCMP_v4i32(N);
- case MVT::v4f32:
- return Select_PPCISD_VCMP_v4f32(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::VCMPo: {
- switch (NVT) {
- case MVT::v16i8:
- return Select_PPCISD_VCMPo_v16i8(N);
- case MVT::v8i16:
- return Select_PPCISD_VCMPo_v8i16(N);
- case MVT::v4i32:
- return Select_PPCISD_VCMPo_v4i32(N);
- case MVT::v4f32:
- return Select_PPCISD_VCMPo_v4f32(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::VMADDFP: {
- switch (NVT) {
- case MVT::v4f32:
- return Select_PPCISD_VMADDFP_v4f32(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::VNMSUBFP: {
- switch (NVT) {
- case MVT::v4f32:
- return Select_PPCISD_VNMSUBFP_v4f32(N);
- default:
- break;
- }
- break;
- }
- case PPCISD::VPERM: {
- switch (NVT) {
- case MVT::v16i8:
- return Select_PPCISD_VPERM_v16i8(N);
- default:
- break;
- }
- break;
}
- } // end of big switch.
-
- if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
- N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
- N->getOpcode() != ISD::INTRINSIC_VOID) {
- CannotYetSelect(N);
- } else {
- CannotYetSelectIntrinsic(N);
}
- return NULL;
}
diff --git a/libclamav/c++/PPCGenInstrInfo.inc b/libclamav/c++/PPCGenInstrInfo.inc
index 285bce1..5d204ac 100644
--- a/libclamav/c++/PPCGenInstrInfo.inc
+++ b/libclamav/c++/PPCGenInstrInfo.inc
@@ -268,379 +268,377 @@ static const TargetInstrDesc PPCInsts[] = {
{ 144, 3, 1, 6, "FDIVS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #144 = FDIVS
{ 145, 4, 1, 7, "FMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #145 = FMADD
{ 146, 4, 1, 8, "FMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #146 = FMADDS
- { 147, 2, 1, 8, "FMRD", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo30 }, // Inst #147 = FMRD
- { 148, 2, 1, 8, "FMRS", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo31 }, // Inst #148 = FMRS
- { 149, 2, 1, 8, "FMRSD", 0, 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #149 = FMRSD
- { 150, 4, 1, 7, "FMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #150 = FMSUB
- { 151, 4, 1, 8, "FMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #151 = FMSUBS
- { 152, 3, 1, 7, "FMUL", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #152 = FMUL
- { 153, 3, 1, 8, "FMULS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #153 = FMULS
- { 154, 2, 1, 8, "FNABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #154 = FNABSD
- { 155, 2, 1, 8, "FNABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #155 = FNABSS
- { 156, 2, 1, 8, "FNEGD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #156 = FNEGD
- { 157, 2, 1, 8, "FNEGS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #157 = FNEGS
- { 158, 4, 1, 7, "FNMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #158 = FNMADD
- { 159, 4, 1, 8, "FNMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #159 = FNMADDS
- { 160, 4, 1, 7, "FNMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #160 = FNMSUB
- { 161, 4, 1, 8, "FNMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #161 = FNMSUBS
- { 162, 2, 1, 8, "FRSP", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo39 }, // Inst #162 = FRSP
- { 163, 4, 1, 8, "FSELD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo36 }, // Inst #163 = FSELD
- { 164, 4, 1, 8, "FSELS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo40 }, // Inst #164 = FSELS
- { 165, 2, 1, 10, "FSQRT", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #165 = FSQRT
- { 166, 2, 1, 10, "FSQRTS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo31 }, // Inst #166 = FSQRTS
- { 167, 3, 1, 8, "FSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #167 = FSUB
- { 168, 3, 1, 8, "FSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #168 = FSUBS
- { 169, 3, 1, 14, "LA", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #169 = LA
- { 170, 3, 1, 33, "LBZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #170 = LBZ
- { 171, 3, 1, 33, "LBZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #171 = LBZ8
- { 172, 4, 2, 33, "LBZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #172 = LBZU
- { 173, 4, 2, 33, "LBZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #173 = LBZU8
- { 174, 3, 1, 33, "LBZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #174 = LBZX
- { 175, 3, 1, 33, "LBZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #175 = LBZX8
- { 176, 3, 1, 35, "LD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #176 = LD
- { 177, 3, 1, 36, "LDARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo47 }, // Inst #177 = LDARX
- { 178, 4, 2, 35, "LDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #178 = LDU
- { 179, 3, 1, 35, "LDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #179 = LDX
- { 180, 1, 0, 35, "LDinto_toc", 0|(1<<TID::FoldableAsLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo48 }, // Inst #180 = LDinto_toc
- { 181, 3, 1, 35, "LDtoc", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 }, // Inst #181 = LDtoc
- { 182, 0, 0, 35, "LDtoc_restore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, 0 }, // Inst #182 = LDtoc_restore
- { 183, 3, 1, 37, "LFD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #183 = LFD
- { 184, 4, 2, 37, "LFDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #184 = LFDU
- { 185, 3, 1, 38, "LFDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #185 = LFDX
- { 186, 3, 1, 38, "LFS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #186 = LFS
- { 187, 4, 2, 38, "LFSU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo54 }, // Inst #187 = LFSU
- { 188, 3, 1, 38, "LFSX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #188 = LFSX
- { 189, 3, 1, 39, "LHA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #189 = LHA
- { 190, 3, 1, 39, "LHA8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #190 = LHA8
- { 191, 4, 2, 33, "LHAU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #191 = LHAU
- { 192, 4, 2, 33, "LHAU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #192 = LHAU8
- { 193, 3, 1, 39, "LHAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #193 = LHAX
- { 194, 3, 1, 39, "LHAX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #194 = LHAX8
- { 195, 3, 1, 33, "LHBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #195 = LHBRX
- { 196, 3, 1, 33, "LHZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #196 = LHZ
- { 197, 3, 1, 33, "LHZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #197 = LHZ8
- { 198, 4, 2, 33, "LHZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #198 = LHZU
- { 199, 4, 2, 33, "LHZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #199 = LHZU8
- { 200, 3, 1, 33, "LHZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #200 = LHZX
- { 201, 3, 1, 33, "LHZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #201 = LHZX8
- { 202, 2, 1, 14, "LI", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #202 = LI
- { 203, 2, 1, 14, "LI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #203 = LI8
- { 204, 2, 1, 14, "LIS", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #204 = LIS
- { 205, 2, 1, 14, "LIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #205 = LIS8
- { 206, 3, 1, 33, "LVEBX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #206 = LVEBX
- { 207, 3, 1, 33, "LVEHX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #207 = LVEHX
- { 208, 3, 1, 33, "LVEWX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #208 = LVEWX
- { 209, 3, 1, 33, "LVSL", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #209 = LVSL
- { 210, 3, 1, 33, "LVSR", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #210 = LVSR
- { 211, 3, 1, 33, "LVX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #211 = LVX
- { 212, 3, 1, 33, "LVXL", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #212 = LVXL
- { 213, 3, 1, 42, "LWA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #213 = LWA
- { 214, 3, 1, 43, "LWARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo46 }, // Inst #214 = LWARX
- { 215, 3, 1, 39, "LWAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #215 = LWAX
- { 216, 3, 1, 33, "LWBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #216 = LWBRX
- { 217, 3, 1, 33, "LWZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #217 = LWZ
- { 218, 3, 1, 33, "LWZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #218 = LWZ8
- { 219, 4, 2, 33, "LWZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #219 = LWZU
- { 220, 4, 2, 33, "LWZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #220 = LWZU8
- { 221, 3, 1, 33, "LWZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #221 = LWZX
- { 222, 3, 1, 33, "LWZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #222 = LWZX8
- { 223, 2, 1, 2, "MCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #223 = MCRF
- { 224, 1, 1, 54, "MFCR", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #224 = MFCR
- { 225, 1, 1, 56, "MFCTR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList4, NULL, NULL, OperandInfo60 }, // Inst #225 = MFCTR
- { 226, 1, 1, 56, "MFCTR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList13, NULL, NULL, OperandInfo48 }, // Inst #226 = MFCTR8
- { 227, 1, 1, 15, "MFFS", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo61 }, // Inst #227 = MFFS
- { 228, 1, 1, 56, "MFLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList14, NULL, NULL, OperandInfo60 }, // Inst #228 = MFLR
- { 229, 1, 1, 56, "MFLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList15, NULL, NULL, OperandInfo48 }, // Inst #229 = MFLR8
- { 230, 2, 1, 54, "MFOCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #230 = MFOCRF
- { 231, 1, 1, 14, "MFVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #231 = MFVRSAVE
- { 232, 1, 1, 33, "MFVSCR", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #232 = MFVSCR
- { 233, 2, 0, 3, "MTCRF", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo63 }, // Inst #233 = MTCRF
- { 234, 1, 0, 60, "MTCTR", 0, 0|1|(1<<3), NULL, ImplicitList4, Barriers4, OperandInfo60 }, // Inst #234 = MTCTR
- { 235, 1, 0, 60, "MTCTR8", 0, 0|1|(1<<3), NULL, ImplicitList13, Barriers5, OperandInfo48 }, // Inst #235 = MTCTR8
- { 236, 1, 0, 17, "MTFSB0", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #236 = MTFSB0
- { 237, 1, 0, 17, "MTFSB1", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #237 = MTFSB1
- { 238, 4, 1, 17, "MTFSF", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo64 }, // Inst #238 = MTFSF
- { 239, 1, 0, 60, "MTLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList14, NULL, OperandInfo60 }, // Inst #239 = MTLR
- { 240, 1, 0, 60, "MTLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList15, NULL, OperandInfo48 }, // Inst #240 = MTLR8
- { 241, 1, 0, 14, "MTVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<1)|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #241 = MTVRSAVE
- { 242, 1, 0, 33, "MTVSCR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #242 = MTVSCR
- { 243, 3, 1, 20, "MULHD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #243 = MULHD
- { 244, 3, 1, 21, "MULHDU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #244 = MULHDU
- { 245, 3, 1, 20, "MULHW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #245 = MULHW
- { 246, 3, 1, 21, "MULHWU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #246 = MULHWU
- { 247, 3, 1, 19, "MULLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #247 = MULLD
- { 248, 3, 1, 22, "MULLI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #248 = MULLI
- { 249, 3, 1, 20, "MULLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #249 = MULLW
- { 250, 1, 0, 52, "MovePCtoLR", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList14, NULL, OperandInfo8 }, // Inst #250 = MovePCtoLR
- { 251, 1, 0, 52, "MovePCtoLR8", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList15, NULL, OperandInfo8 }, // Inst #251 = MovePCtoLR8
- { 252, 3, 1, 14, "NAND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #252 = NAND
- { 253, 3, 1, 14, "NAND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #253 = NAND8
- { 254, 2, 1, 14, "NEG", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #254 = NEG
- { 255, 2, 1, 14, "NEG8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #255 = NEG8
- { 256, 0, 0, 14, "NOP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, 0 }, // Inst #256 = NOP
- { 257, 3, 1, 14, "NOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #257 = NOR
- { 258, 3, 1, 14, "NOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #258 = NOR8
- { 259, 3, 1, 14, "OR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #259 = OR
- { 260, 3, 1, 14, "OR4To8", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo65 }, // Inst #260 = OR4To8
- { 261, 3, 1, 14, "OR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #261 = OR8
- { 262, 3, 1, 14, "OR8To4", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo66 }, // Inst #262 = OR8To4
- { 263, 3, 1, 14, "ORC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #263 = ORC
- { 264, 3, 1, 14, "ORC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #264 = ORC8
- { 265, 3, 1, 14, "ORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #265 = ORI
- { 266, 3, 1, 14, "ORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #266 = ORI8
- { 267, 3, 1, 14, "ORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #267 = ORIS
- { 268, 3, 1, 14, "ORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #268 = ORIS8
- { 269, 4, 1, 25, "RLDCL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo67 }, // Inst #269 = RLDCL
- { 270, 4, 1, 25, "RLDICL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #270 = RLDICL
- { 271, 4, 1, 25, "RLDICR", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #271 = RLDICR
- { 272, 5, 1, 25, "RLDIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo69 }, // Inst #272 = RLDIMI
- { 273, 6, 1, 24, "RLWIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo70 }, // Inst #273 = RLWIMI
- { 274, 5, 1, 14, "RLWINM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo71 }, // Inst #274 = RLWINM
- { 275, 5, 1, 14, "RLWINMo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, ImplicitList3, NULL, OperandInfo71 }, // Inst #275 = RLWINMo
- { 276, 5, 1, 14, "RLWNM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo72 }, // Inst #276 = RLWNM
- { 277, 5, 1, 52, "SELECT_CC_F4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo73 }, // Inst #277 = SELECT_CC_F4
- { 278, 5, 1, 52, "SELECT_CC_F8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo74 }, // Inst #278 = SELECT_CC_F8
- { 279, 5, 1, 52, "SELECT_CC_I4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo75 }, // Inst #279 = SELECT_CC_I4
- { 280, 5, 1, 52, "SELECT_CC_I8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo76 }, // Inst #280 = SELECT_CC_I8
- { 281, 5, 1, 52, "SELECT_CC_VRRC", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo77 }, // Inst #281 = SELECT_CC_VRRC
- { 282, 3, 1, 25, "SLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #282 = SLD
- { 283, 3, 1, 14, "SLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #283 = SLW
- { 284, 3, 0, 52, "SPILL_CR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #284 = SPILL_CR
- { 285, 3, 1, 25, "SRAD", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo78 }, // Inst #285 = SRAD
- { 286, 3, 1, 25, "SRADI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #286 = SRADI
- { 287, 3, 1, 26, "SRAW", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #287 = SRAW
- { 288, 3, 1, 26, "SRAWI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #288 = SRAWI
- { 289, 3, 1, 25, "SRD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #289 = SRD
- { 290, 3, 1, 14, "SRW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #290 = SRW
- { 291, 3, 0, 33, "STB", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #291 = STB
- { 292, 3, 0, 33, "STB8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #292 = STB8
- { 293, 4, 1, 33, "STBU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #293 = STBU
- { 294, 4, 1, 33, "STBU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #294 = STBU8
- { 295, 3, 0, 33, "STBX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #295 = STBX
- { 296, 3, 0, 33, "STBX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #296 = STBX8
- { 297, 3, 0, 46, "STD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #297 = STD
- { 298, 3, 0, 47, "STDCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo47 }, // Inst #298 = STDCX
- { 299, 4, 1, 46, "STDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #299 = STDU
- { 300, 3, 0, 46, "STDUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #300 = STDUX
- { 301, 3, 0, 46, "STDX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #301 = STDX
- { 302, 3, 0, 46, "STDX_32", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #302 = STDX_32
- { 303, 3, 0, 46, "STD_32", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #303 = STD_32
- { 304, 3, 0, 51, "STFD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #304 = STFD
- { 305, 4, 1, 33, "STFDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo81 }, // Inst #305 = STFDU
- { 306, 3, 0, 51, "STFDX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #306 = STFDX
- { 307, 3, 0, 51, "STFIWX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #307 = STFIWX
- { 308, 3, 0, 51, "STFS", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #308 = STFS
- { 309, 4, 1, 33, "STFSU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo82 }, // Inst #309 = STFSU
- { 310, 3, 0, 51, "STFSX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #310 = STFSX
- { 311, 3, 0, 33, "STH", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #311 = STH
- { 312, 3, 0, 33, "STH8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #312 = STH8
- { 313, 3, 0, 33, "STHBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #313 = STHBRX
- { 314, 4, 1, 33, "STHU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #314 = STHU
- { 315, 4, 1, 33, "STHU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #315 = STHU8
- { 316, 3, 0, 33, "STHX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #316 = STHX
- { 317, 3, 0, 33, "STHX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #317 = STHX8
- { 318, 3, 0, 33, "STVEBX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #318 = STVEBX
- { 319, 3, 0, 33, "STVEHX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #319 = STVEHX
- { 320, 3, 0, 33, "STVEWX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #320 = STVEWX
- { 321, 3, 0, 33, "STVX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #321 = STVX
- { 322, 3, 0, 33, "STVXL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #322 = STVXL
- { 323, 3, 0, 33, "STW", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #323 = STW
- { 324, 3, 0, 33, "STW8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #324 = STW8
- { 325, 3, 0, 33, "STWBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #325 = STWBRX
- { 326, 3, 0, 49, "STWCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo46 }, // Inst #326 = STWCX
- { 327, 4, 1, 33, "STWU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #327 = STWU
- { 328, 4, 1, 33, "STWU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #328 = STWU8
- { 329, 3, 0, 33, "STWUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #329 = STWUX
- { 330, 3, 0, 33, "STWX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #330 = STWX
- { 331, 3, 0, 33, "STWX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #331 = STWX8
- { 332, 3, 1, 14, "SUBF", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #332 = SUBF
- { 333, 3, 1, 14, "SUBF8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #333 = SUBF8
- { 334, 3, 1, 14, "SUBFC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #334 = SUBFC
- { 335, 3, 1, 14, "SUBFC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #335 = SUBFC8
- { 336, 3, 1, 14, "SUBFE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #336 = SUBFE
- { 337, 3, 1, 14, "SUBFE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #337 = SUBFE8
- { 338, 3, 1, 14, "SUBFIC", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #338 = SUBFIC
- { 339, 3, 1, 14, "SUBFIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #339 = SUBFIC8
- { 340, 2, 1, 14, "SUBFME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #340 = SUBFME
- { 341, 2, 1, 14, "SUBFME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #341 = SUBFME8
- { 342, 2, 1, 14, "SUBFZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #342 = SUBFZE
- { 343, 2, 1, 14, "SUBFZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #343 = SUBFZE8
- { 344, 0, 0, 50, "SYNC", 0|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #344 = SYNC
- { 345, 1, 0, 0, "TAILB", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #345 = TAILB
- { 346, 1, 0, 0, "TAILB8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #346 = TAILB8
- { 347, 1, 0, 0, "TAILBA", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #347 = TAILBA
- { 348, 1, 0, 0, "TAILBA8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #348 = TAILBA8
- { 349, 0, 0, 0, "TAILBCTR", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #349 = TAILBCTR
- { 350, 0, 0, 0, "TAILBCTR8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #350 = TAILBCTR8
- { 351, 2, 0, 52, "TCRETURNai", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #351 = TCRETURNai
- { 352, 2, 0, 52, "TCRETURNai8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #352 = TCRETURNai8
- { 353, 2, 0, 52, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #353 = TCRETURNdi
- { 354, 2, 0, 52, "TCRETURNdi8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #354 = TCRETURNdi8
- { 355, 2, 0, 52, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo83 }, // Inst #355 = TCRETURNri
- { 356, 2, 0, 52, "TCRETURNri8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo84 }, // Inst #356 = TCRETURNri8
- { 357, 0, 0, 33, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #357 = TRAP
- { 358, 2, 1, 52, "UPDATE_VRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo6 }, // Inst #358 = UPDATE_VRSAVE
- { 359, 3, 1, 67, "VADDCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #359 = VADDCUW
- { 360, 3, 1, 67, "VADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #360 = VADDFP
- { 361, 3, 1, 67, "VADDSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #361 = VADDSBS
- { 362, 3, 1, 67, "VADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #362 = VADDSHS
- { 363, 3, 1, 67, "VADDSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #363 = VADDSWS
- { 364, 3, 1, 70, "VADDUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #364 = VADDUBM
- { 365, 3, 1, 67, "VADDUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #365 = VADDUBS
- { 366, 3, 1, 70, "VADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #366 = VADDUHM
- { 367, 3, 1, 67, "VADDUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #367 = VADDUHS
- { 368, 3, 1, 70, "VADDUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #368 = VADDUWM
- { 369, 3, 1, 67, "VADDUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #369 = VADDUWS
- { 370, 3, 1, 67, "VAND", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #370 = VAND
- { 371, 3, 1, 67, "VANDC", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #371 = VANDC
- { 372, 3, 1, 67, "VAVGSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #372 = VAVGSB
- { 373, 3, 1, 67, "VAVGSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #373 = VAVGSH
- { 374, 3, 1, 67, "VAVGSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #374 = VAVGSW
- { 375, 3, 1, 67, "VAVGUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #375 = VAVGUB
- { 376, 3, 1, 67, "VAVGUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #376 = VAVGUH
- { 377, 3, 1, 67, "VAVGUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #377 = VAVGUW
- { 378, 3, 1, 67, "VCFSX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #378 = VCFSX
- { 379, 3, 1, 67, "VCFUX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #379 = VCFUX
- { 380, 3, 1, 68, "VCMPBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #380 = VCMPBFP
- { 381, 3, 1, 68, "VCMPBFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #381 = VCMPBFPo
- { 382, 3, 1, 68, "VCMPEQFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #382 = VCMPEQFP
- { 383, 3, 1, 68, "VCMPEQFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #383 = VCMPEQFPo
- { 384, 3, 1, 68, "VCMPEQUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #384 = VCMPEQUB
- { 385, 3, 1, 68, "VCMPEQUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #385 = VCMPEQUBo
- { 386, 3, 1, 68, "VCMPEQUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #386 = VCMPEQUH
- { 387, 3, 1, 68, "VCMPEQUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #387 = VCMPEQUHo
- { 388, 3, 1, 68, "VCMPEQUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #388 = VCMPEQUW
- { 389, 3, 1, 68, "VCMPEQUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #389 = VCMPEQUWo
- { 390, 3, 1, 68, "VCMPGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #390 = VCMPGEFP
- { 391, 3, 1, 68, "VCMPGEFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #391 = VCMPGEFPo
- { 392, 3, 1, 68, "VCMPGTFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #392 = VCMPGTFP
- { 393, 3, 1, 68, "VCMPGTFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #393 = VCMPGTFPo
- { 394, 3, 1, 68, "VCMPGTSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #394 = VCMPGTSB
- { 395, 3, 1, 68, "VCMPGTSBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #395 = VCMPGTSBo
- { 396, 3, 1, 68, "VCMPGTSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #396 = VCMPGTSH
- { 397, 3, 1, 68, "VCMPGTSHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #397 = VCMPGTSHo
- { 398, 3, 1, 68, "VCMPGTSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #398 = VCMPGTSW
- { 399, 3, 1, 68, "VCMPGTSWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #399 = VCMPGTSWo
- { 400, 3, 1, 68, "VCMPGTUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #400 = VCMPGTUB
- { 401, 3, 1, 68, "VCMPGTUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #401 = VCMPGTUBo
- { 402, 3, 1, 68, "VCMPGTUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #402 = VCMPGTUH
- { 403, 3, 1, 68, "VCMPGTUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #403 = VCMPGTUHo
- { 404, 3, 1, 68, "VCMPGTUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #404 = VCMPGTUW
- { 405, 3, 1, 68, "VCMPGTUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #405 = VCMPGTUWo
- { 406, 3, 1, 67, "VCTSXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #406 = VCTSXS
- { 407, 3, 1, 67, "VCTUXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #407 = VCTUXS
- { 408, 2, 1, 67, "VEXPTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #408 = VEXPTEFP
- { 409, 2, 1, 67, "VLOGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #409 = VLOGEFP
- { 410, 4, 1, 67, "VMADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #410 = VMADDFP
- { 411, 3, 1, 67, "VMAXFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #411 = VMAXFP
- { 412, 3, 1, 67, "VMAXSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #412 = VMAXSB
- { 413, 3, 1, 67, "VMAXSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #413 = VMAXSH
- { 414, 3, 1, 67, "VMAXSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #414 = VMAXSW
- { 415, 3, 1, 67, "VMAXUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #415 = VMAXUB
- { 416, 3, 1, 67, "VMAXUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #416 = VMAXUH
- { 417, 3, 1, 67, "VMAXUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #417 = VMAXUW
- { 418, 4, 1, 67, "VMHADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #418 = VMHADDSHS
- { 419, 4, 1, 67, "VMHRADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #419 = VMHRADDSHS
- { 420, 3, 1, 67, "VMINFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #420 = VMINFP
- { 421, 3, 1, 67, "VMINSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #421 = VMINSB
- { 422, 3, 1, 67, "VMINSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #422 = VMINSH
- { 423, 3, 1, 67, "VMINSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #423 = VMINSW
- { 424, 3, 1, 67, "VMINUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #424 = VMINUB
- { 425, 3, 1, 67, "VMINUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #425 = VMINUH
- { 426, 3, 1, 67, "VMINUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #426 = VMINUW
- { 427, 4, 1, 67, "VMLADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #427 = VMLADDUHM
- { 428, 3, 1, 67, "VMRGHB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #428 = VMRGHB
- { 429, 3, 1, 67, "VMRGHH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #429 = VMRGHH
- { 430, 3, 1, 67, "VMRGHW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #430 = VMRGHW
- { 431, 3, 1, 67, "VMRGLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #431 = VMRGLB
- { 432, 3, 1, 67, "VMRGLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #432 = VMRGLH
- { 433, 3, 1, 67, "VMRGLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #433 = VMRGLW
- { 434, 4, 1, 67, "VMSUMMBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #434 = VMSUMMBM
- { 435, 4, 1, 67, "VMSUMSHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #435 = VMSUMSHM
- { 436, 4, 1, 67, "VMSUMSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #436 = VMSUMSHS
- { 437, 4, 1, 67, "VMSUMUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #437 = VMSUMUBM
- { 438, 4, 1, 67, "VMSUMUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #438 = VMSUMUHM
- { 439, 4, 1, 67, "VMSUMUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #439 = VMSUMUHS
- { 440, 3, 1, 67, "VMULESB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #440 = VMULESB
- { 441, 3, 1, 67, "VMULESH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #441 = VMULESH
- { 442, 3, 1, 67, "VMULEUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #442 = VMULEUB
- { 443, 3, 1, 67, "VMULEUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #443 = VMULEUH
- { 444, 3, 1, 67, "VMULOSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #444 = VMULOSB
- { 445, 3, 1, 67, "VMULOSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #445 = VMULOSH
- { 446, 3, 1, 67, "VMULOUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #446 = VMULOUB
- { 447, 3, 1, 67, "VMULOUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #447 = VMULOUH
- { 448, 4, 1, 67, "VNMSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #448 = VNMSUBFP
- { 449, 3, 1, 67, "VNOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #449 = VNOR
- { 450, 3, 1, 67, "VOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #450 = VOR
- { 451, 4, 1, 67, "VPERM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #451 = VPERM
- { 452, 3, 1, 67, "VPKPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #452 = VPKPX
- { 453, 3, 1, 67, "VPKSHSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #453 = VPKSHSS
- { 454, 3, 1, 67, "VPKSHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #454 = VPKSHUS
- { 455, 3, 1, 67, "VPKSWSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #455 = VPKSWSS
- { 456, 3, 1, 67, "VPKSWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #456 = VPKSWUS
- { 457, 3, 1, 67, "VPKUHUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #457 = VPKUHUM
- { 458, 3, 1, 67, "VPKUHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #458 = VPKUHUS
- { 459, 3, 1, 67, "VPKUWUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #459 = VPKUWUM
- { 460, 3, 1, 67, "VPKUWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #460 = VPKUWUS
- { 461, 2, 1, 67, "VREFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #461 = VREFP
- { 462, 2, 1, 67, "VRFIM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #462 = VRFIM
- { 463, 2, 1, 67, "VRFIN", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #463 = VRFIN
- { 464, 2, 1, 67, "VRFIP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #464 = VRFIP
- { 465, 2, 1, 67, "VRFIZ", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #465 = VRFIZ
- { 466, 3, 1, 67, "VRLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #466 = VRLB
- { 467, 3, 1, 67, "VRLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #467 = VRLH
- { 468, 3, 1, 67, "VRLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #468 = VRLW
- { 469, 2, 1, 67, "VRSQRTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #469 = VRSQRTEFP
- { 470, 4, 1, 67, "VSEL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #470 = VSEL
- { 471, 3, 1, 67, "VSL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #471 = VSL
- { 472, 3, 1, 67, "VSLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #472 = VSLB
- { 473, 4, 1, 67, "VSLDOI", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 }, // Inst #473 = VSLDOI
- { 474, 3, 1, 67, "VSLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #474 = VSLH
- { 475, 3, 1, 67, "VSLO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #475 = VSLO
- { 476, 3, 1, 67, "VSLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #476 = VSLW
- { 477, 3, 1, 71, "VSPLTB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #477 = VSPLTB
- { 478, 3, 1, 71, "VSPLTH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #478 = VSPLTH
- { 479, 2, 1, 71, "VSPLTISB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #479 = VSPLTISB
- { 480, 2, 1, 71, "VSPLTISH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #480 = VSPLTISH
- { 481, 2, 1, 71, "VSPLTISW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #481 = VSPLTISW
- { 482, 3, 1, 71, "VSPLTW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #482 = VSPLTW
- { 483, 3, 1, 67, "VSR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #483 = VSR
- { 484, 3, 1, 67, "VSRAB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #484 = VSRAB
- { 485, 3, 1, 67, "VSRAH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #485 = VSRAH
- { 486, 3, 1, 67, "VSRAW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #486 = VSRAW
- { 487, 3, 1, 67, "VSRB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #487 = VSRB
- { 488, 3, 1, 67, "VSRH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #488 = VSRH
- { 489, 3, 1, 67, "VSRO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #489 = VSRO
- { 490, 3, 1, 67, "VSRW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #490 = VSRW
- { 491, 3, 1, 67, "VSUBCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #491 = VSUBCUW
- { 492, 3, 1, 70, "VSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #492 = VSUBFP
- { 493, 3, 1, 67, "VSUBSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #493 = VSUBSBS
- { 494, 3, 1, 67, "VSUBSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #494 = VSUBSHS
- { 495, 3, 1, 67, "VSUBSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #495 = VSUBSWS
- { 496, 3, 1, 70, "VSUBUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #496 = VSUBUBM
- { 497, 3, 1, 67, "VSUBUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #497 = VSUBUBS
- { 498, 3, 1, 70, "VSUBUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #498 = VSUBUHM
- { 499, 3, 1, 67, "VSUBUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #499 = VSUBUHS
- { 500, 3, 1, 70, "VSUBUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #500 = VSUBUWM
- { 501, 3, 1, 67, "VSUBUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #501 = VSUBUWS
- { 502, 3, 1, 67, "VSUM2SWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #502 = VSUM2SWS
- { 503, 3, 1, 67, "VSUM4SBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #503 = VSUM4SBS
- { 504, 3, 1, 67, "VSUM4SHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #504 = VSUM4SHS
- { 505, 3, 1, 67, "VSUM4UBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #505 = VSUM4UBS
- { 506, 3, 1, 67, "VSUMSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #506 = VSUMSWS
- { 507, 2, 1, 67, "VUPKHPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #507 = VUPKHPX
- { 508, 2, 1, 67, "VUPKHSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #508 = VUPKHSB
- { 509, 2, 1, 67, "VUPKHSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #509 = VUPKHSH
- { 510, 2, 1, 67, "VUPKLPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #510 = VUPKLPX
- { 511, 2, 1, 67, "VUPKLSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #511 = VUPKLSB
- { 512, 2, 1, 67, "VUPKLSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #512 = VUPKLSH
- { 513, 3, 1, 67, "VXOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #513 = VXOR
- { 514, 1, 1, 67, "V_SET0", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo62 }, // Inst #514 = V_SET0
- { 515, 3, 1, 14, "XOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #515 = XOR
- { 516, 3, 1, 14, "XOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #516 = XOR8
- { 517, 3, 1, 14, "XORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #517 = XORI
- { 518, 3, 1, 14, "XORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #518 = XORI8
- { 519, 3, 1, 14, "XORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #519 = XORIS
- { 520, 3, 1, 14, "XORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #520 = XORIS8
+ { 147, 2, 1, 8, "FMR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo31 }, // Inst #147 = FMR
+ { 148, 2, 1, 8, "FMRSD", 0, 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #148 = FMRSD
+ { 149, 4, 1, 7, "FMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #149 = FMSUB
+ { 150, 4, 1, 8, "FMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #150 = FMSUBS
+ { 151, 3, 1, 7, "FMUL", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #151 = FMUL
+ { 152, 3, 1, 8, "FMULS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #152 = FMULS
+ { 153, 2, 1, 8, "FNABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #153 = FNABSD
+ { 154, 2, 1, 8, "FNABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #154 = FNABSS
+ { 155, 2, 1, 8, "FNEGD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #155 = FNEGD
+ { 156, 2, 1, 8, "FNEGS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #156 = FNEGS
+ { 157, 4, 1, 7, "FNMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #157 = FNMADD
+ { 158, 4, 1, 8, "FNMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #158 = FNMADDS
+ { 159, 4, 1, 7, "FNMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #159 = FNMSUB
+ { 160, 4, 1, 8, "FNMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #160 = FNMSUBS
+ { 161, 2, 1, 8, "FRSP", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo39 }, // Inst #161 = FRSP
+ { 162, 4, 1, 8, "FSELD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo36 }, // Inst #162 = FSELD
+ { 163, 4, 1, 8, "FSELS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo40 }, // Inst #163 = FSELS
+ { 164, 2, 1, 10, "FSQRT", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #164 = FSQRT
+ { 165, 2, 1, 10, "FSQRTS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo31 }, // Inst #165 = FSQRTS
+ { 166, 3, 1, 8, "FSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #166 = FSUB
+ { 167, 3, 1, 8, "FSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #167 = FSUBS
+ { 168, 3, 1, 14, "LA", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #168 = LA
+ { 169, 3, 1, 33, "LBZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #169 = LBZ
+ { 170, 3, 1, 33, "LBZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #170 = LBZ8
+ { 171, 4, 2, 33, "LBZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #171 = LBZU
+ { 172, 4, 2, 33, "LBZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #172 = LBZU8
+ { 173, 3, 1, 33, "LBZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #173 = LBZX
+ { 174, 3, 1, 33, "LBZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #174 = LBZX8
+ { 175, 3, 1, 35, "LD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #175 = LD
+ { 176, 3, 1, 36, "LDARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo47 }, // Inst #176 = LDARX
+ { 177, 4, 2, 35, "LDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #177 = LDU
+ { 178, 3, 1, 35, "LDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #178 = LDX
+ { 179, 1, 0, 35, "LDinto_toc", 0|(1<<TID::FoldableAsLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo48 }, // Inst #179 = LDinto_toc
+ { 180, 3, 1, 35, "LDtoc", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 }, // Inst #180 = LDtoc
+ { 181, 0, 0, 35, "LDtoc_restore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, 0 }, // Inst #181 = LDtoc_restore
+ { 182, 3, 1, 37, "LFD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #182 = LFD
+ { 183, 4, 2, 37, "LFDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #183 = LFDU
+ { 184, 3, 1, 38, "LFDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #184 = LFDX
+ { 185, 3, 1, 38, "LFS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #185 = LFS
+ { 186, 4, 2, 38, "LFSU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo54 }, // Inst #186 = LFSU
+ { 187, 3, 1, 38, "LFSX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #187 = LFSX
+ { 188, 3, 1, 39, "LHA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #188 = LHA
+ { 189, 3, 1, 39, "LHA8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #189 = LHA8
+ { 190, 4, 2, 33, "LHAU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #190 = LHAU
+ { 191, 4, 2, 33, "LHAU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #191 = LHAU8
+ { 192, 3, 1, 39, "LHAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #192 = LHAX
+ { 193, 3, 1, 39, "LHAX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #193 = LHAX8
+ { 194, 3, 1, 33, "LHBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #194 = LHBRX
+ { 195, 3, 1, 33, "LHZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #195 = LHZ
+ { 196, 3, 1, 33, "LHZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #196 = LHZ8
+ { 197, 4, 2, 33, "LHZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #197 = LHZU
+ { 198, 4, 2, 33, "LHZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #198 = LHZU8
+ { 199, 3, 1, 33, "LHZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #199 = LHZX
+ { 200, 3, 1, 33, "LHZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #200 = LHZX8
+ { 201, 2, 1, 14, "LI", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #201 = LI
+ { 202, 2, 1, 14, "LI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #202 = LI8
+ { 203, 2, 1, 14, "LIS", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #203 = LIS
+ { 204, 2, 1, 14, "LIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #204 = LIS8
+ { 205, 3, 1, 33, "LVEBX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #205 = LVEBX
+ { 206, 3, 1, 33, "LVEHX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #206 = LVEHX
+ { 207, 3, 1, 33, "LVEWX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #207 = LVEWX
+ { 208, 3, 1, 33, "LVSL", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #208 = LVSL
+ { 209, 3, 1, 33, "LVSR", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #209 = LVSR
+ { 210, 3, 1, 33, "LVX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #210 = LVX
+ { 211, 3, 1, 33, "LVXL", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #211 = LVXL
+ { 212, 3, 1, 42, "LWA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #212 = LWA
+ { 213, 3, 1, 43, "LWARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo46 }, // Inst #213 = LWARX
+ { 214, 3, 1, 39, "LWAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #214 = LWAX
+ { 215, 3, 1, 33, "LWBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #215 = LWBRX
+ { 216, 3, 1, 33, "LWZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #216 = LWZ
+ { 217, 3, 1, 33, "LWZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #217 = LWZ8
+ { 218, 4, 2, 33, "LWZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #218 = LWZU
+ { 219, 4, 2, 33, "LWZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #219 = LWZU8
+ { 220, 3, 1, 33, "LWZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #220 = LWZX
+ { 221, 3, 1, 33, "LWZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #221 = LWZX8
+ { 222, 2, 1, 2, "MCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #222 = MCRF
+ { 223, 1, 1, 54, "MFCR", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #223 = MFCR
+ { 224, 1, 1, 56, "MFCTR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList4, NULL, NULL, OperandInfo60 }, // Inst #224 = MFCTR
+ { 225, 1, 1, 56, "MFCTR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList13, NULL, NULL, OperandInfo48 }, // Inst #225 = MFCTR8
+ { 226, 1, 1, 15, "MFFS", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo61 }, // Inst #226 = MFFS
+ { 227, 1, 1, 56, "MFLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList14, NULL, NULL, OperandInfo60 }, // Inst #227 = MFLR
+ { 228, 1, 1, 56, "MFLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList15, NULL, NULL, OperandInfo48 }, // Inst #228 = MFLR8
+ { 229, 2, 1, 54, "MFOCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #229 = MFOCRF
+ { 230, 1, 1, 14, "MFVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #230 = MFVRSAVE
+ { 231, 1, 1, 33, "MFVSCR", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #231 = MFVSCR
+ { 232, 2, 0, 3, "MTCRF", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo63 }, // Inst #232 = MTCRF
+ { 233, 1, 0, 60, "MTCTR", 0, 0|1|(1<<3), NULL, ImplicitList4, Barriers4, OperandInfo60 }, // Inst #233 = MTCTR
+ { 234, 1, 0, 60, "MTCTR8", 0, 0|1|(1<<3), NULL, ImplicitList13, Barriers5, OperandInfo48 }, // Inst #234 = MTCTR8
+ { 235, 1, 0, 17, "MTFSB0", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #235 = MTFSB0
+ { 236, 1, 0, 17, "MTFSB1", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #236 = MTFSB1
+ { 237, 4, 1, 17, "MTFSF", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo64 }, // Inst #237 = MTFSF
+ { 238, 1, 0, 60, "MTLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList14, NULL, OperandInfo60 }, // Inst #238 = MTLR
+ { 239, 1, 0, 60, "MTLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList15, NULL, OperandInfo48 }, // Inst #239 = MTLR8
+ { 240, 1, 0, 14, "MTVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<1)|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #240 = MTVRSAVE
+ { 241, 1, 0, 33, "MTVSCR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #241 = MTVSCR
+ { 242, 3, 1, 20, "MULHD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #242 = MULHD
+ { 243, 3, 1, 21, "MULHDU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #243 = MULHDU
+ { 244, 3, 1, 20, "MULHW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #244 = MULHW
+ { 245, 3, 1, 21, "MULHWU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #245 = MULHWU
+ { 246, 3, 1, 19, "MULLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #246 = MULLD
+ { 247, 3, 1, 22, "MULLI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #247 = MULLI
+ { 248, 3, 1, 20, "MULLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #248 = MULLW
+ { 249, 1, 0, 52, "MovePCtoLR", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList14, NULL, OperandInfo8 }, // Inst #249 = MovePCtoLR
+ { 250, 1, 0, 52, "MovePCtoLR8", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList15, NULL, OperandInfo8 }, // Inst #250 = MovePCtoLR8
+ { 251, 3, 1, 14, "NAND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #251 = NAND
+ { 252, 3, 1, 14, "NAND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #252 = NAND8
+ { 253, 2, 1, 14, "NEG", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #253 = NEG
+ { 254, 2, 1, 14, "NEG8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #254 = NEG8
+ { 255, 0, 0, 14, "NOP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, 0 }, // Inst #255 = NOP
+ { 256, 3, 1, 14, "NOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #256 = NOR
+ { 257, 3, 1, 14, "NOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #257 = NOR8
+ { 258, 3, 1, 14, "OR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #258 = OR
+ { 259, 3, 1, 14, "OR4To8", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo65 }, // Inst #259 = OR4To8
+ { 260, 3, 1, 14, "OR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #260 = OR8
+ { 261, 3, 1, 14, "OR8To4", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo66 }, // Inst #261 = OR8To4
+ { 262, 3, 1, 14, "ORC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #262 = ORC
+ { 263, 3, 1, 14, "ORC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #263 = ORC8
+ { 264, 3, 1, 14, "ORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #264 = ORI
+ { 265, 3, 1, 14, "ORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #265 = ORI8
+ { 266, 3, 1, 14, "ORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #266 = ORIS
+ { 267, 3, 1, 14, "ORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #267 = ORIS8
+ { 268, 4, 1, 25, "RLDCL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo67 }, // Inst #268 = RLDCL
+ { 269, 4, 1, 25, "RLDICL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #269 = RLDICL
+ { 270, 4, 1, 25, "RLDICR", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #270 = RLDICR
+ { 271, 5, 1, 25, "RLDIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo69 }, // Inst #271 = RLDIMI
+ { 272, 6, 1, 24, "RLWIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo70 }, // Inst #272 = RLWIMI
+ { 273, 5, 1, 14, "RLWINM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo71 }, // Inst #273 = RLWINM
+ { 274, 5, 1, 14, "RLWINMo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, ImplicitList3, NULL, OperandInfo71 }, // Inst #274 = RLWINMo
+ { 275, 5, 1, 14, "RLWNM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo72 }, // Inst #275 = RLWNM
+ { 276, 5, 1, 52, "SELECT_CC_F4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo73 }, // Inst #276 = SELECT_CC_F4
+ { 277, 5, 1, 52, "SELECT_CC_F8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo74 }, // Inst #277 = SELECT_CC_F8
+ { 278, 5, 1, 52, "SELECT_CC_I4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo75 }, // Inst #278 = SELECT_CC_I4
+ { 279, 5, 1, 52, "SELECT_CC_I8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo76 }, // Inst #279 = SELECT_CC_I8
+ { 280, 5, 1, 52, "SELECT_CC_VRRC", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo77 }, // Inst #280 = SELECT_CC_VRRC
+ { 281, 3, 1, 25, "SLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #281 = SLD
+ { 282, 3, 1, 14, "SLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #282 = SLW
+ { 283, 3, 0, 52, "SPILL_CR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #283 = SPILL_CR
+ { 284, 3, 1, 25, "SRAD", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo78 }, // Inst #284 = SRAD
+ { 285, 3, 1, 25, "SRADI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #285 = SRADI
+ { 286, 3, 1, 26, "SRAW", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #286 = SRAW
+ { 287, 3, 1, 26, "SRAWI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #287 = SRAWI
+ { 288, 3, 1, 25, "SRD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #288 = SRD
+ { 289, 3, 1, 14, "SRW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #289 = SRW
+ { 290, 3, 0, 33, "STB", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #290 = STB
+ { 291, 3, 0, 33, "STB8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #291 = STB8
+ { 292, 4, 1, 33, "STBU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #292 = STBU
+ { 293, 4, 1, 33, "STBU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #293 = STBU8
+ { 294, 3, 0, 33, "STBX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #294 = STBX
+ { 295, 3, 0, 33, "STBX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #295 = STBX8
+ { 296, 3, 0, 46, "STD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #296 = STD
+ { 297, 3, 0, 47, "STDCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo47 }, // Inst #297 = STDCX
+ { 298, 4, 1, 46, "STDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #298 = STDU
+ { 299, 3, 0, 46, "STDUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #299 = STDUX
+ { 300, 3, 0, 46, "STDX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #300 = STDX
+ { 301, 3, 0, 46, "STDX_32", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #301 = STDX_32
+ { 302, 3, 0, 46, "STD_32", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #302 = STD_32
+ { 303, 3, 0, 51, "STFD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #303 = STFD
+ { 304, 4, 1, 33, "STFDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo81 }, // Inst #304 = STFDU
+ { 305, 3, 0, 51, "STFDX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #305 = STFDX
+ { 306, 3, 0, 51, "STFIWX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #306 = STFIWX
+ { 307, 3, 0, 51, "STFS", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #307 = STFS
+ { 308, 4, 1, 33, "STFSU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo82 }, // Inst #308 = STFSU
+ { 309, 3, 0, 51, "STFSX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #309 = STFSX
+ { 310, 3, 0, 33, "STH", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #310 = STH
+ { 311, 3, 0, 33, "STH8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #311 = STH8
+ { 312, 3, 0, 33, "STHBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #312 = STHBRX
+ { 313, 4, 1, 33, "STHU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #313 = STHU
+ { 314, 4, 1, 33, "STHU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #314 = STHU8
+ { 315, 3, 0, 33, "STHX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #315 = STHX
+ { 316, 3, 0, 33, "STHX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #316 = STHX8
+ { 317, 3, 0, 33, "STVEBX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #317 = STVEBX
+ { 318, 3, 0, 33, "STVEHX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #318 = STVEHX
+ { 319, 3, 0, 33, "STVEWX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #319 = STVEWX
+ { 320, 3, 0, 33, "STVX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #320 = STVX
+ { 321, 3, 0, 33, "STVXL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #321 = STVXL
+ { 322, 3, 0, 33, "STW", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #322 = STW
+ { 323, 3, 0, 33, "STW8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #323 = STW8
+ { 324, 3, 0, 33, "STWBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #324 = STWBRX
+ { 325, 3, 0, 49, "STWCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo46 }, // Inst #325 = STWCX
+ { 326, 4, 1, 33, "STWU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #326 = STWU
+ { 327, 3, 0, 33, "STWUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #327 = STWUX
+ { 328, 3, 0, 33, "STWX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #328 = STWX
+ { 329, 3, 0, 33, "STWX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #329 = STWX8
+ { 330, 3, 1, 14, "SUBF", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #330 = SUBF
+ { 331, 3, 1, 14, "SUBF8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #331 = SUBF8
+ { 332, 3, 1, 14, "SUBFC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #332 = SUBFC
+ { 333, 3, 1, 14, "SUBFC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #333 = SUBFC8
+ { 334, 3, 1, 14, "SUBFE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #334 = SUBFE
+ { 335, 3, 1, 14, "SUBFE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #335 = SUBFE8
+ { 336, 3, 1, 14, "SUBFIC", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #336 = SUBFIC
+ { 337, 3, 1, 14, "SUBFIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #337 = SUBFIC8
+ { 338, 2, 1, 14, "SUBFME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #338 = SUBFME
+ { 339, 2, 1, 14, "SUBFME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #339 = SUBFME8
+ { 340, 2, 1, 14, "SUBFZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #340 = SUBFZE
+ { 341, 2, 1, 14, "SUBFZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #341 = SUBFZE8
+ { 342, 0, 0, 50, "SYNC", 0|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #342 = SYNC
+ { 343, 1, 0, 0, "TAILB", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #343 = TAILB
+ { 344, 1, 0, 0, "TAILB8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #344 = TAILB8
+ { 345, 1, 0, 0, "TAILBA", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #345 = TAILBA
+ { 346, 1, 0, 0, "TAILBA8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #346 = TAILBA8
+ { 347, 0, 0, 0, "TAILBCTR", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #347 = TAILBCTR
+ { 348, 0, 0, 0, "TAILBCTR8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #348 = TAILBCTR8
+ { 349, 2, 0, 52, "TCRETURNai", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #349 = TCRETURNai
+ { 350, 2, 0, 52, "TCRETURNai8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #350 = TCRETURNai8
+ { 351, 2, 0, 52, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #351 = TCRETURNdi
+ { 352, 2, 0, 52, "TCRETURNdi8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #352 = TCRETURNdi8
+ { 353, 2, 0, 52, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo83 }, // Inst #353 = TCRETURNri
+ { 354, 2, 0, 52, "TCRETURNri8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo84 }, // Inst #354 = TCRETURNri8
+ { 355, 0, 0, 33, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #355 = TRAP
+ { 356, 2, 1, 52, "UPDATE_VRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo6 }, // Inst #356 = UPDATE_VRSAVE
+ { 357, 3, 1, 67, "VADDCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #357 = VADDCUW
+ { 358, 3, 1, 67, "VADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #358 = VADDFP
+ { 359, 3, 1, 67, "VADDSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #359 = VADDSBS
+ { 360, 3, 1, 67, "VADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #360 = VADDSHS
+ { 361, 3, 1, 67, "VADDSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #361 = VADDSWS
+ { 362, 3, 1, 70, "VADDUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #362 = VADDUBM
+ { 363, 3, 1, 67, "VADDUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #363 = VADDUBS
+ { 364, 3, 1, 70, "VADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #364 = VADDUHM
+ { 365, 3, 1, 67, "VADDUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #365 = VADDUHS
+ { 366, 3, 1, 70, "VADDUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #366 = VADDUWM
+ { 367, 3, 1, 67, "VADDUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #367 = VADDUWS
+ { 368, 3, 1, 67, "VAND", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #368 = VAND
+ { 369, 3, 1, 67, "VANDC", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #369 = VANDC
+ { 370, 3, 1, 67, "VAVGSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #370 = VAVGSB
+ { 371, 3, 1, 67, "VAVGSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #371 = VAVGSH
+ { 372, 3, 1, 67, "VAVGSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #372 = VAVGSW
+ { 373, 3, 1, 67, "VAVGUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #373 = VAVGUB
+ { 374, 3, 1, 67, "VAVGUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #374 = VAVGUH
+ { 375, 3, 1, 67, "VAVGUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #375 = VAVGUW
+ { 376, 3, 1, 67, "VCFSX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #376 = VCFSX
+ { 377, 3, 1, 67, "VCFUX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #377 = VCFUX
+ { 378, 3, 1, 68, "VCMPBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #378 = VCMPBFP
+ { 379, 3, 1, 68, "VCMPBFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #379 = VCMPBFPo
+ { 380, 3, 1, 68, "VCMPEQFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #380 = VCMPEQFP
+ { 381, 3, 1, 68, "VCMPEQFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #381 = VCMPEQFPo
+ { 382, 3, 1, 68, "VCMPEQUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #382 = VCMPEQUB
+ { 383, 3, 1, 68, "VCMPEQUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #383 = VCMPEQUBo
+ { 384, 3, 1, 68, "VCMPEQUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #384 = VCMPEQUH
+ { 385, 3, 1, 68, "VCMPEQUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #385 = VCMPEQUHo
+ { 386, 3, 1, 68, "VCMPEQUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #386 = VCMPEQUW
+ { 387, 3, 1, 68, "VCMPEQUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #387 = VCMPEQUWo
+ { 388, 3, 1, 68, "VCMPGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #388 = VCMPGEFP
+ { 389, 3, 1, 68, "VCMPGEFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #389 = VCMPGEFPo
+ { 390, 3, 1, 68, "VCMPGTFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #390 = VCMPGTFP
+ { 391, 3, 1, 68, "VCMPGTFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #391 = VCMPGTFPo
+ { 392, 3, 1, 68, "VCMPGTSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #392 = VCMPGTSB
+ { 393, 3, 1, 68, "VCMPGTSBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #393 = VCMPGTSBo
+ { 394, 3, 1, 68, "VCMPGTSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #394 = VCMPGTSH
+ { 395, 3, 1, 68, "VCMPGTSHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #395 = VCMPGTSHo
+ { 396, 3, 1, 68, "VCMPGTSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #396 = VCMPGTSW
+ { 397, 3, 1, 68, "VCMPGTSWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #397 = VCMPGTSWo
+ { 398, 3, 1, 68, "VCMPGTUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #398 = VCMPGTUB
+ { 399, 3, 1, 68, "VCMPGTUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #399 = VCMPGTUBo
+ { 400, 3, 1, 68, "VCMPGTUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #400 = VCMPGTUH
+ { 401, 3, 1, 68, "VCMPGTUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #401 = VCMPGTUHo
+ { 402, 3, 1, 68, "VCMPGTUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #402 = VCMPGTUW
+ { 403, 3, 1, 68, "VCMPGTUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #403 = VCMPGTUWo
+ { 404, 3, 1, 67, "VCTSXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #404 = VCTSXS
+ { 405, 3, 1, 67, "VCTUXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #405 = VCTUXS
+ { 406, 2, 1, 67, "VEXPTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #406 = VEXPTEFP
+ { 407, 2, 1, 67, "VLOGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #407 = VLOGEFP
+ { 408, 4, 1, 67, "VMADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #408 = VMADDFP
+ { 409, 3, 1, 67, "VMAXFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #409 = VMAXFP
+ { 410, 3, 1, 67, "VMAXSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #410 = VMAXSB
+ { 411, 3, 1, 67, "VMAXSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #411 = VMAXSH
+ { 412, 3, 1, 67, "VMAXSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #412 = VMAXSW
+ { 413, 3, 1, 67, "VMAXUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #413 = VMAXUB
+ { 414, 3, 1, 67, "VMAXUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #414 = VMAXUH
+ { 415, 3, 1, 67, "VMAXUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #415 = VMAXUW
+ { 416, 4, 1, 67, "VMHADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #416 = VMHADDSHS
+ { 417, 4, 1, 67, "VMHRADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #417 = VMHRADDSHS
+ { 418, 3, 1, 67, "VMINFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #418 = VMINFP
+ { 419, 3, 1, 67, "VMINSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #419 = VMINSB
+ { 420, 3, 1, 67, "VMINSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #420 = VMINSH
+ { 421, 3, 1, 67, "VMINSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #421 = VMINSW
+ { 422, 3, 1, 67, "VMINUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #422 = VMINUB
+ { 423, 3, 1, 67, "VMINUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #423 = VMINUH
+ { 424, 3, 1, 67, "VMINUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #424 = VMINUW
+ { 425, 4, 1, 67, "VMLADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #425 = VMLADDUHM
+ { 426, 3, 1, 67, "VMRGHB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #426 = VMRGHB
+ { 427, 3, 1, 67, "VMRGHH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #427 = VMRGHH
+ { 428, 3, 1, 67, "VMRGHW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #428 = VMRGHW
+ { 429, 3, 1, 67, "VMRGLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #429 = VMRGLB
+ { 430, 3, 1, 67, "VMRGLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #430 = VMRGLH
+ { 431, 3, 1, 67, "VMRGLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #431 = VMRGLW
+ { 432, 4, 1, 67, "VMSUMMBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #432 = VMSUMMBM
+ { 433, 4, 1, 67, "VMSUMSHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #433 = VMSUMSHM
+ { 434, 4, 1, 67, "VMSUMSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #434 = VMSUMSHS
+ { 435, 4, 1, 67, "VMSUMUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #435 = VMSUMUBM
+ { 436, 4, 1, 67, "VMSUMUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #436 = VMSUMUHM
+ { 437, 4, 1, 67, "VMSUMUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #437 = VMSUMUHS
+ { 438, 3, 1, 67, "VMULESB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #438 = VMULESB
+ { 439, 3, 1, 67, "VMULESH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #439 = VMULESH
+ { 440, 3, 1, 67, "VMULEUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #440 = VMULEUB
+ { 441, 3, 1, 67, "VMULEUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #441 = VMULEUH
+ { 442, 3, 1, 67, "VMULOSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #442 = VMULOSB
+ { 443, 3, 1, 67, "VMULOSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #443 = VMULOSH
+ { 444, 3, 1, 67, "VMULOUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #444 = VMULOUB
+ { 445, 3, 1, 67, "VMULOUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #445 = VMULOUH
+ { 446, 4, 1, 67, "VNMSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #446 = VNMSUBFP
+ { 447, 3, 1, 67, "VNOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #447 = VNOR
+ { 448, 3, 1, 67, "VOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #448 = VOR
+ { 449, 4, 1, 67, "VPERM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #449 = VPERM
+ { 450, 3, 1, 67, "VPKPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #450 = VPKPX
+ { 451, 3, 1, 67, "VPKSHSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #451 = VPKSHSS
+ { 452, 3, 1, 67, "VPKSHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #452 = VPKSHUS
+ { 453, 3, 1, 67, "VPKSWSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #453 = VPKSWSS
+ { 454, 3, 1, 67, "VPKSWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #454 = VPKSWUS
+ { 455, 3, 1, 67, "VPKUHUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #455 = VPKUHUM
+ { 456, 3, 1, 67, "VPKUHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #456 = VPKUHUS
+ { 457, 3, 1, 67, "VPKUWUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #457 = VPKUWUM
+ { 458, 3, 1, 67, "VPKUWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #458 = VPKUWUS
+ { 459, 2, 1, 67, "VREFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #459 = VREFP
+ { 460, 2, 1, 67, "VRFIM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #460 = VRFIM
+ { 461, 2, 1, 67, "VRFIN", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #461 = VRFIN
+ { 462, 2, 1, 67, "VRFIP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #462 = VRFIP
+ { 463, 2, 1, 67, "VRFIZ", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #463 = VRFIZ
+ { 464, 3, 1, 67, "VRLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #464 = VRLB
+ { 465, 3, 1, 67, "VRLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #465 = VRLH
+ { 466, 3, 1, 67, "VRLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #466 = VRLW
+ { 467, 2, 1, 67, "VRSQRTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #467 = VRSQRTEFP
+ { 468, 4, 1, 67, "VSEL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #468 = VSEL
+ { 469, 3, 1, 67, "VSL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #469 = VSL
+ { 470, 3, 1, 67, "VSLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #470 = VSLB
+ { 471, 4, 1, 67, "VSLDOI", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 }, // Inst #471 = VSLDOI
+ { 472, 3, 1, 67, "VSLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #472 = VSLH
+ { 473, 3, 1, 67, "VSLO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #473 = VSLO
+ { 474, 3, 1, 67, "VSLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #474 = VSLW
+ { 475, 3, 1, 71, "VSPLTB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #475 = VSPLTB
+ { 476, 3, 1, 71, "VSPLTH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #476 = VSPLTH
+ { 477, 2, 1, 71, "VSPLTISB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #477 = VSPLTISB
+ { 478, 2, 1, 71, "VSPLTISH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #478 = VSPLTISH
+ { 479, 2, 1, 71, "VSPLTISW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #479 = VSPLTISW
+ { 480, 3, 1, 71, "VSPLTW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #480 = VSPLTW
+ { 481, 3, 1, 67, "VSR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #481 = VSR
+ { 482, 3, 1, 67, "VSRAB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #482 = VSRAB
+ { 483, 3, 1, 67, "VSRAH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #483 = VSRAH
+ { 484, 3, 1, 67, "VSRAW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #484 = VSRAW
+ { 485, 3, 1, 67, "VSRB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #485 = VSRB
+ { 486, 3, 1, 67, "VSRH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #486 = VSRH
+ { 487, 3, 1, 67, "VSRO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #487 = VSRO
+ { 488, 3, 1, 67, "VSRW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #488 = VSRW
+ { 489, 3, 1, 67, "VSUBCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #489 = VSUBCUW
+ { 490, 3, 1, 70, "VSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #490 = VSUBFP
+ { 491, 3, 1, 67, "VSUBSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #491 = VSUBSBS
+ { 492, 3, 1, 67, "VSUBSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #492 = VSUBSHS
+ { 493, 3, 1, 67, "VSUBSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #493 = VSUBSWS
+ { 494, 3, 1, 70, "VSUBUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #494 = VSUBUBM
+ { 495, 3, 1, 67, "VSUBUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #495 = VSUBUBS
+ { 496, 3, 1, 70, "VSUBUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #496 = VSUBUHM
+ { 497, 3, 1, 67, "VSUBUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #497 = VSUBUHS
+ { 498, 3, 1, 70, "VSUBUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #498 = VSUBUWM
+ { 499, 3, 1, 67, "VSUBUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #499 = VSUBUWS
+ { 500, 3, 1, 67, "VSUM2SWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #500 = VSUM2SWS
+ { 501, 3, 1, 67, "VSUM4SBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #501 = VSUM4SBS
+ { 502, 3, 1, 67, "VSUM4SHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #502 = VSUM4SHS
+ { 503, 3, 1, 67, "VSUM4UBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #503 = VSUM4UBS
+ { 504, 3, 1, 67, "VSUMSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #504 = VSUMSWS
+ { 505, 2, 1, 67, "VUPKHPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #505 = VUPKHPX
+ { 506, 2, 1, 67, "VUPKHSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #506 = VUPKHSB
+ { 507, 2, 1, 67, "VUPKHSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #507 = VUPKHSH
+ { 508, 2, 1, 67, "VUPKLPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #508 = VUPKLPX
+ { 509, 2, 1, 67, "VUPKLSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #509 = VUPKLSB
+ { 510, 2, 1, 67, "VUPKLSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #510 = VUPKLSH
+ { 511, 3, 1, 67, "VXOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #511 = VXOR
+ { 512, 1, 1, 67, "V_SET0", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo62 }, // Inst #512 = V_SET0
+ { 513, 3, 1, 14, "XOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #513 = XOR
+ { 514, 3, 1, 14, "XOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #514 = XOR8
+ { 515, 3, 1, 14, "XORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #515 = XORI
+ { 516, 3, 1, 14, "XORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #516 = XORI8
+ { 517, 3, 1, 14, "XORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #517 = XORIS
+ { 518, 3, 1, 14, "XORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #518 = XORIS8
};
} // End llvm namespace
diff --git a/libclamav/c++/PPCGenInstrNames.inc b/libclamav/c++/PPCGenInstrNames.inc
index 792e4e5..d9c1a24 100644
--- a/libclamav/c++/PPCGenInstrNames.inc
+++ b/libclamav/c++/PPCGenInstrNames.inc
@@ -157,381 +157,379 @@ namespace PPC {
FDIVS = 144,
FMADD = 145,
FMADDS = 146,
- FMRD = 147,
- FMRS = 148,
- FMRSD = 149,
- FMSUB = 150,
- FMSUBS = 151,
- FMUL = 152,
- FMULS = 153,
- FNABSD = 154,
- FNABSS = 155,
- FNEGD = 156,
- FNEGS = 157,
- FNMADD = 158,
- FNMADDS = 159,
- FNMSUB = 160,
- FNMSUBS = 161,
- FRSP = 162,
- FSELD = 163,
- FSELS = 164,
- FSQRT = 165,
- FSQRTS = 166,
- FSUB = 167,
- FSUBS = 168,
- LA = 169,
- LBZ = 170,
- LBZ8 = 171,
- LBZU = 172,
- LBZU8 = 173,
- LBZX = 174,
- LBZX8 = 175,
- LD = 176,
- LDARX = 177,
- LDU = 178,
- LDX = 179,
- LDinto_toc = 180,
- LDtoc = 181,
- LDtoc_restore = 182,
- LFD = 183,
- LFDU = 184,
- LFDX = 185,
- LFS = 186,
- LFSU = 187,
- LFSX = 188,
- LHA = 189,
- LHA8 = 190,
- LHAU = 191,
- LHAU8 = 192,
- LHAX = 193,
- LHAX8 = 194,
- LHBRX = 195,
- LHZ = 196,
- LHZ8 = 197,
- LHZU = 198,
- LHZU8 = 199,
- LHZX = 200,
- LHZX8 = 201,
- LI = 202,
- LI8 = 203,
- LIS = 204,
- LIS8 = 205,
- LVEBX = 206,
- LVEHX = 207,
- LVEWX = 208,
- LVSL = 209,
- LVSR = 210,
- LVX = 211,
- LVXL = 212,
- LWA = 213,
- LWARX = 214,
- LWAX = 215,
- LWBRX = 216,
- LWZ = 217,
- LWZ8 = 218,
- LWZU = 219,
- LWZU8 = 220,
- LWZX = 221,
- LWZX8 = 222,
- MCRF = 223,
- MFCR = 224,
- MFCTR = 225,
- MFCTR8 = 226,
- MFFS = 227,
- MFLR = 228,
- MFLR8 = 229,
- MFOCRF = 230,
- MFVRSAVE = 231,
- MFVSCR = 232,
- MTCRF = 233,
- MTCTR = 234,
- MTCTR8 = 235,
- MTFSB0 = 236,
- MTFSB1 = 237,
- MTFSF = 238,
- MTLR = 239,
- MTLR8 = 240,
- MTVRSAVE = 241,
- MTVSCR = 242,
- MULHD = 243,
- MULHDU = 244,
- MULHW = 245,
- MULHWU = 246,
- MULLD = 247,
- MULLI = 248,
- MULLW = 249,
- MovePCtoLR = 250,
- MovePCtoLR8 = 251,
- NAND = 252,
- NAND8 = 253,
- NEG = 254,
- NEG8 = 255,
- NOP = 256,
- NOR = 257,
- NOR8 = 258,
- OR = 259,
- OR4To8 = 260,
- OR8 = 261,
- OR8To4 = 262,
- ORC = 263,
- ORC8 = 264,
- ORI = 265,
- ORI8 = 266,
- ORIS = 267,
- ORIS8 = 268,
- RLDCL = 269,
- RLDICL = 270,
- RLDICR = 271,
- RLDIMI = 272,
- RLWIMI = 273,
- RLWINM = 274,
- RLWINMo = 275,
- RLWNM = 276,
- SELECT_CC_F4 = 277,
- SELECT_CC_F8 = 278,
- SELECT_CC_I4 = 279,
- SELECT_CC_I8 = 280,
- SELECT_CC_VRRC = 281,
- SLD = 282,
- SLW = 283,
- SPILL_CR = 284,
- SRAD = 285,
- SRADI = 286,
- SRAW = 287,
- SRAWI = 288,
- SRD = 289,
- SRW = 290,
- STB = 291,
- STB8 = 292,
- STBU = 293,
- STBU8 = 294,
- STBX = 295,
- STBX8 = 296,
- STD = 297,
- STDCX = 298,
- STDU = 299,
- STDUX = 300,
- STDX = 301,
- STDX_32 = 302,
- STD_32 = 303,
- STFD = 304,
- STFDU = 305,
- STFDX = 306,
- STFIWX = 307,
- STFS = 308,
- STFSU = 309,
- STFSX = 310,
- STH = 311,
- STH8 = 312,
- STHBRX = 313,
- STHU = 314,
- STHU8 = 315,
- STHX = 316,
- STHX8 = 317,
- STVEBX = 318,
- STVEHX = 319,
- STVEWX = 320,
- STVX = 321,
- STVXL = 322,
- STW = 323,
- STW8 = 324,
- STWBRX = 325,
- STWCX = 326,
- STWU = 327,
- STWU8 = 328,
- STWUX = 329,
- STWX = 330,
- STWX8 = 331,
- SUBF = 332,
- SUBF8 = 333,
- SUBFC = 334,
- SUBFC8 = 335,
- SUBFE = 336,
- SUBFE8 = 337,
- SUBFIC = 338,
- SUBFIC8 = 339,
- SUBFME = 340,
- SUBFME8 = 341,
- SUBFZE = 342,
- SUBFZE8 = 343,
- SYNC = 344,
- TAILB = 345,
- TAILB8 = 346,
- TAILBA = 347,
- TAILBA8 = 348,
- TAILBCTR = 349,
- TAILBCTR8 = 350,
- TCRETURNai = 351,
- TCRETURNai8 = 352,
- TCRETURNdi = 353,
- TCRETURNdi8 = 354,
- TCRETURNri = 355,
- TCRETURNri8 = 356,
- TRAP = 357,
- UPDATE_VRSAVE = 358,
- VADDCUW = 359,
- VADDFP = 360,
- VADDSBS = 361,
- VADDSHS = 362,
- VADDSWS = 363,
- VADDUBM = 364,
- VADDUBS = 365,
- VADDUHM = 366,
- VADDUHS = 367,
- VADDUWM = 368,
- VADDUWS = 369,
- VAND = 370,
- VANDC = 371,
- VAVGSB = 372,
- VAVGSH = 373,
- VAVGSW = 374,
- VAVGUB = 375,
- VAVGUH = 376,
- VAVGUW = 377,
- VCFSX = 378,
- VCFUX = 379,
- VCMPBFP = 380,
- VCMPBFPo = 381,
- VCMPEQFP = 382,
- VCMPEQFPo = 383,
- VCMPEQUB = 384,
- VCMPEQUBo = 385,
- VCMPEQUH = 386,
- VCMPEQUHo = 387,
- VCMPEQUW = 388,
- VCMPEQUWo = 389,
- VCMPGEFP = 390,
- VCMPGEFPo = 391,
- VCMPGTFP = 392,
- VCMPGTFPo = 393,
- VCMPGTSB = 394,
- VCMPGTSBo = 395,
- VCMPGTSH = 396,
- VCMPGTSHo = 397,
- VCMPGTSW = 398,
- VCMPGTSWo = 399,
- VCMPGTUB = 400,
- VCMPGTUBo = 401,
- VCMPGTUH = 402,
- VCMPGTUHo = 403,
- VCMPGTUW = 404,
- VCMPGTUWo = 405,
- VCTSXS = 406,
- VCTUXS = 407,
- VEXPTEFP = 408,
- VLOGEFP = 409,
- VMADDFP = 410,
- VMAXFP = 411,
- VMAXSB = 412,
- VMAXSH = 413,
- VMAXSW = 414,
- VMAXUB = 415,
- VMAXUH = 416,
- VMAXUW = 417,
- VMHADDSHS = 418,
- VMHRADDSHS = 419,
- VMINFP = 420,
- VMINSB = 421,
- VMINSH = 422,
- VMINSW = 423,
- VMINUB = 424,
- VMINUH = 425,
- VMINUW = 426,
- VMLADDUHM = 427,
- VMRGHB = 428,
- VMRGHH = 429,
- VMRGHW = 430,
- VMRGLB = 431,
- VMRGLH = 432,
- VMRGLW = 433,
- VMSUMMBM = 434,
- VMSUMSHM = 435,
- VMSUMSHS = 436,
- VMSUMUBM = 437,
- VMSUMUHM = 438,
- VMSUMUHS = 439,
- VMULESB = 440,
- VMULESH = 441,
- VMULEUB = 442,
- VMULEUH = 443,
- VMULOSB = 444,
- VMULOSH = 445,
- VMULOUB = 446,
- VMULOUH = 447,
- VNMSUBFP = 448,
- VNOR = 449,
- VOR = 450,
- VPERM = 451,
- VPKPX = 452,
- VPKSHSS = 453,
- VPKSHUS = 454,
- VPKSWSS = 455,
- VPKSWUS = 456,
- VPKUHUM = 457,
- VPKUHUS = 458,
- VPKUWUM = 459,
- VPKUWUS = 460,
- VREFP = 461,
- VRFIM = 462,
- VRFIN = 463,
- VRFIP = 464,
- VRFIZ = 465,
- VRLB = 466,
- VRLH = 467,
- VRLW = 468,
- VRSQRTEFP = 469,
- VSEL = 470,
- VSL = 471,
- VSLB = 472,
- VSLDOI = 473,
- VSLH = 474,
- VSLO = 475,
- VSLW = 476,
- VSPLTB = 477,
- VSPLTH = 478,
- VSPLTISB = 479,
- VSPLTISH = 480,
- VSPLTISW = 481,
- VSPLTW = 482,
- VSR = 483,
- VSRAB = 484,
- VSRAH = 485,
- VSRAW = 486,
- VSRB = 487,
- VSRH = 488,
- VSRO = 489,
- VSRW = 490,
- VSUBCUW = 491,
- VSUBFP = 492,
- VSUBSBS = 493,
- VSUBSHS = 494,
- VSUBSWS = 495,
- VSUBUBM = 496,
- VSUBUBS = 497,
- VSUBUHM = 498,
- VSUBUHS = 499,
- VSUBUWM = 500,
- VSUBUWS = 501,
- VSUM2SWS = 502,
- VSUM4SBS = 503,
- VSUM4SHS = 504,
- VSUM4UBS = 505,
- VSUMSWS = 506,
- VUPKHPX = 507,
- VUPKHSB = 508,
- VUPKHSH = 509,
- VUPKLPX = 510,
- VUPKLSB = 511,
- VUPKLSH = 512,
- VXOR = 513,
- V_SET0 = 514,
- XOR = 515,
- XOR8 = 516,
- XORI = 517,
- XORI8 = 518,
- XORIS = 519,
- XORIS8 = 520,
- INSTRUCTION_LIST_END = 521
+ FMR = 147,
+ FMRSD = 148,
+ FMSUB = 149,
+ FMSUBS = 150,
+ FMUL = 151,
+ FMULS = 152,
+ FNABSD = 153,
+ FNABSS = 154,
+ FNEGD = 155,
+ FNEGS = 156,
+ FNMADD = 157,
+ FNMADDS = 158,
+ FNMSUB = 159,
+ FNMSUBS = 160,
+ FRSP = 161,
+ FSELD = 162,
+ FSELS = 163,
+ FSQRT = 164,
+ FSQRTS = 165,
+ FSUB = 166,
+ FSUBS = 167,
+ LA = 168,
+ LBZ = 169,
+ LBZ8 = 170,
+ LBZU = 171,
+ LBZU8 = 172,
+ LBZX = 173,
+ LBZX8 = 174,
+ LD = 175,
+ LDARX = 176,
+ LDU = 177,
+ LDX = 178,
+ LDinto_toc = 179,
+ LDtoc = 180,
+ LDtoc_restore = 181,
+ LFD = 182,
+ LFDU = 183,
+ LFDX = 184,
+ LFS = 185,
+ LFSU = 186,
+ LFSX = 187,
+ LHA = 188,
+ LHA8 = 189,
+ LHAU = 190,
+ LHAU8 = 191,
+ LHAX = 192,
+ LHAX8 = 193,
+ LHBRX = 194,
+ LHZ = 195,
+ LHZ8 = 196,
+ LHZU = 197,
+ LHZU8 = 198,
+ LHZX = 199,
+ LHZX8 = 200,
+ LI = 201,
+ LI8 = 202,
+ LIS = 203,
+ LIS8 = 204,
+ LVEBX = 205,
+ LVEHX = 206,
+ LVEWX = 207,
+ LVSL = 208,
+ LVSR = 209,
+ LVX = 210,
+ LVXL = 211,
+ LWA = 212,
+ LWARX = 213,
+ LWAX = 214,
+ LWBRX = 215,
+ LWZ = 216,
+ LWZ8 = 217,
+ LWZU = 218,
+ LWZU8 = 219,
+ LWZX = 220,
+ LWZX8 = 221,
+ MCRF = 222,
+ MFCR = 223,
+ MFCTR = 224,
+ MFCTR8 = 225,
+ MFFS = 226,
+ MFLR = 227,
+ MFLR8 = 228,
+ MFOCRF = 229,
+ MFVRSAVE = 230,
+ MFVSCR = 231,
+ MTCRF = 232,
+ MTCTR = 233,
+ MTCTR8 = 234,
+ MTFSB0 = 235,
+ MTFSB1 = 236,
+ MTFSF = 237,
+ MTLR = 238,
+ MTLR8 = 239,
+ MTVRSAVE = 240,
+ MTVSCR = 241,
+ MULHD = 242,
+ MULHDU = 243,
+ MULHW = 244,
+ MULHWU = 245,
+ MULLD = 246,
+ MULLI = 247,
+ MULLW = 248,
+ MovePCtoLR = 249,
+ MovePCtoLR8 = 250,
+ NAND = 251,
+ NAND8 = 252,
+ NEG = 253,
+ NEG8 = 254,
+ NOP = 255,
+ NOR = 256,
+ NOR8 = 257,
+ OR = 258,
+ OR4To8 = 259,
+ OR8 = 260,
+ OR8To4 = 261,
+ ORC = 262,
+ ORC8 = 263,
+ ORI = 264,
+ ORI8 = 265,
+ ORIS = 266,
+ ORIS8 = 267,
+ RLDCL = 268,
+ RLDICL = 269,
+ RLDICR = 270,
+ RLDIMI = 271,
+ RLWIMI = 272,
+ RLWINM = 273,
+ RLWINMo = 274,
+ RLWNM = 275,
+ SELECT_CC_F4 = 276,
+ SELECT_CC_F8 = 277,
+ SELECT_CC_I4 = 278,
+ SELECT_CC_I8 = 279,
+ SELECT_CC_VRRC = 280,
+ SLD = 281,
+ SLW = 282,
+ SPILL_CR = 283,
+ SRAD = 284,
+ SRADI = 285,
+ SRAW = 286,
+ SRAWI = 287,
+ SRD = 288,
+ SRW = 289,
+ STB = 290,
+ STB8 = 291,
+ STBU = 292,
+ STBU8 = 293,
+ STBX = 294,
+ STBX8 = 295,
+ STD = 296,
+ STDCX = 297,
+ STDU = 298,
+ STDUX = 299,
+ STDX = 300,
+ STDX_32 = 301,
+ STD_32 = 302,
+ STFD = 303,
+ STFDU = 304,
+ STFDX = 305,
+ STFIWX = 306,
+ STFS = 307,
+ STFSU = 308,
+ STFSX = 309,
+ STH = 310,
+ STH8 = 311,
+ STHBRX = 312,
+ STHU = 313,
+ STHU8 = 314,
+ STHX = 315,
+ STHX8 = 316,
+ STVEBX = 317,
+ STVEHX = 318,
+ STVEWX = 319,
+ STVX = 320,
+ STVXL = 321,
+ STW = 322,
+ STW8 = 323,
+ STWBRX = 324,
+ STWCX = 325,
+ STWU = 326,
+ STWUX = 327,
+ STWX = 328,
+ STWX8 = 329,
+ SUBF = 330,
+ SUBF8 = 331,
+ SUBFC = 332,
+ SUBFC8 = 333,
+ SUBFE = 334,
+ SUBFE8 = 335,
+ SUBFIC = 336,
+ SUBFIC8 = 337,
+ SUBFME = 338,
+ SUBFME8 = 339,
+ SUBFZE = 340,
+ SUBFZE8 = 341,
+ SYNC = 342,
+ TAILB = 343,
+ TAILB8 = 344,
+ TAILBA = 345,
+ TAILBA8 = 346,
+ TAILBCTR = 347,
+ TAILBCTR8 = 348,
+ TCRETURNai = 349,
+ TCRETURNai8 = 350,
+ TCRETURNdi = 351,
+ TCRETURNdi8 = 352,
+ TCRETURNri = 353,
+ TCRETURNri8 = 354,
+ TRAP = 355,
+ UPDATE_VRSAVE = 356,
+ VADDCUW = 357,
+ VADDFP = 358,
+ VADDSBS = 359,
+ VADDSHS = 360,
+ VADDSWS = 361,
+ VADDUBM = 362,
+ VADDUBS = 363,
+ VADDUHM = 364,
+ VADDUHS = 365,
+ VADDUWM = 366,
+ VADDUWS = 367,
+ VAND = 368,
+ VANDC = 369,
+ VAVGSB = 370,
+ VAVGSH = 371,
+ VAVGSW = 372,
+ VAVGUB = 373,
+ VAVGUH = 374,
+ VAVGUW = 375,
+ VCFSX = 376,
+ VCFUX = 377,
+ VCMPBFP = 378,
+ VCMPBFPo = 379,
+ VCMPEQFP = 380,
+ VCMPEQFPo = 381,
+ VCMPEQUB = 382,
+ VCMPEQUBo = 383,
+ VCMPEQUH = 384,
+ VCMPEQUHo = 385,
+ VCMPEQUW = 386,
+ VCMPEQUWo = 387,
+ VCMPGEFP = 388,
+ VCMPGEFPo = 389,
+ VCMPGTFP = 390,
+ VCMPGTFPo = 391,
+ VCMPGTSB = 392,
+ VCMPGTSBo = 393,
+ VCMPGTSH = 394,
+ VCMPGTSHo = 395,
+ VCMPGTSW = 396,
+ VCMPGTSWo = 397,
+ VCMPGTUB = 398,
+ VCMPGTUBo = 399,
+ VCMPGTUH = 400,
+ VCMPGTUHo = 401,
+ VCMPGTUW = 402,
+ VCMPGTUWo = 403,
+ VCTSXS = 404,
+ VCTUXS = 405,
+ VEXPTEFP = 406,
+ VLOGEFP = 407,
+ VMADDFP = 408,
+ VMAXFP = 409,
+ VMAXSB = 410,
+ VMAXSH = 411,
+ VMAXSW = 412,
+ VMAXUB = 413,
+ VMAXUH = 414,
+ VMAXUW = 415,
+ VMHADDSHS = 416,
+ VMHRADDSHS = 417,
+ VMINFP = 418,
+ VMINSB = 419,
+ VMINSH = 420,
+ VMINSW = 421,
+ VMINUB = 422,
+ VMINUH = 423,
+ VMINUW = 424,
+ VMLADDUHM = 425,
+ VMRGHB = 426,
+ VMRGHH = 427,
+ VMRGHW = 428,
+ VMRGLB = 429,
+ VMRGLH = 430,
+ VMRGLW = 431,
+ VMSUMMBM = 432,
+ VMSUMSHM = 433,
+ VMSUMSHS = 434,
+ VMSUMUBM = 435,
+ VMSUMUHM = 436,
+ VMSUMUHS = 437,
+ VMULESB = 438,
+ VMULESH = 439,
+ VMULEUB = 440,
+ VMULEUH = 441,
+ VMULOSB = 442,
+ VMULOSH = 443,
+ VMULOUB = 444,
+ VMULOUH = 445,
+ VNMSUBFP = 446,
+ VNOR = 447,
+ VOR = 448,
+ VPERM = 449,
+ VPKPX = 450,
+ VPKSHSS = 451,
+ VPKSHUS = 452,
+ VPKSWSS = 453,
+ VPKSWUS = 454,
+ VPKUHUM = 455,
+ VPKUHUS = 456,
+ VPKUWUM = 457,
+ VPKUWUS = 458,
+ VREFP = 459,
+ VRFIM = 460,
+ VRFIN = 461,
+ VRFIP = 462,
+ VRFIZ = 463,
+ VRLB = 464,
+ VRLH = 465,
+ VRLW = 466,
+ VRSQRTEFP = 467,
+ VSEL = 468,
+ VSL = 469,
+ VSLB = 470,
+ VSLDOI = 471,
+ VSLH = 472,
+ VSLO = 473,
+ VSLW = 474,
+ VSPLTB = 475,
+ VSPLTH = 476,
+ VSPLTISB = 477,
+ VSPLTISH = 478,
+ VSPLTISW = 479,
+ VSPLTW = 480,
+ VSR = 481,
+ VSRAB = 482,
+ VSRAH = 483,
+ VSRAW = 484,
+ VSRB = 485,
+ VSRH = 486,
+ VSRO = 487,
+ VSRW = 488,
+ VSUBCUW = 489,
+ VSUBFP = 490,
+ VSUBSBS = 491,
+ VSUBSHS = 492,
+ VSUBSWS = 493,
+ VSUBUBM = 494,
+ VSUBUBS = 495,
+ VSUBUHM = 496,
+ VSUBUHS = 497,
+ VSUBUWM = 498,
+ VSUBUWS = 499,
+ VSUM2SWS = 500,
+ VSUM4SBS = 501,
+ VSUM4SHS = 502,
+ VSUM4UBS = 503,
+ VSUMSWS = 504,
+ VUPKHPX = 505,
+ VUPKHSB = 506,
+ VUPKHSH = 507,
+ VUPKLPX = 508,
+ VUPKLSB = 509,
+ VUPKLSH = 510,
+ VXOR = 511,
+ V_SET0 = 512,
+ XOR = 513,
+ XOR8 = 514,
+ XORI = 515,
+ XORI8 = 516,
+ XORIS = 517,
+ XORIS8 = 518,
+ INSTRUCTION_LIST_END = 519
};
}
} // End llvm namespace
diff --git a/libclamav/c++/PPCGenRegisterInfo.inc b/libclamav/c++/PPCGenRegisterInfo.inc
index ea90909..3a88052 100644
--- a/libclamav/c++/PPCGenRegisterInfo.inc
+++ b/libclamav/c++/PPCGenRegisterInfo.inc
@@ -372,10 +372,8 @@ F8RCClass::F8RCClass() : TargetRegisterClass(F8RCRegClassID, "F8RC", F8RCVTs, F
G8RCClass::iterator
G8RCClass::allocation_order_begin(const MachineFunction &MF) const {
// 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
- if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
- return begin()+1;
-
- return begin();
+ // Darwin: r2 is reserved for CR save/restore sequence.
+ return begin()+1;
}
G8RCClass::iterator
G8RCClass::allocation_order_end(const MachineFunction &MF) const {
@@ -391,10 +389,8 @@ G8RCClass::G8RCClass() : TargetRegisterClass(G8RCRegClassID, "G8RC", G8RCVTs, G
GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
// 32-bit SVR4 ABI: r2 is reserved for the OS.
// 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
- if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
- return begin()+1;
-
- return begin();
+ // Darwin: R2 is reserved for CR save/restore sequence.
+ return begin()+1;
}
GPRCClass::iterator
GPRCClass::allocation_order_end(const MachineFunction &MF) const {
diff --git a/libclamav/c++/X86GenAsmMatcher.inc b/libclamav/c++/X86GenAsmMatcher.inc
index 5bc8928..792085a 100644
--- a/libclamav/c++/X86GenAsmMatcher.inc
+++ b/libclamav/c++/X86GenAsmMatcher.inc
@@ -6293,7 +6293,7 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
unsigned Opcode;
ConversionKind ConvertFn;
MatchClassKind Classes[5];
- } MatchTable[2049] = {
+ } MatchTable[2037] = {
{ X86::CBW, Convert, { MCK_cbtw } },
{ X86::CLC, Convert, { MCK_clc } },
{ X86::CLD, Convert, { MCK_cld } },
@@ -7364,9 +7364,11 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
{ X86::MOVLPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_movlps, MCK_Mem, MCK_FR32 } },
{ X86::MOVMSKPDrr, Convert__Reg1_2__Reg1_1, { MCK_movmskpd, MCK_FR32, MCK_GR32 } },
{ X86::MOVMSKPSrr, Convert__Reg1_2__Reg1_1, { MCK_movmskps, MCK_FR32, MCK_GR32 } },
+ { X86::MOVNTDQ_64mr, Convert__Mem5_2__Reg1_1, { MCK_movntdq, MCK_FR32, MCK_Mem } },
{ X86::MOVNTDQmr, Convert__Mem5_2__Reg1_1, { MCK_movntdq, MCK_FR32, MCK_Mem } },
{ X86::MOVNTDQArm, Convert__Reg1_2__Mem5_1, { MCK_movntdqa, MCK_Mem, MCK_FR32 } },
{ X86::MOVNTImr, Convert__Mem5_2__Reg1_1, { MCK_movnti, MCK_GR32, MCK_Mem } },
+ { X86::MOVNTI_64mr, Convert__Mem5_2__Reg1_1, { MCK_movnti, MCK_GR64, MCK_Mem } },
{ X86::MOVNTPDmr, Convert__Mem5_2__Reg1_1, { MCK_movntpd, MCK_FR32, MCK_Mem } },
{ X86::MOVNTPSmr, Convert__Mem5_2__Reg1_1, { MCK_movntps, MCK_FR32, MCK_Mem } },
{ X86::MMX_MOVNTQmr, Convert__Mem5_2__Reg1_1, { MCK_movntq, MCK_VR64, MCK_Mem } },
@@ -7411,32 +7413,18 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
{ X86::MOVSX64rm8, Convert__Reg1_2__Mem5_1, { MCK_movsbq, MCK_Mem, MCK_GR64 } },
{ X86::MOVSX16rr8W, Convert__Reg1_2__Reg1_1, { MCK_movsbw, MCK_GR8, MCK_GR16 } },
{ X86::MOVSX16rm8W, Convert__Reg1_2__Mem5_1, { MCK_movsbw, MCK_Mem, MCK_GR16 } },
- { X86::MOVLPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVLSD2PDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVPD2SDrr, Convert__Reg1_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVSD2PDrr, Convert__Reg1_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVSDrr, Convert__Reg1_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVPD2SDmr, Convert__Mem5_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
+ { X86::MOVSDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVSDmr, Convert__Mem5_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
- { X86::MOVSD2PDrm, Convert__Reg1_2__Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
{ X86::MOVSDrm, Convert__Reg1_2__Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
- { X86::MOVZSD2PDrm, Convert__Reg1_2__Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
{ X86::MOVSHDUPrr, Convert__Reg1_2__Reg1_1, { MCK_movshdup, MCK_FR32, MCK_FR32 } },
{ X86::MOVSHDUPrm, Convert__Reg1_2__Mem5_1, { MCK_movshdup, MCK_Mem, MCK_FR32 } },
{ X86::MOVSLDUPrr, Convert__Reg1_2__Reg1_1, { MCK_movsldup, MCK_FR32, MCK_FR32 } },
{ X86::MOVSLDUPrm, Convert__Reg1_2__Mem5_1, { MCK_movsldup, MCK_Mem, MCK_FR32 } },
{ X86::MOVSX64rr32, Convert__Reg1_2__Reg1_1, { MCK_movslq, MCK_GR32, MCK_GR64 } },
{ X86::MOVSX64rm32, Convert__Reg1_2__Mem5_1, { MCK_movslq, MCK_Mem, MCK_GR64 } },
- { X86::MOVLPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVLSS2PSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVPS2SSrr, Convert__Reg1_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVSS2PSrr, Convert__Reg1_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVSSrr, Convert__Reg1_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVPS2SSmr, Convert__Mem5_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
+ { X86::MOVSSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVSSmr, Convert__Mem5_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
- { X86::MOVSS2PSrm, Convert__Reg1_2__Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
{ X86::MOVSSrm, Convert__Reg1_2__Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
- { X86::MOVZSS2PSrm, Convert__Reg1_2__Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
{ X86::MOVSX32rr16, Convert__Reg1_2__Reg1_1, { MCK_movswl, MCK_GR16, MCK_GR32 } },
{ X86::MOVSX32rm16, Convert__Reg1_2__Mem5_1, { MCK_movswl, MCK_Mem, MCK_GR32 } },
{ X86::MOVSX64rr16, Convert__Reg1_2__Reg1_1, { MCK_movswq, MCK_GR16, MCK_GR64 } },
@@ -8364,7 +8352,7 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
Classes[i] = InvalidMatchClass;
// Search the table.
- for (const MatchEntry *it = MatchTable, *ie = MatchTable + 2049; it != ie; ++it) {
+ for (const MatchEntry *it = MatchTable, *ie = MatchTable + 2037; it != ie; ++it) {
if (!IsSubclass(Classes[0], it->Classes[0]))
continue;
if (!IsSubclass(Classes[1], it->Classes[1]))
diff --git a/libclamav/c++/X86GenAsmWriter.inc b/libclamav/c++/X86GenAsmWriter.inc
index bf99ac6..9e228ea 100644
--- a/libclamav/c++/X86GenAsmWriter.inc
+++ b/libclamav/c++/X86GenAsmWriter.inc
@@ -1358,51 +1358,45 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
205657149U, // MOVLHPSrr
138286150U, // MOVLPDmr
603984966U, // MOVLPDrm
- 205657166U, // MOVLPDrr
- 138286165U, // MOVLPSmr
- 603984981U, // MOVLPSrm
- 205657181U, // MOVLPSrr
+ 138286158U, // MOVLPSmr
+ 603984974U, // MOVLPSrm
136712635U, // MOVLQ128mr
- 205657166U, // MOVLSD2PDrr
- 205657181U, // MOVLSS2PSrr
- 1279399012U, // MOVMSKPDrr
- 1279399022U, // MOVMSKPSrr
- 2281706616U, // MOVNTDQArm
- 138024066U, // MOVNTDQmr
- 136582283U, // MOVNTImr
- 138155155U, // MOVNTPDmr
- 138155164U, // MOVNTPSmr
+ 1279398998U, // MOVMSKPDrr
+ 1279399008U, // MOVMSKPSrr
+ 2281706602U, // MOVNTDQArm
+ 138024052U, // MOVNTDQ_64mr
+ 138024052U, // MOVNTDQmr
+ 138024052U, // MOVNTDQmr_Int
+ 136713341U, // MOVNTI_64mr
+ 136582269U, // MOVNTImr
+ 136582269U, // MOVNTImr_Int
+ 138024069U, // MOVNTPDmr
+ 138155141U, // MOVNTPDmr_Int
+ 138024078U, // MOVNTPSmr
+ 138155150U, // MOVNTPSmr_Int
0U, // MOVPC32r
- 138286158U, // MOVPD2SDmr
- 1279398990U, // MOVPD2SDrr
136581531U, // MOVPDI2DImr
1279398299U, // MOVPDI2DIrr
136712635U, // MOVPQI2QImr
1279398299U, // MOVPQIto64rr
- 137630813U, // MOVPS2SSmr
- 1279399005U, // MOVPS2SSrr
1409290683U, // MOVQI2PQIrm
1279398331U, // MOVQxrxr
- 5285U, // MOVSB
- 5291U, // MOVSD
- 2013271118U, // MOVSD2PDrm
- 1279398990U, // MOVSD2PDrr
- 138286158U, // MOVSDmr
- 2013271118U, // MOVSDrm
- 1279398990U, // MOVSDrr
+ 5271U, // MOVSB
+ 5277U, // MOVSD
+ 138286243U, // MOVSDmr
+ 2013271203U, // MOVSDrm
+ 205657251U, // MOVSDrr
136712635U, // MOVSDto64mr
1279398299U, // MOVSDto64rr
- 1946162353U, // MOVSHDUPrm
- 1279399089U, // MOVSHDUPrr
- 1946162363U, // MOVSLDUPrm
- 1279399099U, // MOVSLDUPrr
+ 1946162346U, // MOVSHDUPrm
+ 1279399082U, // MOVSHDUPrr
+ 1946162356U, // MOVSLDUPrm
+ 1279399092U, // MOVSLDUPrr
136581531U, // MOVSS2DImr
1279398299U, // MOVSS2DIrr
- 2080379997U, // MOVSS2PSrm
- 1279399005U, // MOVSS2PSrr
- 137630813U, // MOVSSmr
- 2080379997U, // MOVSSrm
- 1279399005U, // MOVSSrr
+ 137630910U, // MOVSSmr
+ 2080380094U, // MOVSSrm
+ 205657278U, // MOVSSrr
5317U, // MOVSW
0U, // MOVSX16rm8
1690309835U, // MOVSX16rm8W
@@ -1434,8 +1428,6 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
1279398331U, // MOVZPQILo2PQIrr
1409290683U, // MOVZQI2PQIrm
1279398299U, // MOVZQI2PQIrr
- 2013271118U, // MOVZSD2PDrm
- 2080379997U, // MOVZSS2PSrm
0U, // MOVZX16rm8
1690309899U, // MOVZX16rm8W
0U, // MOVZX16rr8
@@ -2649,9 +2641,9 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
"r\t\000monitor\000movw\t%ax, \000movw\t\000movl\t%eax, \000movl\t\000mo"
"vq\t%fs:\000movq\t%gs:\000movq\t%rax, \000movabsq\t\000movb\t%al, \000m"
"ovb\t\000movddup\t\000movdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000"
- "movhps\t\000movlhps\t\000movlpd\t\000movsd\t\000movlps\t\000movss\t\000"
- "movmskpd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000movnti\t\000movn"
- "tpd\t\000movntps\t\000movsb\000movsl\000movshdup\t\000movsldup\t\000mov"
+ "movhps\t\000movlhps\t\000movlpd\t\000movlps\t\000movmskpd\t\000movmskps"
+ "\t\000movntdqa\t\000movntdq\t\000movnti\t\000movntpd\t\000movntps\t\000"
+ "movsb\000movsl\000movsd\t\000movshdup\t\000movsldup\t\000movss\t\000mov"
"sw\000movsbw\t\000movswl\t\000movsbl\t\000movswq\t\000movslq\t\000movsb"
"q\t\000movupd\t\000movups\t\000movzbw\t\000movzbl\t\000movzwl\t\000movz"
"wq\t\000movzbq\t\000mpsadbw\t\000mulw\t\000mull\t\000mulq\t\000mulb\t\000"
@@ -3206,7 +3198,7 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
break;
case 10:
- // EXTRACTPSmr, MOVPS2SSmr, MOVSSmr
+ // EXTRACTPSmr, MOVSSmr
printf32mem(MI, 0);
return;
break;
@@ -3222,17 +3214,17 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 13:
- // MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVUPDmr, MOVUPDmr_Int, MOVUPSmr, MOVUP...
+ // MOVAPDmr, MOVAPSmr, MOVNTDQ_64mr, MOVNTDQmr, MOVNTDQmr_Int, MOVNTPDmr,...
printf128mem(MI, 0);
return;
break;
case 14:
- // MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr, MOVNTPSmr
+ // MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr_Int, MOVNTPSmr_Int
printi128mem(MI, 0);
return;
break;
case 15:
- // MOVHPDmr, MOVHPSmr, MOVLPDmr, MOVLPSmr, MOVPD2SDmr, MOVSDmr
+ // MOVHPDmr, MOVHPSmr, MOVLPDmr, MOVLPSmr, MOVSDmr
printf64mem(MI, 0);
return;
break;
@@ -3312,7 +3304,7 @@ const char *X86ATTInstPrinter::getRegisterName(unsigned RegNo) {
/// from the instruction set description. This returns the enum name of the
/// specified instruction.
const char *X86ATTInstPrinter::getInstructionName(unsigned Opcode) {
- assert(Opcode < 2532 && "Invalid instruction number!");
+ assert(Opcode < 2524 && "Invalid instruction number!");
static const unsigned InstAsmOffset[] = {
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 136,
@@ -3411,91 +3403,91 @@ const char *X86ATTInstPrinter::getInstructionName(unsigned Opcode) {
13388, 13400, 13408, 13416, 13424, 13437, 13449, 13461, 13469, 13476, 13483, 13496, 13504, 13511,
13518, 13525, 13538, 13545, 13558, 13569, 13578, 13587, 13596, 13605, 13614, 13623, 13633, 13643,
13655, 13667, 13678, 13689, 13698, 13707, 13716, 13725, 13738, 13747, 13760, 13770, 13779, 13788,
- 13797, 13806, 13816, 13825, 13834, 13843, 13852, 13861, 13870, 13881, 13893, 13905, 13916, 13927,
- 13938, 13948, 13957, 13967, 13977, 13986, 13997, 14008, 14020, 14032, 14044, 14057, 14068, 14079,
- 14091, 14100, 14106, 14112, 14123, 14134, 14142, 14150, 14158, 14170, 14182, 14193, 14204, 14215,
- 14226, 14237, 14248, 14259, 14270, 14278, 14286, 14294, 14300, 14311, 14323, 14334, 14346, 14358,
- 14369, 14381, 14392, 14404, 14416, 14427, 14439, 14451, 14462, 14471, 14484, 14493, 14506, 14515,
- 14524, 14537, 14546, 14559, 14568, 14581, 14594, 14610, 14626, 14639, 14652, 14664, 14676, 14687,
- 14699, 14710, 14722, 14739, 14756, 14768, 14779, 14791, 14802, 14814, 14828, 14840, 14851, 14864,
- 14876, 14890, 14902, 14913, 14926, 14937, 14948, 14959, 14970, 14981, 14992, 15003, 15014, 15025,
- 15036, 15047, 15054, 15061, 15068, 15075, 15082, 15089, 15095, 15101, 15109, 15117, 15125, 15133,
- 15141, 15153, 15161, 15173, 15181, 15193, 15201, 15213, 15222, 15231, 15241, 15251, 15262, 15272,
- 15281, 15291, 15300, 15310, 15322, 15331, 15343, 15355, 15368, 15381, 15394, 15407, 15420, 15433,
- 15443, 15449, 15456, 15463, 15470, 15477, 15484, 15491, 15497, 15503, 15508, 15514, 15520, 15527,
- 15534, 15541, 15548, 15555, 15562, 15568, 15574, 15582, 15589, 15597, 15604, 15611, 15619, 15626,
- 15633, 15644, 15652, 15659, 15667, 15674, 15681, 15689, 15696, 15703, 15714, 15722, 15731, 15739,
- 15746, 15755, 15763, 15770, 15777, 15788, 15794, 15800, 15806, 15812, 15818, 15824, 15834, 15841,
- 15848, 15855, 15862, 15870, 15878, 15886, 15894, 15901, 15908, 15914, 15920, 15926, 15937, 15947,
- 15958, 15968, 15979, 15989, 16000, 16010, 16021, 16031, 16042, 16052, 16063, 16074, 16085, 16096,
- 16107, 16118, 16129, 16140, 16148, 16156, 16164, 16172, 16180, 16188, 16197, 16206, 16215, 16224,
- 16234, 16244, 16254, 16264, 16272, 16280, 16293, 16306, 16318, 16330, 16338, 16346, 16353, 16360,
- 16368, 16376, 16384, 16392, 16404, 16416, 16427, 16438, 16448, 16458, 16468, 16478, 16488, 16498,
- 16508, 16518, 16531, 16544, 16557, 16570, 16583, 16596, 16609, 16622, 16635, 16648, 16660, 16672,
- 16688, 16704, 16719, 16734, 16744, 16754, 16764, 16774, 16784, 16794, 16804, 16814, 16827, 16840,
- 16853, 16866, 16879, 16892, 16905, 16918, 16931, 16944, 16956, 16968, 16984, 17000, 17015, 17030,
- 17039, 17048, 17057, 17066, 17075, 17084, 17093, 17102, 17114, 17125, 17137, 17148, 17161, 17173,
- 17186, 17198, 17210, 17221, 17233, 17244, 17260, 17276, 17288, 17299, 17311, 17322, 17335, 17347,
- 17360, 17372, 17384, 17395, 17407, 17418, 17427, 17436, 17445, 17454, 17463, 17472, 17482, 17492,
- 17507, 17521, 17536, 17550, 17560, 17570, 17579, 17588, 17597, 17606, 17615, 17624, 17633, 17642,
- 17651, 17660, 17669, 17678, 17687, 17696, 17705, 17714, 17723, 17732, 17741, 17750, 17759, 17768,
- 17777, 17786, 17797, 17808, 17819, 17830, 17841, 17852, 17863, 17874, 17885, 17896, 17907, 17918,
- 17929, 17940, 17951, 17962, 17973, 17984, 17995, 18006, 18017, 18028, 18039, 18050, 18061, 18070,
- 18079, 18093, 18106, 18120, 18133, 18143, 18153, 18162, 18171, 18180, 18193, 18202, 18215, 18224,
- 18233, 18243, 18253, 18260, 18269, 18278, 18285, 18294, 18303, 18310, 18319, 18328, 18339, 18350,
- 18361, 18372, 18383, 18394, 18399, 18405, 18411, 18419, 18427, 18435, 18443, 18451, 18459, 18465,
- 18471, 18483, 18494, 18505, 18516, 18525, 18534, 18546, 18557, 18569, 18580, 18589, 18598, 18608,
- 18618, 18628, 18638, 18650, 18661, 18673, 18684, 18696, 18707, 18719, 18730, 18742, 18753, 18765,
- 18776, 18785, 18793, 18801, 18809, 18817, 18825, 18833, 18841, 18849, 18857, 18865, 18873, 18881,
- 18889, 18897, 18905, 18914, 18922, 18930, 18938, 18946, 18954, 18962, 18970, 18978, 18986, 18994,
- 19002, 19010, 19018, 19026, 19034, 19043, 19052, 19061, 19070, 19080, 19090, 19100, 19110, 19118,
- 19126, 19134, 19142, 19154, 19166, 19178, 19190, 19203, 19216, 19228, 19240, 19252, 19264, 19276,
- 19288, 19301, 19314, 19326, 19338, 19346, 19356, 19366, 19376, 19386, 19395, 19403, 19413, 19423,
- 19433, 19443, 19452, 19460, 19470, 19480, 19486, 19493, 19502, 19511, 19520, 19529, 19538, 19547,
- 19556, 19563, 19570, 19578, 19587, 19595, 19603, 19612, 19620, 19628, 19637, 19645, 19653, 19662,
- 19670, 19678, 19687, 19695, 19703, 19712, 19720, 19727, 19735, 19742, 19749, 19757, 19764, 19771,
- 19782, 19789, 19800, 19807, 19818, 19825, 19836, 19844, 19853, 19861, 19869, 19878, 19886, 19894,
- 19903, 19911, 19919, 19928, 19936, 19944, 19953, 19961, 19969, 19978, 19986, 19993, 20001, 20008,
- 20015, 20023, 20030, 20036, 20042, 20048, 20055, 20068, 20078, 20088, 20098, 20108, 20119, 20129,
- 20139, 20149, 20159, 20163, 20168, 20176, 20185, 20193, 20201, 20210, 20218, 20226, 20235, 20243,
- 20251, 20260, 20268, 20276, 20285, 20293, 20301, 20310, 20318, 20325, 20333, 20340, 20347, 20355,
- 20362, 20370, 20379, 20387, 20395, 20404, 20412, 20420, 20429, 20437, 20445, 20454, 20462, 20470,
- 20479, 20487, 20495, 20504, 20512, 20519, 20527, 20534, 20541, 20549, 20556, 20569, 20582, 20595,
- 20608, 20621, 20634, 20647, 20660, 20664, 20673, 20686, 20695, 20708, 20717, 20730, 20739, 20752,
- 20757, 20765, 20774, 20782, 20790, 20799, 20807, 20815, 20824, 20832, 20840, 20849, 20857, 20865,
- 20874, 20882, 20890, 20899, 20907, 20914, 20922, 20929, 20936, 20944, 20951, 20960, 20968, 20977,
- 20985, 20993, 21002, 21010, 21018, 21030, 21039, 21047, 21056, 21064, 21072, 21081, 21089, 21097,
- 21109, 21118, 21128, 21137, 21145, 21155, 21164, 21172, 21180, 21192, 21199, 21206, 21213, 21220,
- 21227, 21234, 21245, 21252, 21259, 21266, 21272, 21279, 21286, 21292, 21298, 21305, 21312, 21322,
- 21332, 21342, 21351, 21357, 21363, 21369, 21375, 21382, 21389, 21395, 21401, 21408, 21415, 21421,
- 21427, 21434, 21441, 21448, 21455, 21462, 21469, 21476, 21483, 21489, 21495, 21501, 21507, 21513,
- 21519, 21526, 21532, 21540, 21549, 21557, 21565, 21574, 21582, 21590, 21599, 21607, 21615, 21624,
- 21632, 21640, 21649, 21657, 21665, 21674, 21682, 21689, 21697, 21704, 21711, 21719, 21726, 21737,
- 21748, 21759, 21770, 21781, 21792, 21803, 21814, 21825, 21836, 21847, 21858, 21866, 21875, 21883,
- 21891, 21900, 21908, 21916, 21925, 21933, 21941, 21950, 21958, 21966, 21975, 21983, 21991, 22000,
- 22008, 22015, 22023, 22030, 22037, 22045, 22052, 22063, 22074, 22085, 22096, 22107, 22118, 22129,
- 22140, 22151, 22162, 22173, 22184, 22194, 22204, 22214, 22224, 22230, 22236, 22245, 22254, 22263,
- 22271, 22279, 22287, 22295, 22303, 22311, 22319, 22327, 22335, 22347, 22355, 22367, 22375, 22387,
- 22395, 22407, 22415, 22427, 22435, 22447, 22455, 22467, 22475, 22487, 22494, 22504, 22514, 22524,
- 22534, 22538, 22542, 22546, 22554, 22560, 22566, 22572, 22577, 22582, 22590, 22598, 22607, 22616,
- 22625, 22633, 22642, 22651, 22662, 22673, 22684, 22694, 22704, 22716, 22726, 22738, 22750, 22757,
- 22766, 22774, 22783, 22791, 22799, 22808, 22816, 22824, 22836, 22845, 22853, 22862, 22870, 22878,
- 22887, 22895, 22903, 22915, 22924, 22934, 22943, 22951, 22961, 22970, 22978, 22986, 22998, 23005,
- 23012, 23019, 23026, 23033, 23040, 23051, 23059, 23067, 23075, 23083, 23093, 23103, 23114, 23125,
- 23137, 23148, 23159, 23170, 23183, 23196, 23209, 23223, 23237, 23251, 23265, 23279, 23293, 23304,
- 23312, 23324, 23332, 23344, 23352, 23364, 23372, 23384, 23393, 23402, 23412, 23422, 23433, 23443,
- 23452, 23462, 23471, 23481, 23493, 23502, 23514, 23526, 23539, 23552, 23565, 23578, 23591, 23604,
- 23614, 23621, 23629, 23638, 23646, 23656, 23663, 23672, 23681, 23690, 23701, 23712, 23725, 23736,
- 23749, 23759, 23768, 23777, 23786, 23795, 23805, 23814, 23823, 23832, 23841, 23851, 23862, 23873,
- 23882, 23891, 23899, 23907, 23915, 23923, 23931, 23942, 23953, 23958, 23964, 23973, 23982, 23991,
- 24001, 24011, 24021, 24031, 24041, 24050, 24060, 24069, 24081, 24093, 24105, 24116, 24127, 24138,
- 24146, 24157, 24168, 24179, 24190, 24201, 24212, 24223, 24234, 24256, 24262, 24268, 24274, 24280,
- 24287, 24296, 24305, 24314, 24323, 24334, 24345, 24356, 24367, 24376, 24388, 24400, 24412, 24424,
- 24431, 24437, 24444, 24457, 24462, 24469, 24480, 24497, 24508, 24514, 24523, 24532, 24541, 24550,
- 24559, 24568, 24576, 24584, 24593, 24602, 24611, 24620, 24629, 24638, 24647, 24656, 24665, 24673,
- 24681, 24687, 24692, 24701, 24709, 24718, 24726, 24734, 24743, 24751, 24759, 24771, 24780, 24788,
- 24797, 24805, 24813, 24822, 24830, 24838, 24850, 24859, 24869, 24878, 24886, 24896, 24905, 24913,
- 24921, 24933, 24940, 24947, 24954, 24961, 24968, 24975, 24986, 24994, 25002, 25010, 0
+ 13797, 13806, 13816, 13825, 13834, 13843, 13852, 13863, 13874, 13885, 13896, 13909, 13919, 13933,
+ 13945, 13954, 13967, 13977, 13991, 14001, 14015, 14024, 14036, 14048, 14060, 14073, 14085, 14094,
+ 14100, 14106, 14114, 14122, 14130, 14142, 14154, 14165, 14176, 14187, 14198, 14209, 14220, 14228,
+ 14236, 14244, 14250, 14261, 14273, 14284, 14296, 14308, 14319, 14331, 14342, 14354, 14366, 14377,
+ 14389, 14401, 14412, 14421, 14434, 14443, 14456, 14465, 14474, 14487, 14496, 14509, 14518, 14531,
+ 14544, 14560, 14576, 14589, 14602, 14613, 14625, 14636, 14648, 14665, 14682, 14694, 14705, 14717,
+ 14728, 14740, 14754, 14766, 14777, 14790, 14802, 14816, 14828, 14839, 14852, 14863, 14874, 14885,
+ 14896, 14907, 14918, 14929, 14940, 14951, 14962, 14973, 14980, 14987, 14994, 15001, 15008, 15015,
+ 15021, 15027, 15035, 15043, 15051, 15059, 15067, 15079, 15087, 15099, 15107, 15119, 15127, 15139,
+ 15148, 15157, 15167, 15177, 15188, 15198, 15207, 15217, 15226, 15236, 15248, 15257, 15269, 15281,
+ 15294, 15307, 15320, 15333, 15346, 15359, 15369, 15375, 15382, 15389, 15396, 15403, 15410, 15417,
+ 15423, 15429, 15434, 15440, 15446, 15453, 15460, 15467, 15474, 15481, 15488, 15494, 15500, 15508,
+ 15515, 15523, 15530, 15537, 15545, 15552, 15559, 15570, 15578, 15585, 15593, 15600, 15607, 15615,
+ 15622, 15629, 15640, 15648, 15657, 15665, 15672, 15681, 15689, 15696, 15703, 15714, 15720, 15726,
+ 15732, 15738, 15744, 15750, 15760, 15767, 15774, 15781, 15788, 15796, 15804, 15812, 15820, 15827,
+ 15834, 15840, 15846, 15852, 15863, 15873, 15884, 15894, 15905, 15915, 15926, 15936, 15947, 15957,
+ 15968, 15978, 15989, 16000, 16011, 16022, 16033, 16044, 16055, 16066, 16074, 16082, 16090, 16098,
+ 16106, 16114, 16123, 16132, 16141, 16150, 16160, 16170, 16180, 16190, 16198, 16206, 16219, 16232,
+ 16244, 16256, 16264, 16272, 16279, 16286, 16294, 16302, 16310, 16318, 16330, 16342, 16353, 16364,
+ 16374, 16384, 16394, 16404, 16414, 16424, 16434, 16444, 16457, 16470, 16483, 16496, 16509, 16522,
+ 16535, 16548, 16561, 16574, 16586, 16598, 16614, 16630, 16645, 16660, 16670, 16680, 16690, 16700,
+ 16710, 16720, 16730, 16740, 16753, 16766, 16779, 16792, 16805, 16818, 16831, 16844, 16857, 16870,
+ 16882, 16894, 16910, 16926, 16941, 16956, 16965, 16974, 16983, 16992, 17001, 17010, 17019, 17028,
+ 17040, 17051, 17063, 17074, 17087, 17099, 17112, 17124, 17136, 17147, 17159, 17170, 17186, 17202,
+ 17214, 17225, 17237, 17248, 17261, 17273, 17286, 17298, 17310, 17321, 17333, 17344, 17353, 17362,
+ 17371, 17380, 17389, 17398, 17408, 17418, 17433, 17447, 17462, 17476, 17486, 17496, 17505, 17514,
+ 17523, 17532, 17541, 17550, 17559, 17568, 17577, 17586, 17595, 17604, 17613, 17622, 17631, 17640,
+ 17649, 17658, 17667, 17676, 17685, 17694, 17703, 17712, 17723, 17734, 17745, 17756, 17767, 17778,
+ 17789, 17800, 17811, 17822, 17833, 17844, 17855, 17866, 17877, 17888, 17899, 17910, 17921, 17932,
+ 17943, 17954, 17965, 17976, 17987, 17996, 18005, 18019, 18032, 18046, 18059, 18069, 18079, 18088,
+ 18097, 18106, 18119, 18128, 18141, 18150, 18159, 18169, 18179, 18186, 18195, 18204, 18211, 18220,
+ 18229, 18236, 18245, 18254, 18265, 18276, 18287, 18298, 18309, 18320, 18325, 18331, 18337, 18345,
+ 18353, 18361, 18369, 18377, 18385, 18391, 18397, 18409, 18420, 18431, 18442, 18451, 18460, 18472,
+ 18483, 18495, 18506, 18515, 18524, 18534, 18544, 18554, 18564, 18576, 18587, 18599, 18610, 18622,
+ 18633, 18645, 18656, 18668, 18679, 18691, 18702, 18711, 18719, 18727, 18735, 18743, 18751, 18759,
+ 18767, 18775, 18783, 18791, 18799, 18807, 18815, 18823, 18831, 18840, 18848, 18856, 18864, 18872,
+ 18880, 18888, 18896, 18904, 18912, 18920, 18928, 18936, 18944, 18952, 18960, 18969, 18978, 18987,
+ 18996, 19006, 19016, 19026, 19036, 19044, 19052, 19060, 19068, 19080, 19092, 19104, 19116, 19129,
+ 19142, 19154, 19166, 19178, 19190, 19202, 19214, 19227, 19240, 19252, 19264, 19272, 19282, 19292,
+ 19302, 19312, 19321, 19329, 19339, 19349, 19359, 19369, 19378, 19386, 19396, 19406, 19412, 19419,
+ 19428, 19437, 19446, 19455, 19464, 19473, 19482, 19489, 19496, 19504, 19513, 19521, 19529, 19538,
+ 19546, 19554, 19563, 19571, 19579, 19588, 19596, 19604, 19613, 19621, 19629, 19638, 19646, 19653,
+ 19661, 19668, 19675, 19683, 19690, 19697, 19708, 19715, 19726, 19733, 19744, 19751, 19762, 19770,
+ 19779, 19787, 19795, 19804, 19812, 19820, 19829, 19837, 19845, 19854, 19862, 19870, 19879, 19887,
+ 19895, 19904, 19912, 19919, 19927, 19934, 19941, 19949, 19956, 19962, 19968, 19974, 19981, 19994,
+ 20004, 20014, 20024, 20034, 20045, 20055, 20065, 20075, 20085, 20089, 20094, 20102, 20111, 20119,
+ 20127, 20136, 20144, 20152, 20161, 20169, 20177, 20186, 20194, 20202, 20211, 20219, 20227, 20236,
+ 20244, 20251, 20259, 20266, 20273, 20281, 20288, 20296, 20305, 20313, 20321, 20330, 20338, 20346,
+ 20355, 20363, 20371, 20380, 20388, 20396, 20405, 20413, 20421, 20430, 20438, 20445, 20453, 20460,
+ 20467, 20475, 20482, 20495, 20508, 20521, 20534, 20547, 20560, 20573, 20586, 20590, 20599, 20612,
+ 20621, 20634, 20643, 20656, 20665, 20678, 20683, 20691, 20700, 20708, 20716, 20725, 20733, 20741,
+ 20750, 20758, 20766, 20775, 20783, 20791, 20800, 20808, 20816, 20825, 20833, 20840, 20848, 20855,
+ 20862, 20870, 20877, 20886, 20894, 20903, 20911, 20919, 20928, 20936, 20944, 20956, 20965, 20973,
+ 20982, 20990, 20998, 21007, 21015, 21023, 21035, 21044, 21054, 21063, 21071, 21081, 21090, 21098,
+ 21106, 21118, 21125, 21132, 21139, 21146, 21153, 21160, 21171, 21178, 21185, 21192, 21198, 21205,
+ 21212, 21218, 21224, 21231, 21238, 21248, 21258, 21268, 21277, 21283, 21289, 21295, 21301, 21308,
+ 21315, 21321, 21327, 21334, 21341, 21347, 21353, 21360, 21367, 21374, 21381, 21388, 21395, 21402,
+ 21409, 21415, 21421, 21427, 21433, 21439, 21445, 21452, 21458, 21466, 21475, 21483, 21491, 21500,
+ 21508, 21516, 21525, 21533, 21541, 21550, 21558, 21566, 21575, 21583, 21591, 21600, 21608, 21615,
+ 21623, 21630, 21637, 21645, 21652, 21663, 21674, 21685, 21696, 21707, 21718, 21729, 21740, 21751,
+ 21762, 21773, 21784, 21792, 21801, 21809, 21817, 21826, 21834, 21842, 21851, 21859, 21867, 21876,
+ 21884, 21892, 21901, 21909, 21917, 21926, 21934, 21941, 21949, 21956, 21963, 21971, 21978, 21989,
+ 22000, 22011, 22022, 22033, 22044, 22055, 22066, 22077, 22088, 22099, 22110, 22120, 22130, 22140,
+ 22150, 22156, 22162, 22171, 22180, 22189, 22197, 22205, 22213, 22221, 22229, 22237, 22245, 22253,
+ 22261, 22273, 22281, 22293, 22301, 22313, 22321, 22333, 22341, 22353, 22361, 22373, 22381, 22393,
+ 22401, 22413, 22420, 22430, 22440, 22450, 22460, 22464, 22468, 22472, 22480, 22486, 22492, 22498,
+ 22503, 22508, 22516, 22524, 22533, 22542, 22551, 22559, 22568, 22577, 22588, 22599, 22610, 22620,
+ 22630, 22642, 22652, 22664, 22676, 22683, 22692, 22700, 22709, 22717, 22725, 22734, 22742, 22750,
+ 22762, 22771, 22779, 22788, 22796, 22804, 22813, 22821, 22829, 22841, 22850, 22860, 22869, 22877,
+ 22887, 22896, 22904, 22912, 22924, 22931, 22938, 22945, 22952, 22959, 22966, 22977, 22985, 22993,
+ 23001, 23009, 23019, 23029, 23040, 23051, 23063, 23074, 23085, 23096, 23109, 23122, 23135, 23149,
+ 23163, 23177, 23191, 23205, 23219, 23230, 23238, 23250, 23258, 23270, 23278, 23290, 23298, 23310,
+ 23319, 23328, 23338, 23348, 23359, 23369, 23378, 23388, 23397, 23407, 23419, 23428, 23440, 23452,
+ 23465, 23478, 23491, 23504, 23517, 23530, 23540, 23547, 23555, 23564, 23572, 23582, 23589, 23598,
+ 23607, 23616, 23627, 23638, 23651, 23662, 23675, 23685, 23694, 23703, 23712, 23721, 23731, 23740,
+ 23749, 23758, 23767, 23777, 23788, 23799, 23808, 23817, 23825, 23833, 23841, 23849, 23857, 23868,
+ 23879, 23884, 23890, 23899, 23908, 23917, 23927, 23937, 23947, 23957, 23967, 23976, 23986, 23995,
+ 24007, 24019, 24031, 24042, 24053, 24064, 24072, 24083, 24094, 24105, 24116, 24127, 24138, 24149,
+ 24160, 24182, 24188, 24194, 24200, 24206, 24213, 24222, 24231, 24240, 24249, 24260, 24271, 24282,
+ 24293, 24302, 24314, 24326, 24338, 24350, 24357, 24363, 24370, 24383, 24388, 24395, 24406, 24423,
+ 24434, 24440, 24449, 24458, 24467, 24476, 24485, 24494, 24502, 24510, 24519, 24528, 24537, 24546,
+ 24555, 24564, 24573, 24582, 24591, 24599, 24607, 24613, 24618, 24627, 24635, 24644, 24652, 24660,
+ 24669, 24677, 24685, 24697, 24706, 24714, 24723, 24731, 24739, 24748, 24756, 24764, 24776, 24785,
+ 24795, 24804, 24812, 24822, 24831, 24839, 24847, 24859, 24866, 24873, 24880, 24887, 24894, 24901,
+ 24912, 24920, 24928, 24936, 0
};
const char *Strs =
@@ -3749,57 +3741,56 @@ const char *X86ATTInstPrinter::getInstructionName(unsigned Opcode) {
"DI2SSrm\000MOVDI2SSrr\000MOVDQAmr\000MOVDQArm\000MOVDQArr\000MOVDQUmr\000"
"MOVDQUmr_Int\000MOVDQUrm\000MOVDQUrm_Int\000MOVHLPSrr\000MOVHPDmr\000MO"
"VHPDrm\000MOVHPSmr\000MOVHPSrm\000MOVLHPSrr\000MOVLPDmr\000MOVLPDrm\000"
- "MOVLPDrr\000MOVLPSmr\000MOVLPSrm\000MOVLPSrr\000MOVLQ128mr\000MOVLSD2PD"
- "rr\000MOVLSS2PSrr\000MOVMSKPDrr\000MOVMSKPSrr\000MOVNTDQArm\000MOVNTDQm"
- "r\000MOVNTImr\000MOVNTPDmr\000MOVNTPSmr\000MOVPC32r\000MOVPD2SDmr\000MO"
- "VPD2SDrr\000MOVPDI2DImr\000MOVPDI2DIrr\000MOVPQI2QImr\000MOVPQIto64rr\000"
- "MOVPS2SSmr\000MOVPS2SSrr\000MOVQI2PQIrm\000MOVQxrxr\000MOVSB\000MOVSD\000"
- "MOVSD2PDrm\000MOVSD2PDrr\000MOVSDmr\000MOVSDrm\000MOVSDrr\000MOVSDto64m"
- "r\000MOVSDto64rr\000MOVSHDUPrm\000MOVSHDUPrr\000MOVSLDUPrm\000MOVSLDUPr"
- "r\000MOVSS2DImr\000MOVSS2DIrr\000MOVSS2PSrm\000MOVSS2PSrr\000MOVSSmr\000"
- "MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16rm8\000MOVSX16rm8W\000MOVSX16rr8\000"
- "MOVSX16rr8W\000MOVSX32rm16\000MOVSX32rm8\000MOVSX32rr16\000MOVSX32rr8\000"
- "MOVSX64rm16\000MOVSX64rm32\000MOVSX64rm8\000MOVSX64rr16\000MOVSX64rr32\000"
- "MOVSX64rr8\000MOVUPDmr\000MOVUPDmr_Int\000MOVUPDrm\000MOVUPDrm_Int\000M"
- "OVUPDrr\000MOVUPSmr\000MOVUPSmr_Int\000MOVUPSrm\000MOVUPSrm_Int\000MOVU"
- "PSrr\000MOVZDI2PDIrm\000MOVZDI2PDIrr\000MOVZPQILo2PQIrm\000MOVZPQILo2PQ"
- "Irr\000MOVZQI2PQIrm\000MOVZQI2PQIrr\000MOVZSD2PDrm\000MOVZSS2PSrm\000MO"
- "VZX16rm8\000MOVZX16rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX32_NOREXrm"
- "8\000MOVZX32_NOREXrr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32rr16\000MO"
- "VZX32rr8\000MOVZX64rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MOVZX64rm8\000"
- "MOVZX64rm8_Q\000MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32\000MOVZX64r"
- "r8\000MOVZX64rr8_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp3280\000MOV_Fp6"
- "432\000MOV_Fp6464\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064\000MOV_Fp80"
- "80\000MPSADBWrmi\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32m\000MUL32r\000"
- "MUL64m\000MUL64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr\000MULPSrm\000"
- "MULPSrr\000MULSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_Int\000MULSSrm\000"
- "MULSSrm_Int\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000MUL_F64m\000MUL_FI"
- "16m\000MUL_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp32\000MUL_Fp32m\000"
- "MUL_Fp64\000MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000MUL_Fp80m32\000MUL_"
- "Fp80m64\000MUL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16m80\000MUL_FpI32m32"
- "\000MUL_FpI32m64\000MUL_FpI32m80\000MUL_FrST0\000MWAIT\000NEG16m\000NEG"
- "16r\000NEG32m\000NEG32r\000NEG64m\000NEG64r\000NEG8m\000NEG8r\000NOOP\000"
- "NOOPL\000NOOPW\000NOT16m\000NOT16r\000NOT32m\000NOT32r\000NOT64m\000NOT"
- "64r\000NOT8m\000NOT8r\000OR16i16\000OR16mi\000OR16mi8\000OR16mr\000OR16"
- "ri\000OR16ri8\000OR16rm\000OR16rr\000OR16rr_REV\000OR32i32\000OR32mi\000"
- "OR32mi8\000OR32mr\000OR32ri\000OR32ri8\000OR32rm\000OR32rr\000OR32rr_RE"
- "V\000OR64i32\000OR64mi32\000OR64mi8\000OR64mr\000OR64ri32\000OR64ri8\000"
- "OR64rm\000OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000OR8mr\000OR8ri\000O"
- "R8rm\000OR8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000ORPSrm\000ORPSrr\000O"
- "UT16ir\000OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000OUT8rr\000OUTSB\000"
- "OUTSD\000OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr128\000PABSBrr64\000"
- "PABSDrm128\000PABSDrm64\000PABSDrr128\000PABSDrr64\000PABSWrm128\000PAB"
- "SWrm64\000PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PACKSSDWrr\000PACKSS"
- "WBrm\000PACKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACKUSWBrm\000PACKUSW"
- "Brr\000PADDBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PADDQrm\000PADDQrr\000"
- "PADDSBrm\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADDUSBrm\000PADDUSBrr\000"
- "PADDUSWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000PALIGNR128rm\000PALIGNR"
- "128rr\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000PANDNrr\000PANDrm\000"
- "PANDrr\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr\000PBLENDVBrm0\000PB"
- "LENDVBrr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm\000PCMPEQBrr\000PCMP"
- "EQDrm\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PCMPEQWrm\000PCMPEQWrr\000"
- "PCMPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000PCMPESTRICrr\000PCMPEST"
- "RIOrm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPESTRISrr\000PCMPESTRIZrm\000"
+ "MOVLPSmr\000MOVLPSrm\000MOVLQ128mr\000MOVMSKPDrr\000MOVMSKPSrr\000MOVNT"
+ "DQArm\000MOVNTDQ_64mr\000MOVNTDQmr\000MOVNTDQmr_Int\000MOVNTI_64mr\000M"
+ "OVNTImr\000MOVNTImr_Int\000MOVNTPDmr\000MOVNTPDmr_Int\000MOVNTPSmr\000M"
+ "OVNTPSmr_Int\000MOVPC32r\000MOVPDI2DImr\000MOVPDI2DIrr\000MOVPQI2QImr\000"
+ "MOVPQIto64rr\000MOVQI2PQIrm\000MOVQxrxr\000MOVSB\000MOVSD\000MOVSDmr\000"
+ "MOVSDrm\000MOVSDrr\000MOVSDto64mr\000MOVSDto64rr\000MOVSHDUPrm\000MOVSH"
+ "DUPrr\000MOVSLDUPrm\000MOVSLDUPrr\000MOVSS2DImr\000MOVSS2DIrr\000MOVSSm"
+ "r\000MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16rm8\000MOVSX16rm8W\000MOVSX1"
+ "6rr8\000MOVSX16rr8W\000MOVSX32rm16\000MOVSX32rm8\000MOVSX32rr16\000MOVS"
+ "X32rr8\000MOVSX64rm16\000MOVSX64rm32\000MOVSX64rm8\000MOVSX64rr16\000MO"
+ "VSX64rr32\000MOVSX64rr8\000MOVUPDmr\000MOVUPDmr_Int\000MOVUPDrm\000MOVU"
+ "PDrm_Int\000MOVUPDrr\000MOVUPSmr\000MOVUPSmr_Int\000MOVUPSrm\000MOVUPSr"
+ "m_Int\000MOVUPSrr\000MOVZDI2PDIrm\000MOVZDI2PDIrr\000MOVZPQILo2PQIrm\000"
+ "MOVZPQILo2PQIrr\000MOVZQI2PQIrm\000MOVZQI2PQIrr\000MOVZX16rm8\000MOVZX1"
+ "6rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX32_NOREXrm8\000MOVZX32_NOREX"
+ "rr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32rr16\000MOVZX32rr8\000MOVZX6"
+ "4rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MOVZX64rm8\000MOVZX64rm8_Q\000"
+ "MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32\000MOVZX64rr8\000MOVZX64rr8"
+ "_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp3280\000MOV_Fp6432\000MOV_Fp646"
+ "4\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064\000MOV_Fp8080\000MPSADBWrmi"
+ "\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32m\000MUL32r\000MUL64m\000MUL"
+ "64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr\000MULPSrm\000MULPSrr\000MU"
+ "LSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_Int\000MULSSrm\000MULSSrm_In"
+ "t\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000MUL_F64m\000MUL_FI16m\000MUL"
+ "_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp32\000MUL_Fp32m\000MUL_Fp64\000"
+ "MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000MUL_Fp80m32\000MUL_Fp80m64\000M"
+ "UL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16m80\000MUL_FpI32m32\000MUL_FpI3"
+ "2m64\000MUL_FpI32m80\000MUL_FrST0\000MWAIT\000NEG16m\000NEG16r\000NEG32"
+ "m\000NEG32r\000NEG64m\000NEG64r\000NEG8m\000NEG8r\000NOOP\000NOOPL\000N"
+ "OOPW\000NOT16m\000NOT16r\000NOT32m\000NOT32r\000NOT64m\000NOT64r\000NOT"
+ "8m\000NOT8r\000OR16i16\000OR16mi\000OR16mi8\000OR16mr\000OR16ri\000OR16"
+ "ri8\000OR16rm\000OR16rr\000OR16rr_REV\000OR32i32\000OR32mi\000OR32mi8\000"
+ "OR32mr\000OR32ri\000OR32ri8\000OR32rm\000OR32rr\000OR32rr_REV\000OR64i3"
+ "2\000OR64mi32\000OR64mi8\000OR64mr\000OR64ri32\000OR64ri8\000OR64rm\000"
+ "OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000OR8mr\000OR8ri\000OR8rm\000OR"
+ "8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000ORPSrm\000ORPSrr\000OUT16ir\000"
+ "OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000OUT8rr\000OUTSB\000OUTSD\000"
+ "OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr128\000PABSBrr64\000PABSDrm1"
+ "28\000PABSDrm64\000PABSDrr128\000PABSDrr64\000PABSWrm128\000PABSWrm64\000"
+ "PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PACKSSDWrr\000PACKSSWBrm\000PA"
+ "CKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACKUSWBrm\000PACKUSWBrr\000PAD"
+ "DBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PADDQrm\000PADDQrr\000PADDSBrm"
+ "\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADDUSBrm\000PADDUSBrr\000PADDU"
+ "SWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000PALIGNR128rm\000PALIGNR128rr"
+ "\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000PANDNrr\000PANDrm\000PANDr"
+ "r\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr\000PBLENDVBrm0\000PBLENDV"
+ "Brr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm\000PCMPEQBrr\000PCMPEQDrm"
+ "\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PCMPEQWrm\000PCMPEQWrr\000PC"
+ "MPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000PCMPESTRICrr\000PCMPESTRI"
+ "Orm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPESTRISrr\000PCMPESTRIZrm\000"
"PCMPESTRIZrr\000PCMPESTRIrm\000PCMPESTRIrr\000PCMPESTRM128MEM\000PCMPES"
"TRM128REG\000PCMPESTRM128rm\000PCMPESTRM128rr\000PCMPGTBrm\000PCMPGTBrr"
"\000PCMPGTDrm\000PCMPGTDrr\000PCMPGTQrm\000PCMPGTQrr\000PCMPGTWrm\000PC"
diff --git a/libclamav/c++/X86GenAsmWriter1.inc b/libclamav/c++/X86GenAsmWriter1.inc
index f6b1d41..813e673 100644
--- a/libclamav/c++/X86GenAsmWriter1.inc
+++ b/libclamav/c++/X86GenAsmWriter1.inc
@@ -1358,52 +1358,46 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
138547133U, // MOVLHPSrr
943722438U, // MOVLPDmr
139333574U, // MOVLPDrm
- 138547150U, // MOVLPDrr
- 943722453U, // MOVLPSmr
- 139333589U, // MOVLPSrm
- 138547165U, // MOVLPSrr
+ 943722446U, // MOVLPSmr
+ 139333582U, // MOVLPSrm
541068621U, // MOVLQ128mr
- 138547150U, // MOVLSD2PDrr
- 138547165U, // MOVLSS2PSrr
- 139857892U, // MOVMSKPDrr
- 139857902U, // MOVMSKPSrr
- 140775416U, // MOVNTDQArm
- 2818576386U, // MOVNTDQmr
- 406851595U, // MOVNTImr
- 1480593427U, // MOVNTPDmr
- 1480593436U, // MOVNTPSmr
+ 139857878U, // MOVMSKPDrr
+ 139857888U, // MOVMSKPSrr
+ 140775402U, // MOVNTDQArm
+ 2818576372U, // MOVNTDQ_64mr
+ 2818576372U, // MOVNTDQmr
+ 2818576372U, // MOVNTDQmr_Int
+ 541069309U, // MOVNTI_64mr
+ 406851581U, // MOVNTImr
+ 406851581U, // MOVNTImr_Int
+ 2818576389U, // MOVNTPDmr
+ 1480593413U, // MOVNTPDmr_Int
+ 2818576398U, // MOVNTPSmr
+ 1480593422U, // MOVNTPSmr_Int
0U, // MOVPC32r
- 943722446U, // MOVPD2SDmr
- 139857870U, // MOVPD2SDrr
406850861U, // MOVPDI2DImr
139857197U, // MOVPDI2DIrr
541068621U, // MOVPQI2QImr
139857229U, // MOVPQIto64rr
- 809504733U, // MOVPS2SSmr
- 139857885U, // MOVPS2SSrr
140119373U, // MOVQI2PQIrm
139857229U, // MOVQxrxr
- 4133U, // MOVSB
- 4134U, // MOVSD
- 140513230U, // MOVSD2PDrm
- 139857870U, // MOVSD2PDrr
- 943722446U, // MOVSDmr
- 140513230U, // MOVSDrm
- 139857870U, // MOVSDrr
+ 4119U, // MOVSB
+ 4120U, // MOVSD
+ 943722526U, // MOVSDmr
+ 140513310U, // MOVSDrm
+ 138547230U, // MOVSDrr
541068621U, // MOVSDto64mr
139857229U, // MOVSDto64rr
- 140382252U, // MOVSHDUPrm
- 139857964U, // MOVSHDUPrr
- 140382262U, // MOVSLDUPrm
- 139857974U, // MOVSLDUPrr
+ 140382245U, // MOVSHDUPrm
+ 139857957U, // MOVSHDUPrr
+ 140382255U, // MOVSLDUPrm
+ 139857967U, // MOVSLDUPrr
406850861U, // MOVSS2DImr
139857197U, // MOVSS2DIrr
- 140644317U, // MOVSS2PSrm
- 139857885U, // MOVSS2PSrr
- 809504733U, // MOVSSmr
- 140644317U, // MOVSSrm
- 139857885U, // MOVSSrr
- 4133U, // MOVSW
+ 809504825U, // MOVSSmr
+ 140644409U, // MOVSSrm
+ 138547257U, // MOVSSrr
+ 4119U, // MOVSW
0U, // MOVSX16rm8
140251200U, // MOVSX16rm8W
0U, // MOVSX16rr8
@@ -1434,8 +1428,6 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
139857229U, // MOVZPQILo2PQIrr
140119373U, // MOVZQI2PQIrm
139857229U, // MOVZQI2PQIrr
- 140513230U, // MOVZSD2PDrm
- 140644317U, // MOVZSS2PSrm
0U, // MOVZX16rm8
140251231U, // MOVZX16rm8W
0U, // MOVZX16rr8
@@ -2282,9 +2274,9 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
5658U, // STD
5662U, // STI
402658850U, // STMXCSR
- 4133U, // STOSB
+ 4119U, // STOSB
5675U, // STOSD
- 4133U, // STOSW
+ 4119U, // STOSW
5681U, // STRm
5681U, // STRr
805312054U, // ST_F32m
@@ -2624,20 +2616,20 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
"pcklbw\t\000punpckldq\t\000punpcklwd\t\000pxor\t\000monitor\000mov\t\000"
"mov\t%ax, \000mov\t%eax, \000movq\t%fs:\000movq\t%gs:\000mov\t%rax, \000"
"movabs\t\000mov\t%al, \000movddup\t\000movdqa\t\000movdqu\t\000movhlps\t"
- "\000movhpd\t\000movhps\t\000movlhps\t\000movlpd\t\000movsd\t\000movlps\t"
- "\000movss\t\000movmskpd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000m"
- "ovnti\t\000movntpd\t\000movntps\t\000\000movsd\000movshdup\t\000movsldu"
- "p\t\000movsx\t\000movsxd\t\000movupd\t\000movups\t\000movzx\t\000mpsadb"
- "w\t\000mul\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmul\t\000f"
- "imul\t\000fmulp\t\000mwait\000neg\t\000nop\000nop\t\000not\t\000or\t%ax"
- ", \000or\t\000or\t%eax, \000or\t%rax, \000or\t%al, \000out\t\000out\t%D"
- "X, %AX\000out\t%DX, %EAX\000out\t%DX, %AL\000outsb\000outsd\000outsw\000"
- "pabsb\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t\000"
- "pblendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000#PC"
- "MPESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#PCM"
- "PISTRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t\000pextrb"
- "\t\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw\t\000phmi"
- "nposuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t\000"
+ "\000movhpd\t\000movhps\t\000movlhps\t\000movlpd\t\000movlps\t\000movmsk"
+ "pd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000movnti\t\000movntpd\t\000"
+ "movntps\t\000\000movsd\000movsd\t\000movshdup\t\000movsldup\t\000movss\t"
+ "\000movsx\t\000movsxd\t\000movupd\t\000movups\t\000movzx\t\000mpsadbw\t"
+ "\000mul\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmul\t\000fimu"
+ "l\t\000fmulp\t\000mwait\000neg\t\000nop\000nop\t\000not\t\000or\t%ax, \000"
+ "or\t\000or\t%eax, \000or\t%rax, \000or\t%al, \000out\t\000out\t%DX, %AX"
+ "\000out\t%DX, %EAX\000out\t%DX, %AL\000outsb\000outsd\000outsw\000pabsb"
+ "\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t\000pb"
+ "lendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000#PCMP"
+ "ESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#PCMPI"
+ "STRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t\000pextrb\t"
+ "\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw\t\000phminp"
+ "osuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t\000"
"pinsrq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pmaxud\t\000pmaxuw\t"
"\000pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000pmovsxbd\t\000pmovs"
"xbq\t\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pmovsxwq\t\000pmovzx"
@@ -2728,7 +2720,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
printSSECC(MI, 3);
break;
case 11:
- // CMPXCHG16B, MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr, MOVNTPSmr
+ // CMPXCHG16B, MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr_Int, MOVNTPSmr...
printi128mem(MI, 0);
break;
case 12:
@@ -2789,7 +2781,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 21:
- // MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVUPDmr, MOVUPDmr_Int, MOVUPSmr, MOVUP...
+ // MOVAPDmr, MOVAPSmr, MOVNTDQ_64mr, MOVNTDQmr, MOVNTDQmr_Int, MOVNTPDmr,...
printf128mem(MI, 0);
O << ", ";
printOperand(MI, 5);
@@ -3374,7 +3366,7 @@ const char *X86IntelInstPrinter::getRegisterName(unsigned RegNo) {
/// from the instruction set description. This returns the enum name of the
/// specified instruction.
const char *X86IntelInstPrinter::getInstructionName(unsigned Opcode) {
- assert(Opcode < 2532 && "Invalid instruction number!");
+ assert(Opcode < 2524 && "Invalid instruction number!");
static const unsigned InstAsmOffset[] = {
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 136,
@@ -3473,91 +3465,91 @@ const char *X86IntelInstPrinter::getInstructionName(unsigned Opcode) {
13388, 13400, 13408, 13416, 13424, 13437, 13449, 13461, 13469, 13476, 13483, 13496, 13504, 13511,
13518, 13525, 13538, 13545, 13558, 13569, 13578, 13587, 13596, 13605, 13614, 13623, 13633, 13643,
13655, 13667, 13678, 13689, 13698, 13707, 13716, 13725, 13738, 13747, 13760, 13770, 13779, 13788,
- 13797, 13806, 13816, 13825, 13834, 13843, 13852, 13861, 13870, 13881, 13893, 13905, 13916, 13927,
- 13938, 13948, 13957, 13967, 13977, 13986, 13997, 14008, 14020, 14032, 14044, 14057, 14068, 14079,
- 14091, 14100, 14106, 14112, 14123, 14134, 14142, 14150, 14158, 14170, 14182, 14193, 14204, 14215,
- 14226, 14237, 14248, 14259, 14270, 14278, 14286, 14294, 14300, 14311, 14323, 14334, 14346, 14358,
- 14369, 14381, 14392, 14404, 14416, 14427, 14439, 14451, 14462, 14471, 14484, 14493, 14506, 14515,
- 14524, 14537, 14546, 14559, 14568, 14581, 14594, 14610, 14626, 14639, 14652, 14664, 14676, 14687,
- 14699, 14710, 14722, 14739, 14756, 14768, 14779, 14791, 14802, 14814, 14828, 14840, 14851, 14864,
- 14876, 14890, 14902, 14913, 14926, 14937, 14948, 14959, 14970, 14981, 14992, 15003, 15014, 15025,
- 15036, 15047, 15054, 15061, 15068, 15075, 15082, 15089, 15095, 15101, 15109, 15117, 15125, 15133,
- 15141, 15153, 15161, 15173, 15181, 15193, 15201, 15213, 15222, 15231, 15241, 15251, 15262, 15272,
- 15281, 15291, 15300, 15310, 15322, 15331, 15343, 15355, 15368, 15381, 15394, 15407, 15420, 15433,
- 15443, 15449, 15456, 15463, 15470, 15477, 15484, 15491, 15497, 15503, 15508, 15514, 15520, 15527,
- 15534, 15541, 15548, 15555, 15562, 15568, 15574, 15582, 15589, 15597, 15604, 15611, 15619, 15626,
- 15633, 15644, 15652, 15659, 15667, 15674, 15681, 15689, 15696, 15703, 15714, 15722, 15731, 15739,
- 15746, 15755, 15763, 15770, 15777, 15788, 15794, 15800, 15806, 15812, 15818, 15824, 15834, 15841,
- 15848, 15855, 15862, 15870, 15878, 15886, 15894, 15901, 15908, 15914, 15920, 15926, 15937, 15947,
- 15958, 15968, 15979, 15989, 16000, 16010, 16021, 16031, 16042, 16052, 16063, 16074, 16085, 16096,
- 16107, 16118, 16129, 16140, 16148, 16156, 16164, 16172, 16180, 16188, 16197, 16206, 16215, 16224,
- 16234, 16244, 16254, 16264, 16272, 16280, 16293, 16306, 16318, 16330, 16338, 16346, 16353, 16360,
- 16368, 16376, 16384, 16392, 16404, 16416, 16427, 16438, 16448, 16458, 16468, 16478, 16488, 16498,
- 16508, 16518, 16531, 16544, 16557, 16570, 16583, 16596, 16609, 16622, 16635, 16648, 16660, 16672,
- 16688, 16704, 16719, 16734, 16744, 16754, 16764, 16774, 16784, 16794, 16804, 16814, 16827, 16840,
- 16853, 16866, 16879, 16892, 16905, 16918, 16931, 16944, 16956, 16968, 16984, 17000, 17015, 17030,
- 17039, 17048, 17057, 17066, 17075, 17084, 17093, 17102, 17114, 17125, 17137, 17148, 17161, 17173,
- 17186, 17198, 17210, 17221, 17233, 17244, 17260, 17276, 17288, 17299, 17311, 17322, 17335, 17347,
- 17360, 17372, 17384, 17395, 17407, 17418, 17427, 17436, 17445, 17454, 17463, 17472, 17482, 17492,
- 17507, 17521, 17536, 17550, 17560, 17570, 17579, 17588, 17597, 17606, 17615, 17624, 17633, 17642,
- 17651, 17660, 17669, 17678, 17687, 17696, 17705, 17714, 17723, 17732, 17741, 17750, 17759, 17768,
- 17777, 17786, 17797, 17808, 17819, 17830, 17841, 17852, 17863, 17874, 17885, 17896, 17907, 17918,
- 17929, 17940, 17951, 17962, 17973, 17984, 17995, 18006, 18017, 18028, 18039, 18050, 18061, 18070,
- 18079, 18093, 18106, 18120, 18133, 18143, 18153, 18162, 18171, 18180, 18193, 18202, 18215, 18224,
- 18233, 18243, 18253, 18260, 18269, 18278, 18285, 18294, 18303, 18310, 18319, 18328, 18339, 18350,
- 18361, 18372, 18383, 18394, 18399, 18405, 18411, 18419, 18427, 18435, 18443, 18451, 18459, 18465,
- 18471, 18483, 18494, 18505, 18516, 18525, 18534, 18546, 18557, 18569, 18580, 18589, 18598, 18608,
- 18618, 18628, 18638, 18650, 18661, 18673, 18684, 18696, 18707, 18719, 18730, 18742, 18753, 18765,
- 18776, 18785, 18793, 18801, 18809, 18817, 18825, 18833, 18841, 18849, 18857, 18865, 18873, 18881,
- 18889, 18897, 18905, 18914, 18922, 18930, 18938, 18946, 18954, 18962, 18970, 18978, 18986, 18994,
- 19002, 19010, 19018, 19026, 19034, 19043, 19052, 19061, 19070, 19080, 19090, 19100, 19110, 19118,
- 19126, 19134, 19142, 19154, 19166, 19178, 19190, 19203, 19216, 19228, 19240, 19252, 19264, 19276,
- 19288, 19301, 19314, 19326, 19338, 19346, 19356, 19366, 19376, 19386, 19395, 19403, 19413, 19423,
- 19433, 19443, 19452, 19460, 19470, 19480, 19486, 19493, 19502, 19511, 19520, 19529, 19538, 19547,
- 19556, 19563, 19570, 19578, 19587, 19595, 19603, 19612, 19620, 19628, 19637, 19645, 19653, 19662,
- 19670, 19678, 19687, 19695, 19703, 19712, 19720, 19727, 19735, 19742, 19749, 19757, 19764, 19771,
- 19782, 19789, 19800, 19807, 19818, 19825, 19836, 19844, 19853, 19861, 19869, 19878, 19886, 19894,
- 19903, 19911, 19919, 19928, 19936, 19944, 19953, 19961, 19969, 19978, 19986, 19993, 20001, 20008,
- 20015, 20023, 20030, 20036, 20042, 20048, 20055, 20068, 20078, 20088, 20098, 20108, 20119, 20129,
- 20139, 20149, 20159, 20163, 20168, 20176, 20185, 20193, 20201, 20210, 20218, 20226, 20235, 20243,
- 20251, 20260, 20268, 20276, 20285, 20293, 20301, 20310, 20318, 20325, 20333, 20340, 20347, 20355,
- 20362, 20370, 20379, 20387, 20395, 20404, 20412, 20420, 20429, 20437, 20445, 20454, 20462, 20470,
- 20479, 20487, 20495, 20504, 20512, 20519, 20527, 20534, 20541, 20549, 20556, 20569, 20582, 20595,
- 20608, 20621, 20634, 20647, 20660, 20664, 20673, 20686, 20695, 20708, 20717, 20730, 20739, 20752,
- 20757, 20765, 20774, 20782, 20790, 20799, 20807, 20815, 20824, 20832, 20840, 20849, 20857, 20865,
- 20874, 20882, 20890, 20899, 20907, 20914, 20922, 20929, 20936, 20944, 20951, 20960, 20968, 20977,
- 20985, 20993, 21002, 21010, 21018, 21030, 21039, 21047, 21056, 21064, 21072, 21081, 21089, 21097,
- 21109, 21118, 21128, 21137, 21145, 21155, 21164, 21172, 21180, 21192, 21199, 21206, 21213, 21220,
- 21227, 21234, 21245, 21252, 21259, 21266, 21272, 21279, 21286, 21292, 21298, 21305, 21312, 21322,
- 21332, 21342, 21351, 21357, 21363, 21369, 21375, 21382, 21389, 21395, 21401, 21408, 21415, 21421,
- 21427, 21434, 21441, 21448, 21455, 21462, 21469, 21476, 21483, 21489, 21495, 21501, 21507, 21513,
- 21519, 21526, 21532, 21540, 21549, 21557, 21565, 21574, 21582, 21590, 21599, 21607, 21615, 21624,
- 21632, 21640, 21649, 21657, 21665, 21674, 21682, 21689, 21697, 21704, 21711, 21719, 21726, 21737,
- 21748, 21759, 21770, 21781, 21792, 21803, 21814, 21825, 21836, 21847, 21858, 21866, 21875, 21883,
- 21891, 21900, 21908, 21916, 21925, 21933, 21941, 21950, 21958, 21966, 21975, 21983, 21991, 22000,
- 22008, 22015, 22023, 22030, 22037, 22045, 22052, 22063, 22074, 22085, 22096, 22107, 22118, 22129,
- 22140, 22151, 22162, 22173, 22184, 22194, 22204, 22214, 22224, 22230, 22236, 22245, 22254, 22263,
- 22271, 22279, 22287, 22295, 22303, 22311, 22319, 22327, 22335, 22347, 22355, 22367, 22375, 22387,
- 22395, 22407, 22415, 22427, 22435, 22447, 22455, 22467, 22475, 22487, 22494, 22504, 22514, 22524,
- 22534, 22538, 22542, 22546, 22554, 22560, 22566, 22572, 22577, 22582, 22590, 22598, 22607, 22616,
- 22625, 22633, 22642, 22651, 22662, 22673, 22684, 22694, 22704, 22716, 22726, 22738, 22750, 22757,
- 22766, 22774, 22783, 22791, 22799, 22808, 22816, 22824, 22836, 22845, 22853, 22862, 22870, 22878,
- 22887, 22895, 22903, 22915, 22924, 22934, 22943, 22951, 22961, 22970, 22978, 22986, 22998, 23005,
- 23012, 23019, 23026, 23033, 23040, 23051, 23059, 23067, 23075, 23083, 23093, 23103, 23114, 23125,
- 23137, 23148, 23159, 23170, 23183, 23196, 23209, 23223, 23237, 23251, 23265, 23279, 23293, 23304,
- 23312, 23324, 23332, 23344, 23352, 23364, 23372, 23384, 23393, 23402, 23412, 23422, 23433, 23443,
- 23452, 23462, 23471, 23481, 23493, 23502, 23514, 23526, 23539, 23552, 23565, 23578, 23591, 23604,
- 23614, 23621, 23629, 23638, 23646, 23656, 23663, 23672, 23681, 23690, 23701, 23712, 23725, 23736,
- 23749, 23759, 23768, 23777, 23786, 23795, 23805, 23814, 23823, 23832, 23841, 23851, 23862, 23873,
- 23882, 23891, 23899, 23907, 23915, 23923, 23931, 23942, 23953, 23958, 23964, 23973, 23982, 23991,
- 24001, 24011, 24021, 24031, 24041, 24050, 24060, 24069, 24081, 24093, 24105, 24116, 24127, 24138,
- 24146, 24157, 24168, 24179, 24190, 24201, 24212, 24223, 24234, 24256, 24262, 24268, 24274, 24280,
- 24287, 24296, 24305, 24314, 24323, 24334, 24345, 24356, 24367, 24376, 24388, 24400, 24412, 24424,
- 24431, 24437, 24444, 24457, 24462, 24469, 24480, 24497, 24508, 24514, 24523, 24532, 24541, 24550,
- 24559, 24568, 24576, 24584, 24593, 24602, 24611, 24620, 24629, 24638, 24647, 24656, 24665, 24673,
- 24681, 24687, 24692, 24701, 24709, 24718, 24726, 24734, 24743, 24751, 24759, 24771, 24780, 24788,
- 24797, 24805, 24813, 24822, 24830, 24838, 24850, 24859, 24869, 24878, 24886, 24896, 24905, 24913,
- 24921, 24933, 24940, 24947, 24954, 24961, 24968, 24975, 24986, 24994, 25002, 25010, 0
+ 13797, 13806, 13816, 13825, 13834, 13843, 13852, 13863, 13874, 13885, 13896, 13909, 13919, 13933,
+ 13945, 13954, 13967, 13977, 13991, 14001, 14015, 14024, 14036, 14048, 14060, 14073, 14085, 14094,
+ 14100, 14106, 14114, 14122, 14130, 14142, 14154, 14165, 14176, 14187, 14198, 14209, 14220, 14228,
+ 14236, 14244, 14250, 14261, 14273, 14284, 14296, 14308, 14319, 14331, 14342, 14354, 14366, 14377,
+ 14389, 14401, 14412, 14421, 14434, 14443, 14456, 14465, 14474, 14487, 14496, 14509, 14518, 14531,
+ 14544, 14560, 14576, 14589, 14602, 14613, 14625, 14636, 14648, 14665, 14682, 14694, 14705, 14717,
+ 14728, 14740, 14754, 14766, 14777, 14790, 14802, 14816, 14828, 14839, 14852, 14863, 14874, 14885,
+ 14896, 14907, 14918, 14929, 14940, 14951, 14962, 14973, 14980, 14987, 14994, 15001, 15008, 15015,
+ 15021, 15027, 15035, 15043, 15051, 15059, 15067, 15079, 15087, 15099, 15107, 15119, 15127, 15139,
+ 15148, 15157, 15167, 15177, 15188, 15198, 15207, 15217, 15226, 15236, 15248, 15257, 15269, 15281,
+ 15294, 15307, 15320, 15333, 15346, 15359, 15369, 15375, 15382, 15389, 15396, 15403, 15410, 15417,
+ 15423, 15429, 15434, 15440, 15446, 15453, 15460, 15467, 15474, 15481, 15488, 15494, 15500, 15508,
+ 15515, 15523, 15530, 15537, 15545, 15552, 15559, 15570, 15578, 15585, 15593, 15600, 15607, 15615,
+ 15622, 15629, 15640, 15648, 15657, 15665, 15672, 15681, 15689, 15696, 15703, 15714, 15720, 15726,
+ 15732, 15738, 15744, 15750, 15760, 15767, 15774, 15781, 15788, 15796, 15804, 15812, 15820, 15827,
+ 15834, 15840, 15846, 15852, 15863, 15873, 15884, 15894, 15905, 15915, 15926, 15936, 15947, 15957,
+ 15968, 15978, 15989, 16000, 16011, 16022, 16033, 16044, 16055, 16066, 16074, 16082, 16090, 16098,
+ 16106, 16114, 16123, 16132, 16141, 16150, 16160, 16170, 16180, 16190, 16198, 16206, 16219, 16232,
+ 16244, 16256, 16264, 16272, 16279, 16286, 16294, 16302, 16310, 16318, 16330, 16342, 16353, 16364,
+ 16374, 16384, 16394, 16404, 16414, 16424, 16434, 16444, 16457, 16470, 16483, 16496, 16509, 16522,
+ 16535, 16548, 16561, 16574, 16586, 16598, 16614, 16630, 16645, 16660, 16670, 16680, 16690, 16700,
+ 16710, 16720, 16730, 16740, 16753, 16766, 16779, 16792, 16805, 16818, 16831, 16844, 16857, 16870,
+ 16882, 16894, 16910, 16926, 16941, 16956, 16965, 16974, 16983, 16992, 17001, 17010, 17019, 17028,
+ 17040, 17051, 17063, 17074, 17087, 17099, 17112, 17124, 17136, 17147, 17159, 17170, 17186, 17202,
+ 17214, 17225, 17237, 17248, 17261, 17273, 17286, 17298, 17310, 17321, 17333, 17344, 17353, 17362,
+ 17371, 17380, 17389, 17398, 17408, 17418, 17433, 17447, 17462, 17476, 17486, 17496, 17505, 17514,
+ 17523, 17532, 17541, 17550, 17559, 17568, 17577, 17586, 17595, 17604, 17613, 17622, 17631, 17640,
+ 17649, 17658, 17667, 17676, 17685, 17694, 17703, 17712, 17723, 17734, 17745, 17756, 17767, 17778,
+ 17789, 17800, 17811, 17822, 17833, 17844, 17855, 17866, 17877, 17888, 17899, 17910, 17921, 17932,
+ 17943, 17954, 17965, 17976, 17987, 17996, 18005, 18019, 18032, 18046, 18059, 18069, 18079, 18088,
+ 18097, 18106, 18119, 18128, 18141, 18150, 18159, 18169, 18179, 18186, 18195, 18204, 18211, 18220,
+ 18229, 18236, 18245, 18254, 18265, 18276, 18287, 18298, 18309, 18320, 18325, 18331, 18337, 18345,
+ 18353, 18361, 18369, 18377, 18385, 18391, 18397, 18409, 18420, 18431, 18442, 18451, 18460, 18472,
+ 18483, 18495, 18506, 18515, 18524, 18534, 18544, 18554, 18564, 18576, 18587, 18599, 18610, 18622,
+ 18633, 18645, 18656, 18668, 18679, 18691, 18702, 18711, 18719, 18727, 18735, 18743, 18751, 18759,
+ 18767, 18775, 18783, 18791, 18799, 18807, 18815, 18823, 18831, 18840, 18848, 18856, 18864, 18872,
+ 18880, 18888, 18896, 18904, 18912, 18920, 18928, 18936, 18944, 18952, 18960, 18969, 18978, 18987,
+ 18996, 19006, 19016, 19026, 19036, 19044, 19052, 19060, 19068, 19080, 19092, 19104, 19116, 19129,
+ 19142, 19154, 19166, 19178, 19190, 19202, 19214, 19227, 19240, 19252, 19264, 19272, 19282, 19292,
+ 19302, 19312, 19321, 19329, 19339, 19349, 19359, 19369, 19378, 19386, 19396, 19406, 19412, 19419,
+ 19428, 19437, 19446, 19455, 19464, 19473, 19482, 19489, 19496, 19504, 19513, 19521, 19529, 19538,
+ 19546, 19554, 19563, 19571, 19579, 19588, 19596, 19604, 19613, 19621, 19629, 19638, 19646, 19653,
+ 19661, 19668, 19675, 19683, 19690, 19697, 19708, 19715, 19726, 19733, 19744, 19751, 19762, 19770,
+ 19779, 19787, 19795, 19804, 19812, 19820, 19829, 19837, 19845, 19854, 19862, 19870, 19879, 19887,
+ 19895, 19904, 19912, 19919, 19927, 19934, 19941, 19949, 19956, 19962, 19968, 19974, 19981, 19994,
+ 20004, 20014, 20024, 20034, 20045, 20055, 20065, 20075, 20085, 20089, 20094, 20102, 20111, 20119,
+ 20127, 20136, 20144, 20152, 20161, 20169, 20177, 20186, 20194, 20202, 20211, 20219, 20227, 20236,
+ 20244, 20251, 20259, 20266, 20273, 20281, 20288, 20296, 20305, 20313, 20321, 20330, 20338, 20346,
+ 20355, 20363, 20371, 20380, 20388, 20396, 20405, 20413, 20421, 20430, 20438, 20445, 20453, 20460,
+ 20467, 20475, 20482, 20495, 20508, 20521, 20534, 20547, 20560, 20573, 20586, 20590, 20599, 20612,
+ 20621, 20634, 20643, 20656, 20665, 20678, 20683, 20691, 20700, 20708, 20716, 20725, 20733, 20741,
+ 20750, 20758, 20766, 20775, 20783, 20791, 20800, 20808, 20816, 20825, 20833, 20840, 20848, 20855,
+ 20862, 20870, 20877, 20886, 20894, 20903, 20911, 20919, 20928, 20936, 20944, 20956, 20965, 20973,
+ 20982, 20990, 20998, 21007, 21015, 21023, 21035, 21044, 21054, 21063, 21071, 21081, 21090, 21098,
+ 21106, 21118, 21125, 21132, 21139, 21146, 21153, 21160, 21171, 21178, 21185, 21192, 21198, 21205,
+ 21212, 21218, 21224, 21231, 21238, 21248, 21258, 21268, 21277, 21283, 21289, 21295, 21301, 21308,
+ 21315, 21321, 21327, 21334, 21341, 21347, 21353, 21360, 21367, 21374, 21381, 21388, 21395, 21402,
+ 21409, 21415, 21421, 21427, 21433, 21439, 21445, 21452, 21458, 21466, 21475, 21483, 21491, 21500,
+ 21508, 21516, 21525, 21533, 21541, 21550, 21558, 21566, 21575, 21583, 21591, 21600, 21608, 21615,
+ 21623, 21630, 21637, 21645, 21652, 21663, 21674, 21685, 21696, 21707, 21718, 21729, 21740, 21751,
+ 21762, 21773, 21784, 21792, 21801, 21809, 21817, 21826, 21834, 21842, 21851, 21859, 21867, 21876,
+ 21884, 21892, 21901, 21909, 21917, 21926, 21934, 21941, 21949, 21956, 21963, 21971, 21978, 21989,
+ 22000, 22011, 22022, 22033, 22044, 22055, 22066, 22077, 22088, 22099, 22110, 22120, 22130, 22140,
+ 22150, 22156, 22162, 22171, 22180, 22189, 22197, 22205, 22213, 22221, 22229, 22237, 22245, 22253,
+ 22261, 22273, 22281, 22293, 22301, 22313, 22321, 22333, 22341, 22353, 22361, 22373, 22381, 22393,
+ 22401, 22413, 22420, 22430, 22440, 22450, 22460, 22464, 22468, 22472, 22480, 22486, 22492, 22498,
+ 22503, 22508, 22516, 22524, 22533, 22542, 22551, 22559, 22568, 22577, 22588, 22599, 22610, 22620,
+ 22630, 22642, 22652, 22664, 22676, 22683, 22692, 22700, 22709, 22717, 22725, 22734, 22742, 22750,
+ 22762, 22771, 22779, 22788, 22796, 22804, 22813, 22821, 22829, 22841, 22850, 22860, 22869, 22877,
+ 22887, 22896, 22904, 22912, 22924, 22931, 22938, 22945, 22952, 22959, 22966, 22977, 22985, 22993,
+ 23001, 23009, 23019, 23029, 23040, 23051, 23063, 23074, 23085, 23096, 23109, 23122, 23135, 23149,
+ 23163, 23177, 23191, 23205, 23219, 23230, 23238, 23250, 23258, 23270, 23278, 23290, 23298, 23310,
+ 23319, 23328, 23338, 23348, 23359, 23369, 23378, 23388, 23397, 23407, 23419, 23428, 23440, 23452,
+ 23465, 23478, 23491, 23504, 23517, 23530, 23540, 23547, 23555, 23564, 23572, 23582, 23589, 23598,
+ 23607, 23616, 23627, 23638, 23651, 23662, 23675, 23685, 23694, 23703, 23712, 23721, 23731, 23740,
+ 23749, 23758, 23767, 23777, 23788, 23799, 23808, 23817, 23825, 23833, 23841, 23849, 23857, 23868,
+ 23879, 23884, 23890, 23899, 23908, 23917, 23927, 23937, 23947, 23957, 23967, 23976, 23986, 23995,
+ 24007, 24019, 24031, 24042, 24053, 24064, 24072, 24083, 24094, 24105, 24116, 24127, 24138, 24149,
+ 24160, 24182, 24188, 24194, 24200, 24206, 24213, 24222, 24231, 24240, 24249, 24260, 24271, 24282,
+ 24293, 24302, 24314, 24326, 24338, 24350, 24357, 24363, 24370, 24383, 24388, 24395, 24406, 24423,
+ 24434, 24440, 24449, 24458, 24467, 24476, 24485, 24494, 24502, 24510, 24519, 24528, 24537, 24546,
+ 24555, 24564, 24573, 24582, 24591, 24599, 24607, 24613, 24618, 24627, 24635, 24644, 24652, 24660,
+ 24669, 24677, 24685, 24697, 24706, 24714, 24723, 24731, 24739, 24748, 24756, 24764, 24776, 24785,
+ 24795, 24804, 24812, 24822, 24831, 24839, 24847, 24859, 24866, 24873, 24880, 24887, 24894, 24901,
+ 24912, 24920, 24928, 24936, 0
};
const char *Strs =
@@ -3811,57 +3803,56 @@ const char *X86IntelInstPrinter::getInstructionName(unsigned Opcode) {
"DI2SSrm\000MOVDI2SSrr\000MOVDQAmr\000MOVDQArm\000MOVDQArr\000MOVDQUmr\000"
"MOVDQUmr_Int\000MOVDQUrm\000MOVDQUrm_Int\000MOVHLPSrr\000MOVHPDmr\000MO"
"VHPDrm\000MOVHPSmr\000MOVHPSrm\000MOVLHPSrr\000MOVLPDmr\000MOVLPDrm\000"
- "MOVLPDrr\000MOVLPSmr\000MOVLPSrm\000MOVLPSrr\000MOVLQ128mr\000MOVLSD2PD"
- "rr\000MOVLSS2PSrr\000MOVMSKPDrr\000MOVMSKPSrr\000MOVNTDQArm\000MOVNTDQm"
- "r\000MOVNTImr\000MOVNTPDmr\000MOVNTPSmr\000MOVPC32r\000MOVPD2SDmr\000MO"
- "VPD2SDrr\000MOVPDI2DImr\000MOVPDI2DIrr\000MOVPQI2QImr\000MOVPQIto64rr\000"
- "MOVPS2SSmr\000MOVPS2SSrr\000MOVQI2PQIrm\000MOVQxrxr\000MOVSB\000MOVSD\000"
- "MOVSD2PDrm\000MOVSD2PDrr\000MOVSDmr\000MOVSDrm\000MOVSDrr\000MOVSDto64m"
- "r\000MOVSDto64rr\000MOVSHDUPrm\000MOVSHDUPrr\000MOVSLDUPrm\000MOVSLDUPr"
- "r\000MOVSS2DImr\000MOVSS2DIrr\000MOVSS2PSrm\000MOVSS2PSrr\000MOVSSmr\000"
- "MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16rm8\000MOVSX16rm8W\000MOVSX16rr8\000"
- "MOVSX16rr8W\000MOVSX32rm16\000MOVSX32rm8\000MOVSX32rr16\000MOVSX32rr8\000"
- "MOVSX64rm16\000MOVSX64rm32\000MOVSX64rm8\000MOVSX64rr16\000MOVSX64rr32\000"
- "MOVSX64rr8\000MOVUPDmr\000MOVUPDmr_Int\000MOVUPDrm\000MOVUPDrm_Int\000M"
- "OVUPDrr\000MOVUPSmr\000MOVUPSmr_Int\000MOVUPSrm\000MOVUPSrm_Int\000MOVU"
- "PSrr\000MOVZDI2PDIrm\000MOVZDI2PDIrr\000MOVZPQILo2PQIrm\000MOVZPQILo2PQ"
- "Irr\000MOVZQI2PQIrm\000MOVZQI2PQIrr\000MOVZSD2PDrm\000MOVZSS2PSrm\000MO"
- "VZX16rm8\000MOVZX16rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX32_NOREXrm"
- "8\000MOVZX32_NOREXrr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32rr16\000MO"
- "VZX32rr8\000MOVZX64rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MOVZX64rm8\000"
- "MOVZX64rm8_Q\000MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32\000MOVZX64r"
- "r8\000MOVZX64rr8_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp3280\000MOV_Fp6"
- "432\000MOV_Fp6464\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064\000MOV_Fp80"
- "80\000MPSADBWrmi\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32m\000MUL32r\000"
- "MUL64m\000MUL64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr\000MULPSrm\000"
- "MULPSrr\000MULSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_Int\000MULSSrm\000"
- "MULSSrm_Int\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000MUL_F64m\000MUL_FI"
- "16m\000MUL_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp32\000MUL_Fp32m\000"
- "MUL_Fp64\000MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000MUL_Fp80m32\000MUL_"
- "Fp80m64\000MUL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16m80\000MUL_FpI32m32"
- "\000MUL_FpI32m64\000MUL_FpI32m80\000MUL_FrST0\000MWAIT\000NEG16m\000NEG"
- "16r\000NEG32m\000NEG32r\000NEG64m\000NEG64r\000NEG8m\000NEG8r\000NOOP\000"
- "NOOPL\000NOOPW\000NOT16m\000NOT16r\000NOT32m\000NOT32r\000NOT64m\000NOT"
- "64r\000NOT8m\000NOT8r\000OR16i16\000OR16mi\000OR16mi8\000OR16mr\000OR16"
- "ri\000OR16ri8\000OR16rm\000OR16rr\000OR16rr_REV\000OR32i32\000OR32mi\000"
- "OR32mi8\000OR32mr\000OR32ri\000OR32ri8\000OR32rm\000OR32rr\000OR32rr_RE"
- "V\000OR64i32\000OR64mi32\000OR64mi8\000OR64mr\000OR64ri32\000OR64ri8\000"
- "OR64rm\000OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000OR8mr\000OR8ri\000O"
- "R8rm\000OR8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000ORPSrm\000ORPSrr\000O"
- "UT16ir\000OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000OUT8rr\000OUTSB\000"
- "OUTSD\000OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr128\000PABSBrr64\000"
- "PABSDrm128\000PABSDrm64\000PABSDrr128\000PABSDrr64\000PABSWrm128\000PAB"
- "SWrm64\000PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PACKSSDWrr\000PACKSS"
- "WBrm\000PACKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACKUSWBrm\000PACKUSW"
- "Brr\000PADDBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PADDQrm\000PADDQrr\000"
- "PADDSBrm\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADDUSBrm\000PADDUSBrr\000"
- "PADDUSWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000PALIGNR128rm\000PALIGNR"
- "128rr\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000PANDNrr\000PANDrm\000"
- "PANDrr\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr\000PBLENDVBrm0\000PB"
- "LENDVBrr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm\000PCMPEQBrr\000PCMP"
- "EQDrm\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PCMPEQWrm\000PCMPEQWrr\000"
- "PCMPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000PCMPESTRICrr\000PCMPEST"
- "RIOrm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPESTRISrr\000PCMPESTRIZrm\000"
+ "MOVLPSmr\000MOVLPSrm\000MOVLQ128mr\000MOVMSKPDrr\000MOVMSKPSrr\000MOVNT"
+ "DQArm\000MOVNTDQ_64mr\000MOVNTDQmr\000MOVNTDQmr_Int\000MOVNTI_64mr\000M"
+ "OVNTImr\000MOVNTImr_Int\000MOVNTPDmr\000MOVNTPDmr_Int\000MOVNTPSmr\000M"
+ "OVNTPSmr_Int\000MOVPC32r\000MOVPDI2DImr\000MOVPDI2DIrr\000MOVPQI2QImr\000"
+ "MOVPQIto64rr\000MOVQI2PQIrm\000MOVQxrxr\000MOVSB\000MOVSD\000MOVSDmr\000"
+ "MOVSDrm\000MOVSDrr\000MOVSDto64mr\000MOVSDto64rr\000MOVSHDUPrm\000MOVSH"
+ "DUPrr\000MOVSLDUPrm\000MOVSLDUPrr\000MOVSS2DImr\000MOVSS2DIrr\000MOVSSm"
+ "r\000MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16rm8\000MOVSX16rm8W\000MOVSX1"
+ "6rr8\000MOVSX16rr8W\000MOVSX32rm16\000MOVSX32rm8\000MOVSX32rr16\000MOVS"
+ "X32rr8\000MOVSX64rm16\000MOVSX64rm32\000MOVSX64rm8\000MOVSX64rr16\000MO"
+ "VSX64rr32\000MOVSX64rr8\000MOVUPDmr\000MOVUPDmr_Int\000MOVUPDrm\000MOVU"
+ "PDrm_Int\000MOVUPDrr\000MOVUPSmr\000MOVUPSmr_Int\000MOVUPSrm\000MOVUPSr"
+ "m_Int\000MOVUPSrr\000MOVZDI2PDIrm\000MOVZDI2PDIrr\000MOVZPQILo2PQIrm\000"
+ "MOVZPQILo2PQIrr\000MOVZQI2PQIrm\000MOVZQI2PQIrr\000MOVZX16rm8\000MOVZX1"
+ "6rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX32_NOREXrm8\000MOVZX32_NOREX"
+ "rr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32rr16\000MOVZX32rr8\000MOVZX6"
+ "4rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MOVZX64rm8\000MOVZX64rm8_Q\000"
+ "MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32\000MOVZX64rr8\000MOVZX64rr8"
+ "_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp3280\000MOV_Fp6432\000MOV_Fp646"
+ "4\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064\000MOV_Fp8080\000MPSADBWrmi"
+ "\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32m\000MUL32r\000MUL64m\000MUL"
+ "64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr\000MULPSrm\000MULPSrr\000MU"
+ "LSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_Int\000MULSSrm\000MULSSrm_In"
+ "t\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000MUL_F64m\000MUL_FI16m\000MUL"
+ "_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp32\000MUL_Fp32m\000MUL_Fp64\000"
+ "MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000MUL_Fp80m32\000MUL_Fp80m64\000M"
+ "UL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16m80\000MUL_FpI32m32\000MUL_FpI3"
+ "2m64\000MUL_FpI32m80\000MUL_FrST0\000MWAIT\000NEG16m\000NEG16r\000NEG32"
+ "m\000NEG32r\000NEG64m\000NEG64r\000NEG8m\000NEG8r\000NOOP\000NOOPL\000N"
+ "OOPW\000NOT16m\000NOT16r\000NOT32m\000NOT32r\000NOT64m\000NOT64r\000NOT"
+ "8m\000NOT8r\000OR16i16\000OR16mi\000OR16mi8\000OR16mr\000OR16ri\000OR16"
+ "ri8\000OR16rm\000OR16rr\000OR16rr_REV\000OR32i32\000OR32mi\000OR32mi8\000"
+ "OR32mr\000OR32ri\000OR32ri8\000OR32rm\000OR32rr\000OR32rr_REV\000OR64i3"
+ "2\000OR64mi32\000OR64mi8\000OR64mr\000OR64ri32\000OR64ri8\000OR64rm\000"
+ "OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000OR8mr\000OR8ri\000OR8rm\000OR"
+ "8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000ORPSrm\000ORPSrr\000OUT16ir\000"
+ "OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000OUT8rr\000OUTSB\000OUTSD\000"
+ "OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr128\000PABSBrr64\000PABSDrm1"
+ "28\000PABSDrm64\000PABSDrr128\000PABSDrr64\000PABSWrm128\000PABSWrm64\000"
+ "PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PACKSSDWrr\000PACKSSWBrm\000PA"
+ "CKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACKUSWBrm\000PACKUSWBrr\000PAD"
+ "DBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PADDQrm\000PADDQrr\000PADDSBrm"
+ "\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADDUSBrm\000PADDUSBrr\000PADDU"
+ "SWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000PALIGNR128rm\000PALIGNR128rr"
+ "\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000PANDNrr\000PANDrm\000PANDr"
+ "r\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr\000PBLENDVBrm0\000PBLENDV"
+ "Brr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm\000PCMPEQBrr\000PCMPEQDrm"
+ "\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PCMPEQWrm\000PCMPEQWrr\000PC"
+ "MPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000PCMPESTRICrr\000PCMPESTRI"
+ "Orm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPESTRISrr\000PCMPESTRIZrm\000"
"PCMPESTRIZrr\000PCMPESTRIrm\000PCMPESTRIrr\000PCMPESTRM128MEM\000PCMPES"
"TRM128REG\000PCMPESTRM128rm\000PCMPESTRM128rr\000PCMPGTBrm\000PCMPGTBrr"
"\000PCMPGTDrm\000PCMPGTDrr\000PCMPGTQrm\000PCMPGTQrr\000PCMPGTWrm\000PC"
diff --git a/libclamav/c++/X86GenDAGISel.inc b/libclamav/c++/X86GenDAGISel.inc
index 75e490e..72257cd 100644
--- a/libclamav/c++/X86GenDAGISel.inc
+++ b/libclamav/c++/X86GenDAGISel.inc
@@ -9,347 +9,318 @@
// *** NOTE: This file is #included into the middle of the target
// *** instruction selector class. These functions are really methods.
-// Include standard, target-independent definitions and methods used
-// by the instruction selector.
-#include "llvm/CodeGen/DAGISelHeader.h"
+// Predicate functions.
+inline bool Predicate_alignedload(SDNode *N) const {
-// Node transformations.
-inline SDValue Transform_BYTE_imm(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // Transformation function: imm >> 3
- return getI32Imm(N->getZExtValue() >> 3);
-
-}
-inline SDValue Transform_MMX_SHUFFLE_get_shuf_imm(SDNode *N) {
-
- return getI8Imm(X86::getShuffleSHUFImmediate(N));
-
-}
-inline SDValue Transform_SHUFFLE_get_palign_imm(SDNode *N) {
-
- return getI8Imm(X86::getShufflePALIGNRImmediate(N));
-
-}
-inline SDValue Transform_SHUFFLE_get_pshufhw_imm(SDNode *N) {
-
- return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
-
-}
-inline SDValue Transform_SHUFFLE_get_pshuflw_imm(SDNode *N) {
-
- return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
-
-}
-inline SDValue Transform_SHUFFLE_get_shuf_imm(SDNode *N) {
-
- return getI8Imm(X86::getShuffleSHUFImmediate(N));
+ return cast<LoadSDNode>(N)->getAlignment() >= 16;
}
+inline bool Predicate_alignednontemporalstore(SDNode *N) const {
-// Predicate functions.
-inline bool Predicate_alignedload(SDNode *N) {
-
- return cast<LoadSDNode>(N)->getAlignment() >= 16;
+ if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
+ return ST->isNonTemporal() && !ST->isTruncatingStore() &&
+ ST->getAddressingMode() == ISD::UNINDEXED &&
+ ST->getAlignment() >= 16;
+ return false;
}
-inline bool Predicate_alignedstore(SDNode *N) {
+inline bool Predicate_alignedstore(SDNode *N) const {
return cast<StoreSDNode>(N)->getAlignment() >= 16;
}
-inline bool Predicate_and_su(SDNode *N) {
+inline bool Predicate_and_su(SDNode *N) const {
return N->hasOneUse();
}
-inline bool Predicate_atomic_cmp_swap_16(SDNode *N) {
+inline bool Predicate_atomic_cmp_swap_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_cmp_swap_32(SDNode *N) {
+inline bool Predicate_atomic_cmp_swap_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_cmp_swap_64(SDNode *N) {
+inline bool Predicate_atomic_cmp_swap_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_cmp_swap_8(SDNode *N) {
+inline bool Predicate_atomic_cmp_swap_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_add_16(SDNode *N) {
+inline bool Predicate_atomic_load_add_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_add_32(SDNode *N) {
+inline bool Predicate_atomic_load_add_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_add_64(SDNode *N) {
+inline bool Predicate_atomic_load_add_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_add_8(SDNode *N) {
+inline bool Predicate_atomic_load_add_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_and_16(SDNode *N) {
+inline bool Predicate_atomic_load_and_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_and_32(SDNode *N) {
+inline bool Predicate_atomic_load_and_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_and_64(SDNode *N) {
+inline bool Predicate_atomic_load_and_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_and_8(SDNode *N) {
+inline bool Predicate_atomic_load_and_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_max_16(SDNode *N) {
+inline bool Predicate_atomic_load_max_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_max_32(SDNode *N) {
+inline bool Predicate_atomic_load_max_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_max_64(SDNode *N) {
+inline bool Predicate_atomic_load_max_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_max_8(SDNode *N) {
+inline bool Predicate_atomic_load_max_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_min_16(SDNode *N) {
+inline bool Predicate_atomic_load_min_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_min_32(SDNode *N) {
+inline bool Predicate_atomic_load_min_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_min_64(SDNode *N) {
+inline bool Predicate_atomic_load_min_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_min_8(SDNode *N) {
+inline bool Predicate_atomic_load_min_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_nand_16(SDNode *N) {
+inline bool Predicate_atomic_load_nand_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_nand_32(SDNode *N) {
+inline bool Predicate_atomic_load_nand_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_nand_64(SDNode *N) {
+inline bool Predicate_atomic_load_nand_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_nand_8(SDNode *N) {
+inline bool Predicate_atomic_load_nand_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_or_16(SDNode *N) {
+inline bool Predicate_atomic_load_or_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_or_32(SDNode *N) {
+inline bool Predicate_atomic_load_or_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_or_64(SDNode *N) {
+inline bool Predicate_atomic_load_or_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_or_8(SDNode *N) {
+inline bool Predicate_atomic_load_or_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_sub_16(SDNode *N) {
+inline bool Predicate_atomic_load_sub_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_sub_32(SDNode *N) {
+inline bool Predicate_atomic_load_sub_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_sub_64(SDNode *N) {
+inline bool Predicate_atomic_load_sub_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_sub_8(SDNode *N) {
+inline bool Predicate_atomic_load_sub_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_umax_16(SDNode *N) {
+inline bool Predicate_atomic_load_umax_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_umax_32(SDNode *N) {
+inline bool Predicate_atomic_load_umax_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_umax_64(SDNode *N) {
+inline bool Predicate_atomic_load_umax_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_umax_8(SDNode *N) {
+inline bool Predicate_atomic_load_umax_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_umin_16(SDNode *N) {
+inline bool Predicate_atomic_load_umin_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_umin_32(SDNode *N) {
+inline bool Predicate_atomic_load_umin_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_umin_64(SDNode *N) {
+inline bool Predicate_atomic_load_umin_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_umin_8(SDNode *N) {
+inline bool Predicate_atomic_load_umin_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_load_xor_16(SDNode *N) {
+inline bool Predicate_atomic_load_xor_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_load_xor_32(SDNode *N) {
+inline bool Predicate_atomic_load_xor_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_load_xor_64(SDNode *N) {
+inline bool Predicate_atomic_load_xor_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_load_xor_8(SDNode *N) {
+inline bool Predicate_atomic_load_xor_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_atomic_swap_16(SDNode *N) {
+inline bool Predicate_atomic_swap_16(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_atomic_swap_32(SDNode *N) {
+inline bool Predicate_atomic_swap_32(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_atomic_swap_64(SDNode *N) {
+inline bool Predicate_atomic_swap_64(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
}
-inline bool Predicate_atomic_swap_8(SDNode *N) {
+inline bool Predicate_atomic_swap_8(SDNode *N) const {
return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_cvtff(SDNode *N) {
+inline bool Predicate_cvtff(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
}
-inline bool Predicate_cvtfs(SDNode *N) {
+inline bool Predicate_cvtfs(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
}
-inline bool Predicate_cvtfu(SDNode *N) {
+inline bool Predicate_cvtfu(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
}
-inline bool Predicate_cvtsf(SDNode *N) {
+inline bool Predicate_cvtsf(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
}
-inline bool Predicate_cvtss(SDNode *N) {
+inline bool Predicate_cvtss(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
}
-inline bool Predicate_cvtsu(SDNode *N) {
+inline bool Predicate_cvtsu(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
}
-inline bool Predicate_cvtuf(SDNode *N) {
+inline bool Predicate_cvtuf(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
}
-inline bool Predicate_cvtus(SDNode *N) {
+inline bool Predicate_cvtus(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
}
-inline bool Predicate_cvtuu(SDNode *N) {
+inline bool Predicate_cvtuu(SDNode *N) const {
return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
}
-inline bool Predicate_def32(SDNode *N) {
+inline bool Predicate_def32(SDNode *N) const {
return N->getOpcode() != ISD::TRUNCATE &&
N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
@@ -357,72 +328,81 @@ inline bool Predicate_def32(SDNode *N) {
N->getOpcode() != X86ISD::CMOV;
}
-inline bool Predicate_extload(SDNode *N) {
+inline bool Predicate_dsload(SDNode *N) const {
+
+ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ return true;
+
+}
+inline bool Predicate_extload(SDNode *N) const {
return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
}
-inline bool Predicate_extloadf32(SDNode *N) {
+inline bool Predicate_extloadf32(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
}
-inline bool Predicate_extloadf64(SDNode *N) {
+inline bool Predicate_extloadf64(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
}
-inline bool Predicate_extloadi1(SDNode *N) {
+inline bool Predicate_extloadi1(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_extloadi16(SDNode *N) {
+inline bool Predicate_extloadi16(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_extloadi32(SDNode *N) {
+inline bool Predicate_extloadi32(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_extloadi8(SDNode *N) {
+inline bool Predicate_extloadi8(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_fp32imm0(SDNode *inN) {
+inline bool Predicate_fp32imm0(SDNode *inN) const {
ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
return N->isExactlyValue(+0.0);
}
-inline bool Predicate_fpimm0(SDNode *inN) {
+inline bool Predicate_fpimm0(SDNode *inN) const {
ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
return N->isExactlyValue(+0.0);
}
-inline bool Predicate_fpimm1(SDNode *inN) {
+inline bool Predicate_fpimm1(SDNode *inN) const {
ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
return N->isExactlyValue(+1.0);
}
-inline bool Predicate_fpimmneg0(SDNode *inN) {
+inline bool Predicate_fpimmneg0(SDNode *inN) const {
ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
return N->isExactlyValue(-0.0);
}
-inline bool Predicate_fpimmneg1(SDNode *inN) {
+inline bool Predicate_fpimmneg1(SDNode *inN) const {
ConstantFPSDNode *N = cast<ConstantFPSDNode>(inN);
return N->isExactlyValue(-1.0);
}
-inline bool Predicate_fsload(SDNode *N) {
+inline bool Predicate_fsload(SDNode *N) const {
if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
@@ -430,7 +410,7 @@ inline bool Predicate_fsload(SDNode *N) {
return false;
}
-inline bool Predicate_gsload(SDNode *N) {
+inline bool Predicate_gsload(SDNode *N) const {
if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
@@ -438,23 +418,7 @@ inline bool Predicate_gsload(SDNode *N) {
return false;
}
-inline bool Predicate_i16immSExt8(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
- // sign extended field.
- return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
-
-}
-inline bool Predicate_i32immSExt8(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
- // sign extended field.
- return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
-
-}
-inline bool Predicate_i64immSExt32(SDNode *inN) {
+inline bool Predicate_i64immSExt32(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
// i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
@@ -462,15 +426,7 @@ inline bool Predicate_i64immSExt32(SDNode *inN) {
return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
}
-inline bool Predicate_i64immSExt8(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
-
- // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
- // sign extended field.
- return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
-
-}
-inline bool Predicate_i64immZExt32(SDNode *inN) {
+inline bool Predicate_i64immZExt32(SDNode *inN) const {
ConstantSDNode *N = cast<ConstantSDNode>(inN);
// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
@@ -478,73 +434,48 @@ inline bool Predicate_i64immZExt32(SDNode *inN) {
return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
}
-inline bool Predicate_immAllOnes(SDNode *inN) {
- ConstantSDNode *N = cast<ConstantSDNode>(inN);
- return N->isAllOnesValue();
-}
-inline bool Predicate_immAllOnesV(SDNode *N) {
+inline bool Predicate_immAllOnesV(SDNode *N) const {
return ISD::isBuildVectorAllOnes(N);
}
-inline bool Predicate_immAllOnesV_bc(SDNode *N) {
+inline bool Predicate_immAllOnesV_bc(SDNode *N) const {
return ISD::isBuildVectorAllOnes(N);
}
-inline bool Predicate_immAllZerosV(SDNode *N) {
+inline bool Predicate_immAllZerosV(SDNode *N) const {
return ISD::isBuildVectorAllZeros(N);
}
-inline bool Predicate_immAllZerosV_bc(SDNode *N) {
+inline bool Predicate_immAllZerosV_bc(SDNode *N) const {
return ISD::isBuildVectorAllZeros(N);
}
-inline bool Predicate_istore(SDNode *N) {
-
- return !cast<StoreSDNode>(N)->isTruncatingStore();
-
-}
-inline bool Predicate_itruncstore(SDNode *N) {
-
- return cast<StoreSDNode>(N)->isTruncatingStore();
-
-}
-inline bool Predicate_load(SDNode *N) {
+inline bool Predicate_immSext8(SDNode *inN) const {
+ ConstantSDNode *N = cast<ConstantSDNode>(inN);
- return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
+ return N->getSExtValue() == (int8_t)N->getSExtValue();
}
-inline bool Predicate_loadf32(SDNode *N) {
+inline bool Predicate_istore(SDNode *N) const {
- if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
- if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
- if (PT->getAddressSpace() > 255)
- return false;
- return true;
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
}
-inline bool Predicate_loadf64(SDNode *N) {
+inline bool Predicate_itruncstore(SDNode *N) const {
- if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
- if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
- if (PT->getAddressSpace() > 255)
- return false;
- return true;
+ return cast<StoreSDNode>(N)->isTruncatingStore();
}
-inline bool Predicate_loadf80(SDNode *N) {
+inline bool Predicate_load(SDNode *N) const {
- if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
- if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
- if (PT->getAddressSpace() > 255)
- return false;
- return true;
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
}
-inline bool Predicate_loadi16(SDNode *N) {
+inline bool Predicate_loadi16(SDNode *N) const {
LoadSDNode *LD = cast<LoadSDNode>(N);
if (const Value *Src = LD->getSrcValue())
@@ -559,7 +490,7 @@ inline bool Predicate_loadi16(SDNode *N) {
return false;
}
-inline bool Predicate_loadi16_anyext(SDNode *N) {
+inline bool Predicate_loadi16_anyext(SDNode *N) const {
LoadSDNode *LD = cast<LoadSDNode>(N);
if (const Value *Src = LD->getSrcValue())
@@ -572,7 +503,7 @@ inline bool Predicate_loadi16_anyext(SDNode *N) {
return false;
}
-inline bool Predicate_loadi32(SDNode *N) {
+inline bool Predicate_loadi32(SDNode *N) const {
LoadSDNode *LD = cast<LoadSDNode>(N);
if (const Value *Src = LD->getSrcValue())
@@ -587,118 +518,90 @@ inline bool Predicate_loadi32(SDNode *N) {
return false;
}
-inline bool Predicate_loadi64(SDNode *N) {
-
- if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
- if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
- if (PT->getAddressSpace() > 255)
- return false;
- return true;
-
-}
-inline bool Predicate_loadi8(SDNode *N) {
-
- if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
- if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
- if (PT->getAddressSpace() > 255)
- return false;
- return true;
-
-}
-inline bool Predicate_memop(SDNode *N) {
+inline bool Predicate_memop(SDNode *N) const {
return Subtarget->hasVectorUAMem()
|| cast<LoadSDNode>(N)->getAlignment() >= 16;
}
-inline bool Predicate_memop64(SDNode *N) {
+inline bool Predicate_memop64(SDNode *N) const {
return cast<LoadSDNode>(N)->getAlignment() >= 8;
}
-inline bool Predicate_mmx_pshufw(SDNode *N) {
+inline bool Predicate_mmx_pshufw(SDNode *N) const {
return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_mmx_unpckh(SDNode *N) {
+inline bool Predicate_mmx_unpckh(SDNode *N) const {
return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_mmx_unpckh_undef(SDNode *N) {
+inline bool Predicate_mmx_unpckh_undef(SDNode *N) const {
return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_mmx_unpckl(SDNode *N) {
+inline bool Predicate_mmx_unpckl(SDNode *N) const {
return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_mmx_unpckl_undef(SDNode *N) {
+inline bool Predicate_mmx_unpckl_undef(SDNode *N) const {
return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_movddup(SDNode *N) {
+inline bool Predicate_movddup(SDNode *N) const {
return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_movhlps(SDNode *N) {
+inline bool Predicate_movhlps(SDNode *N) const {
return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_movhlps_undef(SDNode *N) {
+inline bool Predicate_movhlps_undef(SDNode *N) const {
return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_movl(SDNode *N) {
+inline bool Predicate_movl(SDNode *N) const {
return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_movlhps(SDNode *N) {
+inline bool Predicate_movlhps(SDNode *N) const {
return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_movlp(SDNode *N) {
+inline bool Predicate_movlp(SDNode *N) const {
return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_movshdup(SDNode *N) {
+inline bool Predicate_movshdup(SDNode *N) const {
return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_movsldup(SDNode *N) {
+inline bool Predicate_movsldup(SDNode *N) const {
return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_nvloadi32(SDNode *N) {
+inline bool Predicate_nontemporalstore(SDNode *N) const {
- LoadSDNode *LD = cast<LoadSDNode>(N);
- if (const Value *Src = LD->getSrcValue())
- if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
- if (PT->getAddressSpace() > 255)
- return false;
- if (LD->isVolatile())
- return false;
- ISD::LoadExtType ExtType = LD->getExtensionType();
- if (ExtType == ISD::NON_EXTLOAD)
- return true;
- if (ExtType == ISD::EXTLOAD)
- return LD->getAlignment() >= 4;
+ if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
+ return ST->isNonTemporal();
return false;
}
-inline bool Predicate_or_is_add(SDNode *N) {
+inline bool Predicate_or_is_add(SDNode *N) const {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
@@ -713,126 +616,126 @@ inline bool Predicate_or_is_add(SDNode *N) {
}
}
-inline bool Predicate_palign(SDNode *N) {
+inline bool Predicate_palign(SDNode *N) const {
return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_post_store(SDNode *N) {
+inline bool Predicate_post_store(SDNode *N) const {
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::POST_INC || AM == ISD::POST_DEC;
}
-inline bool Predicate_post_truncst(SDNode *N) {
+inline bool Predicate_post_truncst(SDNode *N) const {
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::POST_INC || AM == ISD::POST_DEC;
}
-inline bool Predicate_post_truncstf32(SDNode *N) {
+inline bool Predicate_post_truncstf32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}
-inline bool Predicate_post_truncsti1(SDNode *N) {
+inline bool Predicate_post_truncsti1(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_post_truncsti16(SDNode *N) {
+inline bool Predicate_post_truncsti16(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_post_truncsti32(SDNode *N) {
+inline bool Predicate_post_truncsti32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_post_truncsti8(SDNode *N) {
+inline bool Predicate_post_truncsti8(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_pre_store(SDNode *N) {
+inline bool Predicate_pre_store(SDNode *N) const {
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
}
-inline bool Predicate_pre_truncst(SDNode *N) {
+inline bool Predicate_pre_truncst(SDNode *N) const {
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
}
-inline bool Predicate_pre_truncstf32(SDNode *N) {
+inline bool Predicate_pre_truncstf32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}
-inline bool Predicate_pre_truncsti1(SDNode *N) {
+inline bool Predicate_pre_truncsti1(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_pre_truncsti16(SDNode *N) {
+inline bool Predicate_pre_truncsti16(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_pre_truncsti32(SDNode *N) {
+inline bool Predicate_pre_truncsti32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_pre_truncsti8(SDNode *N) {
+inline bool Predicate_pre_truncsti8(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_pshufd(SDNode *N) {
+inline bool Predicate_pshufd(SDNode *N) const {
return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_pshufhw(SDNode *N) {
+inline bool Predicate_pshufhw(SDNode *N) const {
return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_pshuflw(SDNode *N) {
+inline bool Predicate_pshuflw(SDNode *N) const {
return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_sextload(SDNode *N) {
+inline bool Predicate_sextload(SDNode *N) const {
return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
}
-inline bool Predicate_sextloadi1(SDNode *N) {
+inline bool Predicate_sextloadi1(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_sextloadi16(SDNode *N) {
+inline bool Predicate_sextloadi16(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_sextloadi32(SDNode *N) {
+inline bool Predicate_sextloadi32(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_sextloadi8(SDNode *N) {
+inline bool Predicate_sextloadi8(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_shld(SDNode *N) {
+inline bool Predicate_shld(SDNode *N) const {
assert(N->getOpcode() == ISD::OR);
return N->getOperand(0).getOpcode() == ISD::SHL &&
@@ -843,7 +746,7 @@ inline bool Predicate_shld(SDNode *N) {
N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
}
-inline bool Predicate_shrd(SDNode *N) {
+inline bool Predicate_shrd(SDNode *N) const {
assert(N->getOpcode() == ISD::OR);
return N->getOperand(0).getOpcode() == ISD::SRL &&
@@ -854,58495 +757,34708 @@ inline bool Predicate_shrd(SDNode *N) {
N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
}
-inline bool Predicate_shufp(SDNode *N) {
+inline bool Predicate_shufp(SDNode *N) const {
return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_splat_lo(SDNode *N) {
+inline bool Predicate_splat_lo(SDNode *N) const {
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
}
-inline bool Predicate_srl_su(SDNode *N) {
+inline bool Predicate_srl_su(SDNode *N) const {
return N->hasOneUse();
}
-inline bool Predicate_store(SDNode *N) {
+inline bool Predicate_store(SDNode *N) const {
return !cast<StoreSDNode>(N)->isTruncatingStore();
}
-inline bool Predicate_trunc_su(SDNode *N) {
+inline bool Predicate_trunc_su(SDNode *N) const {
return N->hasOneUse();
}
-inline bool Predicate_truncstore(SDNode *N) {
+inline bool Predicate_truncstore(SDNode *N) const {
return cast<StoreSDNode>(N)->isTruncatingStore();
}
-inline bool Predicate_truncstoref32(SDNode *N) {
+inline bool Predicate_truncstoref32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
}
-inline bool Predicate_truncstoref64(SDNode *N) {
+inline bool Predicate_truncstoref64(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
}
-inline bool Predicate_truncstorei16(SDNode *N) {
+inline bool Predicate_truncstorei16(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_truncstorei32(SDNode *N) {
+inline bool Predicate_truncstorei32(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_truncstorei8(SDNode *N) {
+inline bool Predicate_truncstorei8(SDNode *N) const {
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}
-inline bool Predicate_unindexedload(SDNode *N) {
+inline bool Predicate_unalignednontemporalstore(SDNode *N) const {
+
+ if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
+ return ST->isNonTemporal() &&
+ ST->getAlignment() < 16;
+ return false;
+
+}
+inline bool Predicate_unindexedload(SDNode *N) const {
return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}
-inline bool Predicate_unindexedstore(SDNode *N) {
+inline bool Predicate_unindexedstore(SDNode *N) const {
return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}
-inline bool Predicate_unpckh(SDNode *N) {
+inline bool Predicate_unpckh(SDNode *N) const {
return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_unpckh_undef(SDNode *N) {
+inline bool Predicate_unpckh_undef(SDNode *N) const {
return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_unpckl(SDNode *N) {
+inline bool Predicate_unpckl(SDNode *N) const {
return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_unpckl_undef(SDNode *N) {
+inline bool Predicate_unpckl_undef(SDNode *N) const {
return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
}
-inline bool Predicate_vtFP(SDNode *inN) {
+inline bool Predicate_vtFP(SDNode *inN) const {
VTSDNode *N = cast<VTSDNode>(inN);
return N->getVT().isFloatingPoint();
}
-inline bool Predicate_vtInt(SDNode *inN) {
+inline bool Predicate_vtInt(SDNode *inN) const {
VTSDNode *N = cast<VTSDNode>(inN);
return N->getVT().isInteger();
}
-inline bool Predicate_zextload(SDNode *N) {
+inline bool Predicate_zextload(SDNode *N) const {
return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
}
-inline bool Predicate_zextloadi1(SDNode *N) {
+inline bool Predicate_zextloadi1(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
}
-inline bool Predicate_zextloadi16(SDNode *N) {
+inline bool Predicate_zextloadi16(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
}
-inline bool Predicate_zextloadi32(SDNode *N) {
+inline bool Predicate_zextloadi32(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
}
-inline bool Predicate_zextloadi8(SDNode *N) {
+inline bool Predicate_zextloadi8(SDNode *N) const {
return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
}
-DISABLE_INLINE SDNode *Emit_0(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0);
-}
-DISABLE_INLINE SDNode *Emit_1(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, N1);
-}
-DISABLE_INLINE SDNode *Emit_2(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 2));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_3(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_4(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
- return ResNode;
-}
-SDNode *Select_ISD_ADD_i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADD8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::ADD8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src1)
- // Emits: (ADD8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::ADD8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (add:i8 GR8:i8:$src, 1:i8)
- // Emits: (INC8r:i8 GR8:i8:$src)
- // Pattern complexity = 8 cost = 1 size = 2
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_0(N, X86::INC8r, MVT::i8);
- return Result;
- }
-
- // Pattern: (add:i8 GR8:i8:$src, -1:i8)
- // Emits: (DEC8r:i8 GR8:i8:$src)
- // Pattern complexity = 8 cost = 1 size = 2
- if (CN1 == INT64_C(-1)) {
- SDNode *Result = Emit_0(N, X86::DEC8r, MVT::i8);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (ADD8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_3(N, X86::ADD8ri, MVT::i8);
- return Result;
- }
- }
-
- // Pattern: (add:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (ADD8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::ADD8rr, MVT::i8);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_5(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_6(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i16);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp3);
-}
-SDNode *Select_ISD_ADD_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADD16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::ADD16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
- // Emits: (ADD16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::ADD16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (add:i16 GR16:i16:$src, 1:i16)
- // Emits: (INC16r:i16 GR16:i16:$src)
- // Pattern complexity = 8 cost = 1 size = 1
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_0(N, X86::INC16r, MVT::i16);
- return Result;
- }
-
- // Pattern: (add:i16 GR16:i16:$src, -1:i16)
- // Emits: (DEC16r:i16 GR16:i16:$src)
- // Pattern complexity = 8 cost = 1 size = 1
- if (CN1 == INT64_C(-1)) {
- SDNode *Result = Emit_0(N, X86::DEC16r, MVT::i16);
- return Result;
- }
- }
- }
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (add:i16 GR16:i16:$src, 1:i16)
- // Emits: (INC64_16r:i16 GR16:i16:$src)
- // Pattern complexity = 8 cost = 1 size = 2
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_0(N, X86::INC64_16r, MVT::i16);
- return Result;
- }
-
- // Pattern: (add:i16 GR16:i16:$src, -1:i16)
- // Emits: (DEC64_16r:i16 GR16:i16:$src)
- // Pattern complexity = 8 cost = 1 size = 2
- if (CN1 == INT64_C(-1)) {
- SDNode *Result = Emit_0(N, X86::DEC64_16r, MVT::i16);
- return Result;
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:i16 GR16:i16:$src1, 128:i16)
- // Emits: (SUB16ri8:i16 GR16:i16:$src1, -128:i16)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(128)) {
- SDNode *Result = Emit_6(N, X86::SUB16ri8, MVT::i16);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (add:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (ADD16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::ADD16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (add:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (ADD16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::ADD16ri, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (add:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (ADD16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::ADD16rr, MVT::i16);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_7(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN_0, SDValue &CPTmpN_1, SDValue &CPTmpN_2, SDValue &CPTmpN_3) {
- SDValue Ops0[] = { CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3 };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_8(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_9(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_10(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N10);
-}
-DISABLE_INLINE SDNode *Emit_11(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N00);
-}
-SDNode *Select_ISD_ADD_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::ADD32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
- // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::ADD32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (tconstpool:i32):$src2))
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (tconstpool:i32):$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (tjumptable:i32):$src2))
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (tjumptable:i32):$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (tglobaladdr:i32):$src2))
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (tglobaladdr:i32):$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (texternalsym:i32):$src2))
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (texternalsym:i32):$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (tblockaddress:i32):$src2))
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (tblockaddress:i32):$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
- }
- }
- if (N0.getNode()->getOpcode() == X86ISD::Wrapper) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (add:i32 (X86Wrapper:i32 (tconstpool:i32):$src2), GR32:i32:$src1)
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (tconstpool:i32):$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 (X86Wrapper:i32 (tjumptable:i32):$src2), GR32:i32:$src1)
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (tjumptable:i32):$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 (X86Wrapper:i32 (tglobaladdr:i32):$src2), GR32:i32:$src1)
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (tglobaladdr:i32):$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 (X86Wrapper:i32 (texternalsym:i32):$src2), GR32:i32:$src1)
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (texternalsym:i32):$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 (X86Wrapper:i32 (tblockaddress:i32):$src2), GR32:i32:$src1)
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (tblockaddress:i32):$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
- }
- }
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (add:i32 GR32:i32:$src, 1:i32)
- // Emits: (INC32r:i32 GR32:i32:$src)
- // Pattern complexity = 8 cost = 1 size = 1
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_0(N, X86::INC32r, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GR32:i32:$src, -1:i32)
- // Emits: (DEC32r:i32 GR32:i32:$src)
- // Pattern complexity = 8 cost = 1 size = 1
- if (CN1 == INT64_C(-1)) {
- SDNode *Result = Emit_0(N, X86::DEC32r, MVT::i32);
- return Result;
- }
- }
- }
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (add:i32 GR32:i32:$src, 1:i32)
- // Emits: (INC64_32r:i32 GR32:i32:$src)
- // Pattern complexity = 8 cost = 1 size = 2
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_0(N, X86::INC64_32r, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GR32:i32:$src, -1:i32)
- // Emits: (DEC64_32r:i32 GR32:i32:$src)
- // Pattern complexity = 8 cost = 1 size = 2
- if (CN1 == INT64_C(-1)) {
- SDNode *Result = Emit_0(N, X86::DEC64_32r, MVT::i32);
- return Result;
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (add:i32 GR32:i32:$src1, 128:i32)
- // Emits: (SUB32ri8:i32 GR32:i32:$src1, -128:i32)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(128)) {
- SDNode *Result = Emit_9(N, X86::SUB32ri8, MVT::i32);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (add:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (ADD32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::ADD32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (add:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (add:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::ADD32rr, MVT::i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_12(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_13(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i64);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_14(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFF80000000ULL, MVT::i64);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp3);
-}
-SDNode *Select_ISD_ADD_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::ADD64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
- // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::ADD64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: lea64addr:i64:$src
- // Emits: (LEA64r:i64 lea64addr:i64:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (add:i64 GR64:i64:$src, 1:i64)
- // Emits: (INC64r:i64 GR64:i64:$src)
- // Pattern complexity = 8 cost = 1 size = 2
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_0(N, X86::INC64r, MVT::i64);
- return Result;
- }
-
- // Pattern: (add:i64 GR64:i64:$src, -1:i64)
- // Emits: (DEC64r:i64 GR64:i64:$src)
- // Pattern complexity = 8 cost = 1 size = 2
- if (CN1 == INT64_C(-1)) {
- SDNode *Result = Emit_0(N, X86::DEC64r, MVT::i64);
- return Result;
- }
-
- // Pattern: (add:i64 GR64:i64:$src1, 128:i64)
- // Emits: (SUB64ri8:i64 GR64:i64:$src1, -128:i64)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(128)) {
- SDNode *Result = Emit_13(N, X86::SUB64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (add:i64 GR64:i64:$src1, 2147483648:i64)
- // Emits: (SUB64ri32:i64 GR64:i64:$src1, -2147483648:i64)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(2147483648)) {
- SDNode *Result = Emit_14(N, X86::SUB64ri32, MVT::i64);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (add:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (ADD64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::ADD64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (add:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (ADD64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::ADD64ri32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (add:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (ADD64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::ADD64rr, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_15(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1);
-}
-DISABLE_INLINE SDNode *Emit_16(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_17(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Chain00 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_ADD_v8i8(SDNode *N) {
- if ((Subtarget->hasMMX())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PADDBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:v8i8 (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PADDBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PADDBrm, MVT::v8i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PADDBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PADDBrr, MVT::v8i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ADD_v16i8(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PADDBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:v16i8 (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PADDBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_17(N, X86::PADDBrm, MVT::v16i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PADDBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PADDBrr, MVT::v16i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ADD_v4i16(SDNode *N) {
- if ((Subtarget->hasMMX())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PADDWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PADDWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PADDWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PADDWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PADDWrr, MVT::v4i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PADDWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PADDWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_17(N, X86::PADDWrm, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PADDWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PADDWrr, MVT::v8i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ADD_v2i32(SDNode *N) {
- if ((Subtarget->hasMMX())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PADDDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
- // Emits: (MMX_PADDDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PADDDrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (MMX_PADDDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PADDDrr, MVT::v2i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PADDDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PADDDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_17(N, X86::PADDDrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PADDDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PADDDrr, MVT::v4i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ADD_v1i64(SDNode *N) {
- if ((Subtarget->hasMMX())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PADDQrm, MVT::v1i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (add:v1i64 (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v1i64:$src1)
- // Emits: (MMX_PADDQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PADDQrm, MVT::v1i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (add:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PADDQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PADDQrr, MVT::v1i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_18(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_19(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_ADD_v2i64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PADDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PADDQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
- // Emits: (PADDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PADDQrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (add:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PADDQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PADDQrr, MVT::v2i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_20(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, N1);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_21(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- SDValue InFlag(ResNode, 2);
- const SDValue Froms[] = {
- SDValue(N1.getNode(), 1),
- SDValue(N, 1)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- InFlag
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_22(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_23(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- SDValue InFlag(ResNode, 2);
- const SDValue Froms[] = {
- SDValue(N0.getNode(), 1),
- SDValue(N, 1)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- InFlag
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_ISD_ADDC_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (addc:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_21(N, X86::ADD32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (addc:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
- // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_23(N, X86::ADD32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (addc:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (ADD32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_22(N, X86::ADD32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (addc:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_22(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (addc:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_20(N, X86::ADD32rr, MVT::i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_24(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1);
- SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_ADDC_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (addc:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_21(N, X86::ADD64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (addc:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
- // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_23(N, X86::ADD64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (addc:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (ADD64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_24(N, X86::ADD64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (addc:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (ADD64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_24(N, X86::ADD64ri32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (addc:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (ADD64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_20(N, X86::ADD64rr, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_25(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, N1, InFlag);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_26(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- InFlag = SDValue(ResNode, 2);
- const SDValue Froms[] = {
- SDValue(N1.getNode(), 1),
- SDValue(N, 1)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- InFlag
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_27(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_28(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- InFlag = SDValue(ResNode, 2);
- const SDValue Froms[] = {
- SDValue(N0.getNode(), 1),
- SDValue(N, 1)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- InFlag
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_ISD_ADDE_i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (adde:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADC8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_26(N, X86::ADC8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (adde:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src1)
- // Emits: (ADC8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_28(N, X86::ADC8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (adde:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (ADC8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_27(N, X86::ADC8ri, MVT::i8);
- return Result;
- }
- }
-
- // Pattern: (adde:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (ADC8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_25(N, X86::ADC8rr, MVT::i8);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_29(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_ADDE_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (adde:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADC16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_26(N, X86::ADC16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (adde:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
- // Emits: (ADC16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_28(N, X86::ADC16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (adde:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (ADC16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_29(N, X86::ADC16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (adde:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (ADC16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_29(N, X86::ADC16ri, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (adde:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (ADC16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_25(N, X86::ADC16rr, MVT::i16);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_30(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_ADDE_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (adde:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADC32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_26(N, X86::ADC32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (adde:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
- // Emits: (ADC32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_28(N, X86::ADC32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (adde:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (ADC32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_30(N, X86::ADC32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (adde:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (ADC32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_30(N, X86::ADC32ri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (adde:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (ADC32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_25(N, X86::ADC32rr, MVT::i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_31(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
- InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N, 1), InFlag);
- return ResNode;
-}
-SDNode *Select_ISD_ADDE_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (adde:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADC64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_26(N, X86::ADC64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (adde:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
- // Emits: (ADC64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_28(N, X86::ADC64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (adde:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (ADC64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_31(N, X86::ADC64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (adde:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (ADC64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_31(N, X86::ADC64ri32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (adde:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (ADC64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_25(N, X86::ADC64rr, MVT::i64);
- return Result;
-}
-
-SDNode *Select_ISD_AND_i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (AND8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::AND8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1)
- // Emits: (AND8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi8(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::AND8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (AND8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_3(N, X86::AND8ri, MVT::i8);
- return Result;
- }
- }
-
- // Pattern: (and:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (AND8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::AND8rr, MVT::i8);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_32(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
- SDValue Tmp4 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp3, Tmp4), 0);
- return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp5);
-}
-DISABLE_INLINE SDNode *Emit_33(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp3);
-}
-SDNode *Select_ISD_AND_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (AND16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::AND16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
- // Emits: (AND16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::AND16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i16 GR16:i16:$src1, 255:i16)
- // Emits: (MOVZX16rr8:i16 (EXTRACT_SUBREG:i8 GR16:i16:$src1, 1:i32))
- // Pattern complexity = 8 cost = 2 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0 &&
- CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_33(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX16rr8, MVT::i8, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (and:i16 GR16:i16:$src1, 255:i16)
- // Emits: (MOVZX16rr8:i16 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src1, GR16_ABCD:i16), 1:i32))
- // Pattern complexity = 8 cost = 3 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0 &&
- CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_32(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX16rr8, MVT::i16, MVT::i8, MVT::i16);
- return Result;
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (and:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (AND16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::AND16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (and:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (AND16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::AND16ri, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (and:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (AND16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::AND16rr, MVT::i16);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_34(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_35(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_36(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
- SDValue Tmp4 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp3, Tmp4), 0);
- return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp5);
-}
-DISABLE_INLINE SDNode *Emit_37(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp4), 0);
- SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp7(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp5, Tmp6), 0);
- return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp7);
-}
-SDNode *Select_ISD_AND_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
-
- // Pattern: (and:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_nvloadi32>>, 255:i32)
- // Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CheckAndMask(N0, Tmp0, INT64_C(255)) &&
- N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_nvloadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_34(N, X86::MOVZX32rm8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_nvloadi32>>, 65535:i32)
- // Emits: (MOVZX32rm16:i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CheckAndMask(N0, Tmp0, INT64_C(65535)) &&
- N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_nvloadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_34(N, X86::MOVZX32rm16, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (and:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (AND32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::AND32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
- // Emits: (AND32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::AND32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i32 (srl:i32 GR32:i32:$src, 8:i8)<<P:Predicate_srl_su>>, 255:i32)
- // Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 2:i32))
- // Pattern complexity = 17 cost = 3 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0 &&
- CheckAndMask(N0, Tmp0, INT64_C(255)) &&
- N0.getNode()->getOpcode() == ISD::SRL &&
- Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8) &&
- N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_37(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i32, MVT::i8, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i32 (srl:i32 GR32:i32:$src, 8:i8)<<P:Predicate_srl_su>>, 255:i32)
- // Emits: (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 2:i32))
- // Pattern complexity = 17 cost = 3 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0 &&
- CheckAndMask(N0, Tmp0, INT64_C(255)) &&
- N0.getNode()->getOpcode() == ISD::SRL &&
- Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8) &&
- N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_37(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i32, MVT::i8, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i32 GR32:i32:$src1, 65535:i32)
- // Emits: (MOVZX32rr16:i32 (EXTRACT_SUBREG:i16 GR32:i32:$src1, 3:i32))
- // Pattern complexity = 8 cost = 2 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0 &&
- CheckAndMask(N0, Tmp0, INT64_C(65535))) {
- SDNode *Result = Emit_35(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr16, MVT::i16, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (and:i32 GR32:i32:$src1, 255:i32)
- // Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 GR32:i32:$src1, 1:i32))
- // Pattern complexity = 8 cost = 2 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0 &&
- CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_33(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i8, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (and:i32 GR32:i32:$src1, 255:i32)
- // Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src1, GR32_ABCD:i32), 1:i32))
- // Pattern complexity = 8 cost = 3 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0 &&
- CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_36(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i32, MVT::i8, MVT::i32);
- return Result;
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (and:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (AND32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::AND32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (and:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (AND32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::AND32ri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (and:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (AND32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::AND32rr, MVT::i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_38(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp3, Tmp4), 0);
- SDValue Tmp6 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp0, Tmp5, Tmp6);
-}
-DISABLE_INLINE SDNode *Emit_39(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_40(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
- SDValue Tmp5 = CurDAG->getTargetConstant(X86::GR64_ABCDRegClassID, MVT::i32);
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp5), 0);
- SDValue Tmp7 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp8(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp6, Tmp7), 0);
- SDValue Tmp9(CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Tmp8), 0);
- SDValue Tmp10 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc3, VT3, Tmp3, Tmp9, Tmp10);
-}
-SDNode *Select_ISD_AND_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (AND64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::AND64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
- // Emits: (AND64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::AND64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
-
- // Pattern: (and:i64 (srl:i64 GR64:i64:$src, 8:i8)<<P:Predicate_srl_su>>, 255:i64)
- // Emits: (SUBREG_TO_REG:i64 0:i64, (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i64 GR64:i64:$src, GR64_ABCD:i64), 2:i32)), 4:i32)
- // Pattern complexity = 17 cost = 4 size = 3
- if (CheckAndMask(N0, Tmp0, INT64_C(255)) &&
- N0.getNode()->getOpcode() == ISD::SRL &&
- Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp1) {
- int64_t CN2 = Tmp1->getSExtValue();
- if (CN2 == INT64_C(8) &&
- N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_40(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetOpcode::SUBREG_TO_REG, MVT::i64, MVT::i8, MVT::i32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i64 GR64:i64:$src, 4294967295:i64)
- // Emits: (MOVZX64rr32:i64 (EXTRACT_SUBREG:i32 GR64:i64:$src, 4:i32))
- // Pattern complexity = 8 cost = 2 size = 3
- if (CheckAndMask(N0, Tmp0, INT64_C(4294967295))) {
- SDNode *Result = Emit_39(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX64rr32, MVT::i32, MVT::i64);
- return Result;
- }
-
- // Pattern: (and:i64 GR64:i64:$src, 65535:i64)
- // Emits: (MOVZX64rr16:i64 (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
- // Pattern complexity = 8 cost = 2 size = 3
- if (CheckAndMask(N0, Tmp0, INT64_C(65535))) {
- SDNode *Result = Emit_35(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX64rr16, MVT::i16, MVT::i64);
- return Result;
- }
-
- // Pattern: (and:i64 GR64:i64:$src, 255:i64)
- // Emits: (MOVZX64rr8:i64 (EXTRACT_SUBREG:i8 GR64:i64:$src, 1:i32))
- // Pattern complexity = 8 cost = 2 size = 3
- if (CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_33(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX64rr8, MVT::i8, MVT::i64);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (and:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (AND64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::AND64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (and:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (AND64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::AND64ri32, MVT::i64);
- return Result;
- }
-
- // Pattern: (and:i64 GR64:i64:$src, (imm:i64)<<P:Predicate_i64immZExt32>>:$imm)
- // Emits: (SUBREG_TO_REG:i64 0:i64, (AND32ri:i32 (EXTRACT_SUBREG:i32 GR64:i64:$src, 4:i32), (imm:i32):$imm), 4:i32)
- // Pattern complexity = 7 cost = 3 size = 3
- if (Predicate_i64immZExt32(N1.getNode())) {
- SDNode *Result = Emit_38(N, TargetOpcode::EXTRACT_SUBREG, X86::AND32ri, TargetOpcode::SUBREG_TO_REG, MVT::i32, MVT::i32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (AND64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::AND64rr, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_41(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N1);
-}
-DISABLE_INLINE SDNode *Emit_42(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N00, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_43(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N1);
-}
-DISABLE_INLINE SDNode *Emit_44(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N00, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_45(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N01, N1);
-}
-DISABLE_INLINE SDNode *Emit_46(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N0);
-}
-DISABLE_INLINE SDNode *Emit_47(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N11, N0);
-}
-DISABLE_INLINE SDNode *Emit_48(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N01, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_49(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N10, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_50(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N11, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_51(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N01, N1);
-}
-DISABLE_INLINE SDNode *Emit_52(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N0);
-}
-DISABLE_INLINE SDNode *Emit_53(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N11, N0);
-}
-DISABLE_INLINE SDNode *Emit_54(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N01, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_55(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N10, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_56(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N11, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_AND_v1i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N010.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_44(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if (N010.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N010.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
-
- // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N010.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_44(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N010.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_44(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_56(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N110.getNode()) &&
- N110.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_56(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N110.getNode()) &&
- N110.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_56(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_42(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (and:v1i64 (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_48(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N11.getNode())) {
- SDNode *Result = Emit_49(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
-
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N10.getNode())) {
- SDNode *Result = Emit_50(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (and:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MMX_PANDrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
- // Emits: (MMX_PANDrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MMX_PANDrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)), VR64:v1i64:$src2)
- // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N010.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_43(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- if (N010.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N010.getNode())) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)), VR64:v1i64:$src2)
- // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N010.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_43(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
-
- // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)), VR64:v1i64:$src2)
- // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N010.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_43(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1), VR64:v1i64:$src2)
- // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_51(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- }
- }
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)))
- // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_52(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1))
- // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_53(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), VR64:v1i64:$src2)
- // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_51(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- }
- }
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)))
- // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N110.getNode()) &&
- N110.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_52(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
- // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_53(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), VR64:v1i64:$src2)
- // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_51(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)))
- // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N110.getNode()) &&
- N110.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_52(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
- // Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_53(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src2)
- // Emits: (MMX_PANDNrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 10 cost = 1 size = 3
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N01.getNode())) {
- SDNode *Result = Emit_41(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (and:v1i64 (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1), VR64:v1i64:$src2)
- // Emits: (MMX_PANDNrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 10 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N00.getNode())) {
- SDNode *Result = Emit_45(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>))
- // Emits: (MMX_PANDNrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 10 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N11.getNode())) {
- SDNode *Result = Emit_46(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1))
- // Emits: (MMX_PANDNrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 10 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N10.getNode())) {
- SDNode *Result = Emit_47(N, X86::MMX_PANDNrr, MVT::v1i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PANDrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PANDrr, MVT::v1i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_57(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N00, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_58(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N000, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_59(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N10);
-}
-DISABLE_INLINE SDNode *Emit_60(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N000, N10);
-}
-DISABLE_INLINE SDNode *Emit_61(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N000, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_62(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N10, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_63(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N010, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_64(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N100, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_65(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N110, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_66(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N010, N10);
-}
-DISABLE_INLINE SDNode *Emit_67(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N100, N00);
-}
-DISABLE_INLINE SDNode *Emit_68(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N110, N00);
-}
-DISABLE_INLINE SDNode *Emit_69(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N010, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_70(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N100, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_71(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N110, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_AND_v2i64(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 38 cost = 1 size = 3
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v4f32 &&
- N010.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_58(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v4f32:$src1)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 38 cost = 1 size = 3
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v4i32 &&
- N010.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_63(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
- // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 38 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N100.getValueType() == MVT::v4f32 &&
- N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_64(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v4f32:$src1)))
- // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 38 cost = 1 size = 3
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N100.getValueType() == MVT::v4i32 &&
- N110.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_65(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_61(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
-
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N010.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_44(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N010.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_44(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N010.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_44(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N010.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_69(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
- // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N11.getNode()) &&
- N100.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_70(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)))
- // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N10.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_71(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_56(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)))
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_56(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)))
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_56(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_42(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_48(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
- // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N11.getNode())) {
- SDNode *Result = Emit_49(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1))
- // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N10.getNode())) {
- SDNode *Result = Emit_50(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ANDPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_57(N, X86::ANDPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ANDPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_57(N, X86::ANDPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v4f32:$src1))
- // Emits: (ANDPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_62(N, X86::ANDPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
- // Emits: (ANDPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_62(N, X86::ANDPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PANDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
- // Emits: (PANDrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PANDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v2f64:$src2))
- // Emits: (ANDNPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 16 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N000.getValueType() == MVT::v2f64 &&
- N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_60(N, X86::ANDNPDrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)), (bitconvert:v2i64 VR128:v2f64:$src2))
- // Emits: (ANDNPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 16 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N010.getValueType() == MVT::v2f64 &&
- N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_66(N, X86::ANDNPDrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src2), (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
- // Emits: (ANDNPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 16 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N11.getNode()) &&
- N00.getValueType() == MVT::v2f64 &&
- N100.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_67(N, X86::ANDNPDrr, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src2), (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)))
- // Emits: (ANDNPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 16 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N10.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N00.getValueType() == MVT::v2f64 &&
- N110.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_68(N, X86::ANDNPDrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), VR128:v2i64:$src2)
- // Emits: (ANDNPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N010.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_43(N, X86::ANDNPSrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), VR128:v2i64:$src2)
- // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N010.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_43(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)), VR128:v2i64:$src2)
- // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N010.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_43(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)), VR128:v2i64:$src2)
- // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N010.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_43(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), VR128:v2i64:$src2)
- // Emits: (ANDNPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_51(N, X86::ANDNPSrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
- // Emits: (ANDNPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_52(N, X86::ANDNPSrr, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
- // Emits: (ANDNPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_53(N, X86::ANDNPSrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), VR128:v2i64:$src2)
- // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_51(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
- // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_52(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
- // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_53(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), VR128:v2i64:$src2)
- // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_51(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)))
- // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_52(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
- // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_53(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), VR128:v2i64:$src2)
- // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N000.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_51(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)))
- // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_52(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
- // Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_53(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src2)
- // Emits: (PANDNrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 10 cost = 1 size = 3
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N01.getNode())) {
- SDNode *Result = Emit_41(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1), VR128:v2i64:$src2)
- // Emits: (PANDNrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 10 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N00.getNode())) {
- SDNode *Result = Emit_45(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
- // Emits: (PANDNrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 10 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N11.getNode())) {
- SDNode *Result = Emit_46(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1))
- // Emits: (PANDNrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 10 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N10.getNode())) {
- SDNode *Result = Emit_47(N, X86::PANDNrr, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (bitconvert:v2i64 VR128:v2f64:$src2))
- // Emits: (ANDPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N00.getValueType() == MVT::v2f64 &&
- N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_59(N, X86::ANDPDrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (ANDPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_15(N, X86::ANDPSrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (and:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PANDrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDNode *Result = Emit_15(N, X86::PANDrr, MVT::v2i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_72(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0);
-}
-DISABLE_INLINE SDNode *Emit_73(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N0.getNode()->getDebugLoc(), X86::EFLAGS, N01, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, InFlag);
-}
-SDNode *Select_ISD_ANY_EXTEND_i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (anyext:i16 (X86setcc_c:i8 2:i8, EFLAGS:i32))
- // Emits: (SETB_C16r:i16)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == X86ISD::SETCC_CARRY) {
- SDValue N00 = N0.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(2)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_73(N, X86::SETB_C16r, MVT::i16);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (anyext:i16 GR8:i8:$src)
- // Emits: (MOVZX16rr8:i16 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_72(N, X86::MOVZX16rr8, MVT::i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_74(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp3), 0);
- SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp6(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp4, Tmp5), 0);
- return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp6);
-}
-SDNode *Select_ISD_ANY_EXTEND_i32(SDNode *N) {
-
- // Pattern: (anyext:i32 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
- // Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
- // Pattern complexity = 12 cost = 3 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRL &&
- Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8) &&
- N0.getValueType() == MVT::i16 &&
- N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_74(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i16, MVT::i8, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (anyext:i32 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
- // Emits: (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
- // Pattern complexity = 12 cost = 3 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRL &&
- Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8) &&
- N0.getValueType() == MVT::i16 &&
- N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_74(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i16, MVT::i8, MVT::i32);
- return Result;
- }
- }
- }
- }
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (anyext:i32 (X86setcc_c:i8 2:i8, EFLAGS:i32))
- // Emits: (SETB_C32r:i32)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == X86ISD::SETCC_CARRY) {
- SDValue N00 = N0.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(2)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_73(N, X86::SETB_C32r, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (anyext:i32 GR8:i8:$src)
- // Emits: (MOVZX32rr8:i32 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_72(N, X86::MOVZX32rr8, MVT::i32);
- return Result;
- }
-
- // Pattern: (anyext:i32 GR16:i16:$src)
- // Emits: (MOVZX32rr16:i32 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_72(N, X86::MOVZX32rr16, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_75(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp0 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0, N0, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_76(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
- SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp4), 0);
- SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp7(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp5, Tmp6), 0);
- SDValue Tmp8(CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Tmp7), 0);
- SDValue Tmp9 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc3, VT3, Tmp2, Tmp8, Tmp9);
-}
-SDNode *Select_ISD_ANY_EXTEND_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (anyext:i64 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
- // Emits: (SUBREG_TO_REG:i64 0:i64, (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 4:i32)
- // Pattern complexity = 12 cost = 4 size = 3
- if (N0.getNode()->getOpcode() == ISD::SRL &&
- Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8) &&
- N0.getValueType() == MVT::i16 &&
- N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_76(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetOpcode::SUBREG_TO_REG, MVT::i16, MVT::i8, MVT::i32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (anyext:i64 (X86setcc_c:i8 2:i8, EFLAGS:i32))
- // Emits: (SETB_C64r:i64)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == X86ISD::SETCC_CARRY) {
- SDValue N00 = N0.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(2)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_73(N, X86::SETB_C64r, MVT::i64);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (anyext:i64 GR32:i32:$src)
- // Emits: (SUBREG_TO_REG:i64 0:i64, GR32:i32:$src, 4:i32)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_75(N, TargetOpcode::SUBREG_TO_REG, MVT::i64);
- return Result;
- }
-
- // Pattern: (anyext:i64 GR8:i8:$src)
- // Emits: (MOVZX64rr8:i64 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_72(N, X86::MOVZX64rr8, MVT::i64);
- return Result;
- }
-
- // Pattern: (anyext:i64 GR16:i16:$src)
- // Emits: (MOVZX64rr16:i64 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_72(N, X86::MOVZX64rr16, MVT::i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_77(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { N2, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i8(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_add_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::LXADD8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i16(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_add_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::LXADD16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_add_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::LXADD32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_add_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::LXADD64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_78(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, N2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i8(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_and_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMAND8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i16(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_and_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMAND16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_and_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMAND32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_and_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMAND64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_MAX_i16(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_max_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMMAX16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_MAX_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_max_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMMAX32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_MAX_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_max_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMMAX64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_MIN_i16(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_min_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMMIN16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_MIN_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_min_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMMIN32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_MIN_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_min_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMMIN64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i8(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_nand_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMNAND8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i16(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_nand_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMNAND16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_nand_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMNAND32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_nand_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMNAND64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i8(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_or_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMOR8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i16(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_or_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMOR16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_or_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMOR32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_or_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMOR64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i16(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_umax_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMUMAX16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_umax_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMUMAX32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_umax_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMUMAX64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i16(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_umin_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMUMIN16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_umin_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMUMIN32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_umin_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMUMIN64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i8(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_xor_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMXOR8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i16(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_xor_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMXOR16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_xor_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMXOR32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_load_xor_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_78(N, X86::ATOMXOR64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_SWAP_i8(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_swap_8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::XCHG8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_SWAP_i16(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_swap_16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::XCHG16rm, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_SWAP_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_swap_32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::XCHG32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ATOMIC_SWAP_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_atomic_swap_64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::XCHG64rm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_i32(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_72(N, X86::MOVSS2DIrr, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_i64(SDNode *N) {
-
- // Pattern: (bitconvert:i64 FR64:f64:$src)
- // Emits: (MOVSDto64rr:i64 FR64:f64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_72(N, X86::MOVSDto64rr, MVT::i64);
- return Result;
- }
- }
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:i64 VR64:v1i64:$src)
- // Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVD64from64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (bitconvert:i64 VR64:v2i32:$src)
- // Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVD64from64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (bitconvert:i64 VR64:v2f32:$src)
- // Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVD64from64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (bitconvert:i64 VR64:v4i16:$src)
- // Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVD64from64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (bitconvert:i64 VR64:v8i8:$src)
- // Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVD64from64rr, MVT::i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_79(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_BIT_CONVERT_f32(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:f32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (MOVDI2SSrm:f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_79(N, X86::MOVDI2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (bitconvert:f32 GR32:i32:$src)
- // Emits: (MOVDI2SSrr:f32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_72(N, X86::MOVDI2SSrr, MVT::f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:f64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (MOV64toSDrm:f64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_79(N, X86::MOV64toSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (bitconvert:f64 GR64:i64:$src)
- // Emits: (MOV64toSDrr:f64 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_72(N, X86::MOV64toSDrr, MVT::f64);
- return Result;
- }
- }
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:f64 VR64:v1i64:$src)
- // Emits: (MMX_MOVQ2FR64rr:f64 VR64:v8i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
- return Result;
- }
-
- // Pattern: (bitconvert:f64 VR64:v2i32:$src)
- // Emits: (MMX_MOVQ2FR64rr:f64 VR64:v8i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
- return Result;
- }
-
- // Pattern: (bitconvert:f64 VR64:v4i16:$src)
- // Emits: (MMX_MOVQ2FR64rr:f64 VR64:v8i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
- return Result;
- }
-
- // Pattern: (bitconvert:f64 VR64:v8i8:$src)
- // Emits: (MMX_MOVQ2FR64rr:f64 VR64:v8i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_80(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- ReplaceUses(SDValue(N, 0), N0);
- return NULL;
-}
-DISABLE_INLINE SDNode *Emit_81(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00);
-}
-SDNode *Select_ISD_BIT_CONVERT_v8i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v8i8 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
- // Emits: (MMX_MOVDQ2Qrr:v8i8 VR128:v16i8:$src)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i64 &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_81(N, X86::MMX_MOVDQ2Qrr, MVT::v8i8);
- return Result;
- }
- }
- }
-
- // Pattern: (bitconvert:v8i8 VR64:v1i64:$src)
- // Emits: VR64:v8i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i8 VR64:v2i32:$src)
- // Emits: VR64:v8i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i8 VR64:v2f32:$src)
- // Emits: VR64:v8i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i8 VR64:v4i16:$src)
- // Emits: VR64:v8i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i8 GR64:i64:$src)
- // Emits: (MMX_MOVD64to64rr:v8i8 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVD64to64rr, MVT::v8i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v16i8(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v16i8 VR128:v2i64:$src)
- // Emits: VR128:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v16i8 VR128:v4i32:$src)
- // Emits: VR128:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v16i8 VR128:v8i16:$src)
- // Emits: VR128:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v16i8 VR128:v2f64:$src)
- // Emits: VR128:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v16i8 VR128:v4f32:$src)
- // Emits: VR128:v16i8:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v4i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v4i16 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
- // Emits: (MMX_MOVDQ2Qrr:v4i16 VR128:v16i8:$src)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i64 &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_81(N, X86::MMX_MOVDQ2Qrr, MVT::v4i16);
- return Result;
- }
- }
- }
-
- // Pattern: (bitconvert:v4i16 VR64:v1i64:$src)
- // Emits: VR64:v4i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i16 VR64:v2i32:$src)
- // Emits: VR64:v4i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i16 VR64:v2f32:$src)
- // Emits: VR64:v4i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i16 VR64:v8i8:$src)
- // Emits: VR64:v4i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i16 GR64:i64:$src)
- // Emits: (MMX_MOVD64to64rr:v4i16 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVD64to64rr, MVT::v4i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v8i16(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v8i16 VR128:v2i64:$src)
- // Emits: VR128:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i16 VR128:v4i32:$src)
- // Emits: VR128:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i16 VR128:v16i8:$src)
- // Emits: VR128:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i16 VR128:v2f64:$src)
- // Emits: VR128:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v8i16 VR128:v4f32:$src)
- // Emits: VR128:v8i16:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_82(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0101_0, SDValue &CPTmpN0101_1, SDValue &CPTmpN0101_2, SDValue &CPTmpN0101_3, SDValue &CPTmpN0101_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue Chain010 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N010.getNode())->getMemOperand();
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, N0101, N0101, Chain010);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N010.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_BIT_CONVERT_v2i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v2i32 (vector_shuffle:v2i32 (build_vector:v2i32)<<P:Predicate_immAllZerosV>>, (scalar_to_vector:v2i32 (ld:v1i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>)
- // Emits: (MMX_PUNPCKLDQrm:v2i32 VR64:v8i8:$src, VR64:v8i8:$src)
- // Pattern complexity = 56 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
- N0.hasOneUse() &&
- Predicate_mmx_unpckl(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllZerosV(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N01.hasOneUse()) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::LOAD &&
- N010.hasOneUse() &&
- IsLegalAndProfitableToFold(N010.getNode(), N01.getNode(), N)) {
- SDValue Chain010 = N010.getNode()->getOperand(0);
- if (Predicate_unindexedload(N010.getNode()) &&
- Predicate_load(N010.getNode())) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue CPTmpN0101_0;
- SDValue CPTmpN0101_1;
- SDValue CPTmpN0101_2;
- SDValue CPTmpN0101_3;
- SDValue CPTmpN0101_4;
- if (SelectAddr(N, N0101, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4) &&
- N0.getValueType() == MVT::v2i32 &&
- N010.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_82(N, X86::MMX_PUNPCKLDQrm, MVT::v2i32, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (bitconvert:v2i32 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
- // Emits: (MMX_MOVDQ2Qrr:v2i32 VR128:v16i8:$src)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i64 &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_81(N, X86::MMX_MOVDQ2Qrr, MVT::v2i32);
- return Result;
- }
- }
- }
-
- // Pattern: (bitconvert:v2i32 VR64:v1i64:$src)
- // Emits: VR64:v2i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i32 VR64:v2f32:$src)
- // Emits: VR64:v2i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i32 VR64:v4i16:$src)
- // Emits: VR64:v2i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i32 VR64:v8i8:$src)
- // Emits: VR64:v2i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i32 GR64:i64:$src)
- // Emits: (MMX_MOVD64to64rr:v2i32 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVD64to64rr, MVT::v2i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v4i32(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v4i32 VR128:v2i64:$src)
- // Emits: VR128:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i32 VR128:v8i16:$src)
- // Emits: VR128:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i32 VR128:v16i8:$src)
- // Emits: VR128:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i32 VR128:v2f64:$src)
- // Emits: VR128:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4i32 VR128:v4f32:$src)
- // Emits: VR128:v4i32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v1i64(SDNode *N) {
-
- // Pattern: (bitconvert:v1i64 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
- // Emits: (MMX_MOVDQ2Qrr:v1i64 VR128:v2i64:$src)
- // Pattern complexity = 11 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i64 &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_81(N, X86::MMX_MOVDQ2Qrr, MVT::v1i64);
- return Result;
- }
- }
- }
- }
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v1i64 VR64:v2i32:$src)
- // Emits: VR64:v1i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v1i64 VR64:v2f32:$src)
- // Emits: VR64:v1i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v1i64 VR64:v4i16:$src)
- // Emits: VR64:v1i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v1i64 VR64:v8i8:$src)
- // Emits: VR64:v1i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v1i64 GR64:i64:$src)
- // Emits: (MMX_MOVD64to64rr:v1i64 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVD64to64rr, MVT::v1i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v2i64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v2i64 VR128:v4i32:$src)
- // Emits: VR128:v2i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i64 VR128:v8i16:$src)
- // Emits: VR128:v2i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i64 VR128:v16i8:$src)
- // Emits: VR128:v2i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i64 VR128:v2f64:$src)
- // Emits: VR128:v2i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2i64 VR128:v4f32:$src)
- // Emits: VR128:v2i64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v2f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v2f32 VR64:v1i64:$src)
- // Emits: VR64:v2f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f32 VR64:v2i32:$src)
- // Emits: VR64:v2f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f32 VR64:v4i16:$src)
- // Emits: VR64:v2f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f32 VR64:v8i8:$src)
- // Emits: VR64:v2f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f32 GR64:i64:$src)
- // Emits: (MMX_MOVD64to64rr:v2f32 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVD64to64rr, MVT::v2f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v4f32 VR128:v2i64:$src)
- // Emits: VR128:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4f32 VR128:v4i32:$src)
- // Emits: VR128:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4f32 VR128:v8i16:$src)
- // Emits: VR128:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4f32 VR128:v16i8:$src)
- // Emits: VR128:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v4f32 VR128:v2f64:$src)
- // Emits: VR128:v4f32:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BIT_CONVERT_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (bitconvert:v2f64 VR128:v2i64:$src)
- // Emits: VR128:v2f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f64 VR128:v4i32:$src)
- // Emits: VR128:v2f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f64 VR128:v8i16:$src)
- // Emits: VR128:v2f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f64 VR128:v16i8:$src)
- // Emits: VR128:v2f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
-
- // Pattern: (bitconvert:v2f64 VR128:v4f32:$src)
- // Emits: VR128:v2f64:$src
- // Pattern complexity = 3 cost = 0 size = 0
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_80(N);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_83(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, N1, Chain);
-}
-SDNode *Select_ISD_BR(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
- SDNode *Result = Emit_83(N, X86::JMP_4);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_84(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N1.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain1);
- Chain1 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
- Chain1 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- const SDValue Froms[] = {
- SDValue(N1.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain1.getNode(), Chain1.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_ISD_BRIND(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N) &&
- (Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode())) {
-
- // Pattern: (brind:isVoid (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (JMP32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_84(N, X86::JMP32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (brind:isVoid (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (JMP64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_84(N, X86::JMP64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (brind:isVoid GR32:i32:$dst)
- // Emits: (JMP32r:isVoid GR32:i32:$dst)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_83(N, X86::JMP32r);
- return Result;
- }
-
- // Pattern: (brind:isVoid GR64:i64:$dst)
- // Emits: (JMP64r:isVoid GR64:i64:$dst)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_83(N, X86::JMP64r);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BSWAP_i32(SDNode *N) {
- SDNode *Result = Emit_72(N, X86::BSWAP32r, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_BSWAP_i64(SDNode *N) {
- SDNode *Result = Emit_72(N, X86::BSWAP64r, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_85(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- return CurDAG->SelectNodeTo(N, Opc0, VT0);
-}
-SDNode *Select_ISD_BUILD_VECTOR_v8i8(SDNode *N) {
- if ((Subtarget->hasMMX()) &&
- Predicate_immAllZerosV(N)) {
- SDNode *Result = Emit_85(N, X86::MMX_V_SET0, MVT::v8i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v16i8(SDNode *N) {
- if ((Subtarget->hasSSE1()) &&
- Predicate_immAllZerosV(N)) {
- SDNode *Result = Emit_85(N, X86::V_SET0, MVT::v16i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v4i16(SDNode *N) {
- if ((Subtarget->hasMMX()) &&
- Predicate_immAllZerosV(N)) {
- SDNode *Result = Emit_85(N, X86::MMX_V_SET0, MVT::v4i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v8i16(SDNode *N) {
- if ((Subtarget->hasSSE1()) &&
- Predicate_immAllZerosV(N)) {
- SDNode *Result = Emit_85(N, X86::V_SET0, MVT::v8i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v2i32(SDNode *N) {
- if ((Subtarget->hasMMX())) {
-
- // Pattern: (build_vector:v2i32)<<P:Predicate_immAllZerosV>>
- // Emits: (MMX_V_SET0:v2i32)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_immAllZerosV(N)) {
- SDNode *Result = Emit_85(N, X86::MMX_V_SET0, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (build_vector:v2i32)<<P:Predicate_immAllOnesV>>
- // Emits: (MMX_V_SETALLONES:v2i32)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_immAllOnesV(N)) {
- SDNode *Result = Emit_85(N, X86::MMX_V_SETALLONES, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v4i32(SDNode *N) {
-
- // Pattern: (build_vector:v4i32)<<P:Predicate_immAllZerosV>>
- // Emits: (V_SET0:v4i32)
- // Pattern complexity = 4 cost = 1 size = 3
- if ((Subtarget->hasSSE1()) &&
- Predicate_immAllZerosV(N)) {
- SDNode *Result = Emit_85(N, X86::V_SET0, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (build_vector:v4i32)<<P:Predicate_immAllOnesV>>
- // Emits: (V_SETALLONES:v4i32)
- // Pattern complexity = 4 cost = 1 size = 3
- if ((Subtarget->hasSSE2()) &&
- Predicate_immAllOnesV(N)) {
- SDNode *Result = Emit_85(N, X86::V_SETALLONES, MVT::v4i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v1i64(SDNode *N) {
- if ((Subtarget->hasMMX()) &&
- Predicate_immAllZerosV(N)) {
- SDNode *Result = Emit_85(N, X86::MMX_V_SET0, MVT::v1i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v2i64(SDNode *N) {
- if ((Subtarget->hasSSE1()) &&
- Predicate_immAllZerosV(N)) {
- SDNode *Result = Emit_85(N, X86::V_SET0, MVT::v2i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1()) &&
- Predicate_immAllZerosV(N)) {
- SDNode *Result = Emit_85(N, X86::V_SET0, MVT::v4f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_BUILD_VECTOR_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE1()) &&
- Predicate_immAllZerosV(N)) {
- SDNode *Result = Emit_85(N, X86::V_SET0, MVT::v2f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_86(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- SDValue Ops0[] = { N1, N2, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_ISD_CALLSEQ_END(SDNode *N) {
-
- // Pattern: (X86callseq_end:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
- // Emits: (ADJCALLSTACKUP32:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
- // Pattern complexity = 9 cost = 1 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_86(N, X86::ADJCALLSTACKUP32);
- return Result;
- }
- }
- }
-
- // Pattern: (X86callseq_end:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
- // Emits: (ADJCALLSTACKUP64:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
- // Pattern complexity = 9 cost = 1 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_86(N, X86::ADJCALLSTACKUP64);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_87(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, N1, Chain);
- Chain = SDValue(ResNode, 0);
- SDValue InFlag(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_ISD_CALLSEQ_START(SDNode *N) {
-
- // Pattern: (X86callseq_start:isVoid (timm:i32):$amt)
- // Emits: (ADJCALLSTACKDOWN32:isVoid (timm:i32):$amt)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_87(N, X86::ADJCALLSTACKDOWN32);
- return Result;
- }
- }
-
- // Pattern: (X86callseq_start:isVoid (timm:i32):$amt)
- // Emits: (ADJCALLSTACKDOWN64:isVoid (timm:i32):$amt)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_87(N, X86::ADJCALLSTACKDOWN64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_88(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0);
-}
-SDNode *Select_ISD_Constant_i8(SDNode *N) {
-
- // Pattern: 0:i8
- // Emits: (MOV8r0:i8)
- // Pattern complexity = 5 cost = 1 size = 3
- if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
- SDNode *Result = Emit_85(N, X86::MOV8r0, MVT::i8);
- return Result;
- }
-
- // Pattern: (imm:i8):$src
- // Emits: (MOV8ri:i8 (imm:i8):$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_88(N, X86::MOV8ri, MVT::i8);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_89(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i16);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0);
-}
-SDNode *Select_ISD_Constant_i16(SDNode *N) {
-
- // Pattern: 0:i16
- // Emits: (MOV16r0:i16)
- // Pattern complexity = 5 cost = 1 size = 3
- if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
- SDNode *Result = Emit_85(N, X86::MOV16r0, MVT::i16);
- return Result;
- }
-
- // Pattern: (imm:i16):$src
- // Emits: (MOV16ri:i16 (imm:i16):$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_89(N, X86::MOV16ri, MVT::i16);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_90(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0);
-}
-SDNode *Select_ISD_Constant_i32(SDNode *N) {
-
- // Pattern: 0:i32
- // Emits: (MOV32r0:i32)
- // Pattern complexity = 5 cost = 1 size = 3
- if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
- SDNode *Result = Emit_85(N, X86::MOV32r0, MVT::i32);
- return Result;
- }
-
- // Pattern: (imm:i32):$src
- // Emits: (MOV32ri:i32 (imm:i32):$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_90(N, X86::MOV32ri, MVT::i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_91(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i64);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0);
-}
-SDNode *Select_ISD_Constant_i64(SDNode *N) {
-
- // Pattern: 0:i64
- // Emits: (MOV64r0:i64)
- // Pattern complexity = 6 cost = 1 size = 3
- if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
- SDNode *Result = Emit_85(N, X86::MOV64r0, MVT::i64);
- return Result;
- }
-
- // Pattern: (imm:i64)<<P:Predicate_i64immZExt32>>:$src
- // Emits: (MOV64ri64i32:i64 (imm:i64):$src)
- // Pattern complexity = 5 cost = 1 size = 3
- if (Predicate_i64immZExt32(N)) {
- SDNode *Result = Emit_91(N, X86::MOV64ri64i32, MVT::i64);
- return Result;
- }
-
- // Pattern: (imm:i64)<<P:Predicate_i64immSExt32>>:$src
- // Emits: (MOV64ri32:i64 (imm:i64):$src)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_i64immSExt32(N)) {
- SDNode *Result = Emit_91(N, X86::MOV64ri32, MVT::i64);
- return Result;
- }
-
- // Pattern: (imm:i64):$src
- // Emits: (MOV64ri:i64 (imm:i64):$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_91(N, X86::MOV64ri, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_92(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp0);
-}
-SDNode *Select_ISD_ConstantFP_f32(SDNode *N) {
- if ((!Subtarget->hasSSE1())) {
-
- // Pattern: (fpimm:f32)<<P:Predicate_fpimm0>>
- // Emits: (LD_Fp032:f32)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_fpimm0(N)) {
- SDNode *Result = Emit_85(N, X86::LD_Fp032, MVT::f32);
- return Result;
- }
-
- // Pattern: (fpimm:f32)<<P:Predicate_fpimm1>>
- // Emits: (LD_Fp132:f32)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_fpimm1(N)) {
- SDNode *Result = Emit_85(N, X86::LD_Fp132, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (fpimm:f32)<<P:Predicate_fp32imm0>>
- // Emits: (FsFLD0SS:f32)
- // Pattern complexity = 4 cost = 1 size = 3
- if ((Subtarget->hasSSE1()) &&
- Predicate_fp32imm0(N)) {
- SDNode *Result = Emit_85(N, X86::FsFLD0SS, MVT::f32);
- return Result;
- }
- if ((!Subtarget->hasSSE1())) {
-
- // Pattern: (fpimm:f32)<<P:Predicate_fpimmneg0>>
- // Emits: (CHS_Fp32:f32 (LD_Fp032:f32))
- // Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_fpimmneg0(N)) {
- SDNode *Result = Emit_92(N, X86::LD_Fp032, X86::CHS_Fp32, MVT::f32, MVT::f32);
- return Result;
- }
-
- // Pattern: (fpimm:f32)<<P:Predicate_fpimmneg1>>
- // Emits: (CHS_Fp32:f32 (LD_Fp132:f32))
- // Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_fpimmneg1(N)) {
- SDNode *Result = Emit_92(N, X86::LD_Fp132, X86::CHS_Fp32, MVT::f32, MVT::f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ConstantFP_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
-
- // Pattern: (fpimm:f64)<<P:Predicate_fpimm0>>
- // Emits: (LD_Fp064:f64)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_fpimm0(N)) {
- SDNode *Result = Emit_85(N, X86::LD_Fp064, MVT::f64);
- return Result;
- }
-
- // Pattern: (fpimm:f64)<<P:Predicate_fpimm1>>
- // Emits: (LD_Fp164:f64)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_fpimm1(N)) {
- SDNode *Result = Emit_85(N, X86::LD_Fp164, MVT::f64);
- return Result;
- }
- }
-
- // Pattern: (fpimm:f64)<<P:Predicate_fpimm0>>
- // Emits: (FsFLD0SD:f64)
- // Pattern complexity = 4 cost = 1 size = 3
- if ((Subtarget->hasSSE2()) &&
- Predicate_fpimm0(N)) {
- SDNode *Result = Emit_85(N, X86::FsFLD0SD, MVT::f64);
- return Result;
- }
- if ((!Subtarget->hasSSE2())) {
-
- // Pattern: (fpimm:f64)<<P:Predicate_fpimmneg0>>
- // Emits: (CHS_Fp64:f64 (LD_Fp064:f64))
- // Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_fpimmneg0(N)) {
- SDNode *Result = Emit_92(N, X86::LD_Fp064, X86::CHS_Fp64, MVT::f64, MVT::f64);
- return Result;
- }
-
- // Pattern: (fpimm:f64)<<P:Predicate_fpimmneg1>>
- // Emits: (CHS_Fp64:f64 (LD_Fp164:f64))
- // Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_fpimmneg1(N)) {
- SDNode *Result = Emit_92(N, X86::LD_Fp164, X86::CHS_Fp64, MVT::f64, MVT::f64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ConstantFP_f80(SDNode *N) {
-
- // Pattern: (fpimm:f80)<<P:Predicate_fpimm0>>
- // Emits: (LD_Fp080:f80)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_fpimm0(N)) {
- SDNode *Result = Emit_85(N, X86::LD_Fp080, MVT::f80);
- return Result;
- }
-
- // Pattern: (fpimm:f80)<<P:Predicate_fpimm1>>
- // Emits: (LD_Fp180:f80)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_fpimm1(N)) {
- SDNode *Result = Emit_85(N, X86::LD_Fp180, MVT::f80);
- return Result;
- }
-
- // Pattern: (fpimm:f80)<<P:Predicate_fpimmneg0>>
- // Emits: (CHS_Fp80:f80 (LD_Fp080:f80))
- // Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_fpimmneg0(N)) {
- SDNode *Result = Emit_92(N, X86::LD_Fp080, X86::CHS_Fp80, MVT::f80, MVT::f80);
- return Result;
- }
-
- // Pattern: (fpimm:f80)<<P:Predicate_fpimmneg1>>
- // Emits: (CHS_Fp80:f80 (LD_Fp180:f80))
- // Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_fpimmneg1(N)) {
- SDNode *Result = Emit_92(N, X86::LD_Fp180, X86::CHS_Fp80, MVT::f80, MVT::f80);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_93(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0);
-}
-DISABLE_INLINE SDNode *Emit_94(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_95(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, Tmp1);
-}
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(SDNode *N) {
-
- // Pattern: (extractelt:i32 (bitconvert:v4i32 VR128:v4f32:$src1), (imm:iPTR):$src2)
- // Emits: (EXTRACTPSrr:i32 VR128:v4f32:$src1, (imm:i32):$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i32 &&
- N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_95(N, X86::EXTRACTPSrr, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (vector_extract:i32 VR128:v4i32:$src, 0:iPTR)
- // Emits: (MOVPDI2DIrr:i32 VR128:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_93(N, X86::MOVPDI2DIrr, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (extractelt:i32 VR128:v4i32:$src1, (imm:iPTR):$src2)
- // Emits: (PEXTRDrr:i32 VR128:v4i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_94(N, X86::PEXTRDrr, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i64(SDNode *N) {
-
- // Pattern: (vector_extract:i64 VR128:v2i64:$src, 0:iPTR)
- // Emits: (MOVPQIto64rr:i64 VR128:v2i64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_93(N, X86::MOVPQIto64rr, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (extractelt:i64 VR128:v2i64:$src1, (imm:iPTR):$src2)
- // Emits: (PEXTRQrr:i64 VR128:v2i64:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_94(N, X86::PEXTRQrr, MVT::i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_93(N, X86::MOVPS2SSrr, MVT::f32);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_93(N, X86::MOVPD2SDrr, MVT::f64);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FABS_f32(SDNode *N) {
- if ((!Subtarget->hasSSE1())) {
- SDNode *Result = Emit_72(N, X86::ABS_Fp32, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FABS_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
- SDNode *Result = Emit_72(N, X86::ABS_Fp64, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FABS_f80(SDNode *N) {
- SDNode *Result = Emit_72(N, X86::ABS_Fp80, MVT::f80);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_96(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_97(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N02 = N0.getNode()->getOperand(2);
- SDValue N1 = N->getOperand(1);
- SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_FADD_f32(SDNode *N) {
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (ADD_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADD_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>, RFP32:f32:$src1)
- // Emits: (ADD_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADD_Fp32m, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADDSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADDSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR32:f32:$src1)
- // Emits: (ADDSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADDSSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->hasSSE1())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::FILD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getNode()->getOperand(2);
-
- // Pattern: (fadd:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
- // Emits: (ADD_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::ADD_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fadd:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
- // Emits: (ADD_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::ADD_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == X86ISD::FILD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N02 = N0.getNode()->getOperand(2);
-
- // Pattern: (fadd:f32 (X86fild:f32 addr:iPTR:$src2, i16:Other), RFP32:f32:$src1)
- // Emits: (ADD_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::ADD_FpI16m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (fadd:f32 (X86fild:f32 addr:iPTR:$src2, i32:Other), RFP32:f32:$src1)
- // Emits: (ADD_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::ADD_FpI32m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Emits: (ADD_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_15(N, X86::ADD_Fp32, MVT::f32);
- return Result;
- }
-
- // Pattern: (fadd:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (ADDSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_15(N, X86::ADDSSrr, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FADD_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode())) {
-
- // Pattern: (fadd:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (ADD_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADD_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fadd:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (ADD_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N1.getNode()) &&
- Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADD_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode())) {
-
- // Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>, RFP64:f64:$src1)
- // Emits: (ADD_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N0.getNode()) &&
- Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADD_Fp64m, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
-
- // Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>, RFP64:f64:$src1)
- // Emits: (ADD_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N0.getNode()) &&
- Predicate_extloadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADD_Fp64m32, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADDSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADDSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR64:f64:$src1)
- // Emits: (ADDSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADDSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::FILD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getNode()->getOperand(2);
-
- // Pattern: (fadd:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
- // Emits: (ADD_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::ADD_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fadd:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
- // Emits: (ADD_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::ADD_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == X86ISD::FILD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N02 = N0.getNode()->getOperand(2);
-
- // Pattern: (fadd:f64 (X86fild:f64 addr:iPTR:$src2, i16:Other), RFP64:f64:$src1)
- // Emits: (ADD_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::ADD_FpI16m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (fadd:f64 (X86fild:f64 addr:iPTR:$src2, i32:Other), RFP64:f64:$src1)
- // Emits: (ADD_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::ADD_FpI32m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Emits: (ADD_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_15(N, X86::ADD_Fp64, MVT::f64);
- return Result;
- }
-
- // Pattern: (fadd:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (ADDSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDNode *Result = Emit_15(N, X86::ADDSDrr, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FADD_f80(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_extload(N1.getNode())) {
-
- // Pattern: (fadd:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (ADD_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADD_Fp80m32, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fadd:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>)
- // Emits: (ADD_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADD_Fp80m64, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_extload(N0.getNode())) {
-
- // Pattern: (fadd:f80 (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>, RFP80:f80:$src1)
- // Emits: (ADD_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADD_Fp80m32, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
-
- // Pattern: (fadd:f80 (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>, RFP80:f80:$src1)
- // Emits: (ADD_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADD_Fp80m64, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::FILD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getNode()->getOperand(2);
-
- // Pattern: (fadd:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
- // Emits: (ADD_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::ADD_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fadd:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
- // Emits: (ADD_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::ADD_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == X86ISD::FILD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N02 = N0.getNode()->getOperand(2);
-
- // Pattern: (fadd:f80 (X86fild:f80 addr:iPTR:$src2, i16:Other), RFP80:f80:$src1)
- // Emits: (ADD_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::ADD_FpI16m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (fadd:f80 (X86fild:f80 addr:iPTR:$src2, i32:Other), RFP80:f80:$src1)
- // Emits: (ADD_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::ADD_FpI32m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Emits: (ADD_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_15(N, X86::ADD_Fp80, MVT::f80);
- return Result;
-}
-
-SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADDPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:v4f32 (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4f32:$src1)
- // Emits: (ADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADDPSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (ADDPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::ADDPSrr, MVT::v4f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FADD_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADDPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:v2f64 (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2f64:$src1)
- // Emits: (ADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADDPDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fadd:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (ADDPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::ADDPDrr, MVT::v2f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FCOS_f32(SDNode *N) {
- if ((!Subtarget->hasSSE1())) {
- SDNode *Result = Emit_72(N, X86::COS_Fp32, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FCOS_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
- SDNode *Result = Emit_72(N, X86::COS_Fp64, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FCOS_f80(SDNode *N) {
- SDNode *Result = Emit_72(N, X86::COS_Fp80, MVT::f80);
- return Result;
-}
-
-SDNode *Select_ISD_FDIV_f32(SDNode *N) {
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
-
- // Pattern: (fdiv:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (DIV_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- {
- SDNode *Result = Emit_18(N, X86::DIV_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fdiv:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (DIVR_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- SDNode *Result = Emit_18(N, X86::DIVR_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fdiv:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (DIVSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->hasSSE1())) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::FILD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getNode()->getOperand(2);
-
- // Pattern: (fdiv:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
- // Emits: (DIV_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::DIV_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fdiv:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
- // Emits: (DIV_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::DIV_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fdiv:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
- // Emits: (DIVR_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::DIVR_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fdiv:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
- // Emits: (DIVR_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::DIVR_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fdiv:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Emits: (DIV_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_15(N, X86::DIV_Fp32, MVT::f32);
- return Result;
- }
-
- // Pattern: (fdiv:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (DIVSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_15(N, X86::DIVSSrr, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FDIV_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode())) {
-
- // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (DIV_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIV_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (DIV_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N1.getNode()) &&
- Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIV_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (DIVR_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVR_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (DIVR_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N1.getNode()) &&
- Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVR_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (fdiv:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (DIVSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::FILD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getNode()->getOperand(2);
-
- // Pattern: (fdiv:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
- // Emits: (DIV_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::DIV_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fdiv:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
- // Emits: (DIV_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::DIV_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fdiv:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
- // Emits: (DIVR_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::DIVR_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fdiv:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
- // Emits: (DIVR_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::DIVR_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fdiv:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Emits: (DIV_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_15(N, X86::DIV_Fp64, MVT::f64);
- return Result;
- }
-
- // Pattern: (fdiv:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (DIVSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDNode *Result = Emit_15(N, X86::DIVSDrr, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FDIV_f80(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_extload(N1.getNode())) {
-
- // Pattern: (fdiv:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (DIV_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIV_Fp80m32, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fdiv:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>)
- // Emits: (DIV_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIV_Fp80m64, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fdiv:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (DIVR_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVR_Fp80m32, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fdiv:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>)
- // Emits: (DIVR_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVR_Fp80m64, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::FILD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getNode()->getOperand(2);
-
- // Pattern: (fdiv:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
- // Emits: (DIV_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::DIV_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fdiv:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
- // Emits: (DIV_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::DIV_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fdiv:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
- // Emits: (DIVR_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::DIVR_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fdiv:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
- // Emits: (DIVR_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::DIVR_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fdiv:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Emits: (DIV_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_15(N, X86::DIV_Fp80, MVT::f80);
- return Result;
-}
-
-SDNode *Select_ISD_FDIV_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (fdiv:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (DIVPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fdiv:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (DIVPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::DIVPSrr, MVT::v4f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FDIV_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (fdiv:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (DIVPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fdiv:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (DIVPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::DIVPDrr, MVT::v2f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FMUL_f32(SDNode *N) {
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (MUL_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MUL_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fmul:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>, RFP32:f32:$src1)
- // Emits: (MUL_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MUL_Fp32m, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MULSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MULSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fmul:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR32:f32:$src1)
- // Emits: (MULSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MULSSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->hasSSE1())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::FILD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getNode()->getOperand(2);
-
- // Pattern: (fmul:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
- // Emits: (MUL_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::MUL_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fmul:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
- // Emits: (MUL_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::MUL_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == X86ISD::FILD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N02 = N0.getNode()->getOperand(2);
-
- // Pattern: (fmul:f32 (X86fild:f32 addr:iPTR:$src2, i16:Other), RFP32:f32:$src1)
- // Emits: (MUL_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::MUL_FpI16m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (fmul:f32 (X86fild:f32 addr:iPTR:$src2, i32:Other), RFP32:f32:$src1)
- // Emits: (MUL_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::MUL_FpI32m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fmul:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Emits: (MUL_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_15(N, X86::MUL_Fp32, MVT::f32);
- return Result;
- }
-
- // Pattern: (fmul:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (MULSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_15(N, X86::MULSSrr, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FMUL_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode())) {
-
- // Pattern: (fmul:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (MUL_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MUL_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fmul:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (MUL_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N1.getNode()) &&
- Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MUL_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode())) {
-
- // Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>, RFP64:f64:$src1)
- // Emits: (MUL_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N0.getNode()) &&
- Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MUL_Fp64m, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
-
- // Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>, RFP64:f64:$src1)
- // Emits: (MUL_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N0.getNode()) &&
- Predicate_extloadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MUL_Fp64m32, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MULSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MULSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR64:f64:$src1)
- // Emits: (MULSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MULSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::FILD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getNode()->getOperand(2);
-
- // Pattern: (fmul:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
- // Emits: (MUL_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::MUL_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fmul:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
- // Emits: (MUL_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::MUL_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == X86ISD::FILD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N02 = N0.getNode()->getOperand(2);
-
- // Pattern: (fmul:f64 (X86fild:f64 addr:iPTR:$src2, i16:Other), RFP64:f64:$src1)
- // Emits: (MUL_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::MUL_FpI16m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (fmul:f64 (X86fild:f64 addr:iPTR:$src2, i32:Other), RFP64:f64:$src1)
- // Emits: (MUL_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::MUL_FpI32m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fmul:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Emits: (MUL_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_15(N, X86::MUL_Fp64, MVT::f64);
- return Result;
- }
-
- // Pattern: (fmul:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (MULSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDNode *Result = Emit_15(N, X86::MULSDrr, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FMUL_f80(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_extload(N1.getNode())) {
-
- // Pattern: (fmul:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (MUL_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MUL_Fp80m32, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fmul:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>)
- // Emits: (MUL_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MUL_Fp80m64, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_extload(N0.getNode())) {
-
- // Pattern: (fmul:f80 (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>, RFP80:f80:$src1)
- // Emits: (MUL_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MUL_Fp80m32, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
-
- // Pattern: (fmul:f80 (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>, RFP80:f80:$src1)
- // Emits: (MUL_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MUL_Fp80m64, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::FILD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getNode()->getOperand(2);
-
- // Pattern: (fmul:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
- // Emits: (MUL_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::MUL_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fmul:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
- // Emits: (MUL_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::MUL_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == X86ISD::FILD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N02 = N0.getNode()->getOperand(2);
-
- // Pattern: (fmul:f80 (X86fild:f80 addr:iPTR:$src2, i16:Other), RFP80:f80:$src1)
- // Emits: (MUL_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::MUL_FpI16m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (fmul:f80 (X86fild:f80 addr:iPTR:$src2, i32:Other), RFP80:f80:$src1)
- // Emits: (MUL_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::MUL_FpI32m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fmul:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Emits: (MUL_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_15(N, X86::MUL_Fp80, MVT::f80);
- return Result;
-}
-
-SDNode *Select_ISD_FMUL_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MULPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MULPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fmul:v4f32 (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4f32:$src1)
- // Emits: (MULPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MULPSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fmul:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (MULPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MULPSrr, MVT::v4f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FMUL_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MULPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MULPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fmul:v2f64 (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2f64:$src1)
- // Emits: (MULPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MULPDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fmul:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (MULPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MULPDrr, MVT::v2f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FNEG_f32(SDNode *N) {
- if ((!Subtarget->hasSSE1())) {
- SDNode *Result = Emit_72(N, X86::CHS_Fp32, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FNEG_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
- SDNode *Result = Emit_72(N, X86::CHS_Fp64, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FNEG_f80(SDNode *N) {
- SDNode *Result = Emit_72(N, X86::CHS_Fp80, MVT::f80);
- return Result;
-}
-
-SDNode *Select_ISD_FP_EXTEND_f64(SDNode *N) {
-
- // Pattern: (fextend:f64 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (CVTSS2SDrm:f64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_79(N, X86::CVTSS2SDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fextend:f64 RFP32:f32:$src)
- // Emits: (MOV_Fp3264:f64 RFP32:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_72(N, X86::MOV_Fp3264, MVT::f64);
- return Result;
- }
- }
-
- // Pattern: (fextend:f64 FR32:f32:$src)
- // Emits: (CVTSS2SDrr:f64 FR32:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_72(N, X86::CVTSS2SDrr, MVT::f64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_EXTEND_f80(SDNode *N) {
-
- // Pattern: (fextend:f80 RFP32:f32:$src)
- // Emits: (MOV_Fp3280:f80 RFP32:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_72(N, X86::MOV_Fp3280, MVT::f80);
- return Result;
- }
- }
-
- // Pattern: (fextend:f80 RFP64:f64:$src)
- // Emits: (MOV_Fp6480:f80 RFP64:f64:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_72(N, X86::MOV_Fp6480, MVT::f80);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_ROUND_f32(SDNode *N) {
-
- // Pattern: (fround:f32 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (CVTSD2SSrm:f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2()) && (OptForSize)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_79(N, X86::CVTSD2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fround:f32 RFP64:f64:$src)
- // Emits: (MOV_Fp6432:f32 RFP64:f64:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_72(N, X86::MOV_Fp6432, MVT::f32);
- return Result;
- }
-
- // Pattern: (fround:f32 RFP80:f80:$src)
- // Emits: (MOV_Fp8032:f32 RFP80:f80:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::f80) {
- SDNode *Result = Emit_72(N, X86::MOV_Fp8032, MVT::f32);
- return Result;
- }
- }
-
- // Pattern: (fround:f32 FR64:f64:$src)
- // Emits: (CVTSD2SSrr:f32 FR64:f64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_72(N, X86::CVTSD2SSrr, MVT::f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_ROUND_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f80) {
- SDNode *Result = Emit_72(N, X86::MOV_Fp8064, MVT::f64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_TO_SINT_i32(SDNode *N) {
-
- // Pattern: (fp_to_sint:i32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (CVTTSS2SIrm:i32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_79(N, X86::CVTTSS2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fp_to_sint:i32 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (CVTTSD2SIrm:i32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_79(N, X86::CVTTSD2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fp_to_sint:i32 FR32:f32:$src)
- // Emits: (CVTTSS2SIrr:i32 FR32:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_72(N, X86::CVTTSS2SIrr, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (fp_to_sint:i32 FR64:f64:$src)
- // Emits: (CVTTSD2SIrr:i32 FR64:f64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_72(N, X86::CVTTSD2SIrr, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_TO_SINT_i64(SDNode *N) {
-
- // Pattern: (fp_to_sint:i64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (CVTTSD2SI64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_79(N, X86::CVTTSD2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fp_to_sint:i64 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (CVTTSS2SI64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_79(N, X86::CVTTSS2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fp_to_sint:i64 FR64:f64:$src)
- // Emits: (CVTTSD2SI64rr:i64 FR64:f64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_72(N, X86::CVTTSD2SI64rr, MVT::i64);
- return Result;
- }
- }
-
- // Pattern: (fp_to_sint:i64 FR32:f32:$src)
- // Emits: (CVTTSS2SI64rr:i64 FR32:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_72(N, X86::CVTTSS2SI64rr, MVT::i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_TO_SINT_v2i32(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_72(N, X86::Int_CVTTPD2PIrr, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FP_TO_SINT_v4i32(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_72(N, X86::Int_CVTTPS2DQrr, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSIN_f32(SDNode *N) {
- if ((!Subtarget->hasSSE1())) {
- SDNode *Result = Emit_72(N, X86::SIN_Fp32, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSIN_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
- SDNode *Result = Emit_72(N, X86::SIN_Fp64, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSIN_f80(SDNode *N) {
- SDNode *Result = Emit_72(N, X86::SIN_Fp80, MVT::f80);
- return Result;
-}
-
-SDNode *Select_ISD_FSQRT_f32(SDNode *N) {
-
- // Pattern: (fsqrt:f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SQRTSSm:f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1()) && (OptForSize)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::SQRTSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fsqrt:f32 RFP32:f32:$src)
- // Emits: (SQRT_Fp32:f32 RFP32:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE1())) {
- SDNode *Result = Emit_72(N, X86::SQRT_Fp32, MVT::f32);
- return Result;
- }
-
- // Pattern: (fsqrt:f32 FR32:f32:$src)
- // Emits: (SQRTSSr:f32 FR32:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_72(N, X86::SQRTSSr, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSQRT_f64(SDNode *N) {
-
- // Pattern: (fsqrt:f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SQRTSDm:f64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::SQRTSDm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fsqrt:f64 RFP64:f64:$src)
- // Emits: (SQRT_Fp64:f64 RFP64:f64:$src)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE2())) {
- SDNode *Result = Emit_72(N, X86::SQRT_Fp64, MVT::f64);
- return Result;
- }
-
- // Pattern: (fsqrt:f64 FR64:f64:$src)
- // Emits: (SQRTSDr:f64 FR64:f64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDNode *Result = Emit_72(N, X86::SQRTSDr, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSQRT_f80(SDNode *N) {
- SDNode *Result = Emit_72(N, X86::SQRT_Fp80, MVT::f80);
- return Result;
-}
-
-SDNode *Select_ISD_FSQRT_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (fsqrt:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (SQRTPSm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::SQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fsqrt:v4f32 VR128:v4f32:$src)
- // Emits: (SQRTPSr:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_72(N, X86::SQRTPSr, MVT::v4f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSQRT_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (fsqrt:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (SQRTPDm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::SQRTPDm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fsqrt:v2f64 VR128:v2f64:$src)
- // Emits: (SQRTPDr:v2f64 VR128:v2f64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_72(N, X86::SQRTPDr, MVT::v2f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSUB_f32(SDNode *N) {
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
-
- // Pattern: (fsub:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (SUB_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- {
- SDNode *Result = Emit_18(N, X86::SUB_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fsub:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (SUBR_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- SDNode *Result = Emit_18(N, X86::SUBR_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fsub:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUBSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->hasSSE1())) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::FILD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getNode()->getOperand(2);
-
- // Pattern: (fsub:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
- // Emits: (SUB_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::SUB_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fsub:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
- // Emits: (SUB_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::SUB_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fsub:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
- // Emits: (SUBR_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::SUBR_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fsub:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
- // Emits: (SUBR_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::SUBR_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fsub:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Emits: (SUB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_15(N, X86::SUB_Fp32, MVT::f32);
- return Result;
- }
-
- // Pattern: (fsub:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (SUBSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_15(N, X86::SUBSSrr, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSUB_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode())) {
-
- // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (SUB_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUB_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (SUB_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N1.getNode()) &&
- Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUB_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (SUBR_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBR_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (SUBR_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N1.getNode()) &&
- Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBR_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (fsub:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUBSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::FILD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getNode()->getOperand(2);
-
- // Pattern: (fsub:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
- // Emits: (SUB_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::SUB_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fsub:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
- // Emits: (SUB_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::SUB_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fsub:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
- // Emits: (SUBR_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::SUBR_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fsub:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
- // Emits: (SUBR_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::SUBR_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fsub:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Emits: (SUB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_15(N, X86::SUB_Fp64, MVT::f64);
- return Result;
- }
-
- // Pattern: (fsub:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (SUBSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDNode *Result = Emit_15(N, X86::SUBSDrr, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSUB_f80(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_extload(N1.getNode())) {
-
- // Pattern: (fsub:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (SUB_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUB_Fp80m32, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fsub:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>)
- // Emits: (SUB_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUB_Fp80m64, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fsub:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (SUBR_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBR_Fp80m32, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fsub:f80 RFP80:f80:$src1, (ld:f80 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>)
- // Emits: (SUBR_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extloadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBR_Fp80m64, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::FILD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getNode()->getOperand(2);
-
- // Pattern: (fsub:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
- // Emits: (SUB_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::SUB_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fsub:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
- // Emits: (SUB_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::SUB_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fsub:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
- // Emits: (SUBR_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_96(N, X86::SUBR_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (fsub:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
- // Emits: (SUBR_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
- // Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_96(N, X86::SUBR_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fsub:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Emits: (SUB_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- SDNode *Result = Emit_15(N, X86::SUB_Fp80, MVT::f80);
- return Result;
-}
-
-SDNode *Select_ISD_FSUB_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (fsub:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (SUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fsub:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (SUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::SUBPSrr, MVT::v4f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FSUB_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (fsub:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (SUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (fsub:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (SUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::SUBPDrr, MVT::v2f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FrameIndex_i32(SDNode *N) {
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_FrameIndex_i64(SDNode *N) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_98(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_99(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Tmp2, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (insertelt:v4i32 VR128:v4i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:iPTR):$src3)
- // Emits: (PINSRDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_99(N, X86::PINSRDrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (insertelt:v4i32 VR128:v4i32:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
- // Emits: (PINSRDrr:v4i32 VR128:v4i32:$src1, GR32:i32:$src2, (imm:i32):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_98(N, X86::PINSRDrr, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i64(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (insertelt:v2i64 VR128:v2i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:iPTR):$src3)
- // Emits: (PINSRQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_99(N, X86::PINSRQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (insertelt:v2i64 VR128:v2i64:$src1, GR64:i64:$src2, (imm:iPTR):$src3)
- // Emits: (PINSRQrr:v2i64 VR128:v2i64:$src1, GR64:i64:$src2, (imm:i32):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_98(N, X86::PINSRQrr, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_100(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N3, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
-}
-DISABLE_INLINE SDNode *Emit_101(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
-}
-DISABLE_INLINE SDNode *Emit_102(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_103(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EDI, N4, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- SDValue Ops0[] = { N2, N3, Chain, InFlag };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_104(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::RDI, N4, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- SDValue Ops0[] = { N2, N3, Chain, InFlag };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_105(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EAX, N2, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::ECX, N3, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EDX, N4, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_106(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::ECX, N2, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EAX, N3, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain, InFlag);
-}
-SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_void:isVoid 715:iPTR, addr:iPTR:$dst, VR128:v4f32:$src)
- // Emits: (MOVUPSmr_Int:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(715)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_100(N, X86::MOVUPSmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 705:iPTR, addr:iPTR:$dst, VR128:v4f32:$src)
- // Emits: (MOVNTPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(705)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_100(N, X86::MOVNTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 698:iPTR, addr:iPTR:$src)
- // Emits: (LDMXCSR:isVoid addr:iPTR:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(698)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_102(N, X86::LDMXCSR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 714:iPTR, addr:iPTR:$dst)
- // Emits: (STMXCSR:isVoid addr:iPTR:$dst)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(714)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_102(N, X86::STMXCSR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_void:isVoid 593:iPTR, addr:iPTR:$dst, VR128:v2f64:$src)
- // Emits: (MOVUPDmr_Int:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(593)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_100(N, X86::MOVUPDmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 592:iPTR, addr:iPTR:$dst, VR128:v16i8:$src)
- // Emits: (MOVDQUmr_Int:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(592)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_100(N, X86::MOVDQUmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 538:iPTR, addr:iPTR:$dst, VR128:v2f64:$src)
- // Emits: (MOVNTPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(538)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_100(N, X86::MOVNTPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 536:iPTR, addr:iPTR:$dst, VR128:v2i64:$src)
- // Emits: (MOVNTDQmr:isVoid addr:iPTR:$dst, VR128:v2i64:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(536)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_100(N, X86::MOVNTDQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 537:iPTR, addr:iPTR:$dst, GR32:i32:$src)
- // Emits: (MOVNTImr:isVoid addr:iPTR:$dst, GR32:i32:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(537)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_100(N, X86::MOVNTImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 500:iPTR, addr:iPTR:$src)
- // Emits: (CLFLUSH:isVoid addr:iPTR:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(500)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_102(N, X86::CLFLUSH, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 591:iPTR, addr:iPTR:$dst, VR128:v4i32:$src)
- // Emits: (MOVLQ128mr:isVoid addr:iPTR:$dst, VR128:v4i32:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(591)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_100(N, X86::MOVLQ128mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 453:iPTR, addr:iPTR:$dst, VR64:v1i64:$src)
- // Emits: (MMX_MOVNTQmr:isVoid addr:iPTR:$dst, VR64:v1i64:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(453)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_100(N, X86::MMX_MOVNTQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 711:iPTR)
- // Emits: (SFENCE:isVoid)
- // Pattern complexity = 8 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(711)) {
- SDNode *Result = Emit_101(N, X86::SFENCE);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(529)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
-
- // Pattern: (intrinsic_void:isVoid 529:iPTR, VR128:v16i8:$src, VR128:v16i8:$mask, EDI:i32)
- // Emits: (MASKMOVDQU:isVoid VR128:v16i8:$src, VR128:v16i8:$mask)
- // Pattern complexity = 8 cost = 1 size = 3
- if (N4.getValueType() == MVT::i32) {
- SDNode *Result = Emit_103(N, X86::MASKMOVDQU);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 529:iPTR, VR128:v16i8:$src, VR128:v16i8:$mask, RDI:i64)
- // Emits: (MASKMOVDQU64:isVoid VR128:v16i8:$src, VR128:v16i8:$mask)
- // Pattern complexity = 8 cost = 1 size = 3
- if (N4.getValueType() == MVT::i64) {
- SDNode *Result = Emit_104(N, X86::MASKMOVDQU64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 526:iPTR)
- // Emits: (LFENCE:isVoid)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(526)) {
- SDNode *Result = Emit_101(N, X86::LFENCE);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 532:iPTR)
- // Emits: (MFENCE:isVoid)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(532)) {
- SDNode *Result = Emit_101(N, X86::MFENCE);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE3())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_void:isVoid 608:iPTR, EAX:i32, ECX:i32, EDX:i32)
- // Emits: (MONITOR:isVoid)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(608)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- if (N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_105(N, X86::MONITOR);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 609:iPTR, ECX:i32, EAX:i32)
- // Emits: (MWAIT:isVoid)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(609)) {
- SDNode *Result = Emit_106(N, X86::MWAIT);
- return Result;
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_void:isVoid 450:iPTR)
- // Emits: (MMX_EMMS:isVoid)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(450)) {
- SDNode *Result = Emit_101(N, X86::MMX_EMMS);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 451:iPTR)
- // Emits: (MMX_FEMMS:isVoid)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(451)) {
- SDNode *Result = Emit_101(N, X86::MMX_FEMMS);
- return Result;
- }
-
- // Pattern: (intrinsic_void:isVoid 452:iPTR, VR64:v8i8:$src, VR64:v8i8:$mask, EDI:i32)
- // Emits: (MMX_MASKMOVQ:isVoid VR64:v8i8:$src, VR64:v8i8:$mask)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(452)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- if (N4.getValueType() == MVT::i32) {
- SDNode *Result = Emit_103(N, X86::MMX_MASKMOVQ);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_void:isVoid 452:iPTR, VR64:v8i8:$src, VR64:v8i8:$mask, RDI:i64)
- // Emits: (MMX_MASKMOVQ64:isVoid VR64:v8i8:$src, VR64:v8i8:$mask)
- // Pattern complexity = 8 cost = 1 size = 3
- if ((Subtarget->hasMMX()) && (Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(452)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- if (N4.getValueType() == MVT::i64) {
- SDNode *Result = Emit_104(N, X86::MMX_MASKMOVQ64);
- return Result;
- }
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_107(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1);
-}
-DISABLE_INLINE SDNode *Emit_108(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_109(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Chain2 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N2.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4, Chain2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_110(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2);
-}
-DISABLE_INLINE SDNode *Emit_111(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::i32, N1, N2, Tmp4);
-}
-DISABLE_INLINE SDNode *Emit_112(SDNode *N, unsigned Opc0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Chain2 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N2.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4, Tmp4, Chain2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::i32, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 2));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_113(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N5)->getZExtValue()), MVT::i8);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EAX, N2, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EDX, N4, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- SDValue Ops0[] = { N1, N3, Tmp4, InFlag };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::i32, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_114(SDNode *N, unsigned Opc0, SDValue &CPTmpN31_0, SDValue &CPTmpN31_1, SDValue &CPTmpN31_2, SDValue &CPTmpN31_3, SDValue &CPTmpN31_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Chain3 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N5)->getZExtValue()), MVT::i8);
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain3, N->getDebugLoc(), X86::EAX, N2, InFlag).getNode();
- Chain3 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain3, N->getDebugLoc(), X86::EDX, N4, InFlag).getNode();
- Chain3 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N3.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4, Tmp4, Chain3, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::i32, MVT::Other, Ops0, 9);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N3.getNode(), 1), SDValue(ResNode, 2));
- return ResNode;
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:i32 669:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRIrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(669)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRIrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 670:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRIArm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(670)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRIArm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 671:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRICrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(671)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRICrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 672:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRIOrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(672)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRIOrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 673:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRISrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(673)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRISrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 674:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRIZrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(674)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRIZrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 661:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRIrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(661)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRIrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 662:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRIArm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(662)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRIArm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 663:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRICrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(663)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRICrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 664:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRIOrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(664)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRIOrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 665:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRISrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(665)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRISrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 666:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRIZrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(666)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRIZrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:i32 691:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTSS2SIrm:i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(691)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 695:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTTSS2SIrm:i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(695)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:i32 515:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTSD2SIrm:i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(515)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 523:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTTSD2SIrm:i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(523)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:i32 660:iPTR, GR32:i32:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (CRC32m8:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(660)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::CRC32m8, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 657:iPTR, GR32:i32:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (CRC32m16:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(657)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::CRC32m16, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 658:iPTR, GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (CRC32m32:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(658)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::CRC32m32, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 669:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Emits: (PCMPISTRIrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(669)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_111(N, X86::PCMPISTRIrr);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 670:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Emits: (PCMPISTRIArr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(670)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_111(N, X86::PCMPISTRIArr);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 671:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Emits: (PCMPISTRICrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(671)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_111(N, X86::PCMPISTRICrr);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 672:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Emits: (PCMPISTRIOrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(672)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_111(N, X86::PCMPISTRIOrr);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 673:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Emits: (PCMPISTRISrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(673)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_111(N, X86::PCMPISTRISrr);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 674:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Emits: (PCMPISTRIZrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(674)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_111(N, X86::PCMPISTRIZrr);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 661:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRIrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(661)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPESTRIrr);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 662:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRIArr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(662)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPESTRIArr);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 663:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRICrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(663)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPESTRICrr);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 664:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRIOrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(664)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPESTRIOrr);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 665:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRISrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(665)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPESTRISrr);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 666:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRIZrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(666)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPESTRIZrr);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:i32 691:iPTR, VR128:v4f32:$src)
- // Emits: (Int_CVTSS2SIrr:i32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(691)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTSS2SIrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:i32 695:iPTR, VR128:v4f32:$src)
- // Emits: (Int_CVTTSS2SIrr:i32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(695)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTSS2SIrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:i32 704:iPTR, VR128:v4f32:$src)
- // Emits: (MOVMSKPSrr:i32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(704)) {
- SDNode *Result = Emit_107(N, X86::MOVMSKPSrr, MVT::i32);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:i32 535:iPTR, VR128:v2f64:$src)
- // Emits: (MOVMSKPDrr:i32 VR128:v2f64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(535)) {
- SDNode *Result = Emit_107(N, X86::MOVMSKPDrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:i32 515:iPTR, VR128:v2f64:$src)
- // Emits: (Int_CVTSD2SIrr:i32 VR128:v2f64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(515)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTSD2SIrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:i32 523:iPTR, VR128:v2f64:$src)
- // Emits: (Int_CVTTSD2SIrr:i32 VR128:v2f64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(523)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTSD2SIrr, MVT::i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:i32 560:iPTR, VR128:v16i8:$src)
- // Emits: (PMOVMSKBrr:i32 VR128:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(560)) {
- SDNode *Result = Emit_107(N, X86::PMOVMSKBrr, MVT::i32);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:i32 660:iPTR, GR32:i32:$src1, GR8:i8:$src2)
- // Emits: (CRC32r8:i32 GR32:i32:$src1, GR8:i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(660)) {
- SDNode *Result = Emit_110(N, X86::CRC32r8, MVT::i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:i32 657:iPTR, GR32:i32:$src1, GR16:i16:$src2)
- // Emits: (CRC32r16:i32 GR32:i32:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(657)) {
- SDNode *Result = Emit_110(N, X86::CRC32r16, MVT::i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:i32 658:iPTR, GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (CRC32r32:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(658)) {
- SDNode *Result = Emit_110(N, X86::CRC32r32, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i32 474:iPTR, VR64:v8i8:$src)
- // Emits: (MMX_PMOVMSKBrr:i32 VR64:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(474)) {
- SDNode *Result = Emit_107(N, X86::MMX_PMOVMSKBrr, MVT::i32);
- return Result;
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:i64 516:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTSD2SI64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(516)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i64 524:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTTSD2SI64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(524)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:i64 692:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTSS2SI64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(692)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i64 696:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTTSS2SI64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(696)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i64 659:iPTR, GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (CRC64m64:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(659)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::CRC64m64, MVT::i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:i64 516:iPTR, VR128:v2f64:$src)
- // Emits: (Int_CVTSD2SI64rr:i64 VR128:v2f64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(516)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTSD2SI64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:i64 524:iPTR, VR128:v2f64:$src)
- // Emits: (Int_CVTTSD2SI64rr:i64 VR128:v2f64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(524)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTSD2SI64rr, MVT::i64);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:i64 692:iPTR, VR128:v4f32:$src)
- // Emits: (Int_CVTSS2SI64rr:i64 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(692)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTSS2SI64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:i64 696:iPTR, VR128:v4f32:$src)
- // Emits: (Int_CVTTSS2SI64rr:i64 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(696)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTSS2SI64rr, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:i64 659:iPTR, GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (CRC64r64:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(659)) {
- SDNode *Result = Emit_110(N, X86::CRC64r64, MVT::i64);
- return Result;
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_115(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_116(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue Chain20 = N20.getNode()->getOperand(0);
- SDValue N201 = N20.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N20.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4, Chain20 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N20.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_117(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { N2, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(SDNode *N) {
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i8 723:iPTR, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PABSBrm64:v8i8 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(723)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_115(N, X86::PABSBrm64, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 747:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PSHUFBrm64:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(747)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_116(N, X86::PSHUFBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 749:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PSIGNBrm64:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(749)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_116(N, X86::PSIGNBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i8 457:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(457)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 459:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(459)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 495:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(495)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSUBSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 497:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(497)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSUBUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 461:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PAVGBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(461)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 473:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMINUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(473)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 471:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMAXUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(471)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 463:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPEQBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(463)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 466:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPGTBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(466)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PCMPGTBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 455:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PACKSSWBrm:v8i8 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(455)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PACKSSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 456:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PACKUSWBrm:v8i8 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(456)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PACKUSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 457:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PADDSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(457)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 459:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PADDUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(459)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 461:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PAVGBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(461)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 473:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PMINUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(473)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 471:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PMAXUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(471)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i8 723:iPTR, VR64:v8i8:$src)
- // Emits: (PABSBrr64:v8i8 VR64:v8i8:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(723)) {
- SDNode *Result = Emit_107(N, X86::PABSBrr64, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 747:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (PSHUFBrr64:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(747)) {
- SDNode *Result = Emit_110(N, X86::PSHUFBrr64, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 749:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (PSIGNBrr64:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(749)) {
- SDNode *Result = Emit_110(N, X86::PSIGNBrr64, MVT::v8i8);
- return Result;
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i8 457:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PADDSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(457)) {
- SDNode *Result = Emit_110(N, X86::MMX_PADDSBrr, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 459:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PADDUSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(459)) {
- SDNode *Result = Emit_110(N, X86::MMX_PADDUSBrr, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 495:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PSUBSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(495)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSUBSBrr, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 497:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PSUBUSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(497)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSUBUSBrr, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 461:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PAVGBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(461)) {
- SDNode *Result = Emit_110(N, X86::MMX_PAVGBrr, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 473:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PMINUBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(473)) {
- SDNode *Result = Emit_110(N, X86::MMX_PMINUBrr, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 471:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PMAXUBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(471)) {
- SDNode *Result = Emit_110(N, X86::MMX_PMAXUBrr, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 463:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PCMPEQBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(463)) {
- SDNode *Result = Emit_110(N, X86::MMX_PCMPEQBrr, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 466:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PCMPGTBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(466)) {
- SDNode *Result = Emit_110(N, X86::MMX_PCMPGTBrr, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 455:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PACKSSWBrr:v8i8 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(455)) {
- SDNode *Result = Emit_110(N, X86::MMX_PACKSSWBrr, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i8 456:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PACKUSWBrr:v8i8 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(456)) {
- SDNode *Result = Emit_110(N, X86::MMX_PACKUSWBrr, MVT::v8i8);
- return Result;
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_118(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2, Tmp4);
-}
-DISABLE_INLINE SDNode *Emit_119(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue Chain20 = N20.getNode()->getOperand(0);
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N20.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4, Tmp4, Chain20 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N20.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_120(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::XMM0, N3, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_121(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N20 = N2.getNode()->getOperand(0);
- SDValue Chain20 = N20.getNode()->getOperand(0);
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue N3 = N->getOperand(3);
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain20, N->getDebugLoc(), X86::XMM0, N3, InFlag).getNode();
- Chain20 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N20.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4, Chain20, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N20.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_122(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2, Tmp4);
-}
-DISABLE_INLINE SDNode *Emit_123(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Chain2 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N2.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4, Tmp4, Chain2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_124(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N5)->getZExtValue()), MVT::i8);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EAX, N2, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EDX, N4, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- SDValue Ops0[] = { N1, N3, Tmp4, InFlag };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_125(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN31_0, SDValue &CPTmpN31_1, SDValue &CPTmpN31_2, SDValue &CPTmpN31_3, SDValue &CPTmpN31_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Chain3 = N3.getNode()->getOperand(0);
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N5)->getZExtValue()), MVT::i8);
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain3, N->getDebugLoc(), X86::EAX, N2, InFlag).getNode();
- Chain3 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain3, N->getDebugLoc(), X86::EDX, N4, InFlag).getNode();
- Chain3 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N3.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4, Tmp4, Chain3, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 9);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N3.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_126(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { N2, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(619)) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (intrinsic_wo_chain:v16i8 619:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
- // Emits: (MPSADBWrmi:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_119(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 619:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1, (imm:i32):$src3)
- // Emits: (MPSADBWrmi:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_126(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v16i8 543:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(543)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PADDSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 545:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(545)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 585:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(585)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSUBSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 587:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(587)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSUBUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 547:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PAVGBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(547)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PAVGBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 559:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMINUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(559)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMINUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 557:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMAXUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(557)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 549:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPEQBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(549)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PCMPEQBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 552:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPGTBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(552)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PCMPGTBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 541:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PACKSSWBrm:v16i8 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(541)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PACKSSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 542:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PACKUSWBrm:v16i8 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(542)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PACKUSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v16i8 724:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PABSBrm128:v16i8 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(724)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PABSBrm128, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 748:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSHUFBrm128:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(748)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PSHUFBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 750:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSIGNBrm128:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(750)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PSIGNBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v16i8 632:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMINSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(632)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMINSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 628:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMAXSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(628)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 621:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v16i8)
- // Emits: (PBLENDVBrm0:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(621)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_121(N, X86::PBLENDVBrm0, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v16i8 543:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PADDSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(543)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PADDSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 545:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PADDUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(545)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 547:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PAVGBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(547)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PAVGBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 559:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PMINUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(559)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMINUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 557:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PMAXUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(557)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v16i8 632:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PMINSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(632)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMINSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 628:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PMAXSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(628)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v16i8 675:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRM128MEM:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 11 size = 3
- if (CN1 == INT64_C(675)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::PCMPISTRM128MEM, MVT::v16i8, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 667:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRM128MEM:v16i8 VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 11 size = 3
- if (CN1 == INT64_C(667)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_125(N, X86::PCMPESTRM128MEM, MVT::v16i8, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 619:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
- // Emits: (MPSADBWrri:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(619)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_118(N, X86::MPSADBWrri, MVT::v16i8);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v16i8 675:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Emits: (PCMPISTRM128REG:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
- // Pattern complexity = 11 cost = 11 size = 3
- if (CN1 == INT64_C(675)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_122(N, X86::PCMPISTRM128REG, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 667:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRM128REG:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
- // Pattern complexity = 11 cost = 11 size = 3
- if (CN1 == INT64_C(667)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_124(N, X86::PCMPESTRM128REG, MVT::v16i8);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v16i8 543:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PADDSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(543)) {
- SDNode *Result = Emit_110(N, X86::PADDSBrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 545:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PADDUSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(545)) {
- SDNode *Result = Emit_110(N, X86::PADDUSBrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 585:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PSUBSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(585)) {
- SDNode *Result = Emit_110(N, X86::PSUBSBrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 587:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PSUBUSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(587)) {
- SDNode *Result = Emit_110(N, X86::PSUBUSBrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 547:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PAVGBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(547)) {
- SDNode *Result = Emit_110(N, X86::PAVGBrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 559:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PMINUBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(559)) {
- SDNode *Result = Emit_110(N, X86::PMINUBrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 557:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PMAXUBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(557)) {
- SDNode *Result = Emit_110(N, X86::PMAXUBrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 549:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PCMPEQBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(549)) {
- SDNode *Result = Emit_110(N, X86::PCMPEQBrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 552:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PCMPGTBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(552)) {
- SDNode *Result = Emit_110(N, X86::PCMPGTBrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 541:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PACKSSWBrr:v16i8 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(541)) {
- SDNode *Result = Emit_110(N, X86::PACKSSWBrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 542:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PACKUSWBrr:v16i8 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(542)) {
- SDNode *Result = Emit_110(N, X86::PACKUSWBrr, MVT::v16i8);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v16i8 724:iPTR, VR128:v16i8:$src)
- // Emits: (PABSBrr128:v16i8 VR128:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(724)) {
- SDNode *Result = Emit_107(N, X86::PABSBrr128, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 748:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PSHUFBrr128:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(748)) {
- SDNode *Result = Emit_110(N, X86::PSHUFBrr128, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 750:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PSIGNBrr128:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(750)) {
- SDNode *Result = Emit_110(N, X86::PSIGNBrr128, MVT::v16i8);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v16i8 632:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PMINSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(632)) {
- SDNode *Result = Emit_110(N, X86::PMINSBrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 628:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PMAXSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(628)) {
- SDNode *Result = Emit_110(N, X86::PMAXSBrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 621:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, XMM0:v16i8)
- // Emits: (PBLENDVBrr0:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(621)) {
- SDNode *Result = Emit_120(N, X86::PBLENDVBrr0, MVT::v16i8);
- return Result;
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_127(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, Tmp3);
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(SDNode *N) {
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i16 727:iPTR, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PABSWrm64:v4i16 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(727)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_115(N, X86::PABSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 735:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHADDWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(735)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PHADDWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 733:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHADDSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(733)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PHADDSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 741:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHSUBWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(741)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PHSUBWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 739:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHSUBSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(739)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PHSUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 743:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PMADDUBSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(743)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_116(N, X86::PMADDUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 745:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PMULHRSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(745)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 753:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PSIGNWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(753)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PSIGNWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i16 458:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(458)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 460:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(460)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 496:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(496)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSUBSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 498:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(498)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSUBUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMULHWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(475)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 476:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMULHUWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(476)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 462:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PAVGWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(462)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 472:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMINSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(472)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 470:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMAXSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(470)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 478:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSADBWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(478)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 491:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSRLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(491)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSRLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 481:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSLLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(481)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSLLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 486:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSRAWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(486)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSRAWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 465:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPEQWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(465)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 468:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPGTWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(468)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PCMPGTWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 454:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PACKSSDWrm:v4i16 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(454)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PACKSSDWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 745:iPTR, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>), VR64:v4i16:$src1)
- // Emits: (PMULHRSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(745)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_117(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i16 458:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PADDSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(458)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 460:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PADDUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(460)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PMULHWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(475)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 476:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PMULHUWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(476)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 462:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PAVGWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(462)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 472:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PMINSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(472)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 470:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PMAXSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(470)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 478:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PSADBWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(478)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 494:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
- // Emits: (MMX_PSRLWri:v4i16 VR64:v4i16:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(494)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::MMX_PSRLWri, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 484:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
- // Emits: (MMX_PSLLWri:v4i16 VR64:v4i16:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(484)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::MMX_PSLLWri, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 488:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
- // Emits: (MMX_PSRAWri:v4i16 VR64:v4i16:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(488)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::MMX_PSRAWri, MVT::v4i16);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i16 727:iPTR, VR64:v4i16:$src)
- // Emits: (PABSWrr64:v4i16 VR64:v4i16:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(727)) {
- SDNode *Result = Emit_107(N, X86::PABSWrr64, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 735:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (PHADDWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(735)) {
- SDNode *Result = Emit_110(N, X86::PHADDWrr64, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 733:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (PHADDSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(733)) {
- SDNode *Result = Emit_110(N, X86::PHADDSWrr64, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 741:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (PHSUBWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(741)) {
- SDNode *Result = Emit_110(N, X86::PHSUBWrr64, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 739:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (PHSUBSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(739)) {
- SDNode *Result = Emit_110(N, X86::PHSUBSWrr64, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 743:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (PMADDUBSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(743)) {
- SDNode *Result = Emit_110(N, X86::PMADDUBSWrr64, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 745:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (PMULHRSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(745)) {
- SDNode *Result = Emit_110(N, X86::PMULHRSWrr64, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 753:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (PSIGNWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(753)) {
- SDNode *Result = Emit_110(N, X86::PSIGNWrr64, MVT::v4i16);
- return Result;
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i16 458:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PADDSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(458)) {
- SDNode *Result = Emit_110(N, X86::MMX_PADDSWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 460:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PADDUSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(460)) {
- SDNode *Result = Emit_110(N, X86::MMX_PADDUSWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 496:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PSUBSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(496)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSUBSWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 498:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PSUBUSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(498)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSUBUSWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PMULHWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(475)) {
- SDNode *Result = Emit_110(N, X86::MMX_PMULHWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 476:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PMULHUWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(476)) {
- SDNode *Result = Emit_110(N, X86::MMX_PMULHUWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 462:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PAVGWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(462)) {
- SDNode *Result = Emit_110(N, X86::MMX_PAVGWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 472:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PMINSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(472)) {
- SDNode *Result = Emit_110(N, X86::MMX_PMINSWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 470:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PMAXSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(470)) {
- SDNode *Result = Emit_110(N, X86::MMX_PMAXSWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 478:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PSADBWrr:v4i16 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(478)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSADBWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 491:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PSRLWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(491)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSRLWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 481:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PSLLWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(481)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSLLWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 486:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PSRAWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(486)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSRAWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 465:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PCMPEQWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(465)) {
- SDNode *Result = Emit_110(N, X86::MMX_PCMPEQWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 468:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PCMPGTWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(468)) {
- SDNode *Result = Emit_110(N, X86::MMX_PCMPGTWrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i16 454:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (MMX_PACKSSDWrr:v4i16 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(454)) {
- SDNode *Result = Emit_110(N, X86::MMX_PACKSSDWrr, MVT::v4i16);
- return Result;
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_128(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue Chain100 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N100.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, Chain100 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N100.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_129(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10001_0, SDValue &CPTmpN10001_1, SDValue &CPTmpN10001_2, SDValue &CPTmpN10001_3, SDValue &CPTmpN10001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- SDValue N10001 = N1000.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1000.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4, Chain1000 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1000.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_130(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, (bitconvert:v16i8 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
- // Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(638)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_load(N1000.getNode()) &&
- Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 644:iPTR, (bitconvert:v16i8 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
- // Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(644)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_load(N1000.getNode()) &&
- Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 622:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
- // Emits: (PBLENDWrmi:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(622)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_119(N, X86::PBLENDWrmi, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, (bitconvert:v16i8 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
- // Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(638)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 644:iPTR, (bitconvert:v16i8 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
- // Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(644)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 544:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(544)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PADDSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 546:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(546)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 586:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(586)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSUBSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 588:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(588)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSUBUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 562:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMULHUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(562)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMULHWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(561)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMULHWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 548:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PAVGWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(548)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PAVGWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 558:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMINSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(558)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMINSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 556:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMAXSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(556)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 569:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSLLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(569)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSLLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 581:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSRLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(581)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSRLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 574:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSRAWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(574)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSRAWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 551:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPEQWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(551)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PCMPEQWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 554:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPGTWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(554)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PCMPGTWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 540:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PACKSSDWrm:v8i16 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(540)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PACKSSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 728:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PABSWrm128:v8i16 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(728)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_115(N, X86::PABSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 736:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHADDWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(736)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PHADDWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 742:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHSUBWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(742)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PHSUBWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 740:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHSUBSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(740)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PHSUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 744:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMADDUBSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(744)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMADDUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 746:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PMULHRSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(746)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 754:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PSIGNWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(754)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PSIGNWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 627:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHMINPOSUWrm128:v8i16 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(627)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_115(N, X86::PHMINPOSUWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 620:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PACKUSDWrm:v8i16 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(620)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PACKUSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 635:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMINUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(635)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMINUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 631:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMAXUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(631)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 544:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PADDSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(544)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PADDSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 546:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PADDUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(546)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 562:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMULHUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(562)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMULHWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(561)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMULHWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 548:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PAVGWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(548)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PAVGWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 558:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMINSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(558)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMINSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 556:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMAXSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(556)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 746:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>), VR128:v8i16:$src1)
- // Emits: (PMULHRSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(746)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_117(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 635:iPTR, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMINUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(635)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMINUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 631:iPTR, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMAXUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(631)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, (bitconvert:v16i8 (X86vzload:v2i64 addr:iPTR:$src)))
- // Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(638)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_130(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 644:iPTR, (bitconvert:v16i8 (X86vzload:v2i64 addr:iPTR:$src)))
- // Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(644)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_130(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 572:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
- // Emits: (PSLLWri:v8i16 VR128:v8i16:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(572)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::PSLLWri, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 584:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
- // Emits: (PSRLWri:v8i16 VR128:v8i16:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(584)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::PSRLWri, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 576:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
- // Emits: (PSRAWri:v8i16 VR128:v8i16:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(576)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::PSRAWri, MVT::v8i16);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 622:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2, (imm:i32):$src3)
- // Emits: (PBLENDWrri:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2, (imm:i32):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(622)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_118(N, X86::PBLENDWrri, MVT::v8i16);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 544:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PADDSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(544)) {
- SDNode *Result = Emit_110(N, X86::PADDSWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 546:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PADDUSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(546)) {
- SDNode *Result = Emit_110(N, X86::PADDUSWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 586:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PSUBSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(586)) {
- SDNode *Result = Emit_110(N, X86::PSUBSWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 588:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PSUBUSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(588)) {
- SDNode *Result = Emit_110(N, X86::PSUBUSWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 562:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PMULHUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(562)) {
- SDNode *Result = Emit_110(N, X86::PMULHUWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PMULHWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(561)) {
- SDNode *Result = Emit_110(N, X86::PMULHWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 548:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PAVGWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(548)) {
- SDNode *Result = Emit_110(N, X86::PAVGWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 558:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PMINSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(558)) {
- SDNode *Result = Emit_110(N, X86::PMINSWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 556:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PMAXSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(556)) {
- SDNode *Result = Emit_110(N, X86::PMAXSWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 569:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PSLLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(569)) {
- SDNode *Result = Emit_110(N, X86::PSLLWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 581:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PSRLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(581)) {
- SDNode *Result = Emit_110(N, X86::PSRLWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 574:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PSRAWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(574)) {
- SDNode *Result = Emit_110(N, X86::PSRAWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 551:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PCMPEQWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(551)) {
- SDNode *Result = Emit_110(N, X86::PCMPEQWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 554:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PCMPGTWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(554)) {
- SDNode *Result = Emit_110(N, X86::PCMPGTWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 540:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PACKSSDWrr:v8i16 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(540)) {
- SDNode *Result = Emit_110(N, X86::PACKSSDWrr, MVT::v8i16);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 728:iPTR, VR128:v8i16:$src)
- // Emits: (PABSWrr128:v8i16 VR128:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(728)) {
- SDNode *Result = Emit_107(N, X86::PABSWrr128, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 736:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PHADDWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(736)) {
- SDNode *Result = Emit_110(N, X86::PHADDWrr128, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 742:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PHSUBWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(742)) {
- SDNode *Result = Emit_110(N, X86::PHSUBWrr128, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 740:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PHSUBSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(740)) {
- SDNode *Result = Emit_110(N, X86::PHSUBSWrr128, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 744:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PMADDUBSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(744)) {
- SDNode *Result = Emit_110(N, X86::PMADDUBSWrr128, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 746:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PMULHRSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(746)) {
- SDNode *Result = Emit_110(N, X86::PMULHRSWrr128, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 754:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PSIGNWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(754)) {
- SDNode *Result = Emit_110(N, X86::PSIGNWrr128, MVT::v8i16);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 627:iPTR, VR128:v8i16:$src)
- // Emits: (PHMINPOSUWrr128:v8i16 VR128:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(627)) {
- SDNode *Result = Emit_107(N, X86::PHMINPOSUWrr128, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 620:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PACKUSDWrr:v8i16 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(620)) {
- SDNode *Result = Emit_110(N, X86::PACKUSDWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 635:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PMINUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(635)) {
- SDNode *Result = Emit_110(N, X86::PMINUWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 631:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PMAXUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(631)) {
- SDNode *Result = Emit_110(N, X86::PMAXUWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, VR128:v16i8:$src)
- // Emits: (PMOVSXBWrr:v8i16 VR128:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(638)) {
- SDNode *Result = Emit_107(N, X86::PMOVSXBWrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 644:iPTR, VR128:v16i8:$src)
- // Emits: (PMOVZXBWrr:v8i16 VR128:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(644)) {
- SDNode *Result = Emit_107(N, X86::PMOVZXBWrr, MVT::v8i16);
- return Result;
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i32 725:iPTR, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PABSDrm64:v2i32 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(725)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_115(N, X86::PABSDrm64, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 731:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHADDDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(731)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_116(N, X86::PHADDDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 737:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHSUBDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(737)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_116(N, X86::PHSUBDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 751:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PSIGNDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(751)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_116(N, X86::PSIGNDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i32 477:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMULUDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(477)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 469:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMADDWDrm:v2i32 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(469)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 489:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSRLDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(489)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSRLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 479:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSLLDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(479)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSLLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 485:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSRADrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(485)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSRADrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 464:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPEQDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(464)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 467:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPGTDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(467)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PCMPGTDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 477:iPTR, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
- // Emits: (MMX_PMULUDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(477)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 469:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PMADDWDrm:v2i32 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(469)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i32 688:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTPS2PIrm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(688)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 694:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTTPS2PIrm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(694)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i32 685:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTPD2PIrm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(685)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 693:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTTPD2PIrm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(693)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i32 492:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
- // Emits: (MMX_PSRLDri:v2i32 VR64:v2i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(492)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::MMX_PSRLDri, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 482:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
- // Emits: (MMX_PSLLDri:v2i32 VR64:v2i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(482)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::MMX_PSLLDri, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 487:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
- // Emits: (MMX_PSRADri:v2i32 VR64:v2i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(487)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::MMX_PSRADri, MVT::v2i32);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i32 688:iPTR, VR128:v4f32:$src)
- // Emits: (Int_CVTPS2PIrr:v2i32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(688)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPS2PIrr, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 694:iPTR, VR128:v4f32:$src)
- // Emits: (Int_CVTTPS2PIrr:v2i32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(694)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTPS2PIrr, MVT::v2i32);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i32 685:iPTR, VR128:v2f64:$src)
- // Emits: (Int_CVTPD2PIrr:v2i32 VR128:v2f64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(685)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPD2PIrr, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 693:iPTR, VR128:v2f64:$src)
- // Emits: (Int_CVTTPD2PIrr:v2i32 VR128:v2f64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(693)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTPD2PIrr, MVT::v2i32);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i32 725:iPTR, VR64:v2i32:$src)
- // Emits: (PABSDrr64:v2i32 VR64:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(725)) {
- SDNode *Result = Emit_107(N, X86::PABSDrr64, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 731:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (PHADDDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(731)) {
- SDNode *Result = Emit_110(N, X86::PHADDDrr64, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 737:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (PHSUBDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(737)) {
- SDNode *Result = Emit_110(N, X86::PHSUBDrr64, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 751:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (PSIGNDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(751)) {
- SDNode *Result = Emit_110(N, X86::PSIGNDrr64, MVT::v2i32);
- return Result;
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i32 477:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (MMX_PMULUDQrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(477)) {
- SDNode *Result = Emit_110(N, X86::MMX_PMULUDQrr, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 469:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PMADDWDrr:v2i32 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(469)) {
- SDNode *Result = Emit_110(N, X86::MMX_PMADDWDrr, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 489:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PSRLDrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(489)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSRLDrr, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 479:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PSLLDrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(479)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSLLDrr, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 485:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PSRADrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(485)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSRADrr, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 464:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (MMX_PCMPEQDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(464)) {
- SDNode *Result = Emit_110(N, X86::MMX_PCMPEQDrr, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i32 467:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (MMX_PCMPGTDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(467)) {
- SDNode *Result = Emit_110(N, X86::MMX_PCMPGTDrr, MVT::v2i32);
- return Result;
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_131(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N2, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 640:iPTR, (bitconvert:v8i16 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
- // Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(640)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_load(N1000.getNode()) &&
- Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 646:iPTR, (bitconvert:v8i16 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
- // Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(646)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_load(N1000.getNode()) &&
- Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 636:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
- // Emits: (PMOVSXBDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(636)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 642:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
- // Emits: (PMOVZXBDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(642)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 640:iPTR, (bitconvert:v8i16 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
- // Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(640)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 646:iPTR, (bitconvert:v8i16 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
- // Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(646)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 636:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
- // Emits: (PMOVSXBDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(636)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 642:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
- // Emits: (PMOVZXBDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(642)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 555:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMADDWDrm:v4i32 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(555)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 565:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSLLDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(565)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSLLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 577:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSRLDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(577)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSRLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 573:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSRADrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(573)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSRADrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 550:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPEQDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(550)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PCMPEQDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 553:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPGTDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(553)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PCMPGTDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 726:iPTR, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PABSDrm128:v4i32 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(726)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_115(N, X86::PABSDrm128, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 732:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PHADDDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(732)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_116(N, X86::PHADDDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 734:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHADDSWrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(734)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PHADDSWrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 738:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PHSUBDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(738)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_116(N, X86::PHSUBDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 752:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSIGNDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(752)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_116(N, X86::PSIGNDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMINSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(633)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMINSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 634:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMINUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(634)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMINUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 629:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMAXSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(629)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 630:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMAXUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(630)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 555:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMADDWDrm:v4i32 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(555)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PMINSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(633)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMINSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 634:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PMINUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(634)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMINUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 629:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PMAXSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(629)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 630:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PMAXUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(630)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 640:iPTR, (bitconvert:v8i16 (X86vzload:v2i64 addr:iPTR:$src)))
- // Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(640)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_130(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 646:iPTR, (bitconvert:v8i16 (X86vzload:v2i64 addr:iPTR:$src)))
- // Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(646)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_130(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 513:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTPS2DQrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(513)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 522:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTTPS2DQrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(522)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 511:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTPD2DQrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(511)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 521:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTTPD2DQrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(521)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(649)) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PMULLDrm_int:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4i32:$src1)
- // Emits: (PMULLDrm_int:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_131(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 570:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
- // Emits: (PSLLDri:v4i32 VR128:v4i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(570)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::PSLLDri, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 582:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
- // Emits: (PSRLDri:v4i32 VR128:v4i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(582)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::PSRLDri, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 575:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
- // Emits: (PSRADri:v4i32 VR128:v4i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(575)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::PSRADri, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 513:iPTR, VR128:v4f32:$src)
- // Emits: (Int_CVTPS2DQrr:v4i32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(513)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPS2DQrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 522:iPTR, VR128:v4f32:$src)
- // Emits: (Int_CVTTPS2DQrr:v4i32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(522)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTPS2DQrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 511:iPTR, VR128:v2f64:$src)
- // Emits: (Int_CVTPD2DQrr:v4i32 VR128:v2f64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(511)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPD2DQrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 521:iPTR, VR128:v2f64:$src)
- // Emits: (Int_CVTTPD2DQrr:v4i32 VR128:v2f64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(521)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTTPD2DQrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 555:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PMADDWDrr:v4i32 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(555)) {
- SDNode *Result = Emit_110(N, X86::PMADDWDrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 565:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PSLLDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(565)) {
- SDNode *Result = Emit_110(N, X86::PSLLDrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 577:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PSRLDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(577)) {
- SDNode *Result = Emit_110(N, X86::PSRLDrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 573:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PSRADrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(573)) {
- SDNode *Result = Emit_110(N, X86::PSRADrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 550:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PCMPEQDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(550)) {
- SDNode *Result = Emit_110(N, X86::PCMPEQDrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 553:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PCMPGTDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(553)) {
- SDNode *Result = Emit_110(N, X86::PCMPGTDrr, MVT::v4i32);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 726:iPTR, VR128:v4i32:$src)
- // Emits: (PABSDrr128:v4i32 VR128:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(726)) {
- SDNode *Result = Emit_107(N, X86::PABSDrr128, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 732:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PHADDDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(732)) {
- SDNode *Result = Emit_110(N, X86::PHADDDrr128, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 734:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PHADDSWrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(734)) {
- SDNode *Result = Emit_110(N, X86::PHADDSWrr128, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 738:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PHSUBDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(738)) {
- SDNode *Result = Emit_110(N, X86::PHSUBDrr128, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 752:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PSIGNDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(752)) {
- SDNode *Result = Emit_110(N, X86::PSIGNDrr128, MVT::v4i32);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PMINSDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(633)) {
- SDNode *Result = Emit_110(N, X86::PMINSDrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 634:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PMINUDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(634)) {
- SDNode *Result = Emit_110(N, X86::PMINUDrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 629:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PMAXSDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(629)) {
- SDNode *Result = Emit_110(N, X86::PMAXSDrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 630:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PMAXUDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(630)) {
- SDNode *Result = Emit_110(N, X86::PMAXUDrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PMULLDrr_int:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(649)) {
- SDNode *Result = Emit_110(N, X86::PMULLDrr_int, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 640:iPTR, VR128:v8i16:$src)
- // Emits: (PMOVSXWDrr:v4i32 VR128:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(640)) {
- SDNode *Result = Emit_107(N, X86::PMOVSXWDrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 646:iPTR, VR128:v8i16:$src)
- // Emits: (PMOVZXWDrr:v4i32 VR128:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(646)) {
- SDNode *Result = Emit_107(N, X86::PMOVZXWDrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 636:iPTR, VR128:v16i8:$src)
- // Emits: (PMOVSXBDrr:v4i32 VR128:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(636)) {
- SDNode *Result = Emit_107(N, X86::PMOVSXBDrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 642:iPTR, VR128:v16i8:$src)
- // Emits: (PMOVZXBDrr:v4i32 VR128:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(642)) {
- SDNode *Result = Emit_107(N, X86::PMOVZXBDrr, MVT::v4i32);
- return Result;
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_132(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
- SDValue Tmp5 = Transform_BYTE_imm(Tmp4.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2, Tmp5);
-}
-DISABLE_INLINE SDNode *Emit_133(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Chain2 = N2.getNode()->getOperand(0);
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
- SDValue Tmp5 = Transform_BYTE_imm(Tmp4.getNode());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N2.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4, Tmp5, Chain2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(SDNode *N) {
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v1i64 490:iPTR, VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSRLQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(490)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSRLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 480:iPTR, VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSLLQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(480)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSLLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 729:iPTR, VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>, (imm:i8):$src3)
- // Emits: (PALIGNR64rm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2, (BYTE_imm:i8 (imm:i8):$src3))
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(729)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop64(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_133(N, X86::PALIGNR64rm, MVT::v1i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v1i64 493:iPTR, VR64:v1i64:$src1, (imm:i32):$src2)
- // Emits: (MMX_PSRLQri:v1i64 VR64:v1i64:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(493)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::MMX_PSRLQri, MVT::v1i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 483:iPTR, VR64:v1i64:$src1, (imm:i32):$src2)
- // Emits: (MMX_PSLLQri:v1i64 VR64:v1i64:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(483)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::MMX_PSLLQri, MVT::v1i64);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 729:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2, (imm:i8):$src3)
- // Emits: (PALIGNR64rr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2, (BYTE_imm:i8 (imm:i8):$src3))
- // Pattern complexity = 11 cost = 1 size = 3
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(729)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_132(N, X86::PALIGNR64rr, MVT::v1i64);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v1i64 490:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PSRLQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(490)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSRLQrr, MVT::v1i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v1i64 480:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PSLLQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(480)) {
- SDNode *Result = Emit_110(N, X86::MMX_PSLLQrr, MVT::v1i64);
- return Result;
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_134(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = Transform_BYTE_imm(Tmp3.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, Tmp4);
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i64 639:iPTR, (bitconvert:v4i32 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
- // Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(639)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_load(N1000.getNode()) &&
- Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 645:iPTR, (bitconvert:v4i32 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
- // Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(645)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_load(N1000.getNode()) &&
- Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 641:iPTR, (bitconvert:v8i16 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
- // Emits: (PMOVSXWQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(641)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 647:iPTR, (bitconvert:v8i16 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
- // Emits: (PMOVZXWQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(647)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 637:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
- // Emits: (PMOVSXBQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(637)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 643:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
- // Emits: (PMOVZXBQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(643)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 639:iPTR, (bitconvert:v4i32 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
- // Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(639)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 645:iPTR, (bitconvert:v4i32 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
- // Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(645)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 641:iPTR, (bitconvert:v8i16 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
- // Emits: (PMOVSXWQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(641)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 647:iPTR, (bitconvert:v8i16 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
- // Emits: (PMOVZXWQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(647)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 637:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16_anyext>>)))
- // Emits: (PMOVSXBQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(637)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16_anyext(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 643:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16_anyext>>)))
- // Emits: (PMOVZXBQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(643)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16_anyext(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i64 563:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMULUDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(563)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 564:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSADBWrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(564)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSADBWrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 568:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSLLQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(568)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSLLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 580:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSRLQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(580)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSRLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i64 623:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPEQQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(623)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMULDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(648)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMULDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 668:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPGTQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(668)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PCMPGTQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 730:iPTR, VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$src3)
- // Emits: (PALIGNR128rm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2, (BYTE_imm:i8 (imm:i8):$src3))
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(730)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_133(N, X86::PALIGNR128rm, MVT::v2i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i64 563:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PMULUDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(563)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 564:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PSADBWrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(564)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSADBWrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i64 623:iPTR, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v2i64:$src1)
- // Emits: (PCMPEQQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(623)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PMULDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(648)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMULDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 639:iPTR, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src)))
- // Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(639)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_130(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 645:iPTR, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src)))
- // Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(645)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_130(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i64 571:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
- // Emits: (PSLLQri:v2i64 VR128:v2i64:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(571)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::PSLLQri, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 583:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
- // Emits: (PSRLQri:v2i64 VR128:v2i64:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(583)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::PSRLQri, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 566:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
- // Emits: (PSLLDQri:v2i64 VR128:v16i8:$src1, (BYTE_imm:i32 (imm:i32):$src2))
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(566)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_134(N, X86::PSLLDQri, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 578:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
- // Emits: (PSRLDQri:v2i64 VR128:v16i8:$src1, (BYTE_imm:i32 (imm:i32):$src2))
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(578)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_134(N, X86::PSRLDQri, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 567:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
- // Emits: (PSLLDQri:v2i64 VR128:v16i8:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(567)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::PSLLDQri, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 579:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
- // Emits: (PSRLDQri:v2i64 VR128:v16i8:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(579)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::PSRLDQri, MVT::v2i64);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 730:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2, (imm:i8):$src3)
- // Emits: (PALIGNR128rr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (BYTE_imm:i8 (imm:i8):$src3))
- // Pattern complexity = 11 cost = 1 size = 3
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(730)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_132(N, X86::PALIGNR128rr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i64 563:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PMULUDQrr:v2i64 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(563)) {
- SDNode *Result = Emit_110(N, X86::PMULUDQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 564:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PSADBWrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(564)) {
- SDNode *Result = Emit_110(N, X86::PSADBWrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 568:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PSLLQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(568)) {
- SDNode *Result = Emit_110(N, X86::PSLLQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 580:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PSRLQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(580)) {
- SDNode *Result = Emit_110(N, X86::PSRLQrr, MVT::v2i64);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i64 623:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PCMPEQQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(623)) {
- SDNode *Result = Emit_110(N, X86::PCMPEQQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PMULDQrr:v2i64 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(648)) {
- SDNode *Result = Emit_110(N, X86::PMULDQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 639:iPTR, VR128:v4i32:$src)
- // Emits: (PMOVSXDQrr:v2i64 VR128:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(639)) {
- SDNode *Result = Emit_107(N, X86::PMOVSXDQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 645:iPTR, VR128:v4i32:$src)
- // Emits: (PMOVZXDQrr:v2i64 VR128:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(645)) {
- SDNode *Result = Emit_107(N, X86::PMOVZXDQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 641:iPTR, VR128:v8i16:$src)
- // Emits: (PMOVSXWQrr:v2i64 VR128:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(641)) {
- SDNode *Result = Emit_107(N, X86::PMOVSXWQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 647:iPTR, VR128:v8i16:$src)
- // Emits: (PMOVZXWQrr:v2i64 VR128:v8i16:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(647)) {
- SDNode *Result = Emit_107(N, X86::PMOVZXWQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 637:iPTR, VR128:v16i8:$src)
- // Emits: (PMOVSXBQrr:v2i64 VR128:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(637)) {
- SDNode *Result = Emit_107(N, X86::PMOVSXBQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 643:iPTR, VR128:v16i8:$src)
- // Emits: (PMOVZXBQrr:v2i64 VR128:v16i8:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(643)) {
- SDNode *Result = Emit_107(N, X86::PMOVZXBQrr, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 668:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PCMPGTQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(668)) {
- SDNode *Result = Emit_110(N, X86::PCMPGTQrr, MVT::v2i64);
- return Result;
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_135(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4, SDValue &Chain2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- ReplaceUses(SDValue(CPInChain.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_136(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4, SDValue &Chain1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- ReplaceUses(SDValue(CPInChain.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_137(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Tmp3, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_138(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4, SDValue &Chain2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
- SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp4, Chain2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- ReplaceUses(SDValue(CPInChain.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 611:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
- // Emits: (BLENDPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(611)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_119(N, X86::BLENDPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (CN1 == INT64_C(615)) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (intrinsic_wo_chain:v4f32 615:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
- // Emits: (DPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_119(N, X86::DPPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 615:iPTR, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4f32:$src1, (imm:i32):$src3)
- // Emits: (DPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_126(N, X86::DPPSrmi, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 678:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$cc)
- // Emits: (Int_CMPSSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src, (imm:i8):$cc)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(678)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::Int_CMPSSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 677:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
- // Emits: (CMPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src, (imm:i8):$cc)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(677)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::CMPPSrmi, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 510:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (Int_CVTDQ2PSrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(510)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::Int_CVTDQ2PSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 654:iPTR, (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i32):$src2)
- // Emits: (ROUNDPSm_Int:v4f32 addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(654)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_137(N, X86::ROUNDPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 613:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v4f32)
- // Emits: (BLENDVPSrm0:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(613)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_121(N, X86::BLENDVPSrm0, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 690:iPTR, VR128:v4f32:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (Int_CVTSI2SS64rm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(690)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_loadi64(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSI2SS64rm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 687:iPTR, VR128:v4f32:$src1, (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTPI2PSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(687)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTPI2PSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 689:iPTR, VR128:v4f32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (Int_CVTSI2SSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(689)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_loadi32(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSI2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 700:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MAXPSrm_Int:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(700)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::MAXPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 702:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MINPSrm_Int:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(702)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::MINPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 712:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (SQRTPSm_Int:v4f32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(712)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::SQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 709:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (RSQRTPSm_Int:v4f32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(709)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::RSQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 707:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (RCPPSm_Int:v4f32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(707)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::RCPPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 512:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTPD2PSrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(512)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPD2PSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 517:iPTR, VR128:v4f32:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTSD2SSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(517)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSD2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 602:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ADDSUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(602)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::ADDSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 604:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (HADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(604)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::HADDPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 606:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (HSUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(606)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::HSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 656:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2, (imm:i32):$src3)
- // Emits: (ROUNDSSm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2, (imm:i32):$src3)
- // Pattern complexity = 29 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(656)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_138(N, X86::ROUNDSSm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 676:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Emits: (ADDSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(676)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::ADDSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 706:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Emits: (MULSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(706)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::MULSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 716:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Emits: (SUBSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(716)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::SUBSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 697:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Emits: (DIVSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(697)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::DIVSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 701:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Emits: (MAXSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(701)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::MAXSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 703:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Emits: (MINSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(703)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::MINSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 713:iPTR, sse_load_f32:v4f32:$src)
- // Emits: (SQRTSSm_Int:v4f32 sse_load_f32:v4f32:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(713)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- SDValue CPInChain;
- SDValue Chain1;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_136(N, X86::SQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 710:iPTR, sse_load_f32:v4f32:$src)
- // Emits: (RSQRTSSm_Int:v4f32 sse_load_f32:v4f32:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(710)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- SDValue CPInChain;
- SDValue Chain1;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_136(N, X86::RSQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 708:iPTR, sse_load_f32:v4f32:$src)
- // Emits: (RCPSSm_Int:v4f32 sse_load_f32:v4f32:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(708)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- SDValue CPInChain;
- SDValue Chain1;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_136(N, X86::RCPSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 678:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
- // Emits: (Int_CMPSSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(678)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_122(N, X86::Int_CMPSSrr, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 677:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
- // Emits: (CMPPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(677)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_122(N, X86::CMPPSrri, MVT::v4f32);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 654:iPTR, VR128:v4f32:$src1, (imm:i32):$src2)
- // Emits: (ROUNDPSr_Int:v4f32 VR128:v4f32:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(654)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::ROUNDPSr_Int, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 656:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
- // Emits: (ROUNDSSr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(656)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_118(N, X86::ROUNDSSr_Int, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 611:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
- // Emits: (BLENDPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(611)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_118(N, X86::BLENDPSrri, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 615:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
- // Emits: (DPPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(615)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_118(N, X86::DPPSrri, MVT::v4f32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 617:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
- // Emits: (INSERTPSrr:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(617)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_118(N, X86::INSERTPSrr, MVT::v4f32);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 690:iPTR, VR128:v4f32:$src1, GR64:i64:$src2)
- // Emits: (Int_CVTSI2SS64rr:v4f32 VR128:v4f32:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(690)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTSI2SS64rr, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 687:iPTR, VR128:v4f32:$src1, VR64:v2i32:$src2)
- // Emits: (Int_CVTPI2PSrr:v4f32 VR128:v4f32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(687)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTPI2PSrr, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 689:iPTR, VR128:v4f32:$src1, GR32:i32:$src2)
- // Emits: (Int_CVTSI2SSrr:v4f32 VR128:v4f32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(689)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTSI2SSrr, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 676:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (ADDSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(676)) {
- SDNode *Result = Emit_110(N, X86::ADDSSrr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 706:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (MULSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(706)) {
- SDNode *Result = Emit_110(N, X86::MULSSrr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 716:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (SUBSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(716)) {
- SDNode *Result = Emit_110(N, X86::SUBSSrr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 697:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (DIVSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(697)) {
- SDNode *Result = Emit_110(N, X86::DIVSSrr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 701:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (MAXSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(701)) {
- SDNode *Result = Emit_110(N, X86::MAXSSrr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 700:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (MAXPSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(700)) {
- SDNode *Result = Emit_110(N, X86::MAXPSrr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 703:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (MINSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(703)) {
- SDNode *Result = Emit_110(N, X86::MINSSrr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 702:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (MINPSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(702)) {
- SDNode *Result = Emit_110(N, X86::MINPSrr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 713:iPTR, VR128:v4f32:$src)
- // Emits: (SQRTSSr_Int:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(713)) {
- SDNode *Result = Emit_107(N, X86::SQRTSSr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 712:iPTR, VR128:v4f32:$src)
- // Emits: (SQRTPSr_Int:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(712)) {
- SDNode *Result = Emit_107(N, X86::SQRTPSr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 710:iPTR, VR128:v4f32:$src)
- // Emits: (RSQRTSSr_Int:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(710)) {
- SDNode *Result = Emit_107(N, X86::RSQRTSSr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 709:iPTR, VR128:v4f32:$src)
- // Emits: (RSQRTPSr_Int:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(709)) {
- SDNode *Result = Emit_107(N, X86::RSQRTPSr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 708:iPTR, VR128:v4f32:$src)
- // Emits: (RCPSSr_Int:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(708)) {
- SDNode *Result = Emit_107(N, X86::RCPSSr_Int, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 707:iPTR, VR128:v4f32:$src)
- // Emits: (RCPPSr_Int:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(707)) {
- SDNode *Result = Emit_107(N, X86::RCPPSr_Int, MVT::v4f32);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 510:iPTR, VR128:v4i32:$src)
- // Emits: (Int_CVTDQ2PSrr:v4f32 VR128:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(510)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTDQ2PSrr, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 512:iPTR, VR128:v2f64:$src)
- // Emits: (Int_CVTPD2PSrr:v4f32 VR128:v2f64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(512)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPD2PSrr, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 517:iPTR, VR128:v4f32:$src1, VR128:v2f64:$src2)
- // Emits: (Int_CVTSD2SSrr:v4f32 VR128:v4f32:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(517)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTSD2SSrr, MVT::v4f32);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4f32 602:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (ADDSUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(602)) {
- SDNode *Result = Emit_110(N, X86::ADDSUBPSrr, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 604:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (HADDPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(604)) {
- SDNode *Result = Emit_110(N, X86::HADDPSrr, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 606:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (HSUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(606)) {
- SDNode *Result = Emit_110(N, X86::HSUBPSrr, MVT::v4f32);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 613:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, XMM0:v4f32)
- // Emits: (BLENDVPSrr0:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(613)) {
- SDNode *Result = Emit_120(N, X86::BLENDVPSrr0, MVT::v4f32);
- return Result;
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2f64 610:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
- // Emits: (BLENDPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(610)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_119(N, X86::BLENDPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (CN1 == INT64_C(614)) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (intrinsic_wo_chain:v2f64 614:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
- // Emits: (DPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_119(N, X86::DPPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 614:iPTR, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v2f64:$src1, (imm:i32):$src3)
- // Emits: (DPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_126(N, X86::DPPDrmi, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2f64 502:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$cc)
- // Emits: (Int_CMPSDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src, (imm:i8):$cc)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(502)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::Int_CMPSDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 509:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (Int_CVTDQ2PDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(509)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::Int_CVTDQ2PDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 501:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
- // Emits: (CMPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src, (imm:i8):$cc)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(501)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::CMPPDrmi, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2f64 653:iPTR, (ld:v2f64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i32):$src2)
- // Emits: (ROUNDPDm_Int:v2f64 addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(653)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_137(N, X86::ROUNDPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 612:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v2f64)
- // Emits: (BLENDVPDrm0:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(612)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_121(N, X86::BLENDVPDrm0, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2f64 519:iPTR, VR128:v2f64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (Int_CVTSI2SD64rm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(519)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_loadi64(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSI2SD64rm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 686:iPTR, (ld:v2i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTPI2PDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(686)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPI2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 530:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MAXPDrm_Int:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(530)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::MAXPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 533:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MINPDrm_Int:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(533)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::MINPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 514:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTPS2PDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(514)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPS2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 518:iPTR, VR128:v2f64:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (Int_CVTSI2SDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(518)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_loadi32(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSI2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 520:iPTR, VR128:v2f64:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTSS2SDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(520)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSS2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 589:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (SQRTPDm_Int:v2f64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(589)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::SQRTPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2f64 601:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ADDSUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(601)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::ADDSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 603:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (HADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(603)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::HADDPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 605:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (HSUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(605)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::HSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 655:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2, (imm:i32):$src3)
- // Emits: (ROUNDSDm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2, (imm:i32):$src3)
- // Pattern complexity = 29 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(655)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_138(N, X86::ROUNDSDm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2f64 499:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Emits: (ADDSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(499)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::ADDSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 539:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Emits: (MULSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(539)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::MULSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 594:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Emits: (SUBSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(594)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::SUBSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 525:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Emits: (DIVSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(525)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::DIVSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 531:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Emits: (MAXSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(531)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::MAXSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 534:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Emits: (MINSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(534)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::MINSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 590:iPTR, sse_load_f64:v2f64:$src)
- // Emits: (SQRTSDm_Int:v2f64 sse_load_f64:v2f64:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(590)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- SDValue CPInChain;
- SDValue Chain1;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_136(N, X86::SQRTSDm_Int, MVT::v2f64, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 502:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
- // Emits: (Int_CMPSDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(502)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_122(N, X86::Int_CMPSDrr, MVT::v2f64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 501:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
- // Emits: (CMPPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(501)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_122(N, X86::CMPPDrri, MVT::v2f64);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2f64 653:iPTR, VR128:v2f64:$src1, (imm:i32):$src2)
- // Emits: (ROUNDPDr_Int:v2f64 VR128:v2f64:$src1, (imm:i32):$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(653)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_127(N, X86::ROUNDPDr_Int, MVT::v2f64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 655:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
- // Emits: (ROUNDSDr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(655)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_118(N, X86::ROUNDSDr_Int, MVT::v2f64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 610:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
- // Emits: (BLENDPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(610)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_118(N, X86::BLENDPDrri, MVT::v2f64);
- return Result;
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 614:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
- // Emits: (DPPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
- // Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(614)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_118(N, X86::DPPDrri, MVT::v2f64);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2f64 519:iPTR, VR128:v2f64:$src1, GR64:i64:$src2)
- // Emits: (Int_CVTSI2SD64rr:v2f64 VR128:v2f64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(519)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTSI2SD64rr, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 686:iPTR, VR64:v2i32:$src)
- // Emits: (Int_CVTPI2PDrr:v2f64 VR64:v2i32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(686)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPI2PDrr, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 499:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (ADDSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(499)) {
- SDNode *Result = Emit_110(N, X86::ADDSDrr_Int, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 539:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (MULSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(539)) {
- SDNode *Result = Emit_110(N, X86::MULSDrr_Int, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 594:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (SUBSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(594)) {
- SDNode *Result = Emit_110(N, X86::SUBSDrr_Int, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 525:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (DIVSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(525)) {
- SDNode *Result = Emit_110(N, X86::DIVSDrr_Int, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 531:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (MAXSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(531)) {
- SDNode *Result = Emit_110(N, X86::MAXSDrr_Int, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 530:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (MAXPDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(530)) {
- SDNode *Result = Emit_110(N, X86::MAXPDrr_Int, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 534:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (MINSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(534)) {
- SDNode *Result = Emit_110(N, X86::MINSDrr_Int, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 533:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (MINPDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(533)) {
- SDNode *Result = Emit_110(N, X86::MINPDrr_Int, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 509:iPTR, VR128:v4i32:$src)
- // Emits: (Int_CVTDQ2PDrr:v2f64 VR128:v4i32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(509)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTDQ2PDrr, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 514:iPTR, VR128:v4f32:$src)
- // Emits: (Int_CVTPS2PDrr:v2f64 VR128:v4f32:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(514)) {
- SDNode *Result = Emit_107(N, X86::Int_CVTPS2PDrr, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 518:iPTR, VR128:v2f64:$src1, GR32:i32:$src2)
- // Emits: (Int_CVTSI2SDrr:v2f64 VR128:v2f64:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(518)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTSI2SDrr, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 520:iPTR, VR128:v2f64:$src1, VR128:v4f32:$src2)
- // Emits: (Int_CVTSS2SDrr:v2f64 VR128:v2f64:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(520)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTSS2SDrr, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 590:iPTR, VR128:v2f64:$src)
- // Emits: (SQRTSDr_Int:v2f64 VR128:v2f64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(590)) {
- SDNode *Result = Emit_107(N, X86::SQRTSDr_Int, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 589:iPTR, VR128:v2f64:$src)
- // Emits: (SQRTPDr_Int:v2f64 VR128:v2f64:$src)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(589)) {
- SDNode *Result = Emit_107(N, X86::SQRTPDr_Int, MVT::v2f64);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2f64 601:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (ADDSUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(601)) {
- SDNode *Result = Emit_110(N, X86::ADDSUBPDrr, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 603:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (HADDPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(603)) {
- SDNode *Result = Emit_110(N, X86::HADDPDrr, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 605:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (HSUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(605)) {
- SDNode *Result = Emit_110(N, X86::HSUBPDrr, MVT::v2f64);
- return Result;
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2f64 612:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, XMM0:v2f64)
- // Emits: (BLENDVPDrr0:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(612)) {
- SDNode *Result = Emit_120(N, X86::BLENDVPDrr0, MVT::v2f64);
- return Result;
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_139(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
-}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(SDNode *N) {
-
- // Pattern: (intrinsic_w_chain:v16i8 527:iPTR, addr:iPTR:$src)
- // Emits: (MOVDQUrm_Int:v16i8 addr:iPTR:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(527)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_139(N, X86::MOVDQUrm_Int, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (intrinsic_w_chain:v16i8 607:iPTR, addr:iPTR:$src)
- // Emits: (LDDQUrm:v16i8 addr:iPTR:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if ((Subtarget->hasSSE3())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(607)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_139(N, X86::LDDQUrm, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i64(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(618)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_139(N, X86::MOVNTDQArm, MVT::v2i64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(699)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_139(N, X86::MOVUPSrm_Int, MVT::v4f32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(528)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_139(N, X86::MOVUPDrm_Int, MVT::v2f64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
-
- CannotYetSelectIntrinsic(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_140(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_LOAD_i8(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>
- // Emits: (MOV8rm:i8 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_load(N) &&
- Predicate_loadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (MOV8rm:i8 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextload(N) &&
- Predicate_zextloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (MOV8rm:i8 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extload(N) &&
- Predicate_extloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_LOAD_i16(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>
- // Emits: (MOV16rm:i16 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_loadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOV16rm, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
- // Emits: (MOVSX16rm8:i16 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextload(N) &&
- Predicate_sextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVSX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- if (Predicate_zextload(N)) {
-
- // Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (MOVZX16rm8:i16 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (MOVZX16rm8:i16 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
- if (Predicate_extload(N)) {
-
- // Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (MOVZX16rm8:i16 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (MOVZX16rm8:i16 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_LOAD_i32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
- if (Predicate_load(N)) {
-
- // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_gsload>>
- // Emits: (GS_MOV32rm:i32 addr:iPTR:$src)
- // Pattern complexity = 27 cost = 1 size = 3
- if (Predicate_gsload(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::GS_MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_fsload>>
- // Emits: (FS_MOV32rm:i32 addr:iPTR:$src)
- // Pattern complexity = 27 cost = 1 size = 3
- if (Predicate_fsload(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::FS_MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>
- // Emits: (MOV32rm:i32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_loadi32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- if (Predicate_sextload(N)) {
-
- // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
- // Emits: (MOVSX32rm8:i32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVSX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (MOVSX32rm16:i32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVSX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
- if (Predicate_zextload(N)) {
-
- // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (MOVZX32rm16:i32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
- if (Predicate_extload(N)) {
-
- // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (MOVZX32rm16:i32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- // Pattern: (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (MOVSX32rm16:i32 addr:iPTR:$dst)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextload(N) &&
- Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVSX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (MOVZX32rm16:i32 addr:iPTR:$dst)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextload(N) &&
- Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (MOVZX32rm16:i32 addr:iPTR:$dst)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extload(N) &&
- Predicate_extloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_141(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp0 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
- Chain = SDValue(Tmp2.getNode(), 1);
- SDValue Tmp3 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
- MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops1[] = { Tmp0, Tmp2, Tmp3, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc1, VT1, MVT::Other, Ops1, 4);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
- return ResNode;
-}
-SDNode *Select_ISD_LOAD_i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
- if (Predicate_load(N)) {
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_gsload>>
- // Emits: (MOV64GSrm:i64 addr:iPTR:$src)
- // Pattern complexity = 27 cost = 1 size = 3
- if (Predicate_gsload(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOV64GSrm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_fsload>>
- // Emits: (MOV64FSrm:i64 addr:iPTR:$src)
- // Pattern complexity = 27 cost = 1 size = 3
- if (Predicate_fsload(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOV64FSrm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (MOV64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOV64rm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- if (Predicate_sextload(N)) {
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
- // Emits: (MOVSX64rm8:i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVSX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (MOVSX64rm16:i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVSX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>
- // Emits: (MOVSX64rm32:i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextloadi32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVSX64rm32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
- if (Predicate_zextload(N)) {
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
- // Emits: (MOVZX64rm8:i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (MOVZX64rm16:i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>
- // Emits: (MOVZX64rm32:i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX64rm32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
- // Emits: (MOVZX64rm8:i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
- if (Predicate_extload(N)) {
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
- // Emits: (MOVZX64rm8:i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi1(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
- // Emits: (MOVZX64rm8:i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi8(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (MOVZX64rm16:i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- // Pattern: (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
- // Emits: (MOVSX64rm16:i64 addr:iPTR:$dst)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextload(N) &&
- Predicate_sextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVSX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
- // Emits: (MOVZX64rm16:i64 addr:iPTR:$dst)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextload(N) &&
- Predicate_zextloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- if (Predicate_extload(N)) {
-
- // Pattern: (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
- // Emits: (MOVZX64rm16:i64 addr:iPTR:$dst)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>
- // Emits: (SUBREG_TO_REG:i64 0:i64, (MOV32rm:i32 addr:iPTR:$src), 4:i32)
- // Pattern complexity = 22 cost = 2 size = 3
- if (Predicate_extloadi32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOV32rm, TargetOpcode::SUBREG_TO_REG, MVT::i32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_LOAD_f32(SDNode *N) {
-
- // Pattern: (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>
- // Emits: (LD_Fp32m:f32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 0
- if ((!Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N) &&
- Predicate_loadf32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N)) {
-
- // Pattern: (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>
- // Emits: (MOVSSrm:f32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_loadf32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVSSrm, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
- // Emits: (FsMOVAPSrm:f32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedload(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::FsMOVAPSrm, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_142(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- SDValue Tmp1(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
- Chain = SDValue(Tmp1.getNode(), 1);
- MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
- MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
- SDNode *ResNode = CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp1);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
- ReplaceUses(SDValue(N, 1), Chain);
- return ResNode;
-}
-SDNode *Select_ISD_LOAD_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>
- // Emits: (LD_Fp64m:f64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_load(N) &&
- Predicate_loadf64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
- // Emits: (LD_Fp32m64:f64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_extload(N) &&
- Predicate_extloadf32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::LD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>
- // Emits: (MOVSDrm:f64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N) &&
- Predicate_loadf64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVSDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
- // Emits: (CVTSS2SDrm:f64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if ((Subtarget->hasSSE2()) && (OptForSize)) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_extload(N) &&
- Predicate_extloadf32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::CVTSS2SDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
- // Emits: (FsMOVAPDrm:f64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N) &&
- Predicate_alignedload(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::FsMOVAPDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- // Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
- // Emits: (CVTSS2SDrr:f64 (MOVSSrm:f32 addr:iPTR:$src))
- // Pattern complexity = 22 cost = 2 size = 6
- if ((Subtarget->hasSSE2()) && (!OptForSize)) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_extload(N) &&
- Predicate_extloadf32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_142(N, X86::MOVSSrm, X86::CVTSS2SDrr, MVT::f32, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_LOAD_f80(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N)) {
-
- // Pattern: (ld:f80 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf80>>
- // Emits: (LD_Fp80m:f80 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_load(N) &&
- Predicate_loadf80(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- if (Predicate_extload(N)) {
-
- // Pattern: (ld:f80 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>
- // Emits: (LD_Fp64m80:f80 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_extloadf64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::LD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:f80 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
- // Emits: (LD_Fp32m80:f80 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_extloadf32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::LD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_LOAD_v4i32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N)) {
-
- // Pattern: (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
- // Emits: (MOVAPSrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedload(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVAPSrm, MVT::v4i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (MOVUPSrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVUPSrm, MVT::v4i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_LOAD_v1i64(SDNode *N) {
- if ((Subtarget->hasMMX())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MMX_MOVQ64rm, MVT::v1i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_LOAD_v2i64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N)) {
-
- // Pattern: (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
- // Emits: (MOVAPSrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedload(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVAPSrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (MOVUPSrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVUPSrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_LOAD_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N)) {
-
- // Pattern: (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
- // Emits: (MOVAPSrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedload(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVAPSrm, MVT::v4f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (MOVUPSrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVUPSrm, MVT::v4f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_LOAD_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedload(N) &&
- Predicate_load(N)) {
-
- // Pattern: (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
- // Emits: (MOVAPDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedload(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVAPDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
-
- // Pattern: (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
- // Emits: (MOVUPDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_140(N, X86::MOVUPDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_143(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
-}
-SDNode *Select_ISD_MEMBARRIER(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (membarrier:isVoid 0:i8, 0:i8, 0:i8, 1:i8, 1:i8)
- // Emits: (SFENCE:isVoid)
- // Pattern complexity = 28 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(0)) {
- SDValue N3 = N->getOperand(3);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N3.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(0)) {
- SDValue N4 = N->getOperand(4);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N4.getNode());
- if (Tmp6) {
- int64_t CN7 = Tmp6->getSExtValue();
- if (CN7 == INT64_C(1)) {
- SDValue N5 = N->getOperand(5);
- ConstantSDNode *Tmp8 = dyn_cast<ConstantSDNode>(N5.getNode());
- if (Tmp8) {
- int64_t CN9 = Tmp8->getSExtValue();
- if (CN9 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_143(N, X86::SFENCE);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (membarrier:isVoid 1:i8, 0:i8, 0:i8, 0:i8, 1:i8)
- // Emits: (LFENCE:isVoid)
- // Pattern complexity = 28 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp2) {
- int64_t CN3 = Tmp2->getSExtValue();
- if (CN3 == INT64_C(0)) {
- SDValue N3 = N->getOperand(3);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N3.getNode());
- if (Tmp4) {
- int64_t CN5 = Tmp4->getSExtValue();
- if (CN5 == INT64_C(0)) {
- SDValue N4 = N->getOperand(4);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N4.getNode());
- if (Tmp6) {
- int64_t CN7 = Tmp6->getSExtValue();
- if (CN7 == INT64_C(0)) {
- SDValue N5 = N->getOperand(5);
- ConstantSDNode *Tmp8 = dyn_cast<ConstantSDNode>(N5.getNode());
- if (Tmp8) {
- int64_t CN9 = Tmp8->getSExtValue();
- if (CN9 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_143(N, X86::LFENCE);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDValue N4 = N->getOperand(4);
- if (N4.getNode()->getOpcode() == ISD::Constant) {
- SDValue N5 = N->getOperand(5);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N5.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (membarrier:isVoid (imm:i8):$ll, (imm:i8):$ls, (imm:i8):$sl, (imm:i8):$ss, 0:i8)
- // Emits: (NOOP:isVoid)
- // Pattern complexity = 20 cost = 1 size = 3
- if (CN1 == INT64_C(0) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_143(N, X86::NOOP);
- return Result;
- }
-
- // Pattern: (membarrier:isVoid (imm:i8):$ll, (imm:i8):$ls, (imm:i8):$sl, (imm:i8):$ss, 1:i8)
- // Emits: (MFENCE:isVoid)
- // Pattern complexity = 20 cost = 1 size = 3
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_143(N, X86::MFENCE);
- return Result;
- }
- }
- }
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_144(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::AL, N0, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i8, MVT::i32, N1, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_145(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain1, N->getDebugLoc(), X86::AL, N0, InFlag).getNode();
- Chain1 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i8, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 2));
- return ResNode;
-}
-SDNode *Select_ISD_MUL_i8(SDNode *N) {
-
- // Pattern: (mul:i8 AL:i8, (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (MUL8m:isVoid addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_145(N, X86::MUL8m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (mul:i8 AL:i8, GR8:i8:$src)
- // Emits: (MUL8r:isVoid GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_144(N, X86::MUL8r);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_146(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
- return ResNode;
-}
-SDNode *Select_ISD_MUL_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (mul:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (IMUL16rmi8:i16 addr:iPTR:$src1, (imm:i16):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_146(N, X86::IMUL16rmi8, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (mul:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16):$src2)
- // Emits: (IMUL16rmi:i16 addr:iPTR:$src1, (imm:i16):$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- SDNode *Result = Emit_146(N, X86::IMUL16rmi, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (mul:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (IMUL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::IMUL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (mul:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
- // Emits: (IMUL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::IMUL16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (mul:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (IMUL16rri8:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::IMUL16rri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (mul:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (IMUL16rri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::IMUL16rri, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (mul:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (IMUL16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::IMUL16rr, MVT::i16);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_147(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
- return ResNode;
-}
-SDNode *Select_ISD_MUL_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (mul:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (IMUL32rmi8:i32 addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_147(N, X86::IMUL32rmi8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (mul:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$src2)
- // Emits: (IMUL32rmi:i32 addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- SDNode *Result = Emit_147(N, X86::IMUL32rmi, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (mul:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (IMUL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::IMUL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (mul:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
- // Emits: (IMUL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::IMUL32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (mul:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (IMUL32rri8:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::IMUL32rri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (mul:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (IMUL32rri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::IMUL32rri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (mul:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (IMUL32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::IMUL32rr, MVT::i32);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_148(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
- return ResNode;
-}
-SDNode *Select_ISD_MUL_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (mul:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (IMUL64rmi8:i64 addr:iPTR:$src1, (imm:i64):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_148(N, X86::IMUL64rmi8, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (mul:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (IMUL64rmi32:i64 addr:iPTR:$src1, (imm:i64):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_148(N, X86::IMUL64rmi32, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (mul:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (IMUL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::IMUL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (mul:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
- // Emits: (IMUL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::IMUL64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: lea64addr:i64:$src
- // Emits: (LEA64r:i64 lea64addr:i64:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (mul:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (IMUL64rri8:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::IMUL64rri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (mul:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (IMUL64rri32:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::IMUL64rri32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (mul:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (IMUL64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::IMUL64rr, MVT::i64);
- return Result;
-}
-
-SDNode *Select_ISD_MUL_v16i8(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:v16i8 VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PMULLDrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PMULLDrm, MVT::v16i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (mul:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v16i8:$src1)
- // Emits: (PMULLDrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PMULLDrm, MVT::v16i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_MUL_v4i16(SDNode *N) {
- if ((Subtarget->hasMMX())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMULLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PMULLWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (mul:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PMULLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PMULLWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (mul:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PMULLWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PMULLWrr, MVT::v4i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_MUL_v8i16(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMULLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PMULLWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (mul:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMULLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_17(N, X86::PMULLWrm, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (mul:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PMULLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PMULLWrr, MVT::v8i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_MUL_v4i32(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDNode *Result = Emit_15(N, X86::PMULLDrr, MVT::v4i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_OR_i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (or:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (OR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::OR8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src1)
- // Emits: (OR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::OR8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (or:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (OR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_3(N, X86::OR8ri, MVT::i8);
- return Result;
- }
- }
-
- // Pattern: (or:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (OR8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::OR8rr, MVT::i8);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_149(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N0.getNode()->getDebugLoc(), X86::CL, N01, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N10, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_150(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getNode()->getDebugLoc(), X86::CX, N010, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N10, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_151(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N10, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_152(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getNode()->getDebugLoc(), X86::CL, N011, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N00, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_153(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N010.getNode()->getDebugLoc(), X86::CX, N0101, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N00, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_154(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N00, Tmp2);
-}
-SDNode *Select_ISD_OR_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (or:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (OR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::OR16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
- // Emits: (OR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::OR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (or:i16 (srl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)), (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))))
- // Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 23 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- if (N010 == N1101 &&
- N01.getValueType() == MVT::i8 &&
- N010.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8 &&
- N110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_150(N, X86::SHRD16rrCL, MVT::i16);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getNode()->getOperand(0);
-
- // Pattern: (or:i16 (shl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)), (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))))
- // Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 23 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- if (N010 == N1101 &&
- N01.getValueType() == MVT::i8 &&
- N010.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8 &&
- N110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_150(N, X86::SHLD16rrCL, MVT::i16);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i16 (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (srl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)))
- // Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 23 cost = 1 size = 3
- if (N010.getNode()->getOpcode() == ISD::SUB) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N0101 == N110 &&
- N01.getValueType() == MVT::i8 &&
- N010.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8 &&
- N110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_153(N, X86::SHRD16rrCL, MVT::i16);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
-
- // Pattern: (or:i16 (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (shl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)))
- // Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 23 cost = 1 size = 3
- if (N01.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::SUB) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N0101 == N110 &&
- N01.getValueType() == MVT::i8 &&
- N010.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8 &&
- N110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_153(N, X86::SHLD16rrCL, MVT::i16);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i16 (srl:i16 GR16:i16:$src1, CL:i8:$amt), (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)))
- // Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 17 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SUB) {
- SDValue N110 = N11.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N01 == N111 &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_149(N, X86::SHRD16rrCL, MVT::i16);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
-
- // Pattern: (or:i16 (shl:i16 GR16:i16:$src1, CL:i8:$amt), (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)))
- // Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 17 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SUB) {
- SDValue N110 = N11.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N01 == N111 &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_149(N, X86::SHLD16rrCL, MVT::i16);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i16 (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (srl:i16 GR16:i16:$src1, CL:i8:$amt))
- // Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 17 cost = 1 size = 3
- if (N01.getNode()->getOpcode() == ISD::SUB) {
- SDValue N010 = N01.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N011 == N11 &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHRD16rrCL, MVT::i16);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i16 (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (shl:i16 GR16:i16:$src1, CL:i8:$amt))
- // Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 17 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SUB) {
- SDValue N010 = N01.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N011 == N11 &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHLD16rrCL, MVT::i16);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i16 (srl:i16 GR16:i16:$src1, (imm:i8):$amt1), (shl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>
- // Emits: (SHRD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$amt1)
- // Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shrd(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_151(N, X86::SHRD16rri8, MVT::i16);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:i16 (shl:i16 GR16:i16:$src1, (imm:i8):$amt1), (srl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>
- // Emits: (SHLD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$amt1)
- // Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shld(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_151(N, X86::SHLD16rri8, MVT::i16);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:i16 (shl:i16 GR16:i16:$src2, (imm:i8):$amt2), (srl:i16 GR16:i16:$src1, (imm:i8):$amt1))<<P:Predicate_shrd>>
- // Emits: (SHRD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$amt1)
- // Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shrd(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_154(N, X86::SHRD16rri8, MVT::i16);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:i16 (srl:i16 GR16:i16:$src2, (imm:i8):$amt2), (shl:i16 GR16:i16:$src1, (imm:i8):$amt1))<<P:Predicate_shld>>
- // Emits: (SHLD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$amt1)
- // Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shld(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_154(N, X86::SHLD16rri8, MVT::i16);
- return Result;
- }
- }
- }
- }
- }
- if (Predicate_or_is_add(N)) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (or:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)<<P:Predicate_or_is_add>>
- // Emits: (ADD16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::ADD16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (or:i16 GR16:i16:$src1, (imm:i16):$src2)<<P:Predicate_or_is_add>>
- // Emits: (ADD16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 12 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::ADD16ri, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (or:i16 GR16:i16:$src1, GR16:i16:$src2)<<P:Predicate_or_is_add>>
- // Emits: (ADD16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::ADD16rr, MVT::i16);
- return Result;
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (or:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (OR16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::OR16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (or:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (OR16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::OR16ri, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (or:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (OR16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::OR16rr, MVT::i16);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_155(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N1100 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getNode()->getDebugLoc(), X86::ECX, N010, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N10, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_156(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N0100 = N010.getNode()->getOperand(0);
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N010.getNode()->getDebugLoc(), X86::ECX, N0101, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N00, InFlag);
-}
-SDNode *Select_ISD_OR_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (or:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (OR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::OR32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
- // Emits: (OR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::OR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (or:i32 (srl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)), (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))))
- // Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 23 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- if (N010 == N1101 &&
- N01.getValueType() == MVT::i8 &&
- N010.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8 &&
- N110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_155(N, X86::SHRD32rrCL, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getNode()->getOperand(0);
-
- // Pattern: (or:i32 (shl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)), (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))))
- // Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 23 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1100 = N110.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- if (N010 == N1101 &&
- N01.getValueType() == MVT::i8 &&
- N010.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8 &&
- N110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_155(N, X86::SHLD32rrCL, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (srl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)))
- // Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 23 cost = 1 size = 3
- if (N010.getNode()->getOpcode() == ISD::SUB) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N0101 == N110 &&
- N01.getValueType() == MVT::i8 &&
- N010.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8 &&
- N110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_156(N, X86::SHRD32rrCL, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
-
- // Pattern: (or:i32 (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (shl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)))
- // Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 23 cost = 1 size = 3
- if (N01.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::SUB) {
- SDValue N0100 = N010.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N0101 == N110 &&
- N01.getValueType() == MVT::i8 &&
- N010.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8 &&
- N110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_156(N, X86::SHLD32rrCL, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (srl:i32 GR32:i32:$src1, CL:i8:$amt), (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)))
- // Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 17 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SUB) {
- SDValue N110 = N11.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N01 == N111 &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_149(N, X86::SHRD32rrCL, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
-
- // Pattern: (or:i32 (shl:i32 GR32:i32:$src1, CL:i8:$amt), (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)))
- // Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 17 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SUB) {
- SDValue N110 = N11.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N01 == N111 &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_149(N, X86::SHLD32rrCL, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (srl:i32 GR32:i32:$src1, CL:i8:$amt))
- // Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 17 cost = 1 size = 3
- if (N01.getNode()->getOpcode() == ISD::SUB) {
- SDValue N010 = N01.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N011 == N11 &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHRD32rrCL, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (shl:i32 GR32:i32:$src1, CL:i8:$amt))
- // Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 17 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SUB) {
- SDValue N010 = N01.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N011 == N11 &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHLD32rrCL, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (srl:i32 GR32:i32:$src1, (imm:i8):$amt1), (shl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>
- // Emits: (SHRD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$amt1)
- // Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shrd(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_151(N, X86::SHRD32rri8, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (shl:i32 GR32:i32:$src1, (imm:i8):$amt1), (srl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>
- // Emits: (SHLD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$amt1)
- // Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shld(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_151(N, X86::SHLD32rri8, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (shl:i32 GR32:i32:$src2, (imm:i8):$amt2), (srl:i32 GR32:i32:$src1, (imm:i8):$amt1))<<P:Predicate_shrd>>
- // Emits: (SHRD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$amt1)
- // Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shrd(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_154(N, X86::SHRD32rri8, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:i32 (srl:i32 GR32:i32:$src2, (imm:i8):$amt2), (shl:i32 GR32:i32:$src1, (imm:i8):$amt1))<<P:Predicate_shld>>
- // Emits: (SHLD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$amt1)
- // Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shld(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_154(N, X86::SHLD32rri8, MVT::i32);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
- if (Predicate_or_is_add(N)) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (or:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)<<P:Predicate_or_is_add>>
- // Emits: (ADD32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::ADD32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (or:i32 GR32:i32:$src1, (imm:i32):$src2)<<P:Predicate_or_is_add>>
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 12 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (or:i32 GR32:i32:$src1, GR32:i32:$src2)<<P:Predicate_or_is_add>>
- // Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::ADD32rr, MVT::i32);
- return Result;
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (or:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (OR32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::OR32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (or:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (OR32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::OR32ri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (or:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (OR32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::OR32rr, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_OR_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (or:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (OR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::OR64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
- // Emits: (OR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::OR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:i64 (srl:i64 GR64:i64:$src1, (imm:i8):$amt1), (shl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>
- // Emits: (SHRD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$amt1)
- // Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shrd(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_151(N, X86::SHRD64rri8, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:i64 (shl:i64 GR64:i64:$src1, (imm:i8):$amt1), (srl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>
- // Emits: (SHLD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$amt1)
- // Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shld(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_151(N, X86::SHLD64rri8, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:i64 (shl:i64 GR64:i64:$src2, (imm:i8):$amt2), (srl:i64 GR64:i64:$src1, (imm:i8):$amt1))<<P:Predicate_shrd>>
- // Emits: (SHRD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$amt1)
- // Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shrd(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_154(N, X86::SHRD64rri8, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:i64 (srl:i64 GR64:i64:$src2, (imm:i8):$amt2), (shl:i64 GR64:i64:$src1, (imm:i8):$amt1))<<P:Predicate_shld>>
- // Emits: (SHLD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$amt1)
- // Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shld(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_154(N, X86::SHLD64rri8, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: lea64addr:i64:$src
- // Emits: (LEA64r:i64 lea64addr:i64:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
- if (Predicate_or_is_add(N)) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (or:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)<<P:Predicate_or_is_add>>
- // Emits: (ADD64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::ADD64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (or:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)<<P:Predicate_or_is_add>>
- // Emits: (ADD64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 13 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::ADD64ri32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (or:i64 GR64:i64:$src1, GR64:i64:$src2)<<P:Predicate_or_is_add>>
- // Emits: (ADD64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::ADD64rr, MVT::i64);
- return Result;
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (or:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (OR64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::OR64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (or:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (OR64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::OR64ri32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (or:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (OR64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::OR64rr, MVT::i64);
- return Result;
-}
-
-SDNode *Select_ISD_OR_v1i64(SDNode *N) {
- if ((Subtarget->hasMMX())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (or:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MMX_PORrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
- // Emits: (MMX_PORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MMX_PORrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PORrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PORrr, MVT::v1i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_OR_v2i64(SDNode *N) {
-
- // Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_57(N, X86::ORPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_57(N, X86::ORPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v4f32:$src1))
- // Emits: (ORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_62(N, X86::ORPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
- // Emits: (ORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_62(N, X86::ORPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PORrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
- // Emits: (PORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PORrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (bitconvert:v2i64 VR128:v2f64:$src2))
- // Emits: (ORPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N00.getValueType() == MVT::v2f64 &&
- N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_59(N, X86::ORPDrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (ORPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_15(N, X86::ORPSrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (or:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PORrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDNode *Result = Emit_15(N, X86::PORrr, MVT::v2i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_157(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
-}
-SDNode *Select_ISD_PREFETCH(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDValue N3 = N->getOperand(3);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N3.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (prefetch:isVoid addr:iPTR:$src, (imm:i32), 3:i32)
- // Emits: (PREFETCHT0:isVoid addr:iPTR:$src)
- // Pattern complexity = 29 cost = 1 size = 3
- if (CN1 == INT64_C(3) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_157(N, X86::PREFETCHT0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
-
- // Pattern: (prefetch:isVoid addr:iPTR:$src, (imm:i32), 2:i32)
- // Emits: (PREFETCHT1:isVoid addr:iPTR:$src)
- // Pattern complexity = 29 cost = 1 size = 3
- if (CN1 == INT64_C(2) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_157(N, X86::PREFETCHT1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
-
- // Pattern: (prefetch:isVoid addr:iPTR:$src, (imm:i32), 1:i32)
- // Emits: (PREFETCHT2:isVoid addr:iPTR:$src)
- // Pattern complexity = 29 cost = 1 size = 3
- if (CN1 == INT64_C(1) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_157(N, X86::PREFETCHT2, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
-
- // Pattern: (prefetch:isVoid addr:iPTR:$src, (imm:i32), 0:i32)
- // Emits: (PREFETCHNTA:isVoid addr:iPTR:$src)
- // Pattern complexity = 29 cost = 1 size = 3
- if (CN1 == INT64_C(0) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_157(N, X86::PREFETCHNTA, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_158(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::CL, N1, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_159(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
-}
-SDNode *Select_ISD_ROTL_i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (rotl:i8 GR8:i8:$src1, 1:i8)
- // Emits: (ROL8r1:i8 GR8:i8:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::ROL8r1, MVT::i8);
- return Result;
- }
- }
- }
-
- // Pattern: (rotl:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (ROL8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROL8ri, MVT::i8);
- return Result;
- }
-
- // Pattern: (rotl:i8 GR8:i8:$src, CL:i8)
- // Emits: (ROL8rCL:i8 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROL8rCL, MVT::i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ROTL_i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (rotl:i16 GR16:i16:$src1, 1:i8)
- // Emits: (ROL16r1:i16 GR16:i16:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::ROL16r1, MVT::i16);
- return Result;
- }
- }
- }
-
- // Pattern: (rotl:i16 GR16:i16:$src1, (imm:i8):$src2)
- // Emits: (ROL16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROL16ri, MVT::i16);
- return Result;
- }
-
- // Pattern: (rotl:i16 GR16:i16:$src, CL:i8)
- // Emits: (ROL16rCL:i16 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROL16rCL, MVT::i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ROTL_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (rotl:i32 GR32:i32:$src1, 1:i8)
- // Emits: (ROL32r1:i32 GR32:i32:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::ROL32r1, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (rotl:i32 GR32:i32:$src1, (imm:i8):$src2)
- // Emits: (ROL32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROL32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (rotl:i32 GR32:i32:$src, CL:i8)
- // Emits: (ROL32rCL:i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROL32rCL, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ROTL_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (rotl:i64 GR64:i64:$src1, 1:i8)
- // Emits: (ROL64r1:i64 GR64:i64:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::ROL64r1, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (rotl:i64 GR64:i64:$src1, (imm:i8):$src2)
- // Emits: (ROL64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROL64ri, MVT::i64);
- return Result;
- }
-
- // Pattern: (rotl:i64 GR64:i64:$src, CL:i8)
- // Emits: (ROL64rCL:i64 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROL64rCL, MVT::i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ROTR_i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (rotr:i8 GR8:i8:$src1, 1:i8)
- // Emits: (ROR8r1:i8 GR8:i8:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::ROR8r1, MVT::i8);
- return Result;
- }
- }
- }
-
- // Pattern: (rotr:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (ROR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROR8ri, MVT::i8);
- return Result;
- }
-
- // Pattern: (rotr:i8 GR8:i8:$src, CL:i8)
- // Emits: (ROR8rCL:i8 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROR8rCL, MVT::i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ROTR_i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (rotr:i16 GR16:i16:$src1, 1:i8)
- // Emits: (ROR16r1:i16 GR16:i16:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::ROR16r1, MVT::i16);
- return Result;
- }
- }
- }
-
- // Pattern: (rotr:i16 GR16:i16:$src1, (imm:i8):$src2)
- // Emits: (ROR16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROR16ri, MVT::i16);
- return Result;
- }
-
- // Pattern: (rotr:i16 GR16:i16:$src, CL:i8)
- // Emits: (ROR16rCL:i16 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROR16rCL, MVT::i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ROTR_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (rotr:i32 GR32:i32:$src1, 1:i8)
- // Emits: (ROR32r1:i32 GR32:i32:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::ROR32r1, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (rotr:i32 GR32:i32:$src1, (imm:i8):$src2)
- // Emits: (ROR32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROR32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (rotr:i32 GR32:i32:$src, CL:i8)
- // Emits: (ROR32rCL:i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROR32rCL, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ROTR_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (rotr:i64 GR64:i64:$src1, 1:i8)
- // Emits: (ROR64r1:i64 GR64:i64:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::ROR64r1, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (rotr:i64 GR64:i64:$src1, (imm:i8):$src2)
- // Emits: (ROR64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::ROR64ri, MVT::i64);
- return Result;
- }
-
- // Pattern: (rotr:i64 GR64:i64:$src, CL:i8)
- // Emits: (ROR64rCL:i64 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::ROR64rCL, MVT::i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(SDNode *N) {
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (MMX_MOVD64rm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_79(N, X86::MMX_MOVD64rm, MVT::v2i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (scalar_to_vector:v2i32 GR32:i32:$src)
- // Emits: (MMX_MOVD64rr:v2i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVD64rr, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (MOVDI2PDIrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_79(N, X86::MOVDI2PDIrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (scalar_to_vector:v4i32 GR32:i32:$src)
- // Emits: (MOVDI2PDIrr:v4i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_72(N, X86::MOVDI2PDIrr, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v1i64(SDNode *N) {
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_72(N, X86::MMX_MOVD64rrv164, MVT::v1i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_160(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N00);
-}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(SDNode *N) {
-
- // Pattern: (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (MOVQI2PQIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_79(N, X86::MOVQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N0.getValueType() == MVT::i64) {
-
- // Pattern: (scalar_to_vector:v2i64 (bitconvert:i64 VR64:v8i8:$src))
- // Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N00.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (scalar_to_vector:v2i64 (bitconvert:i64 VR64:v4i16:$src))
- // Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N00.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (scalar_to_vector:v2i64 (bitconvert:i64 VR64:v2i32:$src))
- // Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N00.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (scalar_to_vector:v2i64 (bitconvert:i64 VR64:v1i64:$src))
- // Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (scalar_to_vector:v2i64 GR64:i64:$src)
- // Emits: (MOV64toPQIrr:v2i64 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_72(N, X86::MOV64toPQIrr, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (MOVSS2PSrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_79(N, X86::MOVSS2PSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (scalar_to_vector:v4f32 FR32:f32:$src)
- // Emits: (MOVSS2PSrr:v4f32 FR32:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_72(N, X86::MOVSS2PSrr, MVT::v4f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (MOVSD2PDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_79(N, X86::MOVSD2PDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (scalar_to_vector:v2f64 FR64:f64:$src)
- // Emits: (MOVSD2PDrr:v2f64 FR64:f64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_72(N, X86::MOVSD2PDrr, MVT::v2f64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_161(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N0);
-}
-DISABLE_INLINE SDNode *Emit_162(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N1.getNode()->getDebugLoc(), X86::CL, N10, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, InFlag);
-}
-SDNode *Select_ISD_SHL_i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (shl:i8 GR8:i8:$src1, (and:i8 CL:i8:$amt, 31:i8))
- // Emits: (SHL8rCL:i8 GR8:i8:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(31)) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHL8rCL, MVT::i8);
- return Result;
- }
- }
-
- // Pattern: (shl:i8 GR8:i8:$src1, 1:i8)
- // Emits: (ADD8rr:i8 GR8:i8:$src1, GR8:i8:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ADD8rr, MVT::i8);
- return Result;
- }
- }
- }
-
- // Pattern: (shl:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (SHL8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHL8ri, MVT::i8);
- return Result;
- }
-
- // Pattern: (shl:i8 GR8:i8:$src, CL:i8)
- // Emits: (SHL8rCL:i8 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHL8rCL, MVT::i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SHL_i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (shl:i16 GR16:i16:$src1, (and:i8 CL:i8:$amt, 31:i8))
- // Emits: (SHL16rCL:i16 GR16:i16:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(31)) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHL16rCL, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (shl:i16 GR16:i16:$src1, 1:i8)
- // Emits: (ADD16rr:i16 GR16:i16:$src1, GR16:i16:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ADD16rr, MVT::i16);
- return Result;
- }
- }
- }
-
- // Pattern: (shl:i16 GR16:i16:$src1, (imm:i8):$src2)
- // Emits: (SHL16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHL16ri, MVT::i16);
- return Result;
- }
-
- // Pattern: (shl:i16 GR16:i16:$src, CL:i8)
- // Emits: (SHL16rCL:i16 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHL16rCL, MVT::i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SHL_i32(SDNode *N) {
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (shl:i32 GR32:i32:$src1, (and:i8 CL:i8:$amt, 31:i8))
- // Emits: (SHL32rCL:i32 GR32:i32:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(31)) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHL32rCL, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (shl:i32 GR32:i32:$src1, 1:i8)
- // Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ADD32rr, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (shl:i32 GR32:i32:$src1, (imm:i8):$src2)
- // Emits: (SHL32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHL32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (shl:i32 GR32:i32:$src, CL:i8)
- // Emits: (SHL32rCL:i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHL32rCL, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SHL_i64(SDNode *N) {
-
- // Pattern: lea64addr:i64:$src
- // Emits: (LEA64r:i64 lea64addr:i64:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (shl:i64 GR64:i64:$src1, (and:i8 CL:i8:$amt, 63:i8))
- // Emits: (SHL64rCL:i64 GR64:i64:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(63)) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHL64rCL, MVT::i64);
- return Result;
- }
- }
-
- // Pattern: (shl:i64 GR64:i64:$src1, 1:i8)
- // Emits: (ADD64rr:i64 GR64:i64:$src1, GR64:i64:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ADD64rr, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (shl:i64 GR64:i64:$src1, (imm:i8):$src2)
- // Emits: (SHL64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHL64ri, MVT::i64);
- return Result;
- }
-
- // Pattern: (shl:i64 GR64:i64:$src, CL:i8)
- // Emits: (SHL64rCL:i64 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHL64rCL, MVT::i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SIGN_EXTEND_i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_72(N, X86::MOVSX16rr8, MVT::i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SIGN_EXTEND_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (sext:i32 GR8:i8:$src)
- // Emits: (MOVSX32rr8:i32 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_72(N, X86::MOVSX32rr8, MVT::i32);
- return Result;
- }
-
- // Pattern: (sext:i32 GR16:i16:$src)
- // Emits: (MOVSX32rr16:i32 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_72(N, X86::MOVSX32rr16, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SIGN_EXTEND_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (sext:i64 GR8:i8:$src)
- // Emits: (MOVSX64rr8:i64 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_72(N, X86::MOVSX64rr8, MVT::i64);
- return Result;
- }
-
- // Pattern: (sext:i64 GR16:i16:$src)
- // Emits: (MOVSX64rr16:i64 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_72(N, X86::MOVSX64rr16, MVT::i64);
- return Result;
- }
-
- // Pattern: (sext:i64 GR32:i32:$src)
- // Emits: (MOVSX64rr32:i64 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_72(N, X86::MOVSX64rr32, MVT::i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_163(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
- SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp4(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp2, Tmp3), 0);
- return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp4);
-}
-DISABLE_INLINE SDNode *Emit_164(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2);
-}
-SDNode *Select_ISD_SIGN_EXTEND_INREG_i16(SDNode *N) {
-
- // Pattern: (sext_inreg:i16 GR16:i16:$src, i8:Other)
- // Emits: (MOVSX16rr8:i16 (EXTRACT_SUBREG:i8 GR16:i16:$src, 1:i32))
- // Pattern complexity = 3 cost = 2 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_164(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i8, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (sext_inreg:i16 GR16:i16:$src, i8:Other)
- // Emits: (MOVSX16rr8:i16 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 1:i32))
- // Pattern complexity = 3 cost = 3 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_163(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i16, MVT::i8, MVT::i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_165(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_166(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
- SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp4(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp2, Tmp3), 0);
- return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp4);
-}
-SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(SDNode *N) {
-
- // Pattern: (sext_inreg:i32 GR32:i32:$src, i16:Other)
- // Emits: (MOVSX32rr16:i32 (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32))
- // Pattern complexity = 3 cost = 2 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_165(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX32rr16, MVT::i16, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (sext_inreg:i32 GR32:i32:$src, i8:Other)
- // Emits: (MOVSX32rr8:i32 (EXTRACT_SUBREG:i8 GR32:i32:$src, 1:i32))
- // Pattern complexity = 3 cost = 2 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_164(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i8, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (sext_inreg:i32 GR32:i32:$src, i8:Other)
- // Emits: (MOVSX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 1:i32))
- // Pattern complexity = 3 cost = 3 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_166(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i32, MVT::i8, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_167(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2);
-}
-SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sext_inreg:i64 GR64:i64:$src, i32:Other)
- // Emits: (MOVSX64rr32:i64 (EXTRACT_SUBREG:i32 GR64:i64:$src, 4:i32))
- // Pattern complexity = 3 cost = 2 size = 3
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_167(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX64rr32, MVT::i32, MVT::i64);
- return Result;
- }
-
- // Pattern: (sext_inreg:i64 GR64:i64:$src, i16:Other)
- // Emits: (MOVSX64rr16:i64 (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
- // Pattern complexity = 3 cost = 2 size = 3
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_165(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX64rr16, MVT::i16, MVT::i64);
- return Result;
- }
-
- // Pattern: (sext_inreg:i64 GR64:i64:$src, i8:Other)
- // Emits: (MOVSX64rr8:i64 (EXTRACT_SUBREG:i8 GR64:i64:$src, 1:i32))
- // Pattern complexity = 3 cost = 2 size = 3
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_164(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX64rr8, MVT::i8, MVT::i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SINT_TO_FP_f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode())) {
-
- // Pattern: (sint_to_fp:f32 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (CVTSI2SS64rm:f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_79(N, X86::CVTSI2SS64rm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
-
- // Pattern: (sint_to_fp:f32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (CVTSI2SSrm:f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_79(N, X86::CVTSI2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (sint_to_fp:f32 GR64:i64:$src)
- // Emits: (CVTSI2SS64rr:f32 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_72(N, X86::CVTSI2SS64rr, MVT::f32);
- return Result;
- }
-
- // Pattern: (sint_to_fp:f32 GR32:i32:$src)
- // Emits: (CVTSI2SSrr:f32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_72(N, X86::CVTSI2SSrr, MVT::f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SINT_TO_FP_f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode())) {
-
- // Pattern: (sint_to_fp:f64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (CVTSI2SD64rm:f64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_79(N, X86::CVTSI2SD64rm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
-
- // Pattern: (sint_to_fp:f64 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (CVTSI2SDrm:f64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_79(N, X86::CVTSI2SDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (sint_to_fp:f64 GR64:i64:$src)
- // Emits: (CVTSI2SD64rr:f64 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_72(N, X86::CVTSI2SD64rr, MVT::f64);
- return Result;
- }
-
- // Pattern: (sint_to_fp:f64 GR32:i32:$src)
- // Emits: (CVTSI2SDrr:f64 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_72(N, X86::CVTSI2SDrr, MVT::f64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SINT_TO_FP_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_72(N, X86::Int_CVTDQ2PSrr, MVT::v4f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SINT_TO_FP_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_72(N, X86::Int_CVTPI2PDrr, MVT::v2f64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRA_i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sra:i8 GR8:i8:$src1, (and:i8 CL:i8:$amt, 31:i8))
- // Emits: (SAR8rCL:i8 GR8:i8:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(31)) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SAR8rCL, MVT::i8);
- return Result;
- }
- }
-
- // Pattern: (sra:i8 GR8:i8:$src1, 1:i8)
- // Emits: (SAR8r1:i8 GR8:i8:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::SAR8r1, MVT::i8);
- return Result;
- }
- }
- }
-
- // Pattern: (sra:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (SAR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SAR8ri, MVT::i8);
- return Result;
- }
-
- // Pattern: (sra:i8 GR8:i8:$src, CL:i8)
- // Emits: (SAR8rCL:i8 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SAR8rCL, MVT::i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRA_i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sra:i16 GR16:i16:$src1, (and:i8 CL:i8:$amt, 31:i8))
- // Emits: (SAR16rCL:i16 GR16:i16:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(31)) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SAR16rCL, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (sra:i16 GR16:i16:$src1, 1:i8)
- // Emits: (SAR16r1:i16 GR16:i16:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::SAR16r1, MVT::i16);
- return Result;
- }
- }
- }
-
- // Pattern: (sra:i16 GR16:i16:$src1, (imm:i8):$src2)
- // Emits: (SAR16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SAR16ri, MVT::i16);
- return Result;
- }
-
- // Pattern: (sra:i16 GR16:i16:$src, CL:i8)
- // Emits: (SAR16rCL:i16 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SAR16rCL, MVT::i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRA_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sra:i32 GR32:i32:$src1, (and:i8 CL:i8:$amt, 31:i8))
- // Emits: (SAR32rCL:i32 GR32:i32:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(31)) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SAR32rCL, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (sra:i32 GR32:i32:$src1, 1:i8)
- // Emits: (SAR32r1:i32 GR32:i32:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::SAR32r1, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (sra:i32 GR32:i32:$src1, (imm:i8):$src2)
- // Emits: (SAR32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SAR32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (sra:i32 GR32:i32:$src, CL:i8)
- // Emits: (SAR32rCL:i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SAR32rCL, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRA_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sra:i64 GR64:i64:$src1, (and:i8 CL:i8:$amt, 63:i8))
- // Emits: (SAR64rCL:i64 GR64:i64:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(63)) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SAR64rCL, MVT::i64);
- return Result;
- }
- }
-
- // Pattern: (sra:i64 GR64:i64:$src1, 1:i8)
- // Emits: (SAR64r1:i64 GR64:i64:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::SAR64r1, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (sra:i64 GR64:i64:$src1, (imm:i8):$src2)
- // Emits: (SAR64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SAR64ri, MVT::i64);
- return Result;
- }
-
- // Pattern: (sra:i64 GR64:i64:$src, CL:i8)
- // Emits: (SAR64rCL:i64 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SAR64rCL, MVT::i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRL_i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (srl:i8 GR8:i8:$src1, (and:i8 CL:i8:$amt, 31:i8))
- // Emits: (SHR8rCL:i8 GR8:i8:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(31)) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHR8rCL, MVT::i8);
- return Result;
- }
- }
-
- // Pattern: (srl:i8 GR8:i8:$src1, 1:i8)
- // Emits: (SHR8r1:i8 GR8:i8:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::SHR8r1, MVT::i8);
- return Result;
- }
- }
- }
-
- // Pattern: (srl:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (SHR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHR8ri, MVT::i8);
- return Result;
- }
-
- // Pattern: (srl:i8 GR8:i8:$src, CL:i8)
- // Emits: (SHR8rCL:i8 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHR8rCL, MVT::i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_168(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp3), 0);
- SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp6(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp4, Tmp5), 0);
- SDValue Tmp7(CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Tmp6), 0);
- SDValue Tmp8 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc3, VT3, Tmp7, Tmp8);
-}
-SDNode *Select_ISD_SRL_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (srl:i16 GR16:i16:$src1, (and:i8 CL:i8:$amt, 31:i8))
- // Emits: (SHR16rCL:i16 GR16:i16:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(31)) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHR16rCL, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (srl:i16 GR16:i16:$src1, 1:i8)
- // Emits: (SHR16r1:i16 GR16:i16:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::SHR16r1, MVT::i16);
- return Result;
- }
- }
- }
-
- // Pattern: (srl:i16 GR16:i16:$src, 8:i8)
- // Emits: (EXTRACT_SUBREG:i16 (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 3:i32)
- // Pattern complexity = 8 cost = 4 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_168(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr8, TargetOpcode::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
- return Result;
- }
- }
- }
-
- // Pattern: (srl:i16 GR16:i16:$src, 8:i8)
- // Emits: (EXTRACT_SUBREG:i16 (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 3:i32)
- // Pattern complexity = 8 cost = 4 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_168(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetOpcode::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
- return Result;
- }
- }
- }
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (srl:i16 GR16:i16:$src1, (imm:i8):$src2)
- // Emits: (SHR16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHR16ri, MVT::i16);
- return Result;
- }
-
- // Pattern: (srl:i16 GR16:i16:$src, CL:i8)
- // Emits: (SHR16rCL:i16 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHR16rCL, MVT::i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRL_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (srl:i32 GR32:i32:$src1, (and:i8 CL:i8:$amt, 31:i8))
- // Emits: (SHR32rCL:i32 GR32:i32:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(31)) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHR32rCL, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (srl:i32 GR32:i32:$src1, 1:i8)
- // Emits: (SHR32r1:i32 GR32:i32:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::SHR32r1, MVT::i32);
- return Result;
- }
- }
- }
-
- // Pattern: (srl:i32 GR32:i32:$src1, (imm:i8):$src2)
- // Emits: (SHR32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHR32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (srl:i32 GR32:i32:$src, CL:i8)
- // Emits: (SHR32rCL:i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHR32rCL, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SRL_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (srl:i64 GR64:i64:$src1, (and:i8 CL:i8:$amt, 63:i8))
- // Emits: (SHR64rCL:i64 GR64:i64:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0 &&
- CheckAndMask(N10, Tmp0, INT64_C(63)) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHR64rCL, MVT::i64);
- return Result;
- }
- }
-
- // Pattern: (srl:i64 GR64:i64:$src1, 1:i8)
- // Emits: (SHR64r1:i64 GR64:i64:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_93(N, X86::SHR64r1, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (srl:i64 GR64:i64:$src1, (imm:i8):$src2)
- // Emits: (SHR64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_159(N, X86::SHR64ri, MVT::i64);
- return Result;
- }
-
- // Pattern: (srl:i64 GR64:i64:$src, CL:i8)
- // Emits: (SHR64rCL:i64 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_158(N, X86::SHR64rCL, MVT::i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_169(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp1, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_170(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp1, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_171(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp1, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_172(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_173(SDNode *N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Chain11 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N11.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain11);
- Chain11 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N11.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4, Chain11 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 6);
- Chain11 = SDValue(ResNode, 1);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N11.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- SDValue(Chain11.getNode(), Chain11.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_174(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_175(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 6);
- Chain10 = SDValue(ResNode, 1);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_176(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 1);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_177(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i8);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 1);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_178(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i16);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 1);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_179(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 1);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_180(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain10, N1.getNode()->getDebugLoc(), X86::CL, N11, InFlag).getNode();
- Chain10 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_181(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i8);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_182(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain10, N1.getNode()->getDebugLoc(), X86::CL, N12, InFlag).getNode();
- Chain10 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Chain10, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_183(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N12)->getZExtValue()), MVT::i8);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Tmp2, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_184(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag = N1.getNode()->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Chain10, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N1.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- InFlag,
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 3);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_185(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i8);
- SDValue InFlag = N1.getNode()->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N1.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- InFlag,
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 3);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_186(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i16);
- SDValue InFlag = N1.getNode()->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N1.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- InFlag,
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 3);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_187(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- SDValue InFlag = N1.getNode()->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N1.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- InFlag,
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 3);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_188(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N1.getNode()->getDebugLoc(), X86::EFLAGS, N11, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_189(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp1, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_190(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i64);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 1);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_191(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i64);
- SDValue InFlag = N1.getNode()->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N1.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- InFlag,
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 3);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_192(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N10, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_193(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N10, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_194(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N100, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_195(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1000, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_196(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N10, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_197(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N100, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_198(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N100, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_199(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i16);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_200(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_201(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain10, N11.getNode()->getDebugLoc(), X86::CL, N110, InFlag).getNode();
- Chain10 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_202(SDNode *N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue Chain100 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N1111 = N111.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N100.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain100);
- Chain100 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N10.getNode()->getDebugLoc(), X86::CL, N101, InFlag).getNode();
- Chain100 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N100.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Chain100, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- Chain100 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N100.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain100.getNode(), Chain100.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_203(SDNode *N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue Chain100 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N11100 = N1110.getNode()->getOperand(0);
- SDValue N11101 = N1110.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N100.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain100);
- Chain100 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N101.getNode()->getDebugLoc(), X86::ECX, N1010, InFlag).getNode();
- Chain100 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N100.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Chain100, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- Chain100 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N100.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain100.getNode(), Chain100.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_204(SDNode *N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue Chain100 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N100.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain100);
- Chain100 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i8);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N100.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Tmp2, Chain100 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- Chain100 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N100.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain100.getNode(), Chain100.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_205(SDNode *N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue Chain100 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N11100 = N1110.getNode()->getOperand(0);
- SDValue N11101 = N1110.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N100.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain100);
- Chain100 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N101.getNode()->getDebugLoc(), X86::CX, N1010, InFlag).getNode();
- Chain100 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N100.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Chain100, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- Chain100 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N100.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain100.getNode(), Chain100.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_206(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 6);
- Chain10 = SDValue(ResNode, 1);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_207(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N1, Tmp2), 0);
- MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
- MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops1[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp3, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc1, MVT::Other, Ops1, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_208(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i64);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_209(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFF80000000ULL, MVT::i64);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_210(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR64_ABCDRegClassID, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N100, Tmp4), 0);
- SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp7(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp5, Tmp6), 0);
- MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
- MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops2[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp7, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc2, MVT::Other, Ops2, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_211(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N100, Tmp4), 0);
- SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp7(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp5, Tmp6), 0);
- MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
- MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops2[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp7, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc2, MVT::Other, Ops2, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_212(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N100, Tmp4), 0);
- SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp7(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp5, Tmp6), 0);
- MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
- MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops2[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp7, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc2, MVT::Other, Ops2, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_213(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N10.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- Chain10 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N10.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain10.getNode(), Chain10.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_214(SDNode *N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue Chain100 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N100.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain100);
- Chain100 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N100.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N11, Chain100 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
- Chain100 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N100.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain100.getNode(), Chain100.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_215(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1000, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_216(SDNode *N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Chain11 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N11.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain11);
- Chain11 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N11.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4, N10, Chain11 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- Chain11 = SDValue(ResNode, 1);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N11.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 1),
- SDValue(Chain11.getNode(), Chain11.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_217(SDNode *N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Chain11 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N11.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain11);
- Chain11 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag = N1.getNode()->getOperand(2);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N11.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4, N10, Chain11, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
- Chain11 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N11.getNode(), 1),
- SDValue(N1.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- InFlag,
- SDValue(Chain11.getNode(), Chain11.getResNo())
- };
- ReplaceUses(Froms, Tos, 3);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_218(SDNode *N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N1011 = N101.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue Chain110 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N110.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain110);
- Chain110 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N101.getNode()->getDebugLoc(), X86::CL, N1011, InFlag).getNode();
- Chain110 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N110.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Chain110, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- Chain110 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N110.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain110.getNode(), Chain110.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_219(SDNode *N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N10100 = N1010.getNode()->getOperand(0);
- SDValue N10101 = N1010.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue Chain110 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N110.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain110);
- Chain110 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N1010.getNode()->getDebugLoc(), X86::ECX, N10101, InFlag).getNode();
- Chain110 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N110.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Chain110, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- Chain110 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N110.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain110.getNode(), Chain110.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_220(SDNode *N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue Chain110 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N110.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain110);
- Chain110 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N111)->getZExtValue()), MVT::i8);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N110.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Tmp2, Chain110 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- Chain110 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N110.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain110.getNode(), Chain110.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_221(SDNode *N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N10100 = N1010.getNode()->getOperand(0);
- SDValue N10101 = N1010.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue Chain110 = N110.getNode()->getOperand(0);
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue N1110 = N111.getNode()->getOperand(0);
- SDValue N2 = N->getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N110.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain110);
- Chain110 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N1010.getNode()->getDebugLoc(), X86::CX, N10101, InFlag).getNode();
- Chain110 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N110.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Chain110, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
- Chain110 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N110.getNode(), 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain110.getNode(), Chain110.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_ISD_STORE(SDNode *N) {
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::OR &&
- N1.hasOneUse()) {
- {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt)), (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N1110.getNode()->getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- if (N1010 == N11101) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_203(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt)), (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SHL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N1110.getNode()->getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- if (N1010 == N11101) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_203(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt)), (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N1110.getNode()->getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- if (N1010 == N11101) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i16 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_205(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N10.getNode()->getOpcode() == ISD::SHL) {
-
- // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt)), (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N1110.getNode()->getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- if (N1010 == N11101) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i16 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_205(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- if (N1010.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N10101 == N1110) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_219(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- if (N1010.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N10101 == N1110) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_219(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- if (N1010.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N10101 == N1110) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i16 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_221(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N10.getNode()->getOpcode() == ISD::SRL) {
-
- // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- if (N1010.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N10101 == N1110) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i16 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_221(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt), (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N1111 = N111.getNode()->getOperand(1);
- if (N101 == N1111) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt), (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SHL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N1111 = N111.getNode()->getOperand(1);
- if (N101 == N1111) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt), (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1111 = N111.getNode()->getOperand(1);
- if (N101 == N1111) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N10.getNode()->getOpcode() == ISD::SHL) {
-
- // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt), (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1111 = N111.getNode()->getOperand(1);
- if (N101 == N1111) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N1011 = N101.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N1011 == N111) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_218(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N1011 = N101.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N1011 == N111) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_218(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1011 = N101.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N1011 == N111) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_218(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1011 = N101.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N1011 == N111) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_218(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1), (shl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHRD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1), (srl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHLD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1), (shl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHRD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1), (srl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHLD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i64 (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1), (shl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHRD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i64 (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1), (srl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHLD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (imm:i8):$amt2), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::SHRD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (imm:i8):$amt2), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::SHLD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (imm:i8):$amt2), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::SHRD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (imm:i8):$amt2), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::SHLD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i64 (shl:i64 GR64:i64:$src2, (imm:i8):$amt2), (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_load(N110.getNode()) &&
- Predicate_loadi64(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::SHRD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i64 (srl:i64 GR64:i64:$src2, (imm:i8):$amt2), (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_load(N110.getNode()) &&
- Predicate_loadi64(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::SHLD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL8mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL16mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL32mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR8mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR16mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR32mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR8mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR16mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR32mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL64mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(63))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR64mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(63))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR64mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(63))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode())) {
-
- // Pattern: (st:isVoid (sub:i8 0:i8, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NEG8m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_load(N11.getNode()) &&
- Predicate_loadi8(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_173(N, X86::NEG8m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (sub:i16 0:i16, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NEG16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi16(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_173(N, X86::NEG16m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (sub:i32 0:i32, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NEG32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi32(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_173(N, X86::NEG32m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC8m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_175(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, -1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC8m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(-1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_175(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, -1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(-1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, -1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(-1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (st:isVoid (sub:i64 0:i64, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NEG64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode()) &&
- Predicate_loadi64(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_173(N, X86::NEG64m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_175(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, -1:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (CN1 == INT64_C(-1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_175(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC64_16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC64_32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, -1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC64_16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(-1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, -1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC64_32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(-1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL8m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL16m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL32m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR8m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR16m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR32m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR8m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SAR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR16m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SAR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR32m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SAR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ROTL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL8m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL16m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL32m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ROTR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR8m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotr:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR16m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotr:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR32m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL64m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR64m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR64m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SAR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL64m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ROTL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR64m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ROTR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 128:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB16mi8:isVoid addr:iPTR:$dst, -128:i16)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(128)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_199(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 128:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB32mi8:isVoid addr:iPTR:$dst, -128:i32)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(128)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_200(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 128:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mi8:isVoid addr:iPTR:$dst, -128:i64)
- // Pattern complexity = 52 cost = 1 size = 3
- if (CN1 == INT64_C(128)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_208(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 34359738368:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mi32:isVoid addr:iPTR:$dst, -2147483648:i64)
- // Pattern complexity = 52 cost = 1 size = 3
- if (CN1 == INT64_C(34359738368)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_209(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NOT8m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 51 cost = 1 size = 2
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::NOT8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NOT16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 51 cost = 1 size = 2
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_174(N, X86::NOT16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NOT32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 51 cost = 1 size = 2
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_174(N, X86::NOT32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (and:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (and:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (or:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADDE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (adde:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_186(N, X86::ADC16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (adde:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::ADC32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (sub:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (sub:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUBE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (sube:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_186(N, X86::SBB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (sube:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::SBB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADDE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
-
- // Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- {
- SDNode *Result = Emit_191(N, X86::ADC64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- SDNode *Result = Emit_191(N, X86::ADC64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (sub:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (sub:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUBE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (sube:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_191(N, X86::SBB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (sube:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_191(N, X86::SBB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NOT64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 51 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_174(N, X86::NOT64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
-
- // Pattern: (st:isVoid (and:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (and:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
-
- // Pattern: (st:isVoid (or:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
-
- // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86add_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86add_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86sub_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86sub_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86or_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86or_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86xor_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86xor_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86and_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86and_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (X86add_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86add_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (X86sub_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86sub_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (X86or_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86or_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (X86xor_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86xor_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (X86and_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86and_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR128:v4i32:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVLPSmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
- N1.hasOneUse() &&
- Predicate_movlp(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_214(N, X86::MOVLPSmr, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (and:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (and:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (and:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (or:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SAR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SAR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SAR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ROTL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ROTR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotr:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotr:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86shld:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$src3)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- if (N12.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHLD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86shrd:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$src3)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- if (N12.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHRD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86shld:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$src3)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- if (N12.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHLD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86shrd:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$src3)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- if (N12.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHRD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADDE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (adde:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_185(N, X86::ADC8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (adde:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_186(N, X86::ADC16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (adde:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::ADC32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (sub:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sub:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sub:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUBE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (sube:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_185(N, X86::SBB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sube:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_186(N, X86::SBB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sube:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::SBB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SAR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ROTL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ROTR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86shld:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$src3)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- if (N12.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHLD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86shrd:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$src3)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- if (N12.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHRD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86add_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86add_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86add_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86sub_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86sub_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86sub_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86or_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86or_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86or_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86xor_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86xor_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86xor_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86and_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86and_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86and_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v4f32:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVLPSmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 48 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
- N1.hasOneUse() &&
- Predicate_movlp(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_213(N, X86::MOVLPSmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
- N1.hasOneUse() &&
- Predicate_movlp(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2) {
-
- // Pattern: (st:isVoid (vector_shuffle:v2f64 (ld:v2f64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v2f64:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVLPDmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 48 cost = 1 size = 3
- if (N1.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_213(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (vector_shuffle:v2i64 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v2i64:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVLPDmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 48 cost = 1 size = 3
- if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_213(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (st:isVoid (X86inc_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC8m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::INC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N10.getValueType() == MVT::i8) {
- SDNode *Result = Emit_206(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86dec_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC8m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::DEC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N10.getValueType() == MVT::i8) {
- SDNode *Result = Emit_206(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((!Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (st:isVoid (X86inc_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::INC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_206(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86dec_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::DEC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_206(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86inc_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::INC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86dec_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::DEC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (st:isVoid (X86inc_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC64_16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::INC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_206(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86dec_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC64_16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::DEC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_206(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86inc_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC64_32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::INC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86dec_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC64_32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::DEC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (st:isVoid (X86inc_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::INC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N10.getValueType() == MVT::i64) {
- SDNode *Result = Emit_206(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86dec_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::DEC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N10.getValueType() == MVT::i64) {
- SDNode *Result = Emit_206(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2) {
-
- // Pattern: (st:isVoid (and:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::AND8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (and:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::AND16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (and:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::AND32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2) {
-
- // Pattern: (st:isVoid (or:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::OR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (or:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::OR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (or:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::OR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2) {
-
- // Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::XOR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::XOR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::XOR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL8mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL16mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL32mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR8mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR16mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR32mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR8mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR16mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR32mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ROTL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL8mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (rotl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL16mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (rotl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL32mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ROTR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR8mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (rotr:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR16mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (rotr:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR32mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86shld:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_182(N, X86::SHLD32mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86shrd:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_182(N, X86::SHRD32mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86shld:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_182(N, X86::SHLD16mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86shrd:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_182(N, X86::SHRD16mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2) {
-
- // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::ADD8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::ADD16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::ADD32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADDE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2) {
-
- // Pattern: (st:isVoid (adde:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::ADC8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (adde:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_184(N, X86::ADC16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (adde:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, X86::ADC32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2) {
-
- // Pattern: (st:isVoid (sub:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::SUB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (sub:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::SUB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (sub:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::SUB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUBE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2) {
-
- // Pattern: (st:isVoid (sube:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SBB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (sube:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_184(N, X86::SBB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (sube:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_184(N, X86::SBB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::ADD64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ADDE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_184(N, X86::ADC64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sub:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::SUB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sube:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SUBE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_184(N, X86::SBB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL64mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR64mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR64mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL64mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ROTL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR64mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ROTR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ROR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86shld:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_182(N, X86::SHLD64mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86shrd:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_182(N, X86::SHRD64mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (and:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::AND64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::OR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::XOR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86add_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::ADD8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86add_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::ADD16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86add_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::ADD32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86sub_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::SUB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86sub_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::SUB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86sub_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::SUB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86or_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::OR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86or_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::OR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86or_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::OR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86xor_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::XOR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86xor_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::XOR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86xor_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::XOR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86and_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::AND8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86and_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::AND16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86and_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::AND32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86add_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::ADD64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86sub_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::SUB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86or_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::OR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86xor_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::XOR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86and_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::AND64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2) {
-
- // Pattern: (st:isVoid (and:i8 GR8:i8:$src, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_216(N, X86::AND8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (and:i16 GR16:i16:$src, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_216(N, X86::AND16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (and:i32 GR32:i32:$src, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_216(N, X86::AND32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2) {
-
- // Pattern: (st:isVoid (or:i8 GR8:i8:$src, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_216(N, X86::OR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (or:i16 GR16:i16:$src, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_216(N, X86::OR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (or:i32 GR32:i32:$src, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_216(N, X86::OR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2) {
-
- // Pattern: (st:isVoid (xor:i8 GR8:i8:$src, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_216(N, X86::XOR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (xor:i16 GR16:i16:$src, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_216(N, X86::XOR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (xor:i32 GR32:i32:$src, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_216(N, X86::XOR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2) {
-
- // Pattern: (st:isVoid (add:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_216(N, X86::ADD8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (add:i16 GR16:i16:$src2, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_216(N, X86::ADD16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (add:i32 GR32:i32:$src2, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_216(N, X86::ADD32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADDE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2) {
-
- // Pattern: (st:isVoid (adde:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_217(N, X86::ADC8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (adde:i16 GR16:i16:$src2, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_217(N, X86::ADC16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (adde:i32 GR32:i32:$src2, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_217(N, X86::ADC32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_216(N, X86::ADD64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (adde:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ADDE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_217(N, X86::ADC64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (and:i64 GR64:i64:$src, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_216(N, X86::AND64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i64 GR64:i64:$src, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_216(N, X86::OR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (xor:i64 GR64:i64:$src, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_216(N, X86::XOR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode())) {
-
- // Pattern: (st:isVoid (X86add_flag:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N11.getNode()) &&
- Predicate_loadi8(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_216(N, X86::ADD8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86add_flag:i16 GR16:i16:$src2, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_216(N, X86::ADD16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86add_flag:i32 GR32:i32:$src2, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_216(N, X86::ADD32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode())) {
-
- // Pattern: (st:isVoid (X86or_flag:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N11.getNode()) &&
- Predicate_loadi8(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_216(N, X86::OR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86or_flag:i16 GR16:i16:$src2, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_216(N, X86::OR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86or_flag:i32 GR32:i32:$src2, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_216(N, X86::OR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode())) {
-
- // Pattern: (st:isVoid (X86xor_flag:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N11.getNode()) &&
- Predicate_loadi8(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_216(N, X86::XOR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86xor_flag:i16 GR16:i16:$src2, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_216(N, X86::XOR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86xor_flag:i32 GR32:i32:$src2, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_216(N, X86::XOR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode())) {
-
- // Pattern: (st:isVoid (X86and_flag:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_load(N11.getNode()) &&
- Predicate_loadi8(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_216(N, X86::AND8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86and_flag:i16 GR16:i16:$src2, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi16(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_216(N, X86::AND16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (X86and_flag:i32 GR32:i32:$src2, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (Predicate_loadi32(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_216(N, X86::AND32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86add_flag:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode()) &&
- Predicate_loadi64(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_216(N, X86::ADD64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86or_flag:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode()) &&
- Predicate_loadi64(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_216(N, X86::OR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86xor_flag:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode()) &&
- Predicate_loadi64(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_216(N, X86::XOR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (X86and_flag:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 47 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode()) &&
- Predicate_loadi64(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_216(N, X86::AND64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (vector_extract:f64 (vector_shuffle:v2f64 (bitconvert:v2f64 VR128:v4f32:$src), (undef:v2f64))<<P:Predicate_unpckh>>, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVHPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
- // Pattern complexity = 40 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
- Predicate_unpckh(N10.getNode())) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::UNDEF) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::f64 &&
- N10.getValueType() == MVT::v2f64 &&
- N1000.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_195(N, X86::MOVHPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (vector_extract:f64 (vector_shuffle:v2f64 VR128:v2f64:$src, (undef:v2f64))<<P:Predicate_unpckh>>, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVHPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
- // Pattern complexity = 37 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
- Predicate_unpckh(N10.getNode())) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::UNDEF) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::f64 &&
- N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_197(N, X86::MOVHPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (trunc:i8 (srl:i64 GR64:i64:$src, 8:i8)<<P:Predicate_srl_su>>)<<P:Predicate_trunc_su>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV8mr_NOREX:isVoid addr:i64:$dst, (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i64 GR64:i64:$src, GR64_ABCD:i64), 2:i32))
- // Pattern complexity = 35 cost = 3 size = 3
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TRUNCATE &&
- Predicate_trunc_su(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- Predicate_srl_su(N10.getNode())) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::i8 &&
- N10.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8) {
- SDNode *Result = Emit_210(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i64, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::TRUNCATE &&
- Predicate_trunc_su(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- Predicate_srl_su(N10.getNode())) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::i8) {
-
- // Pattern: (st:isVoid (trunc:i8 (srl:i32 GR32:i32:$src, 8:i8)<<P:Predicate_srl_su>>)<<P:Predicate_trunc_su>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV8mr_NOREX:isVoid addr:i64:$dst, (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 2:i32))
- // Pattern complexity = 35 cost = 3 size = 3
- if (N10.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8) {
- SDNode *Result = Emit_211(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i32, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (trunc:i8 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)<<P:Predicate_trunc_su>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV8mr_NOREX:isVoid addr:i64:$dst, (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
- // Pattern complexity = 35 cost = 3 size = 3
- if (N10.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8) {
- SDNode *Result = Emit_212(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i16, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (bitconvert:f32 (extractelt:i32 (bitconvert:v4i32 VR128:v4f32:$src1), (imm:iPTR):$src2)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (EXTRACTPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src1, (imm:i32):$src2)
- // Pattern complexity = 34 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::f32 &&
- N10.getValueType() == MVT::i32 &&
- N100.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_215(N, X86::EXTRACTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (vector_extract:f64 (bitconvert:v2f64 VR128:v4f32:$src), 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVLPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::f64 &&
- N10.getValueType() == MVT::v2f64 &&
- N100.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_194(N, X86::MOVLPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (extractelt:i32 (bitconvert:v4i32 VR128:v4f32:$src1), (imm:iPTR):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (EXTRACTPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src1, (imm:i32):$src2)
- // Pattern complexity = 31 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_198(N, X86::EXTRACTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- }
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::SETCC) {
- SDValue N10 = N1.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (st:isVoid (X86setcc:i8 4:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETEm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 9:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETNEm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETNEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 7:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETLm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETLm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 6:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETGEm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETGEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 8:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETLEm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETLEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 5:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETGm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETGm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 2:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETBm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETBm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 1:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETAEm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETAEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 3:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETBEm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETBEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 0:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETAm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETAm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 15:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETSm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETSm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 12:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETNSm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETNSm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 14:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETPm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETPm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 11:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETNPm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETNPm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 13:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETOm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETOm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86setcc:i8 10:i8, EFLAGS:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SETNOm:isVoid addr:iPTR:$dst)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_188(N, X86::SETNOm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (vector_extract:f32 VR128:v4f32:$src, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVPS2SSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::f32 &&
- N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_196(N, X86::MOVPS2SSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (st:isVoid (vector_extract:f64 VR128:v2f64:$src, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVLPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (N1.getValueType() == MVT::f64 &&
- N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_196(N, X86::MOVLPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (vector_extract:i64 VR128:v2i64:$src, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVPQI2QImr:isVoid addr:iPTR:$dst, VR128:v2i64:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (N1.getValueType() == MVT::i64 &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_196(N, X86::MOVPQI2QImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (vector_extract:f64 VR128:v2f64:$src, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVPD2SDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (N1.getValueType() == MVT::f64 &&
- N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_196(N, X86::MOVPD2SDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (vector_extract:i32 VR128:v4i32:$src, 0:iPTR), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVPDI2DImr:isVoid addr:iPTR:$dst, VR128:v4i32:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_196(N, X86::MOVPDI2DImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE41())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (st:isVoid (extractelt:i64 VR128:v2i64:$src1, (imm:iPTR):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (PEXTRQmr:isVoid addr:iPTR:$dst, VR128:v2i64:$src1, (imm:i32):$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N1.getValueType() == MVT::i64 &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_193(N, X86::PEXTRQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (extractelt:i32 VR128:v4i32:$src1, (imm:iPTR):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (PEXTRDmr:isVoid addr:iPTR:$dst, VR128:v4i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_193(N, X86::PEXTRDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((TM.getCodeModel() == CodeModel::Small ||TM.getCodeModel() == CodeModel::Kernel) && (TM.getRelocationModel() == Reloc::Static)) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (st:isVoid (X86Wrapper:i64 (tconstpool:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (tconstpool:i64):$src)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86Wrapper:i64 (tjumptable:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (tjumptable:i64):$src)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86Wrapper:i64 (tglobaladdr:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (tglobaladdr:i64):$src)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86Wrapper:i64 (texternalsym:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (texternalsym:i64):$src)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86Wrapper:i64 (tblockaddress:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (tblockaddress:i64):$src)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == X86ISD::Wrapper) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (st:isVoid (X86Wrapper:i32 (tglobaladdr:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV32mi:isVoid addr:iPTR:$dst, (tglobaladdr:i32):$src)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_192(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86Wrapper:i32 (texternalsym:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV32mi:isVoid addr:iPTR:$dst, (texternalsym:i32):$src)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_192(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (X86Wrapper:i32 (tblockaddress:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV32mi:isVoid addr:iPTR:$dst, (tblockaddress:i32):$src)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_192(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (imm:i64)<<P:Predicate_i64immSExt32>>:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_189(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (st:isVoid (imm:i8):$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_169(N, X86::MOV8mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (imm:i16):$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_170(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (imm:i32):$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_171(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (st:isVoid (bitconvert:i64 FR64:f64:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVSDto64mr:isVoid addr:iPTR:$dst, FR64:f64:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getValueType() == MVT::i64 &&
- N10.getValueType() == MVT::f64) {
- SDNode *Result = Emit_192(N, X86::MOVSDto64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (bitconvert:i32 FR32:f32:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVSS2DImr:isVoid addr:iPTR:$dst, FR32:f32:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::f32) {
- SDNode *Result = Emit_192(N, X86::MOVSS2DImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_truncstore(N) &&
- Predicate_truncstorei16(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (st:isVoid (imm:i32):$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (MOV16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_170(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (imm:i64):$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (MOV16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_170(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid RFP32:f32:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ST_Fp32m:isVoid addr:iPTR:$op, RFP32:f32:$src)
- // Pattern complexity = 22 cost = 1 size = 0
- if ((!Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_172(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- if ((!Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N)) {
-
- // Pattern: (st:isVoid RFP64:f64:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstoref32>>
- // Emits: (ST_Fp64m32:isVoid addr:iPTR:$op, RFP64:f64:$src)
- // Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_truncstore(N) &&
- Predicate_truncstoref32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_172(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid RFP64:f64:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ST_Fp64m:isVoid addr:iPTR:$op, RFP64:f64:$src)
- // Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_172(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N)) {
- if (Predicate_truncstore(N)) {
-
- // Pattern: (st:isVoid RFP80:f80:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstoref32>>
- // Emits: (ST_Fp80m32:isVoid addr:iPTR:$op, RFP80:f80:$src)
- // Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_truncstoref32(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_172(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid RFP80:f80:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstoref64>>
- // Emits: (ST_Fp80m64:isVoid addr:iPTR:$op, RFP80:f80:$src)
- // Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_truncstoref64(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_172(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- if (Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (st:isVoid RFP80:f80:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ST_FpP80m:isVoid addr:iPTR:$op, RFP80:f80:$src)
- // Pattern complexity = 22 cost = 1 size = 0
- if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_172(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid GR8:i8:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_172(N, X86::MOV8mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid GR16:i16:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_172(N, X86::MOV16mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid GR32:i32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_172(N, X86::MOV32mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid GR64:i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOV64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_172(N, X86::MOV64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
-
- // Pattern: (st:isVoid FR32:f32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVSSmr:isVoid addr:iPTR:$dst, FR32:f32:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_172(N, X86::MOVSSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
- // Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedstore(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
-
- // Pattern: (st:isVoid FR64:f64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVSDmr:isVoid addr:iPTR:$dst, FR64:f64:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_172(N, X86::MOVSDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
- // Emits: (MOVAPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedstore(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_172(N, X86::MOVAPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVUPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_172(N, X86::MOVUPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid VR64:v1i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v1i64:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
- N1.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- if (Predicate_alignedstore(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (st:isVoid VR128:v2i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
- // Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid VR128:v4i32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
- // Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid VR128:v8i16:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
- // Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid VR128:v16i8:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
- // Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (st:isVoid VR128:v2i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid VR128:v4i32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid VR128:v8i16:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid VR128:v16i8:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N)) {
- if (Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (st:isVoid VR64:v8i8:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid VR64:v4i16:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid VR64:v2i32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid VR64:v2f32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid VR64:v1i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (N1.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- if (Predicate_truncstore(N) &&
- Predicate_truncstorei16(N)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (st:isVoid GR32:i32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (MOV16mr:isVoid addr:iPTR:$dst, (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32))
- // Pattern complexity = 22 cost = 2 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_207(N, TargetOpcode::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (st:isVoid GR64:i64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
- // Emits: (MOV16mr:isVoid addr:iPTR:$dst, (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
- // Pattern complexity = 22 cost = 2 size = 3
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_207(N, TargetOpcode::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_222(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N1);
-}
-SDNode *Select_ISD_SUB_i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (sub:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::SUB8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (sub:i8 0:i8, GR8:i8:$src)
- // Emits: (NEG8r:i8 GR8:i8:$src)
- // Pattern complexity = 8 cost = 1 size = 2
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_222(N, X86::NEG8r, MVT::i8);
- return Result;
- }
- }
- }
-
- // Pattern: (sub:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (SUB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_3(N, X86::SUB8ri, MVT::i8);
- return Result;
- }
- }
-
- // Pattern: (sub:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (SUB8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::SUB8rr, MVT::i8);
- return Result;
-}
-
-SDNode *Select_ISD_SUB_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (sub:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::SUB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (sub:i16 0:i16, GR16:i16:$src)
- // Emits: (NEG16r:i16 GR16:i16:$src)
- // Pattern complexity = 8 cost = 1 size = 2
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_222(N, X86::NEG16r, MVT::i16);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (sub:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (SUB16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::SUB16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (sub:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (SUB16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::SUB16ri, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (sub:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (SUB16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::SUB16rr, MVT::i16);
- return Result;
-}
-
-SDNode *Select_ISD_SUB_i32(SDNode *N) {
-
- // Pattern: (sub:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::SUB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (sub:i32 0:i32, GR32:i32:$src)
- // Emits: (NEG32r:i32 GR32:i32:$src)
- // Pattern complexity = 8 cost = 1 size = 2
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_222(N, X86::NEG32r, MVT::i32);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (sub:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (SUB32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::SUB32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (sub:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (SUB32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::SUB32ri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (sub:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (SUB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::SUB32rr, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_SUB_i64(SDNode *N) {
-
- // Pattern: (sub:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::SUB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: lea64addr:i64:$src
- // Emits: (LEA64r:i64 lea64addr:i64:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (sub:i64 0:i64, GR64:i64:$src)
- // Emits: (NEG64r:i64 GR64:i64:$src)
- // Pattern complexity = 8 cost = 1 size = 2
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_222(N, X86::NEG64r, MVT::i64);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (sub:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (SUB64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::SUB64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (sub:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (SUB64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::SUB64ri32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (sub:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (SUB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::SUB64rr, MVT::i64);
- return Result;
-}
-
-SDNode *Select_ISD_SUB_v8i8(SDNode *N) {
- if ((Subtarget->hasMMX())) {
-
- // Pattern: (sub:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PSUBBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (sub:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PSUBBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PSUBBrr, MVT::v8i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SUB_v16i8(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (sub:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PSUBBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (sub:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PSUBBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PSUBBrr, MVT::v16i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SUB_v4i16(SDNode *N) {
- if ((Subtarget->hasMMX())) {
-
- // Pattern: (sub:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PSUBWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (sub:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PSUBWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PSUBWrr, MVT::v4i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SUB_v8i16(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (sub:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PSUBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (sub:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PSUBWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PSUBWrr, MVT::v8i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SUB_v2i32(SDNode *N) {
- if ((Subtarget->hasMMX())) {
-
- // Pattern: (sub:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PSUBDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (sub:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (MMX_PSUBDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PSUBDrr, MVT::v2i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SUB_v4i32(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (sub:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PSUBDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (sub:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PSUBDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PSUBDrr, MVT::v4i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SUB_v1i64(SDNode *N) {
- if ((Subtarget->hasMMX())) {
-
- // Pattern: (sub:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PSUBQrm, MVT::v1i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (sub:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PSUBQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PSUBQrr, MVT::v1i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SUB_v2i64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (sub:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PSUBQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PSUBQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (sub:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PSUBQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PSUBQrr, MVT::v2i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_SUBC_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (subc:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_21(N, X86::SUB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (subc:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (SUB32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_22(N, X86::SUB32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (subc:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (SUB32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_22(N, X86::SUB32ri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (subc:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (SUB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_20(N, X86::SUB32rr, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_SUBC_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (subc:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_21(N, X86::SUB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (subc:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (SUB64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_24(N, X86::SUB64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (subc:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Emits: (SUB64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_24(N, X86::SUB64ri32, MVT::i64);
- return Result;
- }
- }
-
- // Pattern: (subc:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (SUB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_20(N, X86::SUB64rr, MVT::i64);
- return Result;
-}
-
-SDNode *Select_ISD_SUBE_i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sube:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SBB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_26(N, X86::SBB8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
-
- // Pattern: (sube:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (SBB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_27(N, X86::SBB8ri, MVT::i8);
- return Result;
- }
- }
-
- // Pattern: (sube:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (SBB8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_25(N, X86::SBB8rr, MVT::i8);
- return Result;
-}
-
-SDNode *Select_ISD_SUBE_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sube:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SBB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_26(N, X86::SBB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (sube:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (SBB16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_29(N, X86::SBB16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (sube:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (SBB16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_29(N, X86::SBB16ri, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (sube:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (SBB16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_25(N, X86::SBB16rr, MVT::i16);
- return Result;
-}
-
-SDNode *Select_ISD_SUBE_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sube:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SBB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_26(N, X86::SBB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (sube:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (SBB32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_30(N, X86::SBB32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (sube:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (SBB32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_30(N, X86::SBB32ri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (sube:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (SBB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_25(N, X86::SBB32rr, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_SUBE_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (sube:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SBB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_26(N, X86::SBB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (sube:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (SBB64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_31(N, X86::SBB64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (sube:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (SBB64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_31(N, X86::SBB64ri32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (sube:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (SBB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_25(N, X86::SBB64rr, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_223(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
-}
-SDNode *Select_ISD_TRAP(SDNode *N) {
- SDNode *Result = Emit_223(N, X86::TRAP);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_224(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
- SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_225(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
- SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_226(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp3), 0);
- SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp4, Tmp5);
-}
-DISABLE_INLINE SDNode *Emit_227(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp3), 0);
- SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp4, Tmp5);
-}
-DISABLE_INLINE SDNode *Emit_228(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp1 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
-}
-SDNode *Select_ISD_TRUNCATE_i8(SDNode *N) {
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRL &&
- Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8)) {
-
- // Pattern: (trunc:i8 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
- // Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR16:i16:$src, GR16_ABCD:i16), 2:i32)
- // Pattern complexity = 12 cost = 2 size = 0
- if (N0.getValueType() == MVT::i16 &&
- N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_226(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::i32, MVT::i8);
- return Result;
- }
-
- // Pattern: (trunc:i8 (srl:i32 GR32:i32:$src, 8:i8)<<P:Predicate_srl_su>>)
- // Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR32:i32:$src, GR32_ABCD:i32), 2:i32)
- // Pattern complexity = 12 cost = 2 size = 0
- if (N0.getValueType() == MVT::i32 &&
- N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_227(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::i16, MVT::i8);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (trunc:i8 GR64:i64:$src)
- // Emits: (EXTRACT_SUBREG:i8 GR64:i64:$src, 1:i32)
- // Pattern complexity = 3 cost = 1 size = 0
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_228(N, TargetOpcode::EXTRACT_SUBREG, MVT::i8);
- return Result;
- }
- }
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (trunc:i8 GR32:i32:$src)
- // Emits: (EXTRACT_SUBREG:i8 GR32:i32:$src, 1:i32)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_228(N, TargetOpcode::EXTRACT_SUBREG, MVT::i8);
- return Result;
- }
-
- // Pattern: (trunc:i8 GR16:i16:$src)
- // Emits: (EXTRACT_SUBREG:i8 GR16:i16:$src, 1:i32)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_228(N, TargetOpcode::EXTRACT_SUBREG, MVT::i8);
- return Result;
- }
- }
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (trunc:i8 GR32:i32:$src)
- // Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 1:i32)
- // Pattern complexity = 3 cost = 2 size = 0
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_224(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::i32, MVT::i8);
- return Result;
- }
-
- // Pattern: (trunc:i8 GR16:i16:$src)
- // Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 1:i32)
- // Pattern complexity = 3 cost = 2 size = 0
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_225(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::i16, MVT::i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_229(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp1 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
-}
-SDNode *Select_ISD_TRUNCATE_i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (trunc:i16 GR32:i32:$src)
- // Emits: (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_229(N, TargetOpcode::EXTRACT_SUBREG, MVT::i16);
- return Result;
- }
-
- // Pattern: (trunc:i16 GR64:i64:$src)
- // Emits: (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_229(N, TargetOpcode::EXTRACT_SUBREG, MVT::i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_230(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp1 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
-}
-SDNode *Select_ISD_TRUNCATE_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_230(N, TargetOpcode::EXTRACT_SUBREG, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(SDNode *N) {
- if ((Subtarget->hasMMX())) {
-
- // Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckh>>
- // Emits: (MMX_PUNPCKHBWrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_mmx_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PUNPCKHBWrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>
- // Emits: (MMX_PUNPCKLBWrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_mmx_unpckl(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PUNPCKLBWrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src, (undef:v8i8))<<P:Predicate_mmx_unpckl_undef>>
- // Emits: (MMX_PUNPCKLBWrr:v8i8 VR64:v8i8:$src, VR64:v8i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_mmx_unpckl_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MMX_PUNPCKLBWrr, MVT::v8i8);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src, (undef:v8i8))<<P:Predicate_mmx_unpckh_undef>>
- // Emits: (MMX_PUNPCKHBWrr:v8i8 VR64:v8i8:$src, VR64:v8i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_mmx_unpckh_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MMX_PUNPCKHBWrr, MVT::v8i8);
- return Result;
- }
- }
- if ((Subtarget->hasMMX())) {
-
- // Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)<<P:Predicate_mmx_unpckh>>
- // Emits: (MMX_PUNPCKHBWrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_mmx_unpckh(N)) {
- SDNode *Result = Emit_15(N, X86::MMX_PUNPCKHBWrr, MVT::v8i8);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)<<P:Predicate_mmx_unpckl>>
- // Emits: (MMX_PUNPCKLBWrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_mmx_unpckl(N)) {
- SDNode *Result = Emit_15(N, X86::MMX_PUNPCKLBWrr, MVT::v8i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_231(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = Transform_SHUFFLE_get_palign_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N0, Tmp3);
-}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckl>>
- // Emits: (PUNPCKLBWrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PUNPCKLBWrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckh>>
- // Emits: (PUNPCKHBWrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PUNPCKHBWrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src, (undef:v16i8))<<P:Predicate_unpckl_undef>>
- // Emits: (PUNPCKLBWrr:v16i8 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckl_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKLBWrr, MVT::v16i8);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src, (undef:v16i8))<<P:Predicate_unpckh_undef>>
- // Emits: (PUNPCKHBWrr:v16i8 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckh_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKHBWrr, MVT::v16i8);
- return Result;
- }
- }
- }
-
- // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)<<P:Predicate_palign>><<X:SHUFFLE_get_palign_imm>>:$src3
- // Emits: (PALIGNR128rr:v16i8 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_palign_imm:i8 VR128:i8:$src3))
- // Pattern complexity = 9 cost = 1 size = 3
- if ((Subtarget->hasSSSE3()) &&
- Predicate_palign(N)) {
- SDNode *Result = Emit_231(N, X86::PALIGNR128rr, MVT::v16i8);
- return Result;
- }
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)<<P:Predicate_unpckl>>
- // Emits: (PUNPCKLBWrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDNode *Result = Emit_15(N, X86::PUNPCKLBWrr, MVT::v16i8);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)<<P:Predicate_unpckh>>
- // Emits: (PUNPCKHBWrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDNode *Result = Emit_15(N, X86::PUNPCKHBWrr, MVT::v16i8);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_232(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = Transform_MMX_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_233(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Chain00 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = Transform_MMX_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp2, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(SDNode *N) {
- if ((Subtarget->hasMMX())) {
-
- // Pattern: (vector_shuffle:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>), (undef:v4i16))<<P:Predicate_mmx_pshufw>><<X:MMX_SHUFFLE_get_shuf_imm>>:$src2
- // Emits: (MMX_PSHUFWmi:v4i16 addr:iPTR:$src1, (MMX_SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>), (undef:v4i16)):$src2))
- // Pattern complexity = 32 cost = 1 size = 3
- if (Predicate_mmx_pshufw(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_233(N, X86::MMX_PSHUFWmi, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckh>>
- // Emits: (MMX_PUNPCKHWDrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_mmx_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PUNPCKHWDrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>
- // Emits: (MMX_PUNPCKLWDrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_mmx_unpckl(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PUNPCKLWDrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src, (undef:v4i16))<<P:Predicate_mmx_unpckl_undef>>
- // Emits: (MMX_PUNPCKLWDrr:v4i16 VR64:v8i8:$src, VR64:v8i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_mmx_unpckl_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MMX_PUNPCKLWDrr, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src, (undef:v4i16))<<P:Predicate_mmx_unpckh_undef>>
- // Emits: (MMX_PUNPCKHWDrr:v4i16 VR64:v8i8:$src, VR64:v8i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_mmx_unpckh_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MMX_PUNPCKHWDrr, MVT::v4i16);
- return Result;
- }
- }
- if ((Subtarget->hasMMX())) {
-
- // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, (undef:v4i16))<<P:Predicate_mmx_pshufw>><<X:MMX_SHUFFLE_get_shuf_imm>>:$src2
- // Emits: (MMX_PSHUFWri:v4i16 VR64:v4i16:$src1, (MMX_SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i16 VR64:v4i16:$src1, (undef:v4i16)):$src2))
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_mmx_pshufw(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_232(N, X86::MMX_PSHUFWri, MVT::v4i16);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)<<P:Predicate_mmx_unpckh>>
- // Emits: (MMX_PUNPCKHWDrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_mmx_unpckh(N)) {
- SDNode *Result = Emit_15(N, X86::MMX_PUNPCKHWDrr, MVT::v4i16);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)<<P:Predicate_mmx_unpckl>>
- // Emits: (MMX_PUNPCKLWDrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_mmx_unpckl(N)) {
- SDNode *Result = Emit_15(N, X86::MMX_PUNPCKLWDrr, MVT::v4i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_234(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = Transform_SHUFFLE_get_pshufhw_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_235(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Chain00 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = Transform_SHUFFLE_get_pshufhw_imm(SDValue(N, 0).getNode());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp2, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_236(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = Transform_SHUFFLE_get_pshuflw_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_237(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Chain00 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = Transform_SHUFFLE_get_pshuflw_imm(SDValue(N, 0).getNode());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp2, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16))<<P:Predicate_pshufhw>><<X:SHUFFLE_get_pshufhw_imm>>:$src2
- // Emits: (PSHUFHWmi:v8i16 addr:iPTR:$src1, (SHUFFLE_get_pshufhw_imm:i8 (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16)):$src2))
- // Pattern complexity = 32 cost = 1 size = 3
- if (Predicate_pshufhw(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_235(N, X86::PSHUFHWmi, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16))<<P:Predicate_pshuflw>><<X:SHUFFLE_get_pshuflw_imm>>:$src2
- // Emits: (PSHUFLWmi:v8i16 addr:iPTR:$src1, (SHUFFLE_get_pshuflw_imm:i8 (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16)):$src2))
- // Pattern complexity = 32 cost = 1 size = 3
- if (Predicate_pshuflw(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_237(N, X86::PSHUFLWmi, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckl>>
- // Emits: (PUNPCKLWDrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PUNPCKLWDrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckh>>
- // Emits: (PUNPCKHWDrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PUNPCKHWDrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src, (undef:v8i16))<<P:Predicate_unpckl_undef>>
- // Emits: (PUNPCKLWDrr:v8i16 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckl_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKLWDrr, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src, (undef:v8i16))<<P:Predicate_unpckh_undef>>
- // Emits: (PUNPCKHWDrr:v8i16 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckh_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKHWDrr, MVT::v8i16);
- return Result;
- }
- }
- }
-
- // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)<<P:Predicate_palign>><<X:SHUFFLE_get_palign_imm>>:$src3
- // Emits: (PALIGNR128rr:v8i16 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_palign_imm:i8 VR128:i8:$src3))
- // Pattern complexity = 9 cost = 1 size = 3
- if ((Subtarget->hasSSSE3()) &&
- Predicate_palign(N)) {
- SDNode *Result = Emit_231(N, X86::PALIGNR128rr, MVT::v8i16);
- return Result;
- }
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, (undef:v8i16))<<P:Predicate_pshufhw>><<X:SHUFFLE_get_pshufhw_imm>>:$src2
- // Emits: (PSHUFHWri:v8i16 VR128:v8i16:$src1, (SHUFFLE_get_pshufhw_imm:i8 (vector_shuffle:v8i16 VR128:v8i16:$src1, (undef:v8i16)):$src2))
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_pshufhw(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_234(N, X86::PSHUFHWri, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, (undef:v8i16))<<P:Predicate_pshuflw>><<X:SHUFFLE_get_pshuflw_imm>>:$src2
- // Emits: (PSHUFLWri:v8i16 VR128:v8i16:$src1, (SHUFFLE_get_pshuflw_imm:i8 (vector_shuffle:v8i16 VR128:v8i16:$src1, (undef:v8i16)):$src2))
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_pshuflw(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_236(N, X86::PSHUFLWri, MVT::v8i16);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)<<P:Predicate_unpckl>>
- // Emits: (PUNPCKLWDrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDNode *Result = Emit_15(N, X86::PUNPCKLWDrr, MVT::v8i16);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)<<P:Predicate_unpckh>>
- // Emits: (PUNPCKHWDrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDNode *Result = Emit_15(N, X86::PUNPCKHWDrr, MVT::v8i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(SDNode *N) {
- if ((Subtarget->hasMMX())) {
-
- // Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckh>>
- // Emits: (MMX_PUNPCKHDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_mmx_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PUNPCKHDQrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>
- // Emits: (MMX_PUNPCKLDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_mmx_unpckl(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PUNPCKLDQrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src, (undef:v2i32))<<P:Predicate_mmx_unpckl_undef>>
- // Emits: (MMX_PUNPCKLDQrr:v2i32 VR64:v8i8:$src, VR64:v8i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_mmx_unpckl_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MMX_PUNPCKLDQrr, MVT::v2i32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src, (undef:v2i32))<<P:Predicate_mmx_unpckh_undef>>
- // Emits: (MMX_PUNPCKHDQrr:v2i32 VR64:v8i8:$src, VR64:v8i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_mmx_unpckh_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MMX_PUNPCKHDQrr, MVT::v2i32);
- return Result;
- }
- }
- if ((Subtarget->hasMMX())) {
-
- // Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)<<P:Predicate_mmx_unpckh>>
- // Emits: (MMX_PUNPCKHDQrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_mmx_unpckh(N)) {
- SDNode *Result = Emit_15(N, X86::MMX_PUNPCKHDQrr, MVT::v2i32);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)<<P:Predicate_mmx_unpckl>>
- // Emits: (MMX_PUNPCKLDQrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_mmx_unpckl(N)) {
- SDNode *Result = Emit_15(N, X86::MMX_PUNPCKLDQrr, MVT::v2i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_238(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_239(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Chain00 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp2 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp2, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_240(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_241(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Chain00 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_242(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_243(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(SDNode *N) {
- if ((Subtarget->hasSSE3())) {
-
- // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movshdup>>
- // Emits: (MOVSHDUPrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_movshdup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_241(N, X86::MOVSHDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movsldup>>
- // Emits: (MOVSLDUPrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_movsldup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_241(N, X86::MOVSLDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
- // Emits: (MOVLPSrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 46 cost = 1 size = 3
- if (Predicate_movlp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MOVLPSrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
- // Emits: (PSHUFDmi:v4i32 addr:iPTR:$src1, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32)):$src2))
- // Pattern complexity = 37 cost = 1 size = 3
- if (Predicate_pshufd(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_239(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 37 cost = 1 size = 3
- if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_241(N, X86::MOVDDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
- // Emits: (PSHUFDmi:v4i32 addr:iPTR:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
- // Pattern complexity = 32 cost = 1 size = 3
- if (Predicate_pshufd(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_239(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckl>>
- // Emits: (PUNPCKLDQrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PUNPCKLDQrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckh>>
- // Emits: (PUNPCKHDQrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PUNPCKHDQrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
- // Emits: (SHUFPSrmi:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_shufp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_243(N, X86::SHUFPSrmi, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src2)))<<P:Predicate_movlhps>>
- // Emits: (MOVHPSrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (Predicate_movlhps(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_240(N, X86::MOVHPSrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (undef:v4i32))<<P:Predicate_movhlps_undef>>
- // Emits: (MOVHLPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src1)
- // Pattern complexity = 27 cost = 1 size = 3
- if (Predicate_movhlps_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MOVHLPSrr, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_movlhps>>
- // Emits: (MOVLHPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 24 cost = 1 size = 3
- if (Predicate_movlhps(N)) {
- SDNode *Result = Emit_15(N, X86::MOVLHPSrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_movhlps>>
- // Emits: (MOVHLPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 24 cost = 1 size = 3
- if (Predicate_movhlps(N)) {
- SDNode *Result = Emit_15(N, X86::MOVHLPSrr, MVT::v4i32);
- return Result;
- }
- if ((Subtarget->hasSSE3())) {
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_movshdup>>
- // Emits: (MOVSHDUPrr:v4i32 VR128:v16i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_movshdup(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_93(N, X86::MOVSHDUPrr, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_movsldup>>
- // Emits: (MOVSLDUPrr:v4i32 VR128:v16i8:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_movsldup(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_93(N, X86::MOVSLDUPrr, MVT::v4i32);
- return Result;
- }
- }
- }
- if ((!OptForSize) && (Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_unpckl_undef>>:$src2
- // Emits: (PSHUFDri:v4i32 VR128:v16i8:$src, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_unpckl_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_238(N, X86::PSHUFDri, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_unpckh_undef>>:$src2
- // Emits: (PSHUFDri:v4i32 VR128:v16i8:$src, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_unpckh_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_238(N, X86::PSHUFDri, MVT::v4i32);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_movl>>
- // Emits: (MOVLPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 19 cost = 1 size = 3
- if (Predicate_movl(N)) {
- SDNode *Result = Emit_15(N, X86::MOVLPSrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_movlp>>
- // Emits: (MOVLPDrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 19 cost = 1 size = 3
- if (Predicate_movlp(N)) {
- SDNode *Result = Emit_15(N, X86::MOVLPDrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_unpckl_undef>>
- // Emits: (PUNPCKLDQrr:v4i32 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckl_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKLDQrr, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_unpckh_undef>>
- // Emits: (PUNPCKHDQrr:v4i32 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckh_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKHDQrr, MVT::v4i32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
- // Emits: (PSHUFDri:v4i32 VR128:v4i32:$src1, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i32 VR128:v4i32:$src1, (undef:v4i32)):$src2))
- // Pattern complexity = 12 cost = 1 size = 3
- if (Predicate_pshufd(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_238(N, X86::PSHUFDri, MVT::v4i32);
- return Result;
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_palign>><<X:SHUFFLE_get_palign_imm>>:$src3
- // Emits: (PALIGNR128rr:v4i32 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_palign_imm:i8 VR128:i8:$src3))
- // Pattern complexity = 9 cost = 1 size = 3
- if ((Subtarget->hasSSSE3()) &&
- Predicate_palign(N)) {
- SDNode *Result = Emit_231(N, X86::PALIGNR128rr, MVT::v4i32);
- return Result;
- }
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_unpckl>>
- // Emits: (PUNPCKLDQrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDNode *Result = Emit_15(N, X86::PUNPCKLDQrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_unpckh>>
- // Emits: (PUNPCKHDQrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDNode *Result = Emit_15(N, X86::PUNPCKHDQrr, MVT::v4i32);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
- // Emits: (SHUFPSrri:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_shufp(N)) {
- SDNode *Result = Emit_242(N, X86::SHUFPSrri, MVT::v4i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_244(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N100);
-}
-DISABLE_INLINE SDNode *Emit_245(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_246(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N0, Tmp3);
-}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(SDNode *N) {
-
- // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
- // Emits: (MOVLPDrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 46 cost = 1 size = 3
- if ((Subtarget->hasSSE2()) &&
- Predicate_movlp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MOVLPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v2i64))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 34 cost = 1 size = 3
- if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_245(N, X86::MOVDDUPrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src, (undef:v2i64))<<P:Predicate_movddup>>
- // Emits: (MOVLHPSrr:v2i64 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 27 cost = 1 size = 3
- if ((Subtarget->hasSSE1()) &&
- Predicate_movddup(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MOVLHPSrr, MVT::v2i64);
- return Result;
- }
- }
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
- // Emits: (PUNPCKLQDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PUNPCKLQDQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
- // Emits: (PUNPCKHQDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PUNPCKHQDQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_movl>>
- // Emits: (MOVLPDrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 19 cost = 1 size = 3
- if (Predicate_movl(N)) {
- SDNode *Result = Emit_15(N, X86::MOVLPDrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src, (undef:v2i64))<<P:Predicate_splat_lo>>
- // Emits: (PUNPCKLQDQrr:v2i64 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_splat_lo(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKLQDQrr, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src, (undef:v2i64))<<P:Predicate_unpckh>>
- // Emits: (PUNPCKHQDQrr:v2i64 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::PUNPCKHQDQrr, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v2i64 (build_vector:v2i64)<<P:Predicate_immAllZerosV>>, (scalar_to_vector:v2i64 (bitconvert:i64 VR64:v8i8:$src)))<<P:Predicate_movl>>
- // Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
- // Pattern complexity = 14 cost = 1 size = 3
- if (Predicate_movl(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllZerosV(N0.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::i64 &&
- N100.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_244(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (undef:v2i64))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src3
- // Emits: (SHUFPDrri:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_pshufd(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_246(N, X86::SHUFPDrri, MVT::v2i64);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_unpckl>>
- // Emits: (PUNPCKLQDQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDNode *Result = Emit_15(N, X86::PUNPCKLQDQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_unpckh>>
- // Emits: (PUNPCKHQDQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDNode *Result = Emit_15(N, X86::PUNPCKHQDQrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
- // Emits: (SHUFPDrri:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_shufp(N)) {
- SDNode *Result = Emit_242(N, X86::SHUFPDrri, MVT::v2i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_247(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue Chain100 = N100.getNode()->getOperand(0);
- SDValue N1001 = N100.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N100.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, Chain100 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N100.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_248(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Tmp3, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_249(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N0, Tmp3);
-}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (bitconvert:v4f32 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)))<<P:Predicate_movlp>>
- // Emits: (MOVLPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_movlp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadf64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2f64 &&
- N100.getValueType() == MVT::f64) {
- SDNode *Result = Emit_247(N, X86::MOVLPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (bitconvert:v4f32 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)))<<P:Predicate_movlhps>>
- // Emits: (MOVHPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_movlhps(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadf64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2f64 &&
- N100.getValueType() == MVT::f64) {
- SDNode *Result = Emit_247(N, X86::MOVHPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
- // Emits: (MOVLPSrm:v4f32 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 46 cost = 1 size = 3
- if (Predicate_movlp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MOVLPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 (bitconvert:v4f32 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4f32))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 37 cost = 1 size = 3
- if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_241(N, X86::MOVDDUPrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
- // Emits: (UNPCKHPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::UNPCKHPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
- // Emits: (UNPCKLPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::UNPCKLPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE3())) {
-
- // Pattern: (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v4f32))<<P:Predicate_movshdup>>
- // Emits: (MOVSHDUPrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_movshdup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_245(N, X86::MOVSHDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v4f32))<<P:Predicate_movsldup>>
- // Emits: (MOVSLDUPrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_movsldup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_245(N, X86::MOVSLDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_movddup>>
- // Emits: (MOVLHPSrr:v4f32 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 27 cost = 1 size = 3
- if ((Subtarget->hasSSE1()) &&
- Predicate_movddup(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MOVLHPSrr, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (undef:v4f32))<<P:Predicate_movhlps_undef>>
- // Emits: (MOVHLPSrr:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src1)
- // Pattern complexity = 27 cost = 1 size = 3
- if (Predicate_movhlps_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::MOVHLPSrr, MVT::v4f32);
- return Result;
- }
- }
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
- // Emits: (SHUFPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>):$src3))
- // Pattern complexity = 26 cost = 1 size = 3
- if (Predicate_shufp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_248(N, X86::SHUFPSrmi, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movlhps>>
- // Emits: (MOVLHPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 24 cost = 1 size = 3
- if (Predicate_movlhps(N)) {
- SDNode *Result = Emit_15(N, X86::MOVLHPSrr, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movhlps>>
- // Emits: (MOVHLPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 24 cost = 1 size = 3
- if (Predicate_movhlps(N)) {
- SDNode *Result = Emit_15(N, X86::MOVHLPSrr, MVT::v4f32);
- return Result;
- }
- }
- if ((!OptForSize) && (Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_unpckl_undef>>:$src2
- // Emits: (PSHUFDri:v4f32 VR128:v16i8:$src, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_unpckl_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_238(N, X86::PSHUFDri, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_unpckh_undef>>:$src2
- // Emits: (PSHUFDri:v4f32 VR128:v16i8:$src, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_unpckh_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_238(N, X86::PSHUFDri, MVT::v4f32);
- return Result;
- }
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movl>>
- // Emits: (MOVLPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 19 cost = 1 size = 3
- if ((Subtarget->hasSSE1()) &&
- Predicate_movl(N)) {
- SDNode *Result = Emit_15(N, X86::MOVLPSrr, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movlp>>
- // Emits: (MOVLPDrr:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 19 cost = 1 size = 3
- if ((Subtarget->hasSSE2()) &&
- Predicate_movlp(N)) {
- SDNode *Result = Emit_15(N, X86::MOVLPDrr, MVT::v4f32);
- return Result;
- }
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_unpckl_undef>>
- // Emits: (UNPCKLPSrr:v4f32 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckl_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::UNPCKLPSrr, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_unpckh_undef>>
- // Emits: (UNPCKHPSrr:v4f32 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckh_undef(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::UNPCKHPSrr, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_unpckh>>
- // Emits: (UNPCKHPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 14 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDNode *Result = Emit_15(N, X86::UNPCKHPSrr, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_unpckl>>
- // Emits: (UNPCKLPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 14 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDNode *Result = Emit_15(N, X86::UNPCKLPSrr, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (undef:v4f32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
- // Emits: (PSHUFDri:v4f32 VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
- // Pattern complexity = 12 cost = 1 size = 3
- if ((Subtarget->hasSSE2()) &&
- Predicate_pshufd(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_238(N, X86::PSHUFDri, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_palign>><<X:SHUFFLE_get_palign_imm>>:$src3
- // Emits: (PALIGNR128rr:v4f32 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_palign_imm:i8 VR128:i8:$src3))
- // Pattern complexity = 9 cost = 1 size = 3
- if ((Subtarget->hasSSSE3()) &&
- Predicate_palign(N)) {
- SDNode *Result = Emit_231(N, X86::PALIGNR128rr, MVT::v4f32);
- return Result;
- }
- if ((Subtarget->hasSSE3())) {
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_movshdup>>
- // Emits: (MOVSHDUPrr:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_movshdup(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_93(N, X86::MOVSHDUPrr, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_movsldup>>
- // Emits: (MOVSLDUPrr:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_movsldup(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_93(N, X86::MOVSLDUPrr, MVT::v4f32);
- return Result;
- }
- }
- }
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (undef:v4f32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src3
- // Emits: (SHUFPSrri:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_pshufd(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_246(N, X86::SHUFPSrri, MVT::v4f32);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
- // Emits: (SHUFPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2):$src3))
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_shufp(N)) {
- SDNode *Result = Emit_242(N, X86::SHUFPSrri, MVT::v4f32);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movlp>>:$src3
- // Emits: (SHUFPSrri:v4f32 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_movlp(N)) {
- SDNode *Result = Emit_249(N, X86::SHUFPSrri, MVT::v4f32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_250(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0001_0, SDValue &CPTmpN0001_1, SDValue &CPTmpN0001_2, SDValue &CPTmpN0001_3, SDValue &CPTmpN0001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue Chain000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N000.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4, Chain000 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N000.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))<<P:Predicate_movlp>>
- // Emits: (MOVLPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 49 cost = 1 size = 3
- if (Predicate_movlp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadf64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::f64) {
- SDNode *Result = Emit_16(N, X86::MOVLPDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))<<P:Predicate_movlhps>>
- // Emits: (MOVHPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 49 cost = 1 size = 3
- if (Predicate_movlhps(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadf64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::f64) {
- SDNode *Result = Emit_16(N, X86::MOVHPDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
- // Emits: (MOVLPDrm:v2f64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 46 cost = 1 size = 3
- if (Predicate_movlp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MOVLPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
- // Emits: (UNPCKHPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::UNPCKHPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
- // Emits: (UNPCKLPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::UNPCKLPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N)) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (vector_shuffle:v2f64 (bitconvert:v2f64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)), (undef:v2f64))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N00.hasOneUse()) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::LOAD &&
- N000.hasOneUse() &&
- IsLegalAndProfitableToFold(N000.getNode(), N00.getNode(), N)) {
- SDValue Chain000 = N000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N000.getNode()) &&
- Predicate_load(N000.getNode()) &&
- Predicate_loadi64(N000.getNode())) {
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue CPTmpN0001_0;
- SDValue CPTmpN0001_1;
- SDValue CPTmpN0001_2;
- SDValue CPTmpN0001_3;
- SDValue CPTmpN0001_4;
- if (SelectAddr(N, N0001, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2i64 &&
- N000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_250(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v2f64))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 34 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_245(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (vector_shuffle:v2f64 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>), (undef:v2f64))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_loadf64(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::f64) {
- SDNode *Result = Emit_241(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
- // Emits: (SHUFPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>):$src3))
- // Pattern complexity = 26 cost = 1 size = 3
- if (Predicate_shufp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_248(N, X86::SHUFPDrmi, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if (Predicate_movl(N)) {
-
- // Pattern: (vector_shuffle:v2f64 (bitconvert:v2f64)<<P:Predicate_immAllZerosV_bc>>, VR128:v2f64:$src)<<P:Predicate_movl>>
- // Emits: (MOVZPQILo2PQIrr:v2f64 VR128:v16i8:$src)
- // Pattern complexity = 23 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllZerosV_bc(N0.getNode())) {
- SDNode *Result = Emit_107(N, X86::MOVZPQILo2PQIrr, MVT::v2f64);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)<<P:Predicate_movl>>
- // Emits: (MOVLPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 19 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MOVLPDrr, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src, (undef:v2f64))<<P:Predicate_splat_lo>>
- // Emits: (UNPCKLPDrr:v2f64 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_splat_lo(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::UNPCKLPDrr, MVT::v2f64);
- return Result;
- }
- }
- if (Predicate_unpckh(N)) {
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src, (undef:v2f64))<<P:Predicate_unpckh>>
- // Emits: (UNPCKHPDrr:v2f64 VR128:v16i8:$src, VR128:v16i8:$src)
- // Pattern complexity = 17 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_161(N, X86::UNPCKHPDrr, MVT::v2f64);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)<<P:Predicate_unpckh>>
- // Emits: (UNPCKHPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 14 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::UNPCKHPDrr, MVT::v2f64);
- return Result;
- }
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)<<P:Predicate_unpckl>>
- // Emits: (UNPCKLPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 14 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDNode *Result = Emit_15(N, X86::UNPCKLPDrr, MVT::v2f64);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src, (undef:v2f64))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrr:v2f64 VR128:v2f64:$src)
- // Pattern complexity = 7 cost = 1 size = 3
- if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_93(N, X86::MOVDDUPrr, MVT::v2f64);
- return Result;
- }
- }
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (undef:v2f64))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src3
- // Emits: (SHUFPDrri:v2f64 VR128:v16i8:$src1, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_pshufd(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_246(N, X86::SHUFPDrri, MVT::v2f64);
- return Result;
- }
- }
-
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
- // Emits: (SHUFPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2):$src3))
- // Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_shufp(N)) {
- SDNode *Result = Emit_242(N, X86::SHUFPDrri, MVT::v2f64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_XOR_i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (xor:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (XOR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::XOR8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (xor:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src1)
- // Emits: (XOR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::XOR8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (xor:i8 GR8:i8:$src, (imm:i8)<<P:Predicate_immAllOnes>>)
- // Emits: (NOT8r:i8 GR8:i8:$src)
- // Pattern complexity = 22 cost = 1 size = 2
- if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_93(N, X86::NOT8r, MVT::i8);
- return Result;
- }
-
- // Pattern: (xor:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (XOR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_3(N, X86::XOR8ri, MVT::i8);
- return Result;
- }
- }
-
- // Pattern: (xor:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (XOR8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::XOR8rr, MVT::i8);
- return Result;
-}
-
-SDNode *Select_ISD_XOR_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (xor:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (XOR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::XOR16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (xor:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
- // Emits: (XOR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::XOR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (xor:i16 GR16:i16:$src, (imm:i16)<<P:Predicate_immAllOnes>>)
- // Emits: (NOT16r:i16 GR16:i16:$src)
- // Pattern complexity = 22 cost = 1 size = 2
- if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_93(N, X86::NOT16r, MVT::i16);
- return Result;
- }
-
- // Pattern: (xor:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (XOR16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::XOR16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (xor:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (XOR16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::XOR16ri, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (xor:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (XOR16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::XOR16rr, MVT::i16);
- return Result;
-}
-
-SDNode *Select_ISD_XOR_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (xor:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (XOR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::XOR32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (xor:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
- // Emits: (XOR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::XOR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (xor:i32 GR32:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
- // Emits: (NOT32r:i32 GR32:i32:$src)
- // Pattern complexity = 22 cost = 1 size = 2
- if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_93(N, X86::NOT32r, MVT::i32);
- return Result;
- }
-
- // Pattern: (xor:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (XOR32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::XOR32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (xor:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (XOR32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::XOR32ri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (xor:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (XOR32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::XOR32rr, MVT::i32);
- return Result;
-}
-
-SDNode *Select_ISD_XOR_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (xor:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (XOR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::XOR64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (xor:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
- // Emits: (XOR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::XOR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (xor:i64 GR64:i64:$src, (imm:i64)<<P:Predicate_immAllOnes>>)
- // Emits: (NOT64r:i64 GR64:i64:$src)
- // Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_93(N, X86::NOT64r, MVT::i64);
- return Result;
- }
-
- // Pattern: (xor:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (XOR64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::XOR64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (xor:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (XOR64ri32:i64 GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::XOR64ri32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (xor:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (XOR64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::XOR64rr, MVT::i64);
- return Result;
-}
-
-SDNode *Select_ISD_XOR_v1i64(SDNode *N) {
- if ((Subtarget->hasMMX())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (xor:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PXORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MMX_PXORrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (xor:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
- // Emits: (MMX_PXORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MMX_PXORrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (xor:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PXORrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PXORrr, MVT::v1i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_XOR_v2i64(SDNode *N) {
-
- // Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (XORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_57(N, X86::XORPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (XORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_57(N, X86::XORPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v4f32:$src1))
- // Emits: (XORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_62(N, X86::XORPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
- // Emits: (XORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_62(N, X86::XORPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (xor:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PXORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PXORrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
- // Emits: (PXORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PXORrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (bitconvert:v2i64 VR128:v2f64:$src2))
- // Emits: (XORPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N00.getValueType() == MVT::v2f64 &&
- N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_59(N, X86::XORPDrr, MVT::v2i64);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (xor:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (XORPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_15(N, X86::XORPSrr, MVT::v2i64);
- return Result;
- }
-
- // Pattern: (xor:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PXORrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDNode *Result = Emit_15(N, X86::PXORrr, MVT::v2i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ZERO_EXTEND_i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_72(N, X86::MOVZX16rr8, MVT::i16);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ZERO_EXTEND_i32(SDNode *N) {
-
- // Pattern: (zext:i32 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
- // Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
- // Pattern complexity = 12 cost = 3 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRL &&
- Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8) &&
- N0.getValueType() == MVT::i16 &&
- N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_74(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i16, MVT::i8, MVT::i32);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (zext:i32 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
- // Emits: (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
- // Pattern complexity = 12 cost = 3 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SRL &&
- Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8) &&
- N0.getValueType() == MVT::i16 &&
- N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_74(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i16, MVT::i8, MVT::i32);
- return Result;
- }
- }
- }
- }
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (zext:i32 GR8:i8:$src)
- // Emits: (MOVZX32rr8:i32 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_72(N, X86::MOVZX32rr8, MVT::i32);
- return Result;
- }
-
- // Pattern: (zext:i32 GR16:i16:$src)
- // Emits: (MOVZX32rr16:i32 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_72(N, X86::MOVZX32rr16, MVT::i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_ZERO_EXTEND_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (zext:i64 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
- // Emits: (SUBREG_TO_REG:i64 0:i64, (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 4:i32)
- // Pattern complexity = 12 cost = 4 size = 3
- if (N0.getNode()->getOpcode() == ISD::SRL &&
- Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8) &&
- N0.getValueType() == MVT::i16 &&
- N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_76(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetOpcode::SUBREG_TO_REG, MVT::i16, MVT::i8, MVT::i32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (zext:i64 GR32:i32<<P:Predicate_def32>>:$src)
- // Emits: (SUBREG_TO_REG:i64 0:i64, GR32:i32:$src, 4:i32)
- // Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_def32(N0.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_75(N, TargetOpcode::SUBREG_TO_REG, MVT::i64);
- return Result;
- }
-
- // Pattern: (zext:i64 GR8:i8:$src)
- // Emits: (MOVZX64rr8:i64 GR8:i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_72(N, X86::MOVZX64rr8, MVT::i64);
- return Result;
- }
-
- // Pattern: (zext:i64 GR16:i16:$src)
- // Emits: (MOVZX64rr16:i64 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_72(N, X86::MOVZX64rr16, MVT::i64);
- return Result;
- }
-
- // Pattern: (zext:i64 GR32:i32:$src)
- // Emits: (MOVZX64rr32:i64 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_72(N, X86::MOVZX64rr32, MVT::i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_ADD_i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86add_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (ADD8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::ADD8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86add_flag:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1)
- // Emits: (ADD8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi8(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::ADD8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (X86add_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (ADD8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_3(N, X86::ADD8ri, MVT::i8);
- return Result;
- }
- }
-
- // Pattern: (X86add_flag:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (ADD8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::ADD8rr, MVT::i8);
- return Result;
-}
-
-SDNode *Select_X86ISD_ADD_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86add_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (ADD16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::ADD16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86add_flag:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
- // Emits: (ADD16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::ADD16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86add_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (ADD16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::ADD16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86add_flag:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (ADD16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::ADD16ri, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (X86add_flag:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (ADD16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::ADD16rr, MVT::i16);
- return Result;
-}
-
-SDNode *Select_X86ISD_ADD_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86add_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::ADD32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86add_flag:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
- // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::ADD32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86add_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (ADD32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::ADD32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86add_flag:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (ADD32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::ADD32ri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (X86add_flag:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::ADD32rr, MVT::i32);
- return Result;
-}
-
-SDNode *Select_X86ISD_ADD_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86add_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::ADD64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86add_flag:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1)
- // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::ADD64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86add_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (ADD64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::ADD64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86add_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (ADD64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::ADD64ri32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (X86add_flag:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (ADD64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::ADD64rr, MVT::i64);
- return Result;
-}
-
-SDNode *Select_X86ISD_AND_i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86and_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (AND8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::AND8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86and_flag:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1)
- // Emits: (AND8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi8(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::AND8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (X86and_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (AND8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_3(N, X86::AND8ri, MVT::i8);
- return Result;
- }
- }
-
- // Pattern: (X86and_flag:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (AND8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::AND8rr, MVT::i8);
- return Result;
-}
-
-SDNode *Select_X86ISD_AND_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86and_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (AND16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::AND16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86and_flag:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
- // Emits: (AND16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::AND16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86and_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (AND16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::AND16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86and_flag:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (AND16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::AND16ri, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (X86and_flag:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (AND16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::AND16rr, MVT::i16);
- return Result;
-}
-
-SDNode *Select_X86ISD_AND_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86and_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (AND32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::AND32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86and_flag:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
- // Emits: (AND32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::AND32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86and_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (AND32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::AND32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86and_flag:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (AND32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::AND32ri, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (X86and_flag:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (AND32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::AND32rr, MVT::i32);
- return Result;
-}
-
-SDNode *Select_X86ISD_AND_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86and_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (AND64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::AND64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86and_flag:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1)
- // Emits: (AND64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::AND64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86and_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (AND64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::AND64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86and_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (AND64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::AND64ri32, MVT::i64);
- return Result;
- }
- }
- }
-
- // Pattern: (X86and_flag:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (AND64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::AND64rr, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_251(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, N1, Chain, InFlag);
-}
-SDNode *Select_X86ISD_BRCOND(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 13:i8, EFLAGS:i32)
- // Emits: (JO_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_251(N, X86::JO_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 10:i8, EFLAGS:i32)
- // Emits: (JNO_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_251(N, X86::JNO_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 2:i8, EFLAGS:i32)
- // Emits: (JB_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_251(N, X86::JB_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 1:i8, EFLAGS:i32)
- // Emits: (JAE_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_251(N, X86::JAE_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 4:i8, EFLAGS:i32)
- // Emits: (JE_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_251(N, X86::JE_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 9:i8, EFLAGS:i32)
- // Emits: (JNE_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_251(N, X86::JNE_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 3:i8, EFLAGS:i32)
- // Emits: (JBE_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_251(N, X86::JBE_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 0:i8, EFLAGS:i32)
- // Emits: (JA_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_251(N, X86::JA_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 15:i8, EFLAGS:i32)
- // Emits: (JS_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_251(N, X86::JS_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 12:i8, EFLAGS:i32)
- // Emits: (JNS_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_251(N, X86::JNS_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 14:i8, EFLAGS:i32)
- // Emits: (JP_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_251(N, X86::JP_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 11:i8, EFLAGS:i32)
- // Emits: (JNP_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_251(N, X86::JNP_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 7:i8, EFLAGS:i32)
- // Emits: (JL_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_251(N, X86::JL_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 6:i8, EFLAGS:i32)
- // Emits: (JGE_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_251(N, X86::JGE_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 8:i8, EFLAGS:i32)
- // Emits: (JLE_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_251(N, X86::JLE_4);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 5:i8, EFLAGS:i32)
- // Emits: (JG_4:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_251(N, X86::JG_4);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_252(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0);
-}
-DISABLE_INLINE SDNode *Emit_253(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
- return ResNode;
-}
-SDNode *Select_X86ISD_BSF_i16(SDNode *N) {
-
- // Pattern: (X86bsf:i16 (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (BSF16rm:i16 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_253(N, X86::BSF16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86bsf:i16 GR16:i16:$src)
- // Emits: (BSF16rr:i16 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_252(N, X86::BSF16rr, MVT::i16);
- return Result;
-}
-
-SDNode *Select_X86ISD_BSF_i32(SDNode *N) {
-
- // Pattern: (X86bsf:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (BSF32rm:i32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_253(N, X86::BSF32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86bsf:i32 GR32:i32:$src)
- // Emits: (BSF32rr:i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_252(N, X86::BSF32rr, MVT::i32);
- return Result;
-}
-
-SDNode *Select_X86ISD_BSF_i64(SDNode *N) {
-
- // Pattern: (X86bsf:i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (BSF64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_253(N, X86::BSF64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86bsf:i64 GR64:i64:$src)
- // Emits: (BSF64rr:i64 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_252(N, X86::BSF64rr, MVT::i64);
- return Result;
-}
-
-SDNode *Select_X86ISD_BSR_i16(SDNode *N) {
-
- // Pattern: (X86bsr:i16 (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (BSR16rm:i16 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_253(N, X86::BSR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86bsr:i16 GR16:i16:$src)
- // Emits: (BSR16rr:i16 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_252(N, X86::BSR16rr, MVT::i16);
- return Result;
-}
-
-SDNode *Select_X86ISD_BSR_i32(SDNode *N) {
-
- // Pattern: (X86bsr:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (BSR32rm:i32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_253(N, X86::BSR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86bsr:i32 GR32:i32:$src)
- // Emits: (BSR32rr:i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_252(N, X86::BSR32rr, MVT::i32);
- return Result;
-}
-
-SDNode *Select_X86ISD_BSR_i64(SDNode *N) {
-
- // Pattern: (X86bsr:i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (BSR64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_253(N, X86::BSR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86bsr:i64 GR64:i64:$src)
- // Emits: (BSR64rr:i64 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_252(N, X86::BSR64rr, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_254(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, N1);
-}
-DISABLE_INLINE SDNode *Emit_255(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_256(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_257(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_258(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_259(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_260(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_X86ISD_BT(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode())) {
-
- // Pattern: (X86bt:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (BT16mi8:isVoid addr:iPTR:$src1, (imm:i16):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_257(N, X86::BT16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (X86bt:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (BT32mi8:isVoid addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_258(N, X86::BT32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (X86bt:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (BT64mi8:isVoid addr:iPTR:$src1, (imm:i64):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_260(N, X86::BT64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86bt:isVoid GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (BT16ri8:isVoid GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_255(N, X86::BT16ri8);
- return Result;
- }
-
- // Pattern: (X86bt:isVoid GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (BT32ri8:isVoid GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_256(N, X86::BT32ri8);
- return Result;
- }
-
- // Pattern: (X86bt:isVoid GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (BT64ri8:isVoid GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_259(N, X86::BT64ri8);
- return Result;
- }
- }
-
- // Pattern: (X86bt:isVoid GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (BT16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_254(N, X86::BT16rr);
- return Result;
- }
-
- // Pattern: (X86bt:isVoid GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (BT32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_254(N, X86::BT32rr);
- return Result;
- }
-
- // Pattern: (X86bt:isVoid GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (BT64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_254(N, X86::BT64rr);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_261(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(N1);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_262(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N1.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain1);
- Chain1 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(CPTmpN11_0);
- Ops0.push_back(CPTmpN11_1);
- Ops0.push_back(CPTmpN11_2);
- Ops0.push_back(CPTmpN11_3);
- Ops0.push_back(CPTmpN11_4);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- Ops0.push_back(Chain1);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
- Chain1 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N1.getNode(), 1),
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- InFlag,
- SDValue(Chain1.getNode(), Chain1.getResNo())
- };
- ReplaceUses(Froms, Tos, 3);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_263(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(Tmp0);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_X86ISD_CALL(SDNode *N) {
-
- // Pattern: (X86call:isVoid (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (CALL32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N) &&
- (Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, X86::CALL32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86call:isVoid (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (CALL64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((!Subtarget->isTargetWin64())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N) &&
- (Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_262(N, X86::CALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86call:isVoid (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (WINCALL64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->isTargetWin64())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N) &&
- (Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_262(N, X86::WINCALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
- return Result;
- }
- }
- }
- }
- if ((!Subtarget->isTargetWin64())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86call:isVoid (tglobaladdr:i64):$dst)
- // Emits: (CALL64pcrel32:isVoid (tglobaladdr:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_261(N, X86::CALL64pcrel32, 1);
- return Result;
- }
-
- // Pattern: (X86call:isVoid (texternalsym:i64):$dst)
- // Emits: (CALL64pcrel32:isVoid (texternalsym:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_261(N, X86::CALL64pcrel32, 1);
- return Result;
- }
- }
- if ((Subtarget->isTargetWin64())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86call:isVoid (tglobaladdr:i64):$dst)
- // Emits: (WINCALL64pcrel32:isVoid (tglobaladdr:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_261(N, X86::WINCALL64pcrel32, 1);
- return Result;
- }
-
- // Pattern: (X86call:isVoid (texternalsym:i64):$dst)
- // Emits: (WINCALL64pcrel32:isVoid (texternalsym:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_261(N, X86::WINCALL64pcrel32, 1);
- return Result;
- }
- }
- {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86call:isVoid (tglobaladdr:i32):$dst)
- // Emits: (CALLpcrel32:isVoid (tglobaladdr:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_261(N, X86::CALLpcrel32, 1);
- return Result;
- }
-
- // Pattern: (X86call:isVoid (texternalsym:i32):$dst)
- // Emits: (CALLpcrel32:isVoid (texternalsym:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_261(N, X86::CALLpcrel32, 1);
- return Result;
- }
- }
-
- // Pattern: (X86call:isVoid (imm:i32):$dst)
- // Emits: (CALLpcrel32:isVoid (imm:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((Subtarget->IsLegalToCallImmediateAddr(TM))) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_263(N, X86::CALLpcrel32, 1);
- return Result;
- }
- }
-
- // Pattern: (X86call:isVoid GR32:i32:$dst)
- // Emits: (CALL32r:isVoid GR32:i32:$dst)
- // Pattern complexity = 3 cost = 1 size = 3
- {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_261(N, X86::CALL32r, 1);
- return Result;
- }
- }
-
- // Pattern: (X86call:isVoid GR64:i64:$dst)
- // Emits: (CALL64r:isVoid GR64:i64:$dst)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((!Subtarget->isTargetWin64())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_261(N, X86::CALL64r, 1);
- return Result;
- }
- }
-
- // Pattern: (X86call:isVoid GR64:i64:$dst)
- // Emits: (WINCALL64r:isVoid GR64:i64:$dst)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->isTargetWin64())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_261(N, X86::WINCALL64r, 1);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_264(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i8);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- SDValue Ops0[] = { N0, N1, Tmp2, InFlag };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
-}
-SDNode *Select_X86ISD_CMOV_i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_264(N, X86::CMOV_GR8, MVT::i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_265(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_266(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain1, N->getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
- Chain1 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_267(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain0, N->getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
- Chain0 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0, InFlag };
- ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 2:i8, EFLAGS:i32)
- // Emits: (CMOVB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_266(N, X86::CMOVB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8, EFLAGS:i32)
- // Emits: (CMOVAE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_266(N, X86::CMOVAE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 4:i8, EFLAGS:i32)
- // Emits: (CMOVE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_266(N, X86::CMOVE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 9:i8, EFLAGS:i32)
- // Emits: (CMOVNE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_266(N, X86::CMOVNE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 3:i8, EFLAGS:i32)
- // Emits: (CMOVBE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_266(N, X86::CMOVBE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 0:i8, EFLAGS:i32)
- // Emits: (CMOVA16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_266(N, X86::CMOVA16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 7:i8, EFLAGS:i32)
- // Emits: (CMOVL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_266(N, X86::CMOVL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 6:i8, EFLAGS:i32)
- // Emits: (CMOVGE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_266(N, X86::CMOVGE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 8:i8, EFLAGS:i32)
- // Emits: (CMOVLE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_266(N, X86::CMOVLE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 5:i8, EFLAGS:i32)
- // Emits: (CMOVG16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_266(N, X86::CMOVG16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 15:i8, EFLAGS:i32)
- // Emits: (CMOVS16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_266(N, X86::CMOVS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 12:i8, EFLAGS:i32)
- // Emits: (CMOVNS16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_266(N, X86::CMOVNS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 14:i8, EFLAGS:i32)
- // Emits: (CMOVP16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_266(N, X86::CMOVP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 11:i8, EFLAGS:i32)
- // Emits: (CMOVNP16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_266(N, X86::CMOVNP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 13:i8, EFLAGS:i32)
- // Emits: (CMOVO16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_266(N, X86::CMOVO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 10:i8, EFLAGS:i32)
- // Emits: (CMOVNO16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_266(N, X86::CMOVNO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 6:i8, EFLAGS:i32)
- // Emits: (CMOVL16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_267(N, X86::CMOVL16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 8:i8, EFLAGS:i32)
- // Emits: (CMOVG16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_267(N, X86::CMOVG16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 5:i8, EFLAGS:i32)
- // Emits: (CMOVLE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_267(N, X86::CMOVLE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 14:i8, EFLAGS:i32)
- // Emits: (CMOVNP16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_267(N, X86::CMOVNP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 11:i8, EFLAGS:i32)
- // Emits: (CMOVP16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_267(N, X86::CMOVP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 15:i8, EFLAGS:i32)
- // Emits: (CMOVNS16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_267(N, X86::CMOVNS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 12:i8, EFLAGS:i32)
- // Emits: (CMOVS16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_267(N, X86::CMOVS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 13:i8, EFLAGS:i32)
- // Emits: (CMOVNO16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_267(N, X86::CMOVNO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 10:i8, EFLAGS:i32)
- // Emits: (CMOVO16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_267(N, X86::CMOVO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 2:i8, EFLAGS:i32)
- // Emits: (CMOVAE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_267(N, X86::CMOVAE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 1:i8, EFLAGS:i32)
- // Emits: (CMOVB16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_267(N, X86::CMOVB16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 4:i8, EFLAGS:i32)
- // Emits: (CMOVNE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_267(N, X86::CMOVNE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 9:i8, EFLAGS:i32)
- // Emits: (CMOVE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_267(N, X86::CMOVE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 3:i8, EFLAGS:i32)
- // Emits: (CMOVA16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_267(N, X86::CMOVA16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 0:i8, EFLAGS:i32)
- // Emits: (CMOVBE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_267(N, X86::CMOVBE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 7:i8, EFLAGS:i32)
- // Emits: (CMOVGE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_267(N, X86::CMOVGE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 2:i8, EFLAGS:i32)
- // Emits: (CMOVB16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_265(N, X86::CMOVB16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 1:i8, EFLAGS:i32)
- // Emits: (CMOVAE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_265(N, X86::CMOVAE16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 4:i8, EFLAGS:i32)
- // Emits: (CMOVE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_265(N, X86::CMOVE16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 9:i8, EFLAGS:i32)
- // Emits: (CMOVNE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_265(N, X86::CMOVNE16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 3:i8, EFLAGS:i32)
- // Emits: (CMOVBE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_265(N, X86::CMOVBE16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 0:i8, EFLAGS:i32)
- // Emits: (CMOVA16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_265(N, X86::CMOVA16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 7:i8, EFLAGS:i32)
- // Emits: (CMOVL16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_265(N, X86::CMOVL16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 6:i8, EFLAGS:i32)
- // Emits: (CMOVGE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_265(N, X86::CMOVGE16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 8:i8, EFLAGS:i32)
- // Emits: (CMOVLE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_265(N, X86::CMOVLE16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 5:i8, EFLAGS:i32)
- // Emits: (CMOVG16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_265(N, X86::CMOVG16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 15:i8, EFLAGS:i32)
- // Emits: (CMOVS16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_265(N, X86::CMOVS16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 12:i8, EFLAGS:i32)
- // Emits: (CMOVNS16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_265(N, X86::CMOVNS16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 14:i8, EFLAGS:i32)
- // Emits: (CMOVP16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_265(N, X86::CMOVP16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 11:i8, EFLAGS:i32)
- // Emits: (CMOVNP16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_265(N, X86::CMOVNP16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 13:i8, EFLAGS:i32)
- // Emits: (CMOVO16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_265(N, X86::CMOVO16rr, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, GR16:i16:$src2, 10:i8, EFLAGS:i32)
- // Emits: (CMOVNO16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_265(N, X86::CMOVNO16rr, MVT::i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 2:i8, EFLAGS:i32)
- // Emits: (CMOVB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_266(N, X86::CMOVB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8, EFLAGS:i32)
- // Emits: (CMOVAE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_266(N, X86::CMOVAE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 4:i8, EFLAGS:i32)
- // Emits: (CMOVE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_266(N, X86::CMOVE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 9:i8, EFLAGS:i32)
- // Emits: (CMOVNE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_266(N, X86::CMOVNE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 3:i8, EFLAGS:i32)
- // Emits: (CMOVBE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_266(N, X86::CMOVBE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 0:i8, EFLAGS:i32)
- // Emits: (CMOVA32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_266(N, X86::CMOVA32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 7:i8, EFLAGS:i32)
- // Emits: (CMOVL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_266(N, X86::CMOVL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 6:i8, EFLAGS:i32)
- // Emits: (CMOVGE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_266(N, X86::CMOVGE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 8:i8, EFLAGS:i32)
- // Emits: (CMOVLE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_266(N, X86::CMOVLE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 5:i8, EFLAGS:i32)
- // Emits: (CMOVG32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_266(N, X86::CMOVG32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 15:i8, EFLAGS:i32)
- // Emits: (CMOVS32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_266(N, X86::CMOVS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 12:i8, EFLAGS:i32)
- // Emits: (CMOVNS32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_266(N, X86::CMOVNS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 14:i8, EFLAGS:i32)
- // Emits: (CMOVP32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_266(N, X86::CMOVP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 11:i8, EFLAGS:i32)
- // Emits: (CMOVNP32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_266(N, X86::CMOVNP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 13:i8, EFLAGS:i32)
- // Emits: (CMOVO32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_266(N, X86::CMOVO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 10:i8, EFLAGS:i32)
- // Emits: (CMOVNO32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_266(N, X86::CMOVNO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 6:i8, EFLAGS:i32)
- // Emits: (CMOVL32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_267(N, X86::CMOVL32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 8:i8, EFLAGS:i32)
- // Emits: (CMOVG32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_267(N, X86::CMOVG32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 5:i8, EFLAGS:i32)
- // Emits: (CMOVLE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_267(N, X86::CMOVLE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 14:i8, EFLAGS:i32)
- // Emits: (CMOVNP32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_267(N, X86::CMOVNP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 11:i8, EFLAGS:i32)
- // Emits: (CMOVP32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_267(N, X86::CMOVP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 15:i8, EFLAGS:i32)
- // Emits: (CMOVNS32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_267(N, X86::CMOVNS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 12:i8, EFLAGS:i32)
- // Emits: (CMOVS32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_267(N, X86::CMOVS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 13:i8, EFLAGS:i32)
- // Emits: (CMOVNO32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_267(N, X86::CMOVNO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 10:i8, EFLAGS:i32)
- // Emits: (CMOVO32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_267(N, X86::CMOVO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 2:i8, EFLAGS:i32)
- // Emits: (CMOVAE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_267(N, X86::CMOVAE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 1:i8, EFLAGS:i32)
- // Emits: (CMOVB32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_267(N, X86::CMOVB32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 4:i8, EFLAGS:i32)
- // Emits: (CMOVNE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_267(N, X86::CMOVNE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 9:i8, EFLAGS:i32)
- // Emits: (CMOVE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_267(N, X86::CMOVE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 3:i8, EFLAGS:i32)
- // Emits: (CMOVA32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_267(N, X86::CMOVA32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 0:i8, EFLAGS:i32)
- // Emits: (CMOVBE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_267(N, X86::CMOVBE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 7:i8, EFLAGS:i32)
- // Emits: (CMOVGE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_267(N, X86::CMOVGE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 2:i8, EFLAGS:i32)
- // Emits: (CMOVB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_265(N, X86::CMOVB32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 1:i8, EFLAGS:i32)
- // Emits: (CMOVAE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_265(N, X86::CMOVAE32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 4:i8, EFLAGS:i32)
- // Emits: (CMOVE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_265(N, X86::CMOVE32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 9:i8, EFLAGS:i32)
- // Emits: (CMOVNE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_265(N, X86::CMOVNE32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 3:i8, EFLAGS:i32)
- // Emits: (CMOVBE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_265(N, X86::CMOVBE32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 0:i8, EFLAGS:i32)
- // Emits: (CMOVA32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_265(N, X86::CMOVA32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 7:i8, EFLAGS:i32)
- // Emits: (CMOVL32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_265(N, X86::CMOVL32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 6:i8, EFLAGS:i32)
- // Emits: (CMOVGE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_265(N, X86::CMOVGE32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 8:i8, EFLAGS:i32)
- // Emits: (CMOVLE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_265(N, X86::CMOVLE32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 5:i8, EFLAGS:i32)
- // Emits: (CMOVG32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_265(N, X86::CMOVG32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 15:i8, EFLAGS:i32)
- // Emits: (CMOVS32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_265(N, X86::CMOVS32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 12:i8, EFLAGS:i32)
- // Emits: (CMOVNS32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_265(N, X86::CMOVNS32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 14:i8, EFLAGS:i32)
- // Emits: (CMOVP32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_265(N, X86::CMOVP32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 11:i8, EFLAGS:i32)
- // Emits: (CMOVNP32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_265(N, X86::CMOVNP32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 13:i8, EFLAGS:i32)
- // Emits: (CMOVO32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_265(N, X86::CMOVO32rr, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, GR32:i32:$src2, 10:i8, EFLAGS:i32)
- // Emits: (CMOVNO32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_265(N, X86::CMOVNO32rr, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 2:i8, EFLAGS:i32)
- // Emits: (CMOVB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_266(N, X86::CMOVB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8, EFLAGS:i32)
- // Emits: (CMOVAE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_266(N, X86::CMOVAE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 4:i8, EFLAGS:i32)
- // Emits: (CMOVE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_266(N, X86::CMOVE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 9:i8, EFLAGS:i32)
- // Emits: (CMOVNE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_266(N, X86::CMOVNE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 3:i8, EFLAGS:i32)
- // Emits: (CMOVBE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_266(N, X86::CMOVBE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 0:i8, EFLAGS:i32)
- // Emits: (CMOVA64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_266(N, X86::CMOVA64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 7:i8, EFLAGS:i32)
- // Emits: (CMOVL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_266(N, X86::CMOVL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 6:i8, EFLAGS:i32)
- // Emits: (CMOVGE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_266(N, X86::CMOVGE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 8:i8, EFLAGS:i32)
- // Emits: (CMOVLE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_266(N, X86::CMOVLE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 5:i8, EFLAGS:i32)
- // Emits: (CMOVG64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_266(N, X86::CMOVG64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 15:i8, EFLAGS:i32)
- // Emits: (CMOVS64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_266(N, X86::CMOVS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 12:i8, EFLAGS:i32)
- // Emits: (CMOVNS64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_266(N, X86::CMOVNS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 14:i8, EFLAGS:i32)
- // Emits: (CMOVP64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_266(N, X86::CMOVP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 11:i8, EFLAGS:i32)
- // Emits: (CMOVNP64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_266(N, X86::CMOVNP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 13:i8, EFLAGS:i32)
- // Emits: (CMOVO64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_266(N, X86::CMOVO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 10:i8, EFLAGS:i32)
- // Emits: (CMOVNO64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_266(N, X86::CMOVNO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 2:i8, EFLAGS:i32)
- // Emits: (CMOVAE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_267(N, X86::CMOVAE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 1:i8, EFLAGS:i32)
- // Emits: (CMOVB64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_267(N, X86::CMOVB64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 4:i8, EFLAGS:i32)
- // Emits: (CMOVNE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_267(N, X86::CMOVNE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 9:i8, EFLAGS:i32)
- // Emits: (CMOVE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_267(N, X86::CMOVE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 3:i8, EFLAGS:i32)
- // Emits: (CMOVA64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_267(N, X86::CMOVA64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 0:i8, EFLAGS:i32)
- // Emits: (CMOVBE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_267(N, X86::CMOVBE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 7:i8, EFLAGS:i32)
- // Emits: (CMOVGE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_267(N, X86::CMOVGE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 6:i8, EFLAGS:i32)
- // Emits: (CMOVL64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_267(N, X86::CMOVL64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 8:i8, EFLAGS:i32)
- // Emits: (CMOVG64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_267(N, X86::CMOVG64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 5:i8, EFLAGS:i32)
- // Emits: (CMOVLE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_267(N, X86::CMOVLE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 14:i8, EFLAGS:i32)
- // Emits: (CMOVNP64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_267(N, X86::CMOVNP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 11:i8, EFLAGS:i32)
- // Emits: (CMOVP64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_267(N, X86::CMOVP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 15:i8, EFLAGS:i32)
- // Emits: (CMOVNS64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_267(N, X86::CMOVNS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 12:i8, EFLAGS:i32)
- // Emits: (CMOVS64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_267(N, X86::CMOVS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 13:i8, EFLAGS:i32)
- // Emits: (CMOVNO64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_267(N, X86::CMOVNO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 10:i8, EFLAGS:i32)
- // Emits: (CMOVO64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_267(N, X86::CMOVO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 2:i8, EFLAGS:i32)
- // Emits: (CMOVB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_265(N, X86::CMOVB64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 1:i8, EFLAGS:i32)
- // Emits: (CMOVAE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_265(N, X86::CMOVAE64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 4:i8, EFLAGS:i32)
- // Emits: (CMOVE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_265(N, X86::CMOVE64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 9:i8, EFLAGS:i32)
- // Emits: (CMOVNE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_265(N, X86::CMOVNE64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 3:i8, EFLAGS:i32)
- // Emits: (CMOVBE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_265(N, X86::CMOVBE64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 0:i8, EFLAGS:i32)
- // Emits: (CMOVA64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_265(N, X86::CMOVA64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 7:i8, EFLAGS:i32)
- // Emits: (CMOVL64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_265(N, X86::CMOVL64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 6:i8, EFLAGS:i32)
- // Emits: (CMOVGE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_265(N, X86::CMOVGE64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 8:i8, EFLAGS:i32)
- // Emits: (CMOVLE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_265(N, X86::CMOVLE64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 5:i8, EFLAGS:i32)
- // Emits: (CMOVG64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_265(N, X86::CMOVG64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 15:i8, EFLAGS:i32)
- // Emits: (CMOVS64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_265(N, X86::CMOVS64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 12:i8, EFLAGS:i32)
- // Emits: (CMOVNS64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_265(N, X86::CMOVNS64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 14:i8, EFLAGS:i32)
- // Emits: (CMOVP64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_265(N, X86::CMOVP64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 11:i8, EFLAGS:i32)
- // Emits: (CMOVNP64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_265(N, X86::CMOVNP64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 13:i8, EFLAGS:i32)
- // Emits: (CMOVO64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_265(N, X86::CMOVO64rr, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, GR64:i64:$src2, 10:i8, EFLAGS:i32)
- // Emits: (CMOVNO64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_265(N, X86::CMOVNO64rr, MVT::i64);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_CMOV_f32(SDNode *N) {
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 2:i8, EFLAGS:i32)
- // Emits: (CMOVB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_265(N, X86::CMOVB_Fp32, MVT::f32);
- return Result;
- }
-
- // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 3:i8, EFLAGS:i32)
- // Emits: (CMOVBE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_265(N, X86::CMOVBE_Fp32, MVT::f32);
- return Result;
- }
-
- // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 4:i8, EFLAGS:i32)
- // Emits: (CMOVE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_265(N, X86::CMOVE_Fp32, MVT::f32);
- return Result;
- }
-
- // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 14:i8, EFLAGS:i32)
- // Emits: (CMOVP_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_265(N, X86::CMOVP_Fp32, MVT::f32);
- return Result;
- }
-
- // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 1:i8, EFLAGS:i32)
- // Emits: (CMOVNB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_265(N, X86::CMOVNB_Fp32, MVT::f32);
- return Result;
- }
-
- // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 0:i8, EFLAGS:i32)
- // Emits: (CMOVNBE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_265(N, X86::CMOVNBE_Fp32, MVT::f32);
- return Result;
- }
-
- // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 9:i8, EFLAGS:i32)
- // Emits: (CMOVNE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_265(N, X86::CMOVNE_Fp32, MVT::f32);
- return Result;
- }
-
- // Pattern: (X86cmov:f32 RFP32:f32:$src1, RFP32:f32:$src2, 11:i8, EFLAGS:i32)
- // Emits: (CMOVNP_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_265(N, X86::CMOVNP_Fp32, MVT::f32);
- return Result;
- }
- }
- }
-
- // Pattern: (X86cmov:f32 FR32:f32:$t, FR32:f32:$f, (imm:i8):$cond, EFLAGS:i32)
- // Emits: (CMOV_FR32:f32 FR32:f32:$t, FR32:f32:$f, (imm:i8):$cond)
- // Pattern complexity = 6 cost = 11 size = 3
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_264(N, X86::CMOV_FR32, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_CMOV_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 2:i8, EFLAGS:i32)
- // Emits: (CMOVB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_265(N, X86::CMOVB_Fp64, MVT::f64);
- return Result;
- }
-
- // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 3:i8, EFLAGS:i32)
- // Emits: (CMOVBE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_265(N, X86::CMOVBE_Fp64, MVT::f64);
- return Result;
- }
-
- // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 4:i8, EFLAGS:i32)
- // Emits: (CMOVE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_265(N, X86::CMOVE_Fp64, MVT::f64);
- return Result;
- }
-
- // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 14:i8, EFLAGS:i32)
- // Emits: (CMOVP_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_265(N, X86::CMOVP_Fp64, MVT::f64);
- return Result;
- }
-
- // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 1:i8, EFLAGS:i32)
- // Emits: (CMOVNB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_265(N, X86::CMOVNB_Fp64, MVT::f64);
- return Result;
- }
-
- // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 0:i8, EFLAGS:i32)
- // Emits: (CMOVNBE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_265(N, X86::CMOVNBE_Fp64, MVT::f64);
- return Result;
- }
-
- // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 9:i8, EFLAGS:i32)
- // Emits: (CMOVNE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_265(N, X86::CMOVNE_Fp64, MVT::f64);
- return Result;
- }
-
- // Pattern: (X86cmov:f64 RFP64:f64:$src1, RFP64:f64:$src2, 11:i8, EFLAGS:i32)
- // Emits: (CMOVNP_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_265(N, X86::CMOVNP_Fp64, MVT::f64);
- return Result;
- }
- }
- }
-
- // Pattern: (X86cmov:f64 FR64:f64:$t, FR64:f64:$f, (imm:i8):$cond, EFLAGS:i32)
- // Emits: (CMOV_FR64:f64 FR64:f64:$t, FR64:f64:$f, (imm:i8):$cond)
- // Pattern complexity = 6 cost = 11 size = 3
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_264(N, X86::CMOV_FR64, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_CMOV_f80(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 2:i8, EFLAGS:i32)
- // Emits: (CMOVB_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_265(N, X86::CMOVB_Fp80, MVT::f80);
- return Result;
- }
-
- // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 3:i8, EFLAGS:i32)
- // Emits: (CMOVBE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_265(N, X86::CMOVBE_Fp80, MVT::f80);
- return Result;
- }
-
- // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 4:i8, EFLAGS:i32)
- // Emits: (CMOVE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_265(N, X86::CMOVE_Fp80, MVT::f80);
- return Result;
- }
-
- // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 14:i8, EFLAGS:i32)
- // Emits: (CMOVP_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_265(N, X86::CMOVP_Fp80, MVT::f80);
- return Result;
- }
-
- // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 1:i8, EFLAGS:i32)
- // Emits: (CMOVNB_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_265(N, X86::CMOVNB_Fp80, MVT::f80);
- return Result;
- }
-
- // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 0:i8, EFLAGS:i32)
- // Emits: (CMOVNBE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_265(N, X86::CMOVNBE_Fp80, MVT::f80);
- return Result;
- }
-
- // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 9:i8, EFLAGS:i32)
- // Emits: (CMOVNE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_265(N, X86::CMOVNE_Fp80, MVT::f80);
- return Result;
- }
-
- // Pattern: (X86cmov:f80 RFP80:f80:$src1, RFP80:f80:$src2, 11:i8, EFLAGS:i32)
- // Emits: (CMOVNP_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
- // Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_265(N, X86::CMOVNP_Fp80, MVT::f80);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_CMOV_v1i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_264(N, X86::CMOV_V1I64, MVT::v1i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_CMOV_v2i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_264(N, X86::CMOV_V2I64, MVT::v2i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_CMOV_v4f32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_264(N, X86::CMOV_V4F32, MVT::v4f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_CMOV_v2f64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_264(N, X86::CMOV_V2F64, MVT::v2f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_268(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, N01);
-}
-DISABLE_INLINE SDNode *Emit_269(SDNode *N, unsigned Opc0, SDValue &CPTmpN011_0, SDValue &CPTmpN011_1, SDValue &CPTmpN011_2, SDValue &CPTmpN011_3, SDValue &CPTmpN011_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue Chain01 = N01.getNode()->getOperand(0);
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N01.getNode())->getMemOperand();
- SDValue Ops0[] = { N00, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4, Chain01 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N01.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_270(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_271(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i16);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_272(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_273(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Chain00 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i8);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp3, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_274(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Chain00 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i16);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp3, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_275(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Chain00 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp3, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_276(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, N1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_277(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_278(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_279(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N->getOperand(0);
- SDValue Chain0 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_280(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i64);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_281(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Chain00 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i64);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp3, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_282(SDNode *N, unsigned Opc0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, N0);
-}
-DISABLE_INLINE SDNode *Emit_283(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Chain00 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
- SDValue Ops0[] = { N01, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_X86ISD_CMP(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode())) {
- if (Predicate_load(N00.getNode())) {
-
- // Pattern: (X86cmp:isVoid (and:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), 0:i64)
- // Emits: (TEST64mi32:isVoid addr:iPTR:$src1, (imm:i64):$src2)
- // Pattern complexity = 37 cost = 1 size = 3
- if (Predicate_loadi64(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt32(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_281(N, X86::TEST64mi32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i8 (ld:i8 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), 0:i8)
- // Emits: (TEST8mi:isVoid addr:iPTR:$src1, (imm:i8):$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_loadi8(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_273(N, X86::TEST8mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), 0:i16)
- // Emits: (TEST16mi:isVoid addr:iPTR:$src1, (imm:i16):$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_loadi16(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_274(N, X86::TEST16mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), 0:i32)
- // Emits: (TEST32mi:isVoid addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_loadi32(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_275(N, X86::TEST32mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::LOAD &&
- N01.hasOneUse() &&
- IsLegalAndProfitableToFold(N01.getNode(), N0.getNode(), N)) {
- SDValue Chain01 = N01.getNode()->getOperand(0);
- if (Predicate_unindexedload(N01.getNode())) {
-
- // Pattern: (X86cmp:isVoid (and:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), 0:i8)
- // Emits: (TEST8rm:isVoid GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_load(N01.getNode()) &&
- Predicate_loadi8(N01.getNode())) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue CPTmpN011_0;
- SDValue CPTmpN011_1;
- SDValue CPTmpN011_2;
- SDValue CPTmpN011_3;
- SDValue CPTmpN011_4;
- if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_269(N, X86::TEST8rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), 0:i16)
- // Emits: (TEST16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_loadi16(N01.getNode())) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue CPTmpN011_0;
- SDValue CPTmpN011_1;
- SDValue CPTmpN011_2;
- SDValue CPTmpN011_3;
- SDValue CPTmpN011_4;
- if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_269(N, X86::TEST16rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), 0:i32)
- // Emits: (TEST32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_loadi32(N01.getNode())) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue CPTmpN011_0;
- SDValue CPTmpN011_1;
- SDValue CPTmpN011_2;
- SDValue CPTmpN011_3;
- SDValue CPTmpN011_4;
- if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_269(N, X86::TEST32rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), 0:i64)
- // Emits: (TEST64rm:isVoid GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_load(N01.getNode()) &&
- Predicate_loadi64(N01.getNode())) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue CPTmpN011_0;
- SDValue CPTmpN011_1;
- SDValue CPTmpN011_2;
- SDValue CPTmpN011_3;
- SDValue CPTmpN011_4;
- if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_269(N, X86::TEST64rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode())) {
-
- // Pattern: (X86cmp:isVoid (and:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1), 0:i8)
- // Emits: (TEST8rm:isVoid GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_load(N00.getNode()) &&
- Predicate_loadi8(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_283(N, X86::TEST8rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1), 0:i16)
- // Emits: (TEST16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_loadi16(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_283(N, X86::TEST16rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1), 0:i32)
- // Emits: (TEST32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_loadi32(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_283(N, X86::TEST32rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1), 0:i64)
- // Emits: (TEST64rm:isVoid GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_load(N00.getNode()) &&
- Predicate_loadi64(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_283(N, X86::TEST64rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode())) {
-
- // Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (CMP16mi8:isVoid addr:iPTR:$src1, (imm:i16):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_257(N, X86::CMP16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (CMP32mi8:isVoid addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_258(N, X86::CMP32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- if (Predicate_load(N0.getNode())) {
- if (Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (CMP64mi8:isVoid addr:iPTR:$src1, (imm:i64):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_260(N, X86::CMP64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (CMP64mi32:isVoid addr:iPTR:$src1, (imm:i64):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode()) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_260(N, X86::CMP64mi32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (ld:i8 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2)
- // Emits: (CMP8mi:isVoid addr:iPTR:$src1, (imm:i8):$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (Predicate_loadi8(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_279(N, X86::CMP8mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2)
- // Emits: (CMP16mi:isVoid addr:iPTR:$src1, (imm:i16):$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_257(N, X86::CMP16mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2)
- // Emits: (CMP32mi:isVoid addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_258(N, X86::CMP32mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (ld:i8 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2)
- // Emits: (CMP8mr:isVoid addr:iPTR:$src1, GR8:i8:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_load(N0.getNode()) &&
- Predicate_loadi8(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_276(N, X86::CMP8mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2)
- // Emits: (CMP16mr:isVoid addr:iPTR:$src1, GR16:i16:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_276(N, X86::CMP16mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2)
- // Emits: (CMP32mr:isVoid addr:iPTR:$src1, GR32:i32:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_276(N, X86::CMP32mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode())) {
-
- // Pattern: (X86cmp:isVoid GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (CMP8rm:isVoid GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_277(N, X86::CMP8rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (X86cmp:isVoid GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (CMP16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_277(N, X86::CMP16rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (X86cmp:isVoid GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (CMP32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_277(N, X86::CMP32rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2)
- // Emits: (CMP64mr:isVoid addr:iPTR:$src1, GR64:i64:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_276(N, X86::CMP64mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (CMP64rm:isVoid GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_277(N, X86::CMP64rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (UCOMISSrm:isVoid FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_277(N, X86::UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (UCOMISDrm:isVoid FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_277(N, X86::UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND) {
- if (Predicate_and_su(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
-
- // Pattern: (X86cmp:isVoid (and:i8 GR8:i8:$src1, (imm:i8):$src2)<<P:Predicate_and_su>>, 0:i8)
- // Emits: (TEST8ri:isVoid GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 15 cost = 1 size = 3
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_270(N, X86::TEST8ri);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid (and:i16 GR16:i16:$src1, (imm:i16):$src2)<<P:Predicate_and_su>>, 0:i16)
- // Emits: (TEST16ri:isVoid GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 15 cost = 1 size = 3
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_271(N, X86::TEST16ri);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid (and:i32 GR32:i32:$src1, (imm:i32):$src2)<<P:Predicate_and_su>>, 0:i32)
- // Emits: (TEST32ri:isVoid GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 15 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_272(N, X86::TEST32ri);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), 0:i64)
- // Emits: (TEST64ri32:isVoid GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 15 cost = 1 size = 3
- {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt32(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_280(N, X86::TEST64ri32);
- return Result;
- }
- }
- }
- }
- if (Predicate_and_su(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
-
- // Pattern: (X86cmp:isVoid (and:i8 GR8:i8:$src1, GR8:i8:$src2)<<P:Predicate_and_su>>, 0:i8)
- // Emits: (TEST8rr:isVoid GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 12 cost = 1 size = 3
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_268(N, X86::TEST8rr);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid (and:i16 GR16:i16:$src1, GR16:i16:$src2)<<P:Predicate_and_su>>, 0:i16)
- // Emits: (TEST16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 12 cost = 1 size = 3
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_268(N, X86::TEST16rr);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid (and:i32 GR32:i32:$src1, GR32:i32:$src2)<<P:Predicate_and_su>>, 0:i32)
- // Emits: (TEST32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 12 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, X86::TEST32rr);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i64 GR64:i64:$src1, GR64:i64:$src2), 0:i64)
- // Emits: (TEST64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 11 cost = 1 size = 3
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_268(N, X86::TEST64rr);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
-
- // Pattern: (X86cmp:isVoid GR64:i64:$src1, 0:i64)
- // Emits: (TEST64rr:isVoid GR64:i64:$src1, GR64:i64:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_282(N, X86::TEST64rr);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR8:i8:$src1, 0:i8)
- // Emits: (TEST8rr:isVoid GR8:i8:$src1, GR8:i8:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_282(N, X86::TEST8rr);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR16:i16:$src1, 0:i16)
- // Emits: (TEST16rr:isVoid GR16:i16:$src1, GR16:i16:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_282(N, X86::TEST16rr);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR32:i32:$src1, 0:i32)
- // Emits: (TEST32rr:isVoid GR32:i32:$src1, GR32:i32:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_282(N, X86::TEST32rr);
- return Result;
- }
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86cmp:isVoid GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (CMP16ri8:isVoid GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_255(N, X86::CMP16ri8);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (CMP32ri8:isVoid GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_256(N, X86::CMP32ri8);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (CMP64ri8:isVoid GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_259(N, X86::CMP64ri8);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (CMP64ri32:isVoid GR64:i64:$src1, (imm:i64):$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode()) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_259(N, X86::CMP64ri32);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (CMP8ri:isVoid GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_278(N, X86::CMP8ri);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (CMP16ri:isVoid GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_255(N, X86::CMP16ri);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (CMP32ri:isVoid GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_256(N, X86::CMP32ri);
- return Result;
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid RFP32:f32:$lhs, RFP32:f32:$rhs)
- // Emits: (UCOM_FpIr32:isVoid RFP32:f32:$lhs, RFP32:f32:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_254(N, X86::UCOM_FpIr32);
- return Result;
- }
- }
-
- // Pattern: (X86cmp:isVoid RFP64:f64:$lhs, RFP64:f64:$rhs)
- // Emits: (UCOM_FpIr64:isVoid RFP64:f64:$lhs, RFP64:f64:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_254(N, X86::UCOM_FpIr64);
- return Result;
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86cmp:isVoid RFP80:f80:$lhs, RFP80:f80:$rhs)
- // Emits: (UCOM_FpIr80:isVoid RFP80:f80:$lhs, RFP80:f80:$rhs)
- // Pattern complexity = 3 cost = 1 size = 0
- if (N0.getValueType() == MVT::f80) {
- SDNode *Result = Emit_254(N, X86::UCOM_FpIr80);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (CMP8rr:isVoid GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_254(N, X86::CMP8rr);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (CMP16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_254(N, X86::CMP16rr);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (CMP32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_254(N, X86::CMP32rr);
- return Result;
- }
-
- // Pattern: (X86cmp:isVoid GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (CMP64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_254(N, X86::CMP64rr);
- return Result;
- }
- }
-
- // Pattern: (X86cmp:isVoid FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (UCOMISSrr:isVoid FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_254(N, X86::UCOMISSrr);
- return Result;
- }
- }
-
- // Pattern: (X86cmp:isVoid FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (UCOMISDrr:isVoid FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_254(N, X86::UCOMISDrr);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_284(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_285(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain1 = N1.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i8);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Tmp2, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_X86ISD_CMPPD_v2i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86cmppd:v2i64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
- // Emits: (CMPPDrmi:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$cc)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_285(N, X86::CMPPDrmi, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmppd:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i8):$cc)
- // Emits: (CMPPDrri:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$cc)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_284(N, X86::CMPPDrri, MVT::v2i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_CMPPS_v4i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86cmpps:v4i32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
- // Emits: (CMPPSrmi:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$cc)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_285(N, X86::CMPPSrmi, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmpps:v4i32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i8):$cc)
- // Emits: (CMPPSrri:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$cc)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_284(N, X86::CMPPSrri, MVT::v4i32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_COMI(SDNode *N) {
-
- // Pattern: (X86comi:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_COMISSrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_277(N, X86::Int_COMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86comi:isVoid VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_COMISDrm:isVoid VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_277(N, X86::Int_COMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86comi:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (Int_COMISSrr:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_254(N, X86::Int_COMISSrr);
- return Result;
- }
- }
-
- // Pattern: (X86comi:isVoid VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (Int_COMISDrr:isVoid VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_254(N, X86::Int_COMISDrr);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_DEC_i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_252(N, X86::DEC8r, MVT::i8);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_DEC_i16(SDNode *N) {
-
- // Pattern: (X86dec_flag:i16 GR16:i16:$src)
- // Emits: (DEC16r:i16 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 1
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_252(N, X86::DEC16r, MVT::i16);
- return Result;
- }
- }
-
- // Pattern: (X86dec_flag:i16 GR16:i16:$src)
- // Emits: (DEC64_16r:i16 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 2
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_252(N, X86::DEC64_16r, MVT::i16);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_DEC_i32(SDNode *N) {
-
- // Pattern: (X86dec_flag:i32 GR32:i32:$src)
- // Emits: (DEC32r:i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 1
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_252(N, X86::DEC32r, MVT::i32);
- return Result;
- }
- }
-
- // Pattern: (X86dec_flag:i32 GR32:i32:$src)
- // Emits: (DEC64_32r:i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 2
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_252(N, X86::DEC64_32r, MVT::i32);
- return Result;
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_DEC_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_252(N, X86::DEC64r, MVT::i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_EH_RETURN(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86ehret:isVoid GR32:i32:$addr)
- // Emits: (EH_RETURN:isVoid GR32:i32:$addr)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_83(N, X86::EH_RETURN);
- return Result;
- }
-
- // Pattern: (X86ehret:isVoid GR64:i64:$addr)
- // Emits: (EH_RETURN64:isVoid GR64:i64:$addr)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_83(N, X86::EH_RETURN64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_FAND_f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86fand:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (FsANDPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::FsANDPSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fand:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
- // Emits: (FsANDPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::FsANDPSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fand:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (FsANDPSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::FsANDPSrr, MVT::f32);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_FAND_f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86fand:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (FsANDPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::FsANDPDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fand:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
- // Emits: (FsANDPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::FsANDPDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fand:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (FsANDPDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::FsANDPDrr, MVT::f64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_286(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
-}
-SDNode *Select_X86ISD_FILD_f32(SDNode *N) {
- if ((!Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N->getOperand(2);
-
- // Pattern: (X86fild:f32 addr:iPTR:$src, i16:Other)
- // Emits: (ILD_Fp16m32:f32 addr:iPTR:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_286(N, X86::ILD_Fp16m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
-
- // Pattern: (X86fild:f32 addr:iPTR:$src, i32:Other)
- // Emits: (ILD_Fp32m32:f32 addr:iPTR:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_286(N, X86::ILD_Fp32m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
-
- // Pattern: (X86fild:f32 addr:iPTR:$src, i64:Other)
- // Emits: (ILD_Fp64m32:f32 addr:iPTR:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i64) {
- SDNode *Result = Emit_286(N, X86::ILD_Fp64m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_FILD_f64(SDNode *N) {
- if ((!Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N->getOperand(2);
-
- // Pattern: (X86fild:f64 addr:iPTR:$src, i16:Other)
- // Emits: (ILD_Fp16m64:f64 addr:iPTR:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_286(N, X86::ILD_Fp16m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
-
- // Pattern: (X86fild:f64 addr:iPTR:$src, i32:Other)
- // Emits: (ILD_Fp32m64:f64 addr:iPTR:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_286(N, X86::ILD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
-
- // Pattern: (X86fild:f64 addr:iPTR:$src, i64:Other)
- // Emits: (ILD_Fp64m64:f64 addr:iPTR:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i64) {
- SDNode *Result = Emit_286(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
- }
-
- CannotYetSelect(N);
- return NULL;
-}
+// The main instruction selector code.
+SDNode *SelectCode(SDNode *N) {
+ // Opcodes are emitted as 2 bytes, TARGET_OPCODE handles this.
+ #define TARGET_OPCODE(X) X & 255, unsigned(X) >> 8
+ static const unsigned char MatcherTable[] = {
+ OPC_SwitchOpcode , 105|128,2|128,1, ISD::STORE,
+ OPC_Scope, 77,
+ OPC_CheckPredicate, 0,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 23,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 23,
+ OPC_CheckChild1Type, MVT::v2f64,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTDQ_64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTDQ_64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 0,
+ 55,
+ OPC_CheckPredicate, 1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 23,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTImr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 23,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTI_64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 77,
+ OPC_CheckPredicate, 0,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 23,
+ OPC_CheckChild1Type, MVT::v2f64,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 23,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTDQmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTDQmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 0,
+ 16|128,1|128,1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 54|128,121,
+ OPC_CheckPredicate, 3,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_Scope, 64|128,120,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 94|128,20, ISD::OR,
+ OPC_Scope, 82|128,9,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 100|128,4, ISD::SRL,
+ OPC_Scope, 40|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 79,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_RecordChild0,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::ECX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 79,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_RecordChild0,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 0,
+ 31|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 72,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 5,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::ECX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 72,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 5,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::CX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 0,
+ 12|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 65,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 65,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 0,
+ 7|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 62,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 5,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 62,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 5,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 0,
+ 0,
+ 100|128,4, ISD::SHL,
+ OPC_Scope, 40|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 79,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_RecordChild0,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::ECX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 79,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_RecordChild0,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 0,
+ 31|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 72,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 5,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::ECX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 72,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 5,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::CX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 0,
+ 12|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 65,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 65,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 0,
+ 7|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 62,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 5,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 62,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 5,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 0,
+ 0,
+ 0,
+ 71,
+ OPC_CheckPredicate, 7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 4, 10,
+ 71,
+ OPC_CheckPredicate, 8,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 4, 10,
+ 71,
+ OPC_CheckPredicate, 7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 4, 10,
+ 71,
+ OPC_CheckPredicate, 8,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 4, 10,
+ 73,
+ OPC_CheckPredicate, 7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 4, 10,
+ 73,
+ OPC_CheckPredicate, 8,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 4, 10,
+ 71,
+ OPC_CheckPredicate, 7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 1, 10,
+ 71,
+ OPC_CheckPredicate, 8,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 1, 10,
+ 71,
+ OPC_CheckPredicate, 7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 1, 10,
+ 71,
+ OPC_CheckPredicate, 8,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 1, 10,
+ 73,
+ OPC_CheckPredicate, 7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 1, 10,
+ 73,
+ OPC_CheckPredicate, 8,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 1, 10,
+ 28|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 63|128,1,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 105,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 28, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 28, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 28, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 80,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 33,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 122,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 26, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 0,
+ 0|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 26, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 26, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 26, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 26, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 47|128,5, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 46,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 44,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 81,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_Scope, 35,
+ OPC_CheckAndImm, 63,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 31,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 0,
+ 40,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 83,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 37,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 44,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 81,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 39,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 39,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 41,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 47|128,5, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 46,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 44,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 81,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_Scope, 35,
+ OPC_CheckAndImm, 63,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 31,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 0,
+ 40,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 83,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 37,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 44,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 81,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 39,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 39,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 41,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 47|128,5, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 46,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 44,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 81,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_Scope, 35,
+ OPC_CheckAndImm, 63,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 31,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 0,
+ 40,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 83,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 37,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 44,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 81,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 39,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 39,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 41,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 62|128,4, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 27|128,1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 36,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG8m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 34,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 34,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 36,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 0,
+ 27|128,3,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 64|128,1,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 14|128,1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 95,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 28, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 28, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 28, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 33,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 43,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 122,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 26, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 0,
+ 0,
+ 100|128,5, ISD::XOR,
+ OPC_Scope, 94|128,4,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 49,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT8m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 47,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 47,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 111|128,1,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 105,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 28, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 28, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 28, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 80,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 33,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 122,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 26, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 0,
+ 0|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 26, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 26, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 26, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 26, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 27|128,10, ISD::ADD,
+ OPC_Scope, 21|128,9,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 41,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC8m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 50,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC8m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 50,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 50,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 84,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_Scope, 30,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 39,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 0,
+ 41,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 50,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 50,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 52,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitInteger, MVT::i16, 0|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 52,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 0|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 40|128,2,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 103,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_Scope, 43,
+ OPC_CheckInteger, 0|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitInteger, MVT::i64, 0|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 47,
+ OPC_CheckInteger, 0|128,0|128,0|128,0|128,0|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitInteger, MVT::i64, 0|128,0|128,0|128,0|128,120|128,127|128,127|128,127|128,127|128,1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 14|128,1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 95,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 28, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 28, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 28, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 33,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 43,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 122,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 26, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 0,
+ 0|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 26, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 26, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 26, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 26, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 127|128,3, ISD::ROTL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 42,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL8m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL16m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL32m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 83,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL64m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 37,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 44,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 81,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL64mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 39,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 39,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 41,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 127|128,3, ISD::ROTR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 42,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR8m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR16m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR32m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 83,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR64m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 37,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 44,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 81,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR64mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 39,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 39,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 41,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 34|128,4, ISD::AND,
+ OPC_Scope, 28|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 63|128,1,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 105,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 28, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 28, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 28, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 80,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 33,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 122,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 26, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 26, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 0,
+ 0|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 26, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 26, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 26, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 26, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 68|128,4, ISD::ADDE,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_Scope, 52|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 74|128,1,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 22|128,1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 101,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 30, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 30, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 30, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 0,
+ 35,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64mi32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 0,
+ 45,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 0,
+ 45,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 45,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 2|128,1,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 28, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 28, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 28, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 28, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 0,
+ 0,
+ 8|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 28, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 4,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/4,
+ OPC_EmitMergeInputChains, 2, 0, 3,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 2,
+ 28, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 4,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/4,
+ OPC_EmitMergeInputChains, 2, 0, 3,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 2,
+ 28, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 4,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/4,
+ OPC_EmitMergeInputChains, 2, 0, 3,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 2,
+ 28, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 4,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/4,
+ OPC_EmitMergeInputChains, 2, 0, 3,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 2,
+ 0,
+ 0,
+ 54|128,3, ISD::SUBE,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 74|128,1,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 22|128,1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 101,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 30, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 30, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 30, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 0,
+ 35,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64mi32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 0,
+ 45,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB8mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 0,
+ 45,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 45,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 2|128,1,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 28, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB8mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 28, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 28, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 28, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 0,
+ 0,
+ 108|128,4, X86ISD::ADD,
+ OPC_Scope, 73|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 45,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 45,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 116,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 33,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 33,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 29|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 37,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 73|128,3, X86ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 45,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 45,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 116,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 33,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 33,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 108|128,4, X86ISD::OR,
+ OPC_Scope, 73|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 45,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 45,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 116,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 33,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 33,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 29|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 37,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 108|128,4, X86ISD::XOR,
+ OPC_Scope, 73|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 45,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 45,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 116,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 33,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 33,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 29|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 37,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 108|128,4, X86ISD::AND,
+ OPC_Scope, 73|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 45,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 45,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 116,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 33,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 33,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 31,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 29|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 37,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 19|128,1, ISD::VECTOR_SHUFFLE,
+ OPC_CheckPredicate, 13,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 44, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 3,
+ 93, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 25, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 3,
+ 25, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 3,
+ 25, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 0,
+ 23|128,2, X86ISD::SHLD,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 46,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 3, 10,
+ 46,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 3, 10,
+ 48,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 3, 10,
+ 41,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 3,
+ 41,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 3,
+ 43,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 3,
+ 0,
+ 23|128,2, X86ISD::SHRD,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 46,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 3, 10,
+ 46,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 3, 10,
+ 48,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 3, 10,
+ 41,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 3,
+ 41,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 3,
+ 43,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 3,
+ 0,
+ 114|128,1, X86ISD::INC,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC8m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 0,
+ 114|128,1, X86ISD::DEC,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC8m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 38,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 0,
+ 41|128,3, ISD::EXTRACT_VECTOR_ELT,
+ OPC_Scope, 42|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 89, ISD::VECTOR_SHUFFLE,
+ OPC_CheckPredicate, 14,
+ OPC_Scope, 45,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 38,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 73, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_SwitchType , 30, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 34, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::EXTRACTPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 4, 5, 6, 7, 8, 1, 9,
+ 0,
+ 0,
+ 121|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 65,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 30,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 1, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 9,
+ 0,
+ 68,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_Scope, 29,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVPQI2QImr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 33,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PEXTRQmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 4, 5, 6, 7, 8, 1, 9,
+ 0,
+ 68,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_Scope, 29,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVPDI2DImr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 33,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PEXTRDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 4, 5, 6, 7, 8, 1, 9,
+ 0,
+ 41,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 1, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 9,
+ 0,
+ 0,
+ 41|128,1, ISD::TRUNCATE,
+ OPC_CheckPredicate, 15,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_CheckPredicate, 16,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 47, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, X86::GR64_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i64, 2, 1, 8,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 9, 10,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mr_NOREX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 11,
+ 49, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, X86::GR32_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i32, 2, 1, 8,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 9, 10,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mr_NOREX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 11,
+ 49, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 1, 8,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 9, 10,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mr_NOREX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 11,
+ 0,
+ 50, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::EXTRACT_VECTOR_ELT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::EXTRACTPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 4, 5, 6, 7, 8, 1, 9,
+ 52|128,3, X86ISD::SETCC,
+ OPC_MoveChild, 0,
+ OPC_Scope, 26,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 7,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETLm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETGEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETLEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETGm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETBm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETAEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETBEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETAm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 15,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETSm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 12,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNSm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 14,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETPm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 11,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNPm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 13,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETOm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckInteger, 10,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNOm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 0,
+ 84|128,1, X86ISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 49, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 22, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 49, ISD::TargetExternalSymbol,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 22, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 49, ISD::TargetBlockAddress,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 22, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 25, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 25, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 0,
+ 109,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 26,
+ OPC_CheckPredicate, 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 24,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 24,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 24,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 0,
+ 35,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPredicate, 18,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 35,
+ OPC_CheckPredicate, 3,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDto64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 35,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPredicate, 18,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 63,
+ OPC_CheckPredicate, 3,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_Scope, 31,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSS2DImr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 24,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 30,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPredicate, 19,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp64m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 28,
+ OPC_CheckPredicate, 3,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 58,
+ OPC_CheckPredicate, 17,
+ OPC_Scope, 26,
+ OPC_CheckPredicate, 19,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::f80,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 26,
+ OPC_CheckPredicate, 20,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::f80,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 97|128,4,
+ OPC_CheckPredicate, 3,
+ OPC_Scope, 11|128,1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 21,
+ OPC_CheckChild1Type, MVT::f80,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_FpP80m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::i16,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 23,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 28,
+ OPC_CheckPredicate, 21,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 53,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 23,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 23,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 28,
+ OPC_CheckPredicate, 21,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::v2f64,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::v2f64,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 95,
+ OPC_CheckPredicate, 21,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 21,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 99|128,1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 21,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 45,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 21,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 0,
+ 77,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPredicate, 18,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 33,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i16, 2, 1, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 9,
+ 33,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i16, 2, 1, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 9,
+ 0,
+ 0,
+ 0,
+ 66|128,26, ISD::VECTOR_SHUFFLE,
+ OPC_Scope, 55,
+ OPC_CheckPredicate, 13,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 55,
+ OPC_CheckPredicate, 22,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 51,
+ OPC_CheckPredicate, 23,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSHDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 51,
+ OPC_CheckPredicate, 25,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSLDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 48,
+ OPC_CheckPredicate, 13,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 48,
+ OPC_CheckPredicate, 22,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 102,
+ OPC_CheckPredicate, 13,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 19, MVT::v4f32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::v2f64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::v2i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 56,
+ OPC_RecordNode,
+ OPC_CheckPredicate, 26,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFDmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 3, 4, 5, 6, 7, 8,
+ 84,
+ OPC_CheckPredicate, 27,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 29, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 29, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 41,
+ OPC_CheckPredicate, 14,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckPredicate, 28,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckPredicate, 14,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckPredicate, 28,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 124,
+ OPC_CheckPredicate, 27,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 52, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
+ 62, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::v2f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
+ 20, MVT::v2i64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 0,
+ 115,
+ OPC_RecordNode,
+ OPC_Scope, 55,
+ OPC_CheckPredicate, 29,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitNodeXForm, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFHWmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 3, 4, 5, 6, 7, 8,
+ 55,
+ OPC_CheckPredicate, 30,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitNodeXForm, 2, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFLWmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 51,
+ OPC_CheckPredicate, 27,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
+ 113,
+ OPC_RecordNode,
+ OPC_Scope, 55,
+ OPC_CheckPredicate, 26,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFDmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 3, 4, 5, 6, 7, 8,
+ 53,
+ OPC_CheckPredicate, 31,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitNodeXForm, 3, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSHUFWmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 96,
+ OPC_CheckPredicate, 28,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 96,
+ OPC_CheckPredicate, 14,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 44,
+ OPC_CheckPredicate, 23,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSHDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 44,
+ OPC_CheckPredicate, 25,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSLDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 53,
+ OPC_RecordNode,
+ OPC_CheckPredicate, 32,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 2,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPSrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 7, 1, 4, 5, 6, 7, 8, 9,
+ 94,
+ OPC_CheckPredicate, 33,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 94,
+ OPC_CheckPredicate, 34,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 39,
+ OPC_CheckPredicate, 22,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, X86ISD::VZEXT_LOAD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPSrm), 0|OPFL_Chain,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 32,
+ OPC_CheckPredicate, 27,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLHPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 0,
+ 9, MVT::v2i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLHPSrr), 0,
+ 1, MVT::v2i64, 2, 0, 0,
+ 0,
+ 32,
+ OPC_CheckPredicate, 35,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHLPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 0,
+ 9, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHLPSrr), 0,
+ 1, MVT::v4i32, 2, 0, 0,
+ 0,
+ 75,
+ OPC_RecordNode,
+ OPC_CheckPredicate, 32,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 25, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 2,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPSrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 7, 1, 4, 5, 6, 7, 8, 9,
+ 25, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 2,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPDrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 7, 1, 4, 5, 6, 7, 8, 9,
+ 0,
+ 41,
+ OPC_CheckPredicate, 28,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLQDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckPredicate, 14,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHQDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 17,
+ OPC_CheckPredicate, 22,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLHPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 17,
+ OPC_CheckPredicate, 36,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHLPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 15,
+ OPC_CheckPredicate, 22,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLHPSrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 15,
+ OPC_CheckPredicate, 36,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHLPSrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 22,
+ OPC_CheckPredicate, 37,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 38,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZPQILo2PQIrr), 0,
+ 1, MVT::v2f64, 1, 0,
+ 20,
+ OPC_CheckPredicate, 23,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSHDUPrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 20,
+ OPC_CheckPredicate, 25,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSLDUPrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 89,
+ OPC_RecordNode,
+ OPC_Scope, 42,
+ OPC_CheckPredicate, 39,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_SwitchType , 14, MVT::v4i32,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFDri), 0,
+ 1, MVT::v4i32, 2, 1, 2,
+ 14, MVT::v4f32,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFDri), 0,
+ 1, MVT::v4f32, 2, 1, 2,
+ 0,
+ 42,
+ OPC_CheckPredicate, 40,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_SwitchType , 14, MVT::v4i32,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFDri), 0,
+ 1, MVT::v4i32, 2, 1, 2,
+ 14, MVT::v4f32,
+ OPC_CheckPatternPredicate, 10,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFDri), 0,
+ 1, MVT::v4f32, 2, 1, 2,
+ 0,
+ 0,
+ 98,
+ OPC_CheckPredicate, 37,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 21, MVT::v4f32,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrr), 0,
+ 1, MVT::v4f32, 2, 0, 3,
+ 21, MVT::v2f64,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
+ 1, MVT::v2f64, 2, 0, 3,
+ 21, MVT::v4i32,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrr), 0,
+ 1, MVT::v4i32, 2, 0, 3,
+ 21, MVT::v2i64,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
+ 1, MVT::v2i64, 2, 0, 3,
+ 0,
+ 56,
+ OPC_CheckPredicate, 13,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 23, MVT::v4f32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
+ 1, MVT::v4f32, 2, 0, 3,
+ 23, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
+ 1, MVT::v4i32, 2, 0, 3,
+ 0,
+ 21,
+ OPC_CheckPredicate, 41,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 0,
+ 21,
+ OPC_CheckPredicate, 14,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 0,
+ 21,
+ OPC_CheckPredicate, 41,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLQDQrr), 0,
+ 1, MVT::v2i64, 2, 0, 0,
+ 21,
+ OPC_CheckPredicate, 14,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHQDQrr), 0,
+ 1, MVT::v2i64, 2, 0, 0,
+ 54,
+ OPC_CheckPredicate, 39,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 0,
+ 9, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLBWrr), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 9, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLWDrr), 0,
+ 1, MVT::v8i16, 2, 0, 0,
+ 9, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLDQrr), 0,
+ 1, MVT::v4i32, 2, 0, 0,
+ 0,
+ 54,
+ OPC_CheckPredicate, 40,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 0,
+ 9, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHBWrr), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 9, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHWDrr), 0,
+ 1, MVT::v8i16, 2, 0, 0,
+ 9, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHDQrr), 0,
+ 1, MVT::v4i32, 2, 0, 0,
+ 0,
+ 43,
+ OPC_CheckPredicate, 42,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::v8i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLBWrr), 0,
+ 1, MVT::v8i8, 2, 0, 0,
+ 9, MVT::v4i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLWDrr), 0,
+ 1, MVT::v4i16, 2, 0, 0,
+ 9, MVT::v2i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLDQrr), 0,
+ 1, MVT::v2i32, 2, 0, 0,
+ 0,
+ 43,
+ OPC_CheckPredicate, 43,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::v8i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHBWrr), 0,
+ 1, MVT::v8i8, 2, 0, 0,
+ 9, MVT::v4i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHWDrr), 0,
+ 1, MVT::v4i16, 2, 0, 0,
+ 9, MVT::v2i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHDQrr), 0,
+ 1, MVT::v2i32, 2, 0, 0,
+ 0,
+ 17,
+ OPC_CheckPredicate, 14,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 17,
+ OPC_CheckPredicate, 28,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 17,
+ OPC_CheckPredicate, 14,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 17,
+ OPC_CheckPredicate, 28,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 36,
+ OPC_CheckPredicate, 37,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 44,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2DQrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 121,
+ OPC_RecordNode,
+ OPC_Scope, 42,
+ OPC_CheckPredicate, 26,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_SwitchType , 14, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFDri), 0,
+ 1, MVT::v4i32, 2, 1, 2,
+ 14, MVT::v4f32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFDri), 0,
+ 1, MVT::v4f32, 2, 1, 2,
+ 0,
+ 74,
+ OPC_CheckPredicate, 45,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 15, MVT::v4i32,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNodeXForm, 4, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PALIGNR128rr), 0,
+ 1, MVT::v4i32, 3, 2, 1, 3,
+ 15, MVT::v4f32,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNodeXForm, 4, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PALIGNR128rr), 0,
+ 1, MVT::v4f32, 3, 2, 1, 3,
+ 15, MVT::v8i16,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNodeXForm, 4, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PALIGNR128rr), 0,
+ 1, MVT::v8i16, 3, 2, 1, 3,
+ 15, MVT::v16i8,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitNodeXForm, 4, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PALIGNR128rr), 0,
+ 1, MVT::v16i8, 3, 2, 1, 3,
+ 0,
+ 0,
+ 44,
+ OPC_CheckPredicate, 37,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_RecordChild0,
+ OPC_Scope, 16,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 16,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 53,
+ OPC_RecordNode,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitNodeXForm, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFHWri), 0,
+ 1, MVT::v8i16, 2, 1, 2,
+ 24,
+ OPC_CheckPredicate, 30,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitNodeXForm, 2, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFLWri), 0,
+ 1, MVT::v8i16, 2, 1, 2,
+ 0,
+ 20,
+ OPC_CheckPredicate, 23,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSHDUPrr), 0,
+ 1, MVT::v4f32, 1, 0,
+ 20,
+ OPC_CheckPredicate, 25,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSLDUPrr), 0,
+ 1, MVT::v4f32, 1, 0,
+ 20,
+ OPC_CheckPredicate, 27,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrr), 0,
+ 1, MVT::v2f64, 1, 0,
+ 1|128,1,
+ OPC_RecordNode,
+ OPC_Scope, 59,
+ OPC_CheckPredicate, 26,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_SwitchType , 13, MVT::v4f32,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPSrri), 0,
+ 1, MVT::v4f32, 3, 1, 1, 2,
+ 15, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPDrri), 0,
+ 1, MVT::v2i64, 3, 1, 1, 2,
+ 15, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPDrri), 0,
+ 1, MVT::v2f64, 3, 1, 1, 2,
+ 0,
+ 24,
+ OPC_CheckPredicate, 31,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitNodeXForm, 3, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSHUFWri), 0,
+ 1, MVT::v4i16, 2, 1, 2,
+ 40,
+ OPC_CheckPredicate, 32,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 15, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPSrri), 0,
+ 1, MVT::v4f32, 3, 1, 2, 3,
+ 15, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPDrri), 0,
+ 1, MVT::v2f64, 3, 1, 2, 3,
+ 0,
+ 0,
+ 58,
+ OPC_CheckPredicate, 28,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 11, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLBWrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 11, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLWDrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 11, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLDQrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 11, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLQDQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 58,
+ OPC_CheckPredicate, 14,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 11, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHBWrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 11, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHWDrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 11, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHDQrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 11, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHQDQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 64,
+ OPC_RecordNode,
+ OPC_Scope, 40,
+ OPC_CheckPredicate, 32,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 15, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPSrri), 0,
+ 1, MVT::v4i32, 3, 1, 2, 3,
+ 15, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPDrri), 0,
+ 1, MVT::v2i64, 3, 1, 2, 3,
+ 0,
+ 19,
+ OPC_CheckPredicate, 13,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPSrri), 0,
+ 1, MVT::v4f32, 3, 2, 1, 3,
+ 0,
+ 45,
+ OPC_CheckPredicate, 33,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 11, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHBWrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 11, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHWDrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 11, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHDQrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 45,
+ OPC_CheckPredicate, 34,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 11, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLBWrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 11, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLWDrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 11, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLDQrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 0,
+ 95|128,5, X86ISD::VZEXT_MOVL,
+ OPC_Scope, 113|128,4,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 42|128,2, ISD::SCALAR_TO_VECTOR,
+ OPC_Scope, 72|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZDI2PDIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 34,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZQI2PQIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 32,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVZDI2PDIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 5, 2, 3, 4, 5, 6,
+ 90,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 38, MVT::f32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVSSrm), 0|OPFL_Chain,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 3, 7, 8, 9,
+ 38, MVT::f64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVSDrm), 0|OPFL_Chain,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 3, 7, 8, 9,
+ 0,
+ 0,
+ 93,
+ OPC_RecordChild0,
+ OPC_Scope, 29,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_MoveParent,
+ OPC_SwitchType , 10, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZDI2PDIrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 10, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVZDI2PDIrr), 0,
+ 1, MVT::v2i32, 1, 0,
+ 0,
+ 15,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZQI2PQIrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 21,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_EmitNode, TARGET_OPCODE(X86::V_SET0), 0,
+ 1, MVT::v2f64, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
+ 1, MVT::v2f64, 2, 1, 0,
+ 21,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_EmitNode, TARGET_OPCODE(X86::V_SET0), 0,
+ 1, MVT::v4f32, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrr), 0,
+ 1, MVT::v4f32, 2, 1, 0,
+ 0,
+ 0,
+ 40|128,1, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 80, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 18, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZDI2PDIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 18, MVT::v2i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZQI2PQIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 34, MVT::v2f64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVSDrm), 0|OPFL_Chain,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 3, 7, 8, 9,
+ 0,
+ 22, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZDI2PDIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 22, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZPQILo2PQIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 22, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVZDI2PDIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 18|128,1, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 18, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZDI2PDIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 42, MVT::v2i64,
+ OPC_Scope, 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZQI2PQIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 20,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZPQILo2PQIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 34, MVT::v4f32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVSSrm), 0|OPFL_Chain,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 3, 7, 8, 9,
+ 34, MVT::v2f64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVSDrm), 0|OPFL_Chain,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 3, 7, 8, 9,
+ 0,
+ 0,
+ 105,
+ OPC_RecordChild0,
+ OPC_SwitchType , 10, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZPQILo2PQIrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 16, MVT::v2i32,
+ OPC_EmitNode, TARGET_OPCODE(X86::MMX_V_SET0), 0,
+ 1, MVT::v8i8, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLDQrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 28, MVT::v4f32,
+ OPC_EmitNode, TARGET_OPCODE(X86::V_SET0), 0,
+ 1, MVT::v4f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrr), 0,
+ 1, MVT::v4f32, 2, 1, 3,
+ 28, MVT::v4i32,
+ OPC_EmitNode, TARGET_OPCODE(X86::V_SET0), 0,
+ 1, MVT::v4i32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrr), 0,
+ 1, MVT::v4i32, 2, 1, 3,
+ 10, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZPQILo2PQIrr), 0,
+ 1, MVT::v2f64, 1, 0,
+ 0,
+ 0,
+ 123|128,2, ISD::SCALAR_TO_VECTOR,
+ OPC_Scope, 7|128,2,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 59|128,1, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 87,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 37, MVT::f32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 0,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVSSrm), 0|OPFL_Chain,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 3, 7, 8, 9,
+ 37, MVT::f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVSDrm), 0|OPFL_Chain,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 3, 7, 8, 9,
+ 0,
+ 30,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDI2PDIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 32,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVQI2PQIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 30,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 67, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_Scope, 15,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2DQrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 15,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2DQrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 15,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2DQrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 15,
+ OPC_CheckChild0Type, MVT::v1i64,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2DQrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 0,
+ 0,
+ 111,
+ OPC_RecordChild0,
+ OPC_Scope, 28,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_SwitchType , 10, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64toPQIrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 10, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64rrv164), 0,
+ 1, MVT::v1i64, 1, 0,
+ 0,
+ 28,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_SwitchType , 10, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDI2PDIrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 10, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64rr), 0,
+ 1, MVT::v2i32, 1, 0,
+ 0,
+ 24,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_CheckType, MVT::v4f32,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v4f32, 0,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v4f32, 3, 1, 0, 2,
+ 24,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_CheckType, MVT::v2f64,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::IMPLICIT_DEF), 0,
+ 1, MVT::v2f64, 0,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::INSERT_SUBREG), 0,
+ 1, MVT::v2f64, 3, 1, 0, 2,
+ 0,
+ 0,
+ 122|128,12, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 80|128,1,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 46,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::GS_MOV32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 47,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FS_MOV32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 46,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64GSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 47,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64FSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 71,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 20, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 18, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp80m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 0,
+ 0,
+ 84,
+ OPC_CheckPredicate, 48,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp32m64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 50,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp64m80), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp32m80), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 0,
+ 27,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i8, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 78,
+ OPC_CheckPredicate, 51,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 52,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 18, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX16rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 5, 2, 3, 4, 5, 6,
+ 18, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 25,
+ OPC_CheckPredicate, 53,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rm16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 18|128,1,
+ OPC_CheckPredicate, 54,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 55,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 18, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX16rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 5, 2, 3, 4, 5, 6,
+ 18, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 25,
+ OPC_CheckPredicate, 56,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 67,
+ OPC_CheckPredicate, 57,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 18, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i8, 5, 2, 3, 4, 5, 6,
+ 18, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX16rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 5, 2, 3, 4, 5, 6,
+ 18, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 0,
+ 18|128,1,
+ OPC_CheckPredicate, 48,
+ OPC_Scope, 67,
+ OPC_CheckPredicate, 58,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 18, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i8, 5, 2, 3, 4, 5, 6,
+ 18, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX16rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 5, 2, 3, 4, 5, 6,
+ 18, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 47,
+ OPC_CheckPredicate, 59,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 18, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX16rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 5, 2, 3, 4, 5, 6,
+ 18, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 25,
+ OPC_CheckPredicate, 60,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 27,
+ OPC_CheckPredicate, 51,
+ OPC_CheckPredicate, 53,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rm16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 27,
+ OPC_CheckPredicate, 54,
+ OPC_CheckPredicate, 56,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 27,
+ OPC_CheckPredicate, 48,
+ OPC_CheckPredicate, 60,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 82,
+ OPC_CheckPredicate, 51,
+ OPC_Scope, 25,
+ OPC_CheckPredicate, 52,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 53,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rm16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 61,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rm32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 108,
+ OPC_CheckPredicate, 54,
+ OPC_Scope, 25,
+ OPC_CheckPredicate, 55,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 56,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 62,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 57,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 82,
+ OPC_CheckPredicate, 48,
+ OPC_Scope, 25,
+ OPC_CheckPredicate, 58,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 59,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 60,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 27,
+ OPC_CheckPredicate, 51,
+ OPC_CheckPredicate, 53,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rm16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 27,
+ OPC_CheckPredicate, 54,
+ OPC_CheckPredicate, 56,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 27,
+ OPC_CheckPredicate, 48,
+ OPC_CheckPredicate, 60,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 110,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 51,
+ OPC_CheckPredicate, 63,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsMOVAPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 20, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 25,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 29,
+ OPC_CheckPredicate, 48,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 12,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSS2SDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 78|128,1,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 51,
+ OPC_CheckPredicate, 63,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsMOVAPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 20, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 25,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 63,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 23,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckPredicate, 63,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 47,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 18, MVT::v2i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 20, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 0,
+ 85,
+ OPC_CheckPredicate, 48,
+ OPC_Scope, 41,
+ OPC_CheckPredicate, 64,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOV32rm), 0|OPFL_Chain,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 3, 7, 8, 9,
+ 38,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 13,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVSSrm), 0|OPFL_Chain,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ OPC_EmitNode, TARGET_OPCODE(X86::CVTSS2SDrr), 0|OPFL_MemRefs,
+ 1, MVT::f64, 1, 7,
+ OPC_CompleteMatch, 1, 8,
+
+ 0,
+ 0,
+ 60, X86ISD::VZEXT_LOAD,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 18, MVT::v2i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZQI2PQIrm), 0|OPFL_Chain,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 34, MVT::v2f64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVSDrm), 0|OPFL_Chain,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0|OPFL_Chain,
+ 1, MVT::v2f64, 3, 7, 8, 9,
+ 0,
+ 9|128,9|128,1, ISD::INTRINSIC_WO_CHAIN,
+ OPC_MoveChild, 0,
+ OPC_Scope, 20|128,1,
+ OPC_CheckInteger, 126|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 0|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 46, X86ISD::VZEXT_MOVL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 5, 2, 3, 4, 5, 6,
+ 41, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 5, 2, 3, 4, 5, 6,
+ 27, X86ISD::VZEXT_LOAD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXBWrm), 0|OPFL_Chain,
+ 1, MVT::v8i16, 5, 2, 3, 4, 5, 6,
+ 0,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXBWrr), 0,
+ 1, MVT::v8i16, 1, 0,
+ 0,
+ 20|128,1,
+ OPC_CheckInteger, 0|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 0|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 46, X86ISD::VZEXT_MOVL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 41, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 27, X86ISD::VZEXT_LOAD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXWDrm), 0|OPFL_Chain,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXWDrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 0,
+ 20|128,1,
+ OPC_CheckInteger, 127|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 0|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 46, X86ISD::VZEXT_MOVL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 41, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 27, X86ISD::VZEXT_LOAD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXDQrm), 0|OPFL_Chain,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXDQrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 0,
+ 20|128,1,
+ OPC_CheckInteger, 4|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 0|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 46, X86ISD::VZEXT_MOVL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 5, 2, 3, 4, 5, 6,
+ 41, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 5, 2, 3, 4, 5, 6,
+ 27, X86ISD::VZEXT_LOAD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXBWrm), 0|OPFL_Chain,
+ 1, MVT::v8i16, 5, 2, 3, 4, 5, 6,
+ 0,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXBWrr), 0,
+ 1, MVT::v8i16, 1, 0,
+ 0,
+ 20|128,1,
+ OPC_CheckInteger, 6|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 0|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 46, X86ISD::VZEXT_MOVL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 41, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 27, X86ISD::VZEXT_LOAD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXWDrm), 0|OPFL_Chain,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXWDrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 0,
+ 20|128,1,
+ OPC_CheckInteger, 5|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 0|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 46, X86ISD::VZEXT_MOVL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 41, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 27, X86ISD::VZEXT_LOAD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXDQrm), 0|OPFL_Chain,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXDQrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 0,
+ 114,
+ OPC_CheckInteger, 124|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 95,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 44, X86ISD::VZEXT_MOVL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXBDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 39, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXBDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXBDrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 0,
+ 114,
+ OPC_CheckInteger, 1|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 95,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 44, X86ISD::VZEXT_MOVL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXWQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 39, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXWQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXWQrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 0,
+ 114,
+ OPC_CheckInteger, 2|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 95,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 44, X86ISD::VZEXT_MOVL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXBDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 39, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXBDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXBDrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 0,
+ 114,
+ OPC_CheckInteger, 7|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 95,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 44, X86ISD::VZEXT_MOVL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXWQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 39, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXWQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXWQrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 0,
+ 114,
+ OPC_CheckInteger, 125|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 95,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 44, X86ISD::VZEXT_MOVL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXBQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 39, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 65,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXBQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVSXBQrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 0,
+ 114,
+ OPC_CheckInteger, 3|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 95,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 44, X86ISD::VZEXT_MOVL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXBQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 39, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 65,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXBQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVZXBQrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 0,
+ 82,
+ OPC_CheckInteger, 99|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 52,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BLENDPSrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BLENDPSrri), 0,
+ 1, MVT::v4f32, 3, 0, 1, 3,
+ 0,
+ 82,
+ OPC_CheckInteger, 98|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 52,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BLENDPDrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BLENDPDrri), 0,
+ 1, MVT::v2f64, 3, 0, 1, 3,
+ 0,
+ 82,
+ OPC_CheckInteger, 110|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 52,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PBLENDWrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PBLENDWrri), 0,
+ 1, MVT::v8i16, 3, 0, 1, 3,
+ 0,
+ 9|128,1,
+ OPC_CheckInteger, 103|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 53,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DPPSrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 53,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DPPSrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 7, 2, 4, 5, 6, 7, 8, 9,
+ 22,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DPPSrri), 0,
+ 1, MVT::v4f32, 3, 0, 1, 3,
+ 0,
+ 9|128,1,
+ OPC_CheckInteger, 102|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 53,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DPPDrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 7, 0, 4, 5, 6, 7, 8, 9,
+ 53,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DPPDrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 7, 2, 4, 5, 6, 7, 8, 9,
+ 22,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DPPDrri), 0,
+ 1, MVT::v2f64, 3, 0, 1, 3,
+ 0,
+ 9|128,1,
+ OPC_CheckInteger, 107|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 53,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MPSADBWrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 7, 0, 4, 5, 6, 7, 8, 9,
+ 53,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MPSADBWrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 7, 2, 4, 5, 6, 7, 8, 9,
+ 22,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MPSADBWrri), 0,
+ 1, MVT::v16i8, 3, 0, 1, 3,
+ 0,
+ 73,
+ OPC_CheckInteger, 38|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CMPSSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CMPSSrr), 0,
+ 1, MVT::v4f32, 3, 0, 1, 3,
+ 0,
+ 75,
+ OPC_CheckInteger, 37|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 45,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMPPSrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMPPSrri), 0,
+ 1, MVT::v4f32, 3, 0, 1, 3,
+ 0,
+ 73,
+ OPC_CheckInteger, 118|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CMPSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CMPSDrr), 0,
+ 1, MVT::v2f64, 3, 0, 1, 3,
+ 0,
+ 61,
+ OPC_CheckInteger, 126|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTDQ2PSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTDQ2PSrr), 0,
+ 1, MVT::v4f32, 1, 0,
+ 0,
+ 61,
+ OPC_CheckInteger, 125|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTDQ2PDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTDQ2PDrr), 0,
+ 1, MVT::v2f64, 1, 0,
+ 0,
+ 75,
+ OPC_CheckInteger, 117|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 45,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMPPDrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMPPDrri), 0,
+ 1, MVT::v2f64, 3, 0, 1, 3,
+ 0,
+ 110,
+ OPC_CheckInteger, 31|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDSBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 32|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDSWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 33|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDUSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDUSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDUSBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 34|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDUSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDUSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDUSWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 73|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBSBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 74|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBSWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 75|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBUSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBUSBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 76|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBUSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBUSWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 50|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULHUWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULHUWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULHUWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 49|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULHWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULHWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULHWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 51|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULUDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULUDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULUDQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 43|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMADDWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMADDWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMADDWDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 35|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PAVGBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PAVGBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PAVGBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 36|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PAVGWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PAVGWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PAVGWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 47|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINUBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINUBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINUBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 46|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINSWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 45|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXUBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXUBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXUBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 44|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXSWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 52|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSADBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSADBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSADBWrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 57|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSLLWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSLLWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 53|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSLLDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSLLDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 56|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSLLQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSLLQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 69|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 65|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 68|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 62|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRAWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRAWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 61|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRADrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRADrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 37|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 39|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 38|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 40|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 42|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 41|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 29|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PACKSSWBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PACKSSWBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 28|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PACKSSDWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PACKSSDWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 30|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PACKUSWBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PACKUSWBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 61,
+ OPC_CheckInteger, 83|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PABSBrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PABSBrr64), 0,
+ 1, MVT::v8i8, 1, 0,
+ 0,
+ 61,
+ OPC_CheckInteger, 84|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PABSBrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PABSBrr128), 0,
+ 1, MVT::v16i8, 1, 0,
+ 0,
+ 61,
+ OPC_CheckInteger, 87|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PABSWrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PABSWrr64), 0,
+ 1, MVT::v4i16, 1, 0,
+ 0,
+ 61,
+ OPC_CheckInteger, 88|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PABSWrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PABSWrr128), 0,
+ 1, MVT::v8i16, 1, 0,
+ 0,
+ 61,
+ OPC_CheckInteger, 85|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PABSDrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PABSDrr64), 0,
+ 1, MVT::v2i32, 1, 0,
+ 0,
+ 61,
+ OPC_CheckInteger, 86|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PABSDrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PABSDrr128), 0,
+ 1, MVT::v4i32, 1, 0,
+ 0,
+ 64,
+ OPC_CheckInteger, 95|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHADDWrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHADDWrr64), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 96|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHADDWrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHADDWrr128), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 91|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHADDDrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHADDDrr64), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 92|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHADDDrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHADDDrr128), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 93|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHADDSWrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHADDSWrr64), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 94|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHADDSWrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHADDSWrr128), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 101|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHSUBWrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHSUBWrr64), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 102|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHSUBWrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHSUBWrr128), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 97|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHSUBDrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHSUBDrr64), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 98|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHSUBDrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHSUBDrr128), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 99|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHSUBSWrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHSUBSWrr64), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 100|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHSUBSWrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHSUBSWrr128), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 103|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMADDUBSWrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMADDUBSWrr64), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 104|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMADDUBSWrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMADDUBSWrr128), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 105|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULHRSWrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULHRSWrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULHRSWrr64), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 106|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULHRSWrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULHRSWrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULHRSWrr128), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 107|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFBrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFBrr64), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 108|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFBrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFBrr128), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 109|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSIGNBrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSIGNBrr64), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 110|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSIGNBrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSIGNBrr128), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 113|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSIGNWrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSIGNWrr64), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 114|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSIGNWrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSIGNWrr128), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 111|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSIGNDrm64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSIGNDrr64), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 112|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSIGNDrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSIGNDrr128), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 81,
+ OPC_CheckInteger, 89|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 48,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 5, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PALIGNR64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 7, 0, 4, 5, 6, 7, 8, 10,
+ 24,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 5, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PALIGNR64rr), 0,
+ 1, MVT::v1i64, 3, 0, 1, 4,
+ 0,
+ 81,
+ OPC_CheckInteger, 90|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 48,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_EmitNodeXForm, 5, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PALIGNR128rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 7, 0, 4, 5, 6, 7, 8, 10,
+ 24,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitNodeXForm, 5, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PALIGNR128rr), 0,
+ 1, MVT::v2i64, 3, 0, 1, 4,
+ 0,
+ 72,
+ OPC_CheckInteger, 14|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROUNDPSm_Int), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 3, 4, 5, 6, 7, 8,
+ 20,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROUNDPSr_Int), 0,
+ 1, MVT::v4f32, 2, 0, 2,
+ 0,
+ 72,
+ OPC_CheckInteger, 13|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROUNDPDm_Int), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 3, 4, 5, 6, 7, 8,
+ 20,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROUNDPDr_Int), 0,
+ 1, MVT::v2f64, 2, 0, 2,
+ 0,
+ 61,
+ OPC_CheckInteger, 115|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 66,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHMINPOSUWrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PHMINPOSUWrr128), 0,
+ 1, MVT::v8i16, 1, 0,
+ 0,
+ 110,
+ OPC_CheckInteger, 111|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 108|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PACKUSDWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PACKUSDWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 120|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINSBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 121|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINSDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 122|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINUDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINUDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINUDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 123|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINUWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINUWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMINUWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 116|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXSBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 117|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXSDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 118|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXUDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXUDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXUDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 119|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXUWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXUWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMAXUWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 0,
+ 110,
+ OPC_CheckInteger, 8|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 44,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 44,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULDQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 72,
+ OPC_CheckInteger, 100|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 47,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::XMM0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BLENDVPDrm0), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 4, 5, 6, 7, 8,
+ 16,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitCopyToReg, 2, X86::XMM0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BLENDVPDrr0), 0|OPFL_FlagInput,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 72,
+ OPC_CheckInteger, 101|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 47,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::XMM0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BLENDVPSrm0), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 4, 5, 6, 7, 8,
+ 16,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitCopyToReg, 2, X86::XMM0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BLENDVPSrr0), 0|OPFL_FlagInput,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 72,
+ OPC_CheckInteger, 109|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 47,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::XMM0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PBLENDVBrm0), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 4, 5, 6, 7, 8,
+ 16,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitCopyToReg, 2, X86::XMM0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PBLENDVBrr0), 0|OPFL_FlagInput,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 64,
+ OPC_CheckInteger, 28|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 75,
+ OPC_CheckInteger, 29|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 44,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 22,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRIrr), 0,
+ 2, MVT::i32, MVT::i32, 3, 0, 1, 3,
+ 0,
+ 75,
+ OPC_CheckInteger, 30|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 44,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRIArm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 22,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRIArr), 0,
+ 2, MVT::i32, MVT::i32, 3, 0, 1, 3,
+ 0,
+ 75,
+ OPC_CheckInteger, 31|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 44,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRICrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 22,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRICrr), 0,
+ 2, MVT::i32, MVT::i32, 3, 0, 1, 3,
+ 0,
+ 75,
+ OPC_CheckInteger, 32|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 44,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRIOrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 22,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRIOrr), 0,
+ 2, MVT::i32, MVT::i32, 3, 0, 1, 3,
+ 0,
+ 75,
+ OPC_CheckInteger, 33|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 44,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRISrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 22,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRISrr), 0,
+ 2, MVT::i32, MVT::i32, 3, 0, 1, 3,
+ 0,
+ 75,
+ OPC_CheckInteger, 34|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 44,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRIZrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 22,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRIZrr), 0,
+ 2, MVT::i32, MVT::i32, 3, 0, 1, 3,
+ 0,
+ 90,
+ OPC_CheckInteger, 21|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_Scope, 51,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 2,
+ OPC_EmitConvertToTarget, 5,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 4, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRIrm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 7, 0, 6, 7, 8, 9, 10, 11,
+ 29,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 4,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 3, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRIrr), 0|OPFL_FlagInput,
+ 2, MVT::i32, MVT::i32, 3, 0, 2, 5,
+ 0,
+ 90,
+ OPC_CheckInteger, 22|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_Scope, 51,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 2,
+ OPC_EmitConvertToTarget, 5,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 4, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRIArm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 7, 0, 6, 7, 8, 9, 10, 11,
+ 29,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 4,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 3, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRIArr), 0|OPFL_FlagInput,
+ 2, MVT::i32, MVT::i32, 3, 0, 2, 5,
+ 0,
+ 90,
+ OPC_CheckInteger, 23|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_Scope, 51,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 2,
+ OPC_EmitConvertToTarget, 5,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 4, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRICrm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 7, 0, 6, 7, 8, 9, 10, 11,
+ 29,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 4,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 3, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRICrr), 0|OPFL_FlagInput,
+ 2, MVT::i32, MVT::i32, 3, 0, 2, 5,
+ 0,
+ 90,
+ OPC_CheckInteger, 24|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_Scope, 51,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 2,
+ OPC_EmitConvertToTarget, 5,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 4, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRIOrm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 7, 0, 6, 7, 8, 9, 10, 11,
+ 29,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 4,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 3, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRIOrr), 0|OPFL_FlagInput,
+ 2, MVT::i32, MVT::i32, 3, 0, 2, 5,
+ 0,
+ 90,
+ OPC_CheckInteger, 25|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_Scope, 51,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 2,
+ OPC_EmitConvertToTarget, 5,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 4, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRISrm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 7, 0, 6, 7, 8, 9, 10, 11,
+ 29,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 4,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 3, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRISrr), 0|OPFL_FlagInput,
+ 2, MVT::i32, MVT::i32, 3, 0, 2, 5,
+ 0,
+ 90,
+ OPC_CheckInteger, 26|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_Scope, 51,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 2,
+ OPC_EmitConvertToTarget, 5,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 4, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRIZrm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 7, 0, 6, 7, 8, 9, 10, 11,
+ 29,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 4,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 3, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRIZrr), 0|OPFL_FlagInput,
+ 2, MVT::i32, MVT::i32, 3, 0, 2, 5,
+ 0,
+ 106,
+ OPC_CheckInteger, 73|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDSBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 74|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDSWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 75|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDUSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDUSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDUSBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 76|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDUSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDUSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDUSWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 111|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBSBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 112|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBSWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 113|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBUSBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBUSBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 114|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBUSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBUSWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 91|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULHWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULHWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULHWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 92|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULHUWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULHUWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULHUWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 93|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULUDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULUDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULUDQrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 85|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMADDWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMADDWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMADDWDrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 77|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PAVGBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PAVGBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PAVGBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 78|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PAVGWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PAVGWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PAVGWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 89|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMINUBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMINUBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMINUBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 88|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMINSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMINSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMINSWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 87|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMAXUBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMAXUBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMAXUBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 86|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMAXSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMAXSWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMAXSWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 106,
+ OPC_CheckInteger, 94|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 42,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSADBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSADBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSADBWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 107|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRLWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRLWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 105|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRLDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRLDrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 106|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRLQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRLQrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 97|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSLLWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSLLWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 95|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSLLDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSLLDrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 96|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSLLQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSLLQrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 102|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRAWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRAWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 101|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRADrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRADrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 79|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 81|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 80|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQDrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 82|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 84|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 83|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTDrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 71|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PACKSSWBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PACKSSWBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 70|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PACKSSDWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PACKSSDWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 62,
+ OPC_CheckInteger, 72|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 41,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PACKUSWBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PACKUSWBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 73,
+ OPC_CheckInteger, 35|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 43,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRM128MEM), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPISTRM128REG), 0,
+ 1, MVT::v16i8, 3, 0, 1, 3,
+ 0,
+ 88,
+ OPC_CheckInteger, 27|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_Scope, 50,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 2,
+ OPC_EmitConvertToTarget, 5,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 4, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRM128MEM), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::v16i8, 7, 0, 6, 7, 8, 9, 10, 11,
+ 28,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_RecordChild5,
+ OPC_MoveChild, 5,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_EmitConvertToTarget, 4,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 3, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPESTRM128REG), 0|OPFL_FlagInput,
+ 1, MVT::v16i8, 3, 0, 2, 5,
+ 0,
+ 52,
+ OPC_CheckInteger, 4|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSD2SI64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSD2SI64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 52,
+ OPC_CheckInteger, 12|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTSD2SI64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTSD2SI64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 57,
+ OPC_CheckInteger, 7|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSI2SD64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSI2SD64rr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 57,
+ OPC_CheckInteger, 50|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSI2SS64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSI2SS64rr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 52,
+ OPC_CheckInteger, 52|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSS2SI64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSS2SI64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 52,
+ OPC_CheckInteger, 56|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTSS2SI64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTSS2SI64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 52,
+ OPC_CheckInteger, 51|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSS2SIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSS2SIrr), 0,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 52,
+ OPC_CheckInteger, 48|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPS2PIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPS2PIrr), 0,
+ 1, MVT::v2i32, 1, 0,
+ 0,
+ 52,
+ OPC_CheckInteger, 54|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTPS2PIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTPS2PIrr), 0,
+ 1, MVT::v2i32, 1, 0,
+ 0,
+ 55,
+ OPC_CheckInteger, 47|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 34,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPI2PSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPI2PSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 52,
+ OPC_CheckInteger, 55|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTSS2SIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTSS2SIrr), 0,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 55,
+ OPC_CheckInteger, 49|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 34,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSI2SSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSI2SSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 57,
+ OPC_CheckInteger, 60|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXPSrm_Int), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXPSrr_Int), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 57,
+ OPC_CheckInteger, 62|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINPSrm_Int), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINPSrr_Int), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 54,
+ OPC_CheckInteger, 72|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTPSm_Int), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTPSr_Int), 0,
+ 1, MVT::v4f32, 1, 0,
+ 0,
+ 54,
+ OPC_CheckInteger, 69|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RSQRTPSm_Int), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RSQRTPSr_Int), 0,
+ 1, MVT::v4f32, 1, 0,
+ 0,
+ 54,
+ OPC_CheckInteger, 67|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RCPPSm_Int), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RCPPSr_Int), 0,
+ 1, MVT::v4f32, 1, 0,
+ 0,
+ 52,
+ OPC_CheckInteger, 3|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSD2SIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSD2SIrr), 0,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 54,
+ OPC_CheckInteger, 45|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPD2PIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPD2PIrr), 0,
+ 1, MVT::v2i32, 1, 0,
+ 0,
+ 54,
+ OPC_CheckInteger, 53|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTPD2PIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTPD2PIrr), 0,
+ 1, MVT::v2i32, 1, 0,
+ 0,
+ 52,
+ OPC_CheckInteger, 46|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPI2PDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPI2PDrr), 0,
+ 1, MVT::v2f64, 1, 0,
+ 0,
+ 52,
+ OPC_CheckInteger, 11|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTSD2SIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTSD2SIrr), 0,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 57,
+ OPC_CheckInteger, 18|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXPDrm_Int), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXPDrr_Int), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 57,
+ OPC_CheckInteger, 21|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINPDrm_Int), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINPDrr_Int), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 54,
+ OPC_CheckInteger, 1|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPS2DQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPS2DQrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 0,
+ 54,
+ OPC_CheckInteger, 10|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTPS2DQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTPS2DQrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 0,
+ 54,
+ OPC_CheckInteger, 127|128,3,
+ OPC_MoveParent,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPD2DQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPD2DQrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 0,
+ 54,
+ OPC_CheckInteger, 9|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTPD2DQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTPD2DQrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 0,
+ 52,
+ OPC_CheckInteger, 2|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPS2PDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPS2PDrr), 0,
+ 1, MVT::v2f64, 1, 0,
+ 0,
+ 54,
+ OPC_CheckInteger, 0|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPD2PSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPD2PSrr), 0,
+ 1, MVT::v4f32, 1, 0,
+ 0,
+ 55,
+ OPC_CheckInteger, 6|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 34,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSI2SDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSI2SDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 55,
+ OPC_CheckInteger, 5|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 34,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSD2SSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSD2SSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 55,
+ OPC_CheckInteger, 8|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 34,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSS2SDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTSS2SDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 54,
+ OPC_CheckInteger, 77|128,4,
+ OPC_MoveParent,
+ OPC_Scope, 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTPDm_Int), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
+ 11,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTPDr_Int), 0,
+ 1, MVT::v2f64, 1, 0,
+ 0,
+ 57,
+ OPC_CheckInteger, 90|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSUBPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSUBPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 57,
+ OPC_CheckInteger, 89|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSUBPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSUBPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 57,
+ OPC_CheckInteger, 92|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::HADDPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::HADDPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 57,
+ OPC_CheckInteger, 91|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::HADDPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::HADDPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 57,
+ OPC_CheckInteger, 94|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::HSUBPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::HSUBPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 57,
+ OPC_CheckInteger, 93|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::HSUBPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::HSUBPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 96,
+ OPC_CheckInteger, 9|128,5,
+ OPC_MoveParent,
+ OPC_Scope, 37,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULLDrm_int), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 37,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULLDrm_int), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULLDrr_int), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 55,
+ OPC_CheckInteger, 20|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 34,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CRC32m8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CRC32r8), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 55,
+ OPC_CheckInteger, 17|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 34,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CRC32m16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CRC32r16), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 55,
+ OPC_CheckInteger, 18|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 34,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CRC32m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CRC32r32), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 55,
+ OPC_CheckInteger, 19|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 34,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 14,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CRC64m64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 14,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CRC64r64), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 52,
+ OPC_CheckInteger, 16|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_Scope, 22,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 8,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROUNDSSm_Int), 0|OPFL_Chain,
+ 1, MVT::v4f32, 7, 0, 3, 4, 5, 6, 7, 9,
+ 12,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROUNDSSr_Int), 0,
+ 1, MVT::v4f32, 3, 0, 1, 3,
+ 0,
+ 52,
+ OPC_CheckInteger, 15|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_Scope, 22,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 8,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROUNDSDm_Int), 0|OPFL_Chain,
+ 1, MVT::v2f64, 7, 0, 3, 4, 5, 6, 7, 9,
+ 12,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROUNDSDr_Int), 0,
+ 1, MVT::v2f64, 3, 0, 1, 3,
+ 0,
+ 40,
+ OPC_CheckInteger, 36|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_Scope, 19,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSSrm_Int), 0|OPFL_Chain,
+ 1, MVT::v4f32, 6, 0, 2, 3, 4, 5, 6,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSSrr_Int), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 40,
+ OPC_CheckInteger, 66|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_Scope, 19,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSSrm_Int), 0|OPFL_Chain,
+ 1, MVT::v4f32, 6, 0, 2, 3, 4, 5, 6,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSSrr_Int), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 40,
+ OPC_CheckInteger, 76|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_Scope, 19,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBSSrm_Int), 0|OPFL_Chain,
+ 1, MVT::v4f32, 6, 0, 2, 3, 4, 5, 6,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBSSrr_Int), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 40,
+ OPC_CheckInteger, 57|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_Scope, 19,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVSSrm_Int), 0|OPFL_Chain,
+ 1, MVT::v4f32, 6, 0, 2, 3, 4, 5, 6,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVSSrr_Int), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 40,
+ OPC_CheckInteger, 61|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_Scope, 19,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXSSrm_Int), 0|OPFL_Chain,
+ 1, MVT::v4f32, 6, 0, 2, 3, 4, 5, 6,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXSSrr_Int), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 40,
+ OPC_CheckInteger, 63|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_Scope, 19,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINSSrm_Int), 0|OPFL_Chain,
+ 1, MVT::v4f32, 6, 0, 2, 3, 4, 5, 6,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINSSrr_Int), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 37,
+ OPC_CheckInteger, 73|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_Scope, 18,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitMergeInputChains, 1, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTSSm_Int), 0|OPFL_Chain,
+ 1, MVT::v4f32, 5, 1, 2, 3, 4, 5,
+ 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTSSr_Int), 0,
+ 1, MVT::v4f32, 1, 0,
+ 0,
+ 37,
+ OPC_CheckInteger, 70|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_Scope, 18,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitMergeInputChains, 1, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RSQRTSSm_Int), 0|OPFL_Chain,
+ 1, MVT::v4f32, 5, 1, 2, 3, 4, 5,
+ 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RSQRTSSr_Int), 0,
+ 1, MVT::v4f32, 1, 0,
+ 0,
+ 37,
+ OPC_CheckInteger, 68|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_Scope, 18,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_EmitMergeInputChains, 1, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RCPSSm_Int), 0|OPFL_Chain,
+ 1, MVT::v4f32, 5, 1, 2, 3, 4, 5,
+ 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RCPSSr_Int), 0,
+ 1, MVT::v4f32, 1, 0,
+ 0,
+ 40,
+ OPC_CheckInteger, 115|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_Scope, 19,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSDrm_Int), 0|OPFL_Chain,
+ 1, MVT::v2f64, 6, 0, 2, 3, 4, 5, 6,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSDrr_Int), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 40,
+ OPC_CheckInteger, 27|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_Scope, 19,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSDrm_Int), 0|OPFL_Chain,
+ 1, MVT::v2f64, 6, 0, 2, 3, 4, 5, 6,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSDrr_Int), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 40,
+ OPC_CheckInteger, 82|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_Scope, 19,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBSDrm_Int), 0|OPFL_Chain,
+ 1, MVT::v2f64, 6, 0, 2, 3, 4, 5, 6,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBSDrr_Int), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 40,
+ OPC_CheckInteger, 13|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_Scope, 19,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVSDrm_Int), 0|OPFL_Chain,
+ 1, MVT::v2f64, 6, 0, 2, 3, 4, 5, 6,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVSDrr_Int), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 40,
+ OPC_CheckInteger, 19|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_Scope, 19,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXSDrm_Int), 0|OPFL_Chain,
+ 1, MVT::v2f64, 6, 0, 2, 3, 4, 5, 6,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXSDrr_Int), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 40,
+ OPC_CheckInteger, 22|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_Scope, 19,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINSDrm_Int), 0|OPFL_Chain,
+ 1, MVT::v2f64, 6, 0, 2, 3, 4, 5, 6,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINSDrr_Int), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 37,
+ OPC_CheckInteger, 78|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_Scope, 18,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/0,
+ OPC_EmitMergeInputChains, 1, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTSDm_Int), 0|OPFL_Chain,
+ 1, MVT::v2f64, 5, 1, 2, 3, 4, 5,
+ 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTSDr_Int), 0,
+ 1, MVT::v2f64, 1, 0,
+ 0,
+ 24,
+ OPC_CheckInteger, 60|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSLLWri), 0,
+ 1, MVT::v8i16, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 58|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSLLDri), 0,
+ 1, MVT::v4i32, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 59|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSLLQri), 0,
+ 1, MVT::v2i64, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 72|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLWri), 0,
+ 1, MVT::v8i16, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 70|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLDri), 0,
+ 1, MVT::v4i32, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 71|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLQri), 0,
+ 1, MVT::v2i64, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 64|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRAWri), 0,
+ 1, MVT::v8i16, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 63|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRADri), 0,
+ 1, MVT::v4i32, 2, 0, 2,
+ 27,
+ OPC_CheckInteger, 54|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 5, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSLLDQri), 0,
+ 1, MVT::v2i64, 2, 0, 3,
+ 27,
+ OPC_CheckInteger, 66|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 5, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLDQri), 0,
+ 1, MVT::v2i64, 2, 0, 3,
+ 24,
+ OPC_CheckInteger, 55|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSLLDQri), 0,
+ 1, MVT::v2i64, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 67|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLDQri), 0,
+ 1, MVT::v2i64, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 105|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INSERTPSrr), 0,
+ 1, MVT::v4f32, 3, 0, 1, 3,
+ 24,
+ OPC_CheckInteger, 110|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRLWri), 0,
+ 1, MVT::v4i16, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 108|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRLDri), 0,
+ 1, MVT::v2i32, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 109|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRLQri), 0,
+ 1, MVT::v1i64, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 100|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSLLWri), 0,
+ 1, MVT::v4i16, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 98|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSLLDri), 0,
+ 1, MVT::v2i32, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 99|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSLLQri), 0,
+ 1, MVT::v1i64, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 104|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRAWri), 0,
+ 1, MVT::v4i16, 2, 0, 2,
+ 24,
+ OPC_CheckInteger, 103|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRADri), 0,
+ 1, MVT::v2i32, 2, 0, 2,
+ 15,
+ OPC_CheckInteger, 64|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVMSKPSrr), 0,
+ 1, MVT::i32, 1, 0,
+ 15,
+ OPC_CheckInteger, 23|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVMSKPDrr), 0,
+ 1, MVT::i32, 1, 0,
+ 15,
+ OPC_CheckInteger, 48|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMOVMSKBrr), 0,
+ 1, MVT::i32, 1, 0,
+ 15,
+ OPC_CheckInteger, 90|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMOVMSKBrr), 0,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 1|128,33, ISD::AND,
+ OPC_Scope, 14|128,15,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 41|128,7, ISD::XOR,
+ OPC_Scope, 45|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_Scope, 57,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 57,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 50,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 12|128,2,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 44|128,1, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_SwitchType , 41, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 41, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 41, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 37, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 82, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_SwitchType , 37, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 37, MVT::v8i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 72|128,2,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 50, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 13|128,2, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 48|128,1, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_SwitchType , 42, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 42, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 42, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 38, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 84, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_SwitchType , 38, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 38, MVT::v8i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 0,
+ 79,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 79,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 2|128,7, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 38|128,3,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 39|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 124, ISD::BIT_CONVERT,
+ OPC_Scope, 42,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 35,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 35, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 39,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 39,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 39,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 39,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 39,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 39,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 111|128,1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 37,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 37,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 37,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 37,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 37,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_CheckType, MVT::v8i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 37,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_CheckType, MVT::v8i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 79,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 32,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 32,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 77,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 32,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 32,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 68,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_Scope, 26,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 87, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_Scope, 41,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 66|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 92,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 27,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 71|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 95,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 16|128,1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_CheckPredicate, 16,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 72, MVT::i32,
+ OPC_Scope, 34,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, X86::GR32_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i32, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rr8), 0,
+ 1, MVT::i32, 1, 4,
+ 34,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, X86::GR32_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i32, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32_NOREXrr8), 0,
+ 1, MVT::i32, 1, 4,
+ 0,
+ 48, MVT::i64,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_EmitInteger, MVT::i32, X86::GR64_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i64, 2, 0, 2,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 3, 4,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVZX32_NOREXrr8), 0,
+ 1, MVT::i32, 1, 5,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0,
+ 1, MVT::i64, 3, 1, 6, 7,
+ 0,
+ 73|128,2,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 126|128,1, ISD::XOR,
+ OPC_Scope, 74,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 33, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPDrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 33, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPDrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 16|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 93, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_SwitchType , 32, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPSrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 17, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 17, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 15, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 0,
+ 38, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_SwitchType , 15, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 15, MVT::v8i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 0,
+ 0,
+ 30,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPSrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 66, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 25, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPDrr), 0,
+ 1, MVT::v2i64, 2, 1, 0,
+ 25, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPDrr), 0,
+ 1, MVT::v2i64, 2, 1, 0,
+ 0,
+ 0,
+ 67,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPSrr), 0,
+ 1, MVT::v2i64, 2, 1, 0,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDNPSrr), 0,
+ 1, MVT::v2i64, 2, 1, 0,
+ 0,
+ 34,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 67,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 1, 0,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 1, 0,
+ 0,
+ 34,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 67,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 1, 0,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 1, 0,
+ 0,
+ 34,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 67,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 29,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 1, 0,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v16i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 1, 0,
+ 0,
+ 32,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 63,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 27,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 1, 0,
+ 27,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 1, 0,
+ 0,
+ 32,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 63,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 27,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 1, 0,
+ 27,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_CheckType, MVT::v4i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 1, 0,
+ 0,
+ 32,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_CheckType, MVT::v8i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 63,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 27,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_CheckType, MVT::v8i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 1, 0,
+ 27,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_CheckPredicate, 68,
+ OPC_CheckType, MVT::v8i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 1, 0,
+ 0,
+ 69,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 38,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 11, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 11, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 0,
+ 23,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 53,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 22,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 1, 0,
+ 22,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrr), 0,
+ 1, MVT::v2i64, 2, 1, 0,
+ 0,
+ 27,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 53,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::XOR,
+ OPC_Scope, 22,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 1, 0,
+ 22,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BUILD_VECTOR,
+ OPC_CheckPredicate, 67,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrr), 0,
+ 1, MVT::v1i64, 2, 1, 0,
+ 0,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDPDrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 27,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitInteger, MVT::i32, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rr16), 0,
+ 1, MVT::i32, 1, 2,
+ 29,
+ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rr32), 0,
+ 1, MVT::i64, 1, 2,
+ 27,
+ OPC_CheckAndImm, 127|128,127|128,3,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitInteger, MVT::i32, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rr16), 0,
+ 1, MVT::i64, 1, 2,
+ 24|128,1,
+ OPC_CheckAndImm, 127|128,1,
+ OPC_RecordChild0,
+ OPC_SwitchType , 20, MVT::i64,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rr8), 0,
+ 1, MVT::i64, 1, 2,
+ 60, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rr8), 0,
+ 1, MVT::i32, 1, 2,
+ 34,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, X86::GR32_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i32, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rr8), 0,
+ 1, MVT::i32, 1, 4,
+ 0,
+ 60, MVT::i16,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX16rr8), 0,
+ 1, MVT::i16, 1, 2,
+ 34,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX16rr8), 0,
+ 1, MVT::i16, 1, 4,
+ 0,
+ 0,
+ 11|128,2,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 38|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16ri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32ri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64ri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64ri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 47,
+ OPC_CheckPredicate, 69,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i32, 2, 0, 3,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 6, 5,
+ OPC_EmitNode, TARGET_OPCODE(X86::AND32ri), 0,
+ 1, MVT::i32, 2, 4, 6,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0,
+ 1, MVT::i64, 3, 2, 7, 8,
+ 45,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8ri), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 2,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16ri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32ri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8rr), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 28,
+ OPC_CheckType, MVT::v2i64,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ANDPSrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 13,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 0,
+ 0,
+ 109|128,12, X86ISD::CMP,
+ OPC_Scope, 83|128,6,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 108|128,3, ISD::AND,
+ OPC_Scope, 47|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 80,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 30,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 42,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 42,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 25|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 36,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 34,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 34,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 36,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 28|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 35,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 35,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 37,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 93|128,2, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 100,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 58, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 24,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 28, MVT::i8,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 36,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
+ 29,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
+ 29,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
+ 0,
+ 0,
+ 110,
+ OPC_RecordChild0,
+ OPC_Scope, 36,
+ OPC_CheckChild0Type, MVT::i8,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 34,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 34,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 37,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
+ 118,
+ OPC_RecordChild0,
+ OPC_Scope, 36,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 38,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UCOMISSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 38,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UCOMISDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 54|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::AND,
+ OPC_Scope, 68,
+ OPC_CheckPredicate, 70,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 17, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST8ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 17, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST16ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 17, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST32ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
+ 28,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST64ri32), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 57,
+ OPC_CheckPredicate, 70,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 15, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST8rr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 15, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST16rr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 15, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST32rr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 19,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST64rr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 80|128,2,
+ OPC_RecordChild0,
+ OPC_Scope, 50,
+ OPC_CheckChild0Type, MVT::i8,
+ OPC_Scope, 14,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST8rr), 0,
+ 1, MVT::i32, 2, 0, 0,
+ 30,
+ OPC_RecordChild1,
+ OPC_Scope, 16,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP8ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP8rr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 68,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_Scope, 14,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST16rr), 0,
+ 1, MVT::i32, 2, 0, 0,
+ 48,
+ OPC_RecordChild1,
+ OPC_Scope, 34,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 14,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP16ri8), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 12,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP16ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP16rr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 68,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_Scope, 14,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST32rr), 0,
+ 1, MVT::i32, 2, 0, 0,
+ 48,
+ OPC_RecordChild1,
+ OPC_Scope, 34,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 14,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP32ri8), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 12,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP32ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP32rr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 70,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_Scope, 14,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST64rr), 0,
+ 1, MVT::i32, 2, 0, 0,
+ 50,
+ OPC_RecordChild1,
+ OPC_Scope, 36,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 14,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP64ri8), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 14,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP64ri32), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP64rr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_RecordChild1,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UCOM_FpIr32), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UCOMISSrr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 29,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_RecordChild1,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UCOM_FpIr64), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UCOMISDrr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 12,
+ OPC_CheckChild0Type, MVT::f80,
+ OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UCOM_FpIr80), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 78, X86ISD::INSERTPS,
+ OPC_RecordChild0,
+ OPC_Scope, 52,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INSERTPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INSERTPSrr), 0,
+ 1, MVT::v4f32, 3, 0, 1, 3,
+ 0,
+ 76, X86ISD::MMX_PINSRW,
+ OPC_RecordChild0,
+ OPC_Scope, 50,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::ANY_EXTEND,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PINSRWrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PINSRWrri), 0,
+ 1, MVT::v4i16, 3, 0, 1, 3,
+ 0,
+ 88, X86ISD::MOVQ2DQ,
+ OPC_Scope, 75,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 41, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDI2PDIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 26, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVQI2PQIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 9,
+ OPC_RecordChild0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2DQrr), 0,
+ 1, MVT::v2i64, 1, 0,
+ 0,
+ 17|128,37, X86ISD::CMOV,
+ OPC_Scope, 73|128,9,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 9,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 9,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 7,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 7,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 5,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 5,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 15,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 15,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 12,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 12,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 14,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 14,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 11,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 11,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 13,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVO16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 13,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVO32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 10,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 10,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
+ 0,
+ 104|128,9,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 9,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 9,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 7,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 7,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 5,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 5,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 14,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 14,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 11,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 11,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 15,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 15,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 12,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 12,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 13,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 13,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 10,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVO16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 10,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVO32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
+ 0,
+ 100|128,3,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_Scope, 28,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 9,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 7,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 5,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 15,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 12,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 14,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 11,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 13,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVO64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 10,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 4, 5, 6, 7, 8,
+ 0,
+ 100|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_Scope, 28,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 9,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 7,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 5,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 14,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 11,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 15,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 12,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 13,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 28,
+ OPC_CheckInteger, 10,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVO64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 4, 5, 6, 7, 8,
+ 0,
+ 12|128,10,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 4|128,9,
+ OPC_MoveChild, 2,
+ OPC_Scope, 94,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 14, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB_Fp32), 0|OPFL_FlagInput,
+ 1, MVT::f32, 2, 0, 1,
+ 14, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB_Fp64), 0|OPFL_FlagInput,
+ 1, MVT::f64, 2, 0, 1,
+ 12, MVT::f80,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB_Fp80), 0|OPFL_FlagInput,
+ 1, MVT::f80, 2, 0, 1,
+ 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 94,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 14, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE_Fp32), 0|OPFL_FlagInput,
+ 1, MVT::f32, 2, 0, 1,
+ 14, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE_Fp64), 0|OPFL_FlagInput,
+ 1, MVT::f64, 2, 0, 1,
+ 12, MVT::f80,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE_Fp80), 0|OPFL_FlagInput,
+ 1, MVT::f80, 2, 0, 1,
+ 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 94,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 14, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE_Fp32), 0|OPFL_FlagInput,
+ 1, MVT::f32, 2, 0, 1,
+ 14, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE_Fp64), 0|OPFL_FlagInput,
+ 1, MVT::f64, 2, 0, 1,
+ 12, MVT::f80,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE_Fp80), 0|OPFL_FlagInput,
+ 1, MVT::f80, 2, 0, 1,
+ 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 94,
+ OPC_CheckInteger, 14,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 14, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP_Fp32), 0|OPFL_FlagInput,
+ 1, MVT::f32, 2, 0, 1,
+ 14, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP_Fp64), 0|OPFL_FlagInput,
+ 1, MVT::f64, 2, 0, 1,
+ 12, MVT::f80,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP_Fp80), 0|OPFL_FlagInput,
+ 1, MVT::f80, 2, 0, 1,
+ 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 94,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 14, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNB_Fp32), 0|OPFL_FlagInput,
+ 1, MVT::f32, 2, 0, 1,
+ 14, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNB_Fp64), 0|OPFL_FlagInput,
+ 1, MVT::f64, 2, 0, 1,
+ 12, MVT::f80,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNB_Fp80), 0|OPFL_FlagInput,
+ 1, MVT::f80, 2, 0, 1,
+ 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 94,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 14, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNBE_Fp32), 0|OPFL_FlagInput,
+ 1, MVT::f32, 2, 0, 1,
+ 14, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNBE_Fp64), 0|OPFL_FlagInput,
+ 1, MVT::f64, 2, 0, 1,
+ 12, MVT::f80,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNBE_Fp80), 0|OPFL_FlagInput,
+ 1, MVT::f80, 2, 0, 1,
+ 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 94,
+ OPC_CheckInteger, 9,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 14, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE_Fp32), 0|OPFL_FlagInput,
+ 1, MVT::f32, 2, 0, 1,
+ 14, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE_Fp64), 0|OPFL_FlagInput,
+ 1, MVT::f64, 2, 0, 1,
+ 12, MVT::f80,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE_Fp80), 0|OPFL_FlagInput,
+ 1, MVT::f80, 2, 0, 1,
+ 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 94,
+ OPC_CheckInteger, 11,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 14, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP_Fp32), 0|OPFL_FlagInput,
+ 1, MVT::f32, 2, 0, 1,
+ 14, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP_Fp64), 0|OPFL_FlagInput,
+ 1, MVT::f64, 2, 0, 1,
+ 12, MVT::f80,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP_Fp80), 0|OPFL_FlagInput,
+ 1, MVT::f80, 2, 0, 1,
+ 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 48,
+ OPC_CheckInteger, 7,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 48,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 48,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 48,
+ OPC_CheckInteger, 5,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 48,
+ OPC_CheckInteger, 15,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 48,
+ OPC_CheckInteger, 12,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 48,
+ OPC_CheckInteger, 13,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVO16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVO32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVO64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 48,
+ OPC_CheckInteger, 10,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO16rr), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO32rr), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO64rr), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 0|128,1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_SwitchType , 15, MVT::i8,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOV_GR8), 0|OPFL_FlagInput,
+ 1, MVT::i8, 3, 0, 1, 4,
+ 15, MVT::f32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOV_FR32), 0|OPFL_FlagInput,
+ 1, MVT::f32, 3, 0, 1, 4,
+ 15, MVT::f64,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOV_FR64), 0|OPFL_FlagInput,
+ 1, MVT::f64, 3, 0, 1, 4,
+ 15, MVT::v4f32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOV_V4F32), 0|OPFL_FlagInput,
+ 1, MVT::v4f32, 3, 0, 1, 4,
+ 15, MVT::v2f64,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOV_V2F64), 0|OPFL_FlagInput,
+ 1, MVT::v2f64, 3, 0, 1, 4,
+ 15, MVT::v2i64,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOV_V2I64), 0|OPFL_FlagInput,
+ 1, MVT::v2i64, 3, 0, 1, 4,
+ 15, MVT::v1i64,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitCopyToReg, 3, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOV_V1I64), 0|OPFL_FlagInput,
+ 1, MVT::v1i64, 3, 0, 1, 4,
+ 0,
+ 0,
+ 0,
+ 112|128,6, ISD::MUL,
+ OPC_Scope, 50|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 77,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rmi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 22, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rmi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 22, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rmi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 27,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rmi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 51,
+ OPC_MoveParent,
+ OPC_SwitchType , 22, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 22, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 0,
+ 81,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 33,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULLWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULLWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 82,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 34,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULLWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULLWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 20|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 31,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitCopyToReg, 0, X86::AL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL8m), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 73,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULLDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 117,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 74,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 20, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 20, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 31,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULLDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 57,
+ OPC_RecordNode,
+ OPC_SwitchType , 36, MVT::i32,
+ OPC_Scope, 16,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64_32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 14, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64r), 0,
+ 1, MVT::i64, 4, 1, 2, 3, 4,
+ 0,
+ 77|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 104,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 31,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 14,
+ OPC_CheckType, MVT::i8,
+ OPC_EmitCopyToReg, 0, X86::AL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL8r), 0|OPFL_FlagInput,
+ 2, MVT::i8, MVT::i32, 1, 1,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULLWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULLDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULLWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 0,
+ 111|128,1, X86ISD::BT,
+ OPC_Scope, 127,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BT16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 38,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BT32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 40,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BT64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 108,
+ OPC_RecordChild0,
+ OPC_Scope, 34,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_RecordChild1,
+ OPC_Scope, 18,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BT16ri8), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BT16rr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 34,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_RecordChild1,
+ OPC_Scope, 18,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BT32ri8), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BT32rr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 34,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_RecordChild1,
+ OPC_Scope, 18,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BT64ri8), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BT64rr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 0,
+ 121|128,4, X86ISD::SMUL,
+ OPC_Scope, 109|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 39,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rmi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 39,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rmi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 72,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rmi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 27,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rmi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 37,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 37,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 101,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 29,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 103,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 30,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 32,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 56|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 31,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_SwitchType , 10, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 0,
+ 10, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 0,
+ 0,
+ 19|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 104,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 31,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 0,
+ 105, ISD::PREFETCH,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 3,
+ OPC_Scope, 22,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PREFETCHT0), 0|OPFL_Chain,
+ 0, 5, 2, 3, 4, 5, 6,
+ 22,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PREFETCHT1), 0|OPFL_Chain,
+ 0, 5, 2, 3, 4, 5, 6,
+ 22,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PREFETCHT2), 0|OPFL_Chain,
+ 0, 5, 2, 3, 4, 5, 6,
+ 22,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PREFETCHNTA), 0|OPFL_Chain,
+ 0, 5, 2, 3, 4, 5, 6,
+ 0,
+ 8|128,1, ISD::INSERT_VECTOR_ELT,
+ OPC_RecordChild0,
+ OPC_Scope, 90,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 41,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PINSRQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 7, 0, 4, 5, 6, 7, 8, 9,
+ 39,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PINSRDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 0,
+ 41,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_SwitchType , 14, MVT::v2i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PINSRQrr), 0,
+ 1, MVT::v2i64, 3, 0, 1, 3,
+ 14, MVT::v4i32,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PINSRDrr), 0,
+ 1, MVT::v4i32, 3, 0, 1, 3,
+ 0,
+ 0,
+ 70|128,17, ISD::OR,
+ OPC_Scope, 39|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 87, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_Scope, 41,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ORPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ORPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 72, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_Scope, 26,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ORPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ORPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 39|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 95,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PORrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PORrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 20|128,7,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 37|128,1, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 96,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 20, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 20, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 20, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 31,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PORrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PORrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 113|128,2, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_Scope, 84|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_Scope, 106,
+ OPC_RecordChild0,
+ OPC_RecordChild0,
+ OPC_Scope, 50,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::ECX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 3,
+ 50,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::CX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 3,
+ 0,
+ 98,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 44,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::ECX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 3, 0,
+ 44,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::CX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 3, 0,
+ 0,
+ 0,
+ 72,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 26,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 3,
+ 26,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 3,
+ 0,
+ 78,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 34,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 3, 0,
+ 34,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 3, 0,
+ 0,
+ 0,
+ 113|128,2, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_Scope, 84|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_Scope, 106,
+ OPC_RecordChild0,
+ OPC_RecordChild0,
+ OPC_Scope, 50,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::ECX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 3,
+ 50,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::CX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 3,
+ 0,
+ 98,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 44,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::ECX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 3, 0,
+ 44,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::CX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 3, 0,
+ 0,
+ 0,
+ 72,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 26,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 3,
+ 26,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 3,
+ 0,
+ 78,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 34,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 3, 0,
+ 34,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 1,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 3, 0,
+ 0,
+ 0,
+ 0,
+ 43,
+ OPC_CheckPredicate, 7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rri8), 0,
+ 1, MVT::i32, 3, 0, 2, 3,
+ 43,
+ OPC_CheckPredicate, 8,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rri8), 0,
+ 1, MVT::i32, 3, 0, 2, 3,
+ 43,
+ OPC_CheckPredicate, 7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rri8), 0,
+ 1, MVT::i16, 3, 0, 2, 3,
+ 43,
+ OPC_CheckPredicate, 8,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rri8), 0,
+ 1, MVT::i16, 3, 0, 2, 3,
+ 43,
+ OPC_CheckPredicate, 7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64rri8), 0,
+ 1, MVT::i64, 3, 0, 2, 3,
+ 43,
+ OPC_CheckPredicate, 8,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64rri8), 0,
+ 1, MVT::i64, 3, 0, 2, 3,
+ 43,
+ OPC_CheckPredicate, 7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rri8), 0,
+ 1, MVT::i32, 3, 1, 0, 3,
+ 43,
+ OPC_CheckPredicate, 8,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rri8), 0,
+ 1, MVT::i32, 3, 1, 0, 3,
+ 43,
+ OPC_CheckPredicate, 7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rri8), 0,
+ 1, MVT::i16, 3, 1, 0, 3,
+ 43,
+ OPC_CheckPredicate, 8,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rri8), 0,
+ 1, MVT::i16, 3, 1, 0, 3,
+ 43,
+ OPC_CheckPredicate, 7,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64rri8), 0,
+ 1, MVT::i64, 3, 1, 0, 3,
+ 43,
+ OPC_CheckPredicate, 8,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64rri8), 0,
+ 1, MVT::i64, 3, 1, 0, 3,
+ 57,
+ OPC_RecordNode,
+ OPC_SwitchType , 36, MVT::i32,
+ OPC_Scope, 16,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64_32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 14, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64r), 0,
+ 1, MVT::i64, 4, 1, 2, 3, 4,
+ 0,
+ 22|128,1,
+ OPC_CheckPredicate, 71,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 104,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16ri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64ri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64ri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 31,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16ri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 0,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ORPDrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 90|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 118,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16ri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32ri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64ri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64ri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 45,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8ri), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 2,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16ri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32ri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8rr), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 28,
+ OPC_CheckType, MVT::v2i64,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ORPSrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PORrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 13,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PORrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 0,
+ 0,
+ 51|128,6, ISD::XOR,
+ OPC_Scope, 39|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 87, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_Scope, 41,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XORPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XORPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 72, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_Scope, 26,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XORPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XORPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 39|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 95,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PXORrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PXORrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 41|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 96,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 20, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 20, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 20, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 31,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PXORrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PXORrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 57,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT8r), 0,
+ 1, MVT::i8, 1, 0,
+ 8, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT16r), 0,
+ 1, MVT::i16, 1, 0,
+ 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT32r), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT64r), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 29,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XORPDrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 90|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 118,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16ri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32ri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64ri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64ri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 45,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8ri), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 2,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16ri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32ri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8rr), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 28,
+ OPC_CheckType, MVT::v2i64,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XORPSrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PXORrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 13,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PXORrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 0,
+ 0,
+ 73, X86ISD::CMPPS,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_Scope, 45,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMPPSrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMPPSrri), 0,
+ 1, MVT::v4i32, 3, 0, 1, 3,
+ 0,
+ 73, X86ISD::CMPPD,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_Scope, 45,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMPPDrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CMPPDrri), 0,
+ 1, MVT::v2i64, 3, 0, 1, 3,
+ 0,
+ 97|128,11, ISD::ADD,
+ OPC_Scope, 72|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 81,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 102,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 73|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 82,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 103,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 10|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 95,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 11|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 96,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 20, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 20, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 20, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 20, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 31,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 57,
+ OPC_RecordNode,
+ OPC_SwitchType , 36, MVT::i32,
+ OPC_Scope, 16,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64_32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 14, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64r), 0,
+ 1, MVT::i64, 4, 1, 2, 3, 4,
+ 0,
+ 85,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, X86ISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 13, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 13, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 13, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 13, ISD::TargetExternalSymbol,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 13, ISD::TargetBlockAddress,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 89,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, X86ISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 14, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 14, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 14, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 14, ISD::TargetExternalSymbol,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 14, ISD::TargetBlockAddress,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 1, MVT::i32, 2, 1, 0,
+ 0,
+ 69|128,4,
+ OPC_RecordChild0,
+ OPC_Scope, 32|128,2,
+ OPC_MoveChild, 1,
+ OPC_Scope, 83,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_SwitchType , 26, MVT::i16,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC16r), 0,
+ 2, MVT::i16, MVT::i32, 1, 0,
+ 11,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_16r), 0,
+ 2, MVT::i16, MVT::i32, 1, 0,
+ 0,
+ 26, MVT::i32,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC32r), 0,
+ 2, MVT::i32, MVT::i32, 1, 0,
+ 11,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_32r), 0,
+ 2, MVT::i32, MVT::i32, 1, 0,
+ 0,
+ 9, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC8r), 0,
+ 2, MVT::i8, MVT::i32, 1, 0,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64r), 0,
+ 2, MVT::i64, MVT::i32, 1, 0,
+ 0,
+ 92,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_SwitchType , 26, MVT::i16,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC16r), 0,
+ 2, MVT::i16, MVT::i32, 1, 0,
+ 11,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_16r), 0,
+ 2, MVT::i16, MVT::i32, 1, 0,
+ 0,
+ 26, MVT::i32,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC32r), 0,
+ 2, MVT::i32, MVT::i32, 1, 0,
+ 11,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_32r), 0,
+ 2, MVT::i32, MVT::i32, 1, 0,
+ 0,
+ 9, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC8r), 0,
+ 2, MVT::i8, MVT::i32, 1, 0,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64r), 0,
+ 2, MVT::i64, MVT::i32, 1, 0,
+ 0,
+ 75,
+ OPC_CheckInteger, 0|128,1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::i16,
+ OPC_EmitInteger, MVT::i16, 0|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16ri8), 0,
+ 1, MVT::i16, 2, 0, 1,
+ 21, MVT::i32,
+ OPC_EmitInteger, MVT::i32, 0|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32ri8), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 21, MVT::i64,
+ OPC_EmitInteger, MVT::i64, 0|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64ri8), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 30,
+ OPC_CheckInteger, 0|128,0|128,0|128,0|128,8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitInteger, MVT::i64, 0|128,0|128,0|128,0|128,120|128,127|128,127|128,127|128,127|128,1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64ri32), 0,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 30|128,2,
+ OPC_RecordChild1,
+ OPC_Scope, 118,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16ri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64ri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64ri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 45,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8ri), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 2,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16ri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8rr), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDDrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PADDQrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 0,
+ 0,
+ 0,
+ 103|128,5, ISD::SUB,
+ OPC_Scope, 83|128,2,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 67|128,1, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 81,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 102,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 5|128,1, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 95,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 20, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 57,
+ OPC_RecordNode,
+ OPC_SwitchType , 36, MVT::i32,
+ OPC_Scope, 16,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64_32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 14, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64r), 0,
+ 1, MVT::i64, 4, 1, 2, 3, 4,
+ 0,
+ 52,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG8r), 0,
+ 2, MVT::i8, MVT::i32, 1, 0,
+ 9, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG16r), 0,
+ 2, MVT::i16, MVT::i32, 1, 0,
+ 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG32r), 0,
+ 2, MVT::i32, MVT::i32, 1, 0,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG64r), 0,
+ 2, MVT::i64, MVT::i32, 1, 0,
+ 0,
+ 31|128,2,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 118,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16ri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32ri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64ri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64ri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 45,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8ri), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 2,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16ri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32ri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8rr), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBDrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 13,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSUBQrr), 0,
+ 1, MVT::v1i64, 2, 0, 1,
+ 0,
+ 0,
+ 71, X86ISD::PINSRW,
+ OPC_RecordChild0,
+ OPC_Scope, 45,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 48,
+ OPC_CheckPredicate, 60,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PINSRWrmi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PINSRWrri), 0,
+ 1, MVT::v8i16, 3, 0, 1, 3,
+ 0,
+ 126, ISD::MEMBARRIER,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_Scope, 34,
+ OPC_CheckInteger, 0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 3,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 4,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_MoveChild, 5,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SFENCE), 0|OPFL_Chain,
+ 0, 0,
+ 34,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 3,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 4,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 5,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LFENCE), 0|OPFL_Chain,
+ 0, 0,
+ 50,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveChild, 4,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_MoveChild, 5,
+ OPC_Scope, 12,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOOP), 0|OPFL_Chain,
+ 0, 0,
+ 12,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MFENCE), 0|OPFL_Chain,
+ 0, 0,
+ 0,
+ 0,
+ 60, X86ISD::PSHUFB,
+ OPC_RecordChild0,
+ OPC_Scope, 43,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 11,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFBrm128), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFBrr128), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
+ 71, X86ISD::PINSRB,
+ OPC_RecordChild0,
+ OPC_Scope, 45,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 48,
+ OPC_CheckPredicate, 59,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PINSRBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 7, 0, 4, 5, 6, 7, 8, 9,
+ 21,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PINSRBrr), 0,
+ 1, MVT::v16i8, 3, 0, 1, 3,
+ 0,
+ 63|128,1, X86ISD::PCMPEQB,
+ OPC_Scope, 42,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 2, 3, 4, 5, 6, 7,
+ 37,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 37,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 2, 3, 4, 5, 6, 7,
+ 26,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 9, MVT::v8i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 0,
+ 63|128,1, X86ISD::PCMPEQW,
+ OPC_Scope, 42,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
+ 37,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 37,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
+ 26,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 9, MVT::v4i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 0,
+ 63|128,1, X86ISD::PCMPEQD,
+ OPC_Scope, 42,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 42,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 2, 3, 4, 5, 6, 7,
+ 37,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 37,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 2, 3, 4, 5, 6, 7,
+ 26,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 9, MVT::v2i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPEQDrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 0,
+ 107, X86ISD::PCMPGTB,
+ OPC_RecordChild0,
+ OPC_Scope, 77,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 37, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 32, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTBrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 25,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTBrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 9, MVT::v8i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTBrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 0,
+ 0,
+ 107, X86ISD::PCMPGTW,
+ OPC_RecordChild0,
+ OPC_Scope, 77,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 37, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 32, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 25,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTWrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 9, MVT::v4i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTWrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 0,
+ 0,
+ 107, X86ISD::PCMPGTD,
+ OPC_RecordChild0,
+ OPC_Scope, 77,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 37, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 32, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 25,
+ OPC_RecordChild1,
+ OPC_SwitchType , 9, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTDrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 9, MVT::v2i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTDrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 0,
+ 110, X86ISD::LCMPXCHG_DAG,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_Scope, 25,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_MoveChild, 3,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LCMPXCHG32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 25,
+ OPC_CheckChild2Type, MVT::i16,
+ OPC_MoveChild, 3,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LCMPXCHG16), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 25,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_MoveChild, 3,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LCMPXCHG8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 25,
+ OPC_CheckChild2Type, MVT::i64,
+ OPC_MoveChild, 3,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LCMPXCHG64), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 0,
+ 7|128,1, ISD::INTRINSIC_W_CHAIN,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_Scope, 25,
+ OPC_CheckInteger, 59|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSrm_Int), 0|OPFL_Chain,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckInteger, 16|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPDrm_Int), 0|OPFL_Chain,
+ 1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckInteger, 15|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDQUrm_Int), 0|OPFL_Chain,
+ 1, MVT::v16i8, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckInteger, 95|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LDDQUrm), 0|OPFL_Chain,
+ 1, MVT::v16i8, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckInteger, 106|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTDQArm), 0|OPFL_Chain,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 41|128,4, ISD::INTRINSIC_VOID,
+ OPC_RecordNode,
+ OPC_MoveChild, 1,
+ OPC_Scope, 26,
+ OPC_CheckInteger, 75|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr_Int), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 26,
+ OPC_CheckInteger, 65|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTPSmr_Int), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 24,
+ OPC_CheckInteger, 58|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LDMXCSR), 0|OPFL_Chain,
+ 0, 5, 2, 3, 4, 5, 6,
+ 24,
+ OPC_CheckInteger, 74|128,5,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::STMXCSR), 0|OPFL_Chain,
+ 0, 5, 2, 3, 4, 5, 6,
+ 26,
+ OPC_CheckInteger, 81|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPDmr_Int), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 26,
+ OPC_CheckInteger, 80|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDQUmr_Int), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 26,
+ OPC_CheckInteger, 26|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTPDmr_Int), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 26,
+ OPC_CheckInteger, 24|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTDQmr_Int), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 26,
+ OPC_CheckInteger, 25|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTImr_Int), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 24,
+ OPC_CheckInteger, 116|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CLFLUSH), 0|OPFL_Chain,
+ 0, 5, 2, 3, 4, 5, 6,
+ 26,
+ OPC_CheckInteger, 79|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLQ128mr), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 26,
+ OPC_CheckInteger, 69|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVNTQmr), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 2,
+ 15,
+ OPC_CheckInteger, 71|128,5,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SFENCE), 0|OPFL_Chain,
+ 0, 0,
+ 47,
+ OPC_CheckInteger, 17|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_Scope, 18,
+ OPC_CheckChild4Type, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EDI,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MASKMOVDQU), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 2, 1, 2,
+ 18,
+ OPC_CheckChild4Type, MVT::i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::RDI,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MASKMOVDQU64), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 2, 1, 2,
+ 0,
+ 15,
+ OPC_CheckInteger, 14|128,4,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LFENCE), 0|OPFL_Chain,
+ 0, 0,
+ 15,
+ OPC_CheckInteger, 20|128,4,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MFENCE), 0|OPFL_Chain,
+ 0, 0,
+ 29,
+ OPC_CheckInteger, 96|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EAX,
+ OPC_EmitCopyToReg, 2, X86::ECX,
+ OPC_EmitCopyToReg, 3, X86::EDX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MONITOR), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 0,
+ 23,
+ OPC_CheckInteger, 97|128,4,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckPatternPredicate, 9,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::ECX,
+ OPC_EmitCopyToReg, 2, X86::EAX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MWAIT), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 0,
+ 15,
+ OPC_CheckInteger, 66|128,3,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_EMMS), 0|OPFL_Chain,
+ 0, 0,
+ 15,
+ OPC_CheckInteger, 67|128,3,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_FEMMS), 0|OPFL_Chain,
+ 0, 0,
+ 47,
+ OPC_CheckInteger, 68|128,3,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_RecordChild4,
+ OPC_Scope, 18,
+ OPC_CheckChild4Type, MVT::i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::EDI,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MASKMOVQ), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 2, 1, 2,
+ 18,
+ OPC_CheckChild4Type, MVT::i64,
+ OPC_CheckPatternPredicate, 15,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 3, X86::RDI,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MASKMOVQ64), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 2, 1, 2,
+ 0,
+ 0,
+ 22|128,8, ISD::FADD,
+ OPC_Scope, 27|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 57,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 87,
+ OPC_CheckPredicate, 48,
+ OPC_Scope, 53,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp64m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 28,
+ OPC_CheckPredicate, 50,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 29|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 58,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 89,
+ OPC_CheckPredicate, 48,
+ OPC_Scope, 54,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp64m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 29,
+ OPC_CheckPredicate, 50,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 3|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 6|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 2, 3, 4, 5, 6, 7,
+ 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 48|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, X86ISD::FILD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_Scope, 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 25,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 25,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 53|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, X86ISD::FILD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_Scope, 28,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 28,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 28,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 28,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 97,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 26, MVT::f32,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp32), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSSrr), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 0,
+ 26, MVT::f64,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp64), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSDrr), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 0,
+ 9, MVT::f80,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp80), 0,
+ 1, MVT::f80, 2, 0, 1,
+ 11, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 11, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 0,
+ 100|128,6, ISD::FSUB,
+ OPC_RecordChild0,
+ OPC_Scope, 126|128,5,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 37|128,3, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 57,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_Fp32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 87,
+ OPC_CheckPredicate, 48,
+ OPC_Scope, 53,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_Fp64m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 28,
+ OPC_CheckPredicate, 50,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 57,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_Fp32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 87,
+ OPC_CheckPredicate, 48,
+ OPC_Scope, 53,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_Fp64m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 28,
+ OPC_CheckPredicate, 50,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 124,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBSSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 79|128,2, X86ISD::FILD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_Scope, 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 25,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 25,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 25,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 25,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 96,
+ OPC_RecordChild1,
+ OPC_SwitchType , 26, MVT::f32,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_Fp32), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBSSrr), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 0,
+ 26, MVT::f64,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_Fp64), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBSDrr), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 0,
+ 9, MVT::f80,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_Fp80), 0,
+ 1, MVT::f80, 2, 0, 1,
+ 11, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 11, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 0,
+ 22|128,8, ISD::FMUL,
+ OPC_Scope, 27|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 57,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 87,
+ OPC_CheckPredicate, 48,
+ OPC_Scope, 53,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp64m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 28,
+ OPC_CheckPredicate, 50,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 29|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 58,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 89,
+ OPC_CheckPredicate, 48,
+ OPC_Scope, 54,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp64m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 29,
+ OPC_CheckPredicate, 50,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 3|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 6|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 2, 3, 4, 5, 6, 7,
+ 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 48|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, X86ISD::FILD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_Scope, 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 25,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 25,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 53|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, X86ISD::FILD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_Scope, 28,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 28,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 28,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 28,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ 26,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 97,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 26, MVT::f32,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp32), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSSrr), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 0,
+ 26, MVT::f64,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp64), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSDrr), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 0,
+ 9, MVT::f80,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp80), 0,
+ 1, MVT::f80, 2, 0, 1,
+ 11, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 11, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MULPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 0,
+ 100|128,6, ISD::FDIV,
+ OPC_RecordChild0,
+ OPC_Scope, 126|128,5,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 37|128,3, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 57,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_Fp32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 87,
+ OPC_CheckPredicate, 48,
+ OPC_Scope, 53,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_Fp64m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 28,
+ OPC_CheckPredicate, 50,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 57,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_Fp32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 87,
+ OPC_CheckPredicate, 48,
+ OPC_Scope, 53,
+ OPC_CheckPredicate, 49,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_Fp64m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 28,
+ OPC_CheckPredicate, 50,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 124,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVSSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 79|128,2, X86ISD::FILD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_Scope, 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 25,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 25,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 25,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 25,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 96,
+ OPC_RecordChild1,
+ OPC_SwitchType , 26, MVT::f32,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_Fp32), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVSSrr), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 0,
+ 26, MVT::f64,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_Fp64), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 11,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVSDrr), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 0,
+ 9, MVT::f80,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_Fp80), 0,
+ 1, MVT::f80, 2, 0, 1,
+ 11, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 11, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 0,
+ 100, ISD::BRIND,
+ OPC_RecordNode,
+ OPC_Scope, 66,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JMP32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JMP64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 0,
+ 29,
+ OPC_RecordChild1,
+ OPC_Scope, 12,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JMP32r), 0|OPFL_Chain,
+ 0, 1, 1,
+ 12,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JMP64r), 0|OPFL_Chain,
+ 0, 1, 1,
+ 0,
+ 0,
+ 10|128,2, X86ISD::CALL,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_Scope, 92,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CALL32m), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs|OPFL_Variadic1,
+ 0, 5, 3, 4, 5, 6, 7,
+ 55,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CALL64m), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs|OPFL_Variadic1,
+ 0, 5, 3, 4, 5, 6, 7,
+ 20,
+ OPC_CheckPatternPredicate, 17,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::WINCALL64m), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs|OPFL_Variadic1,
+ 0, 5, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 39|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 119,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 46, ISD::TargetGlobalAddress,
+ OPC_SwitchType , 11, MVT::i32,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CALLpcrel32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 29, MVT::i64,
+ OPC_MoveParent,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 16,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CALL64pcrel32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 17,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::WINCALL64pcrel32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 0,
+ 46, ISD::TargetExternalSymbol,
+ OPC_SwitchType , 11, MVT::i32,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CALLpcrel32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 29, MVT::i64,
+ OPC_MoveParent,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 16,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CALL64pcrel32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 17,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::WINCALL64pcrel32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 0,
+ 17, ISD::Constant,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 18,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CALLpcrel32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 2,
+ 0,
+ 12,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CALL32r), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 30,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 16,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CALL64r), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 17,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::WINCALL64r), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 0,
+ 0,
+ 6|128,1, X86ISD::BSF,
+ OPC_Scope, 94,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSF16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 27,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSF32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 29,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSF64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 36,
+ OPC_RecordChild0,
+ OPC_SwitchType , 9, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSF16rr), 0,
+ 2, MVT::i16, MVT::i32, 1, 0,
+ 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSF32rr), 0,
+ 2, MVT::i32, MVT::i32, 1, 0,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSF64rr), 0,
+ 2, MVT::i64, MVT::i32, 1, 0,
+ 0,
+ 0,
+ 6|128,1, X86ISD::BSR,
+ OPC_Scope, 94,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSR16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 27,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSR32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 29,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSR64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 36,
+ OPC_RecordChild0,
+ OPC_SwitchType , 9, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSR16rr), 0,
+ 2, MVT::i16, MVT::i32, 1, 0,
+ 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSR32rr), 0,
+ 2, MVT::i32, MVT::i32, 1, 0,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSR64rr), 0,
+ 2, MVT::i64, MVT::i32, 1, 0,
+ 0,
+ 0,
+ 115|128,2, ISD::ADDE,
+ OPC_CaptureFlagInput,
+ OPC_Scope, 100,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 19, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i8, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 100,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 19, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i8, 6, 2, 3, 4, 5, 6, 7,
+ 19, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 3, 4, 5, 6, 7,
+ 19, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 19, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 36|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 111,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 44,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16ri8), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i16, 2, 0, 2,
+ 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32ri8), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64ri8), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 16,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64ri32), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 2,
+ 42,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8ri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i8, 2, 0, 2,
+ 11, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16ri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i16, 2, 0, 2,
+ 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32ri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 11,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8rr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i8, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16rr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i16, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32rr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64rr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 13|128,2, ISD::SUBE,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_Scope, 99,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 19, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB8rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i8, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i16, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 35|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 111,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 44,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16ri8), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i16, 2, 0, 2,
+ 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32ri8), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64ri8), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 16,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64ri32), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 2,
+ 42,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB8ri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i8, 2, 0, 2,
+ 11, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16ri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i16, 2, 0, 2,
+ 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32ri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 11,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB8rr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i8, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16rr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i16, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32rr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64rr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 92|128,1, ISD::ADDC,
+ OPC_Scope, 58,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 19, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rm), 0|OPFL_Chain|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rm), 0|OPFL_Chain|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 58,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 19, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rm), 0|OPFL_Chain|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 3, 4, 5, 6, 7,
+ 19, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rm), 0|OPFL_Chain|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 99,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 70,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 31,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri8), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64ri8), 0|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 16,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64ri32), 0|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 2,
+ 14,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
+ 11,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rr), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rr), 0|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 30|128,1, ISD::SUBC,
+ OPC_RecordChild0,
+ OPC_Scope, 57,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 19, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32rm), 0|OPFL_Chain|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64rm), 0|OPFL_Chain|OPFL_FlagOutput|OPFL_MemRefs,
+ 1, MVT::i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 96,
+ OPC_RecordChild1,
+ OPC_Scope, 68,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 31,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32ri8), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64ri8), 0|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 29,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32ri), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64ri32), 0|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 0,
+ 11,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32rr), 0|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 1,
+ 11,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64rr), 0|OPFL_FlagOutput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 68|128,3, X86ISD::ADD,
+ OPC_Scope, 5|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 8|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 32,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 47|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 118,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16ri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64ri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64ri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 45,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8ri), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 2,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16ri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32ri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8rr), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 57|128,2, X86ISD::SUB,
+ OPC_RecordChild0,
+ OPC_Scope, 4|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 46|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 118,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16ri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32ri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64ri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64ri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 45,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8ri), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 2,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16ri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32ri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8rr), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 68|128,3, X86ISD::OR,
+ OPC_Scope, 5|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 8|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 32,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 47|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 118,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16ri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32ri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64ri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64ri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 45,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8ri), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 2,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16ri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32ri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8rr), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 68|128,3, X86ISD::XOR,
+ OPC_Scope, 5|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 8|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 32,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 47|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 118,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16ri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32ri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64ri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64ri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 45,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8ri), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 2,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16ri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32ri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8rr), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 68|128,3, X86ISD::AND,
+ OPC_Scope, 5|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 8|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 6,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 32,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 47|128,1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 118,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16ri8), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32ri8), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64ri8), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 0,
+ 17,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64ri32), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 2,
+ 45,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8ri), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 2,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16ri), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 2,
+ 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32ri), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 12,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8rr), 0,
+ 2, MVT::i8, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 80|128,1, ISD::FP_TO_SINT,
+ OPC_Scope, 113,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_SwitchType , 47, MVT::f64,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTTSD2SI64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 20, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTTSD2SIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 47, MVT::f32,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTTSS2SI64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 5, 2, 3, 4, 5, 6,
+ 20, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTTSS2SIrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 0,
+ 91,
+ OPC_RecordChild0,
+ OPC_Scope, 28,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTTSD2SI64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTTSD2SIrr), 0,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 28,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_SwitchType , 10, MVT::i64,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTTSS2SI64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 10, MVT::i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTTSS2SIrr), 0,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 14,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTPS2DQrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 14,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTTPD2PIrr), 0,
+ 1, MVT::v2i32, 1, 0,
+ 0,
+ 0,
+ 87|128,1, ISD::SINT_TO_FP,
+ OPC_Scope, 120,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 56,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSI2SD64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 20, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSI2SS64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 54,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSI2SSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 20, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSI2SDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 0,
+ 91,
+ OPC_RecordChild0,
+ OPC_Scope, 28,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_SwitchType , 10, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSI2SD64rr), 0,
+ 1, MVT::f64, 1, 0,
+ 10, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSI2SS64rr), 0,
+ 1, MVT::f32, 1, 0,
+ 0,
+ 28,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSI2SSrr), 0,
+ 1, MVT::f32, 1, 0,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSI2SDrr), 0,
+ 1, MVT::f64, 1, 0,
+ 0,
+ 14,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTDQ2PSrr), 0,
+ 1, MVT::v4f32, 1, 0,
+ 14,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_CVTPI2PDrr), 0,
+ 1, MVT::v2f64, 1, 0,
+ 0,
+ 0,
+ 67|128,5, ISD::BIT_CONVERT,
+ OPC_Scope, 3|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 68, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64toSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 30,
+ OPC_CheckPredicate, 5,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDI2SSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 55, ISD::EXTRACT_VECTOR_ELT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_SwitchType , 10, MVT::v1i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVDQ2Qrr), 0,
+ 1, MVT::v1i64, 1, 0,
+ 8, MVT::v2i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVDQ2Qrr), 0,
+ 1, MVT::v2i32, 1, 0,
+ 8, MVT::v4i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVDQ2Qrr), 0,
+ 1, MVT::v4i16, 1, 0,
+ 8, MVT::v8i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVDQ2Qrr), 0,
+ 1, MVT::v8i8, 1, 0,
+ 0,
+ 0,
+ 58|128,4,
+ OPC_RecordChild0,
+ OPC_Scope, 39,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_SwitchType , 5, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v4f32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 39,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_SwitchType , 5, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v4f32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 39,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_SwitchType , 5, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v4f32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 39,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_SwitchType , 5, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v4f32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 39,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_SwitchType , 5, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 39,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_SwitchType , 5, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v4f32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 5, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CompleteMatch, 1, 0,
+
+ 0,
+ 44,
+ OPC_CheckChild0Type, MVT::v1i64,
+ OPC_SwitchType , 3, MVT::v8i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64from64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 8, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2FR64rr), 0,
+ 1, MVT::f64, 1, 0,
+ 0,
+ 44,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_SwitchType , 3, MVT::v8i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v1i64,
+ OPC_CompleteMatch, 1, 0,
+
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64from64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 8, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2FR64rr), 0,
+ 1, MVT::f64, 1, 0,
+ 0,
+ 34,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_SwitchType , 3, MVT::v8i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v4i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v1i64,
+ OPC_CompleteMatch, 1, 0,
+
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64from64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 44,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_SwitchType , 3, MVT::v8i8,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v1i64,
+ OPC_CompleteMatch, 1, 0,
+
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64from64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 8, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2FR64rr), 0,
+ 1, MVT::f64, 1, 0,
+ 0,
+ 44,
+ OPC_CheckChild0Type, MVT::v8i8,
+ OPC_SwitchType , 3, MVT::v4i16,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2i32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v2f32,
+ OPC_CompleteMatch, 1, 0,
+
+ 3, MVT::v1i64,
+ OPC_CompleteMatch, 1, 0,
+
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64from64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 8, MVT::f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2FR64rr), 0,
+ 1, MVT::f64, 1, 0,
+ 0,
+ 66,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_SwitchType , 10, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64toSDrr), 0,
+ 1, MVT::f64, 1, 0,
+ 8, MVT::v1i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64to64rr), 0,
+ 1, MVT::v1i64, 1, 0,
+ 8, MVT::v2i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64to64rr), 0,
+ 1, MVT::v2i32, 1, 0,
+ 8, MVT::v2f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64to64rr), 0,
+ 1, MVT::v2f32, 1, 0,
+ 8, MVT::v4i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64to64rr), 0,
+ 1, MVT::v4i16, 1, 0,
+ 8, MVT::v8i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64to64rr), 0,
+ 1, MVT::v8i8, 1, 0,
+ 0,
+ 14,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDto64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 14,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDI2SSrr), 0,
+ 1, MVT::f32, 1, 0,
+ 14,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSS2DIrr), 0,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 0,
+ 109, X86ISD::UCOMI,
+ OPC_RecordChild0,
+ OPC_Scope, 52,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_Scope, 34,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_UCOMISSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_UCOMISSrr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 52,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_Scope, 34,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_UCOMISDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_UCOMISDrr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 109, X86ISD::COMI,
+ OPC_RecordChild0,
+ OPC_Scope, 52,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_Scope, 34,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_COMISSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_COMISSrr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 52,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_Scope, 34,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_COMISDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::Int_COMISDrr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 0,
+ 35|128,1, X86ISD::FAND,
+ OPC_Scope, 64,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsANDPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsANDPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 64,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsANDPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsANDPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 30,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 11, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsANDPSrr), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 11, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsANDPDrr), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 0,
+ 0,
+ 35|128,1, X86ISD::FOR,
+ OPC_Scope, 64,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsORPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsORPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 64,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsORPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsORPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 30,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 11, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsORPSrr), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 11, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsORPDrr), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 0,
+ 0,
+ 35|128,1, X86ISD::FXOR,
+ OPC_Scope, 64,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsXORPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsXORPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 64,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsXORPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsXORPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 30,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_SwitchType , 11, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsXORPSrr), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 11, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsXORPDrr), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 0,
+ 0,
+ 63|128,1, X86ISD::FMAX,
+ OPC_RecordChild0,
+ OPC_Scope, 2|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXSSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 55,
+ OPC_RecordChild1,
+ OPC_SwitchType , 11, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXSSrr), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 11, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 11, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXSDrr), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 11, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 0,
+ 63|128,1, X86ISD::FMIN,
+ OPC_RecordChild0,
+ OPC_Scope, 2|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINSSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 28,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINSDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 55,
+ OPC_RecordChild1,
+ OPC_SwitchType , 11, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINSSrr), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 11, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 11, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINSDrr), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 11, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 0,
+ 87|128,1, ISD::FSQRT,
+ OPC_Scope, 122,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 19,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTSSm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTPSm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTSDm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTPDm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
+ 0,
+ 89,
+ OPC_RecordChild0,
+ OPC_SwitchType , 24, MVT::f32,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRT_Fp32), 0,
+ 1, MVT::f32, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTSSr), 0,
+ 1, MVT::f32, 1, 0,
+ 0,
+ 24, MVT::f64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRT_Fp64), 0,
+ 1, MVT::f64, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTSDr), 0,
+ 1, MVT::f64, 1, 0,
+ 0,
+ 8, MVT::f80,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRT_Fp80), 0,
+ 1, MVT::f80, 1, 0,
+ 10, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTPSr), 0,
+ 1, MVT::v4f32, 1, 0,
+ 10, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTPDr), 0,
+ 1, MVT::v2f64, 1, 0,
+ 0,
+ 0,
+ 97, X86ISD::FRSQRT,
+ OPC_Scope, 66,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 19,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RSQRTSSm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RSQRTPSm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 27,
+ OPC_RecordChild0,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RSQRTSSr), 0,
+ 1, MVT::f32, 1, 0,
+ 10, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RSQRTPSr), 0,
+ 1, MVT::v4f32, 1, 0,
+ 0,
+ 0,
+ 97, X86ISD::FRCP,
+ OPC_Scope, 66,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_Scope, 26,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 19,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RCPSSm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RCPPSm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 27,
+ OPC_RecordChild0,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RCPSSr), 0,
+ 1, MVT::f32, 1, 0,
+ 10, MVT::v4f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RCPPSr), 0,
+ 1, MVT::v4f32, 1, 0,
+ 0,
+ 0,
+ 103, ISD::FP_ROUND,
+ OPC_Scope, 38,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 12,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSD2SSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 61,
+ OPC_RecordChild0,
+ OPC_Scope, 28,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_CheckType, MVT::f32,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV_Fp6432), 0,
+ 1, MVT::f32, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSD2SSrr), 0,
+ 1, MVT::f32, 1, 0,
+ 0,
+ 28,
+ OPC_CheckChild0Type, MVT::f80,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV_Fp8032), 0,
+ 1, MVT::f32, 1, 0,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV_Fp8064), 0,
+ 1, MVT::f64, 1, 0,
+ 0,
+ 0,
+ 0,
+ 103, ISD::FP_EXTEND,
+ OPC_Scope, 38,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 10,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::f32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSS2SDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 61,
+ OPC_RecordChild0,
+ OPC_Scope, 42,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_SwitchType , 24, MVT::f64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV_Fp3264), 0,
+ 1, MVT::f64, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSS2SDrr), 0,
+ 1, MVT::f64, 1, 0,
+ 0,
+ 10, MVT::f80,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV_Fp3280), 0,
+ 1, MVT::f80, 1, 0,
+ 0,
+ 14,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV_Fp6480), 0,
+ 1, MVT::f80, 1, 0,
+ 0,
+ 0,
+ 92, X86ISD::PCMPEQQ,
+ OPC_Scope, 37,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 37,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
+ 13,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPEQQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 51, X86ISD::PTEST,
+ OPC_RecordChild0,
+ OPC_Scope, 34,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PTESTrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PTESTrr), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 0,
+ 53, X86ISD::PCMPGTQ,
+ OPC_RecordChild0,
+ OPC_Scope, 36,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 9,
+ OPC_CheckPredicate, 24,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 12,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 114, ISD::ATOMIC_SWAP,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 72,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XCHG32rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckPredicate, 73,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XCHG16rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckPredicate, 74,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XCHG8rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i8, 6, 2, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckPredicate, 75,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XCHG64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 114, ISD::ATOMIC_LOAD_ADD,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 76,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LXADD32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckPredicate, 77,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LXADD16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 6, 2, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckPredicate, 78,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LXADD8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i8, 6, 2, 3, 4, 5, 6, 7,
+ 27,
+ OPC_CheckPredicate, 79,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LXADD64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 114, ISD::ATOMIC_LOAD_AND,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 80,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMAND32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 81,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMAND16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 82,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMAND8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i8, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 83,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMAND64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
+ 0,
+ 114, ISD::ATOMIC_LOAD_OR,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 84,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMOR32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 85,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMOR16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 86,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMOR8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i8, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 87,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMOR64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
+ 0,
+ 114, ISD::ATOMIC_LOAD_XOR,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 88,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMXOR32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 89,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMXOR16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 90,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMXOR8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i8, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 91,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMXOR64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
+ 0,
+ 114, ISD::ATOMIC_LOAD_NAND,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 92,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMNAND32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 93,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMNAND16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 94,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMNAND8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i8, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 95,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMNAND64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
+ 0,
+ 86, ISD::ATOMIC_LOAD_MIN,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 96,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMMIN32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 97,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMMIN16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 98,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMMIN64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
+ 0,
+ 86, ISD::ATOMIC_LOAD_MAX,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 99,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMMAX32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 100,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMMAX16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 101,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMMAX64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
+ 0,
+ 86, ISD::ATOMIC_LOAD_UMIN,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 102,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMUMIN32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 103,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMUMIN16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 104,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMUMIN64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
+ 0,
+ 86, ISD::ATOMIC_LOAD_UMAX,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 105,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMUMAX32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 106,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i16,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMUMAX16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
+ 27,
+ OPC_CheckPredicate, 107,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMUMAX64), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
+ 0,
+ 106|128,1, X86ISD::FILD,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_Scope, 25,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckValueType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp64m32), 0|OPFL_Chain,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 25,
+ OPC_CheckValueType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp64m64), 0|OPFL_Chain,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 23,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 23,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 23,
+ OPC_CheckValueType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp64m80), 0|OPFL_Chain,
+ 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 0,
+ 14|128,1, X86ISD::FP_TO_INT16_IN_MEM,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 45,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ISTT_Fp16m32), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FP32_TO_INT16_IN_MEM), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 45,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ISTT_Fp16m64), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FP64_TO_INT16_IN_MEM), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 45,
+ OPC_CheckChild1Type, MVT::f80,
+ OPC_RecordChild2,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ISTT_Fp16m80), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FP80_TO_INT16_IN_MEM), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 0,
+ 14|128,1, X86ISD::FP_TO_INT32_IN_MEM,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 45,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ISTT_Fp32m32), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FP32_TO_INT32_IN_MEM), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 45,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ISTT_Fp32m64), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FP64_TO_INT32_IN_MEM), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 45,
+ OPC_CheckChild1Type, MVT::f80,
+ OPC_RecordChild2,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ISTT_Fp32m80), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FP80_TO_INT32_IN_MEM), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 0,
+ 14|128,1, X86ISD::FP_TO_INT64_IN_MEM,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 45,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ISTT_Fp64m32), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FP32_TO_INT64_IN_MEM), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 45,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ISTT_Fp64m64), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FP64_TO_INT64_IN_MEM), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 45,
+ OPC_CheckChild1Type, MVT::f80,
+ OPC_RecordChild2,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ISTT_Fp64m80), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FP80_TO_INT64_IN_MEM), 0|OPFL_Chain,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 0,
+ 78, X86ISD::FLD,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_Scope, 23,
+ OPC_CheckValueType, MVT::f32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp32m), 0|OPFL_Chain,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 23,
+ OPC_CheckValueType, MVT::f64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp64m), 0|OPFL_Chain,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 23,
+ OPC_CheckValueType, MVT::f80,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp80m), 0|OPFL_Chain,
+ 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 0,
+ 30|128,1, X86ISD::FST,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_Scope, 26,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 3,
+ OPC_CheckValueType, MVT::f32,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp32m), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 51,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_MoveChild, 3,
+ OPC_Scope, 21,
+ OPC_CheckValueType, MVT::f32,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp64m32), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckValueType, MVT::f64,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp64m), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 73,
+ OPC_CheckChild1Type, MVT::f80,
+ OPC_RecordChild2,
+ OPC_MoveChild, 3,
+ OPC_Scope, 21,
+ OPC_CheckValueType, MVT::f32,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp80m32), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckValueType, MVT::f64,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp80m64), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 21,
+ OPC_CheckValueType, MVT::f80,
+ OPC_MoveParent,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_FpP80m), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 0,
+ 27, X86ISD::FILD_FLAG,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 2,
+ OPC_CheckValueType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp64m64), 0|OPFL_Chain|OPFL_FlagOutput,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 20, X86ISD::LCMPXCHG8_DAG,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LCMPXCHG8B), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 5, 2, 3, 4, 5, 6,
+ 19, X86ISD::FNSTCW16m,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FNSTCW16m), 0|OPFL_Chain,
+ 0, 5, 2, 3, 4, 5, 6,
+ 47, X86ISD::TLSADDR,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_Scope, 20,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/5, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TLS_addr32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 4, 2, 3, 4, 5,
+ 20,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/6, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TLS_addr64), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 4, 2, 3, 4, 5,
+ 0,
+ 57, X86ISD::MUL_IMM,
+ OPC_RecordNode,
+ OPC_SwitchType , 36, MVT::i32,
+ OPC_Scope, 16,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64_32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 14, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64r), 0,
+ 1, MVT::i64, 4, 1, 2, 3, 4,
+ 0,
+ 57|128,2, ISD::SHL,
+ OPC_Scope, 57,
+ OPC_RecordNode,
+ OPC_SwitchType , 36, MVT::i32,
+ OPC_Scope, 16,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64_32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 14, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64r), 0,
+ 1, MVT::i64, 4, 1, 2, 3, 4,
+ 0,
+ 123|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 124,
+ OPC_MoveChild, 1,
+ OPC_Scope, 47,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8rCL), 0|OPFL_FlagInput,
+ 1, MVT::i8, 1, 0,
+ 11, MVT::i16,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16rCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 1, 0,
+ 11, MVT::i32,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32rCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 19,
+ OPC_CheckAndImm, 63,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64rCL), 0|OPFL_FlagInput,
+ 1, MVT::i64, 1, 0,
+ 51,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 9, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8rr), 0,
+ 1, MVT::i8, 2, 0, 0,
+ 9, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rr), 0,
+ 1, MVT::i16, 2, 0, 0,
+ 9, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rr), 0,
+ 1, MVT::i32, 2, 0, 0,
+ 9, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rr), 0,
+ 1, MVT::i64, 2, 0, 0,
+ 0,
+ 0,
+ 122,
+ OPC_RecordChild1,
+ OPC_Scope, 61,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8ri), 0,
+ 1, MVT::i8, 2, 0, 2,
+ 11, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16ri), 0,
+ 1, MVT::i16, 2, 0, 2,
+ 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64ri), 0,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 56,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8rCL), 0|OPFL_FlagInput,
+ 1, MVT::i8, 1, 0,
+ 11, MVT::i16,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16rCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 1, 0,
+ 11, MVT::i32,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32rCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 1, 0,
+ 11, MVT::i64,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64rCL), 0|OPFL_FlagInput,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 57, ISD::FrameIndex,
+ OPC_RecordNode,
+ OPC_SwitchType , 36, MVT::i32,
+ OPC_Scope, 16,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64_32r), 0,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 14, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64r), 0,
+ 1, MVT::i64, 4, 1, 2, 3, 4,
+ 0,
+ 17, X86ISD::WrapperRIP,
+ OPC_RecordNode,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64r), 0,
+ 1, MVT::i64, 4, 1, 2, 3, 4,
+ 119|128,1, ISD::TRUNCATE,
+ OPC_Scope, 78,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_CheckPredicate, 16,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 29, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i32, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ 29, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, X86::GR32_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ 0,
+ 36|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 64,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_SwitchType , 12, MVT::i16,
+ OPC_EmitInteger, MVT::i32, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i16, 2, 0, 1,
+ 44, MVT::i8,
+ OPC_Scope, 14,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 0, 1,
+ 26,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, X86::GR32_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i32, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ 0,
+ 0,
+ 46,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_SwitchType , 12, MVT::i32,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i16,
+ OPC_EmitInteger, MVT::i32, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i8,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 0, 1,
+ 0,
+ 48,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_CheckType, MVT::i8,
+ OPC_Scope, 14,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 0, 1,
+ 26,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ 0,
+ 0,
+ 0,
+ 122|128,1, ISD::ZERO_EXTEND,
+ OPC_Scope, 15|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_CheckPredicate, 16,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_SwitchType , 72, MVT::i32,
+ OPC_Scope, 34,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rr8), 0,
+ 1, MVT::i32, 1, 4,
+ 34,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32_NOREXrr8), 0,
+ 1, MVT::i32, 1, 4,
+ 0,
+ 48, MVT::i64,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 0, 2,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 3, 4,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVZX32_NOREXrr8), 0,
+ 1, MVT::i32, 1, 5,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0,
+ 1, MVT::i64, 3, 1, 6, 7,
+ 0,
+ 102,
+ OPC_RecordChild0,
+ OPC_Scope, 25,
+ OPC_MoveChild, 0,
+ OPC_CheckPredicate, 108,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0,
+ 1, MVT::i64, 3, 1, 0, 2,
+ 34,
+ OPC_CheckChild0Type, MVT::i8,
+ OPC_SwitchType , 8, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX16rr8), 0,
+ 1, MVT::i16, 1, 0,
+ 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rr8), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rr8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 24,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rr16), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rr16), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 12,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rr32), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 28|128,2, ISD::ANY_EXTEND,
+ OPC_Scope, 67|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 11|128,1, ISD::SRL,
+ OPC_CheckPredicate, 16,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_SwitchType , 72, MVT::i32,
+ OPC_Scope, 34,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rr8), 0,
+ 1, MVT::i32, 1, 4,
+ 34,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32_NOREXrr8), 0,
+ 1, MVT::i32, 1, 4,
+ 0,
+ 48, MVT::i64,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 0, 2,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 3, 4,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVZX32_NOREXrr8), 0,
+ 1, MVT::i32, 1, 5,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0,
+ 1, MVT::i64, 3, 1, 6, 7,
+ 0,
+ 47, X86ISD::SETCC_CARRY,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 10, MVT::i16,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETB_C16r), 0|OPFL_FlagInput,
+ 1, MVT::i16, 0,
+ 10, MVT::i32,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETB_C32r), 0|OPFL_FlagInput,
+ 1, MVT::i32, 0,
+ 10, MVT::i64,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETB_C64r), 0|OPFL_FlagInput,
+ 1, MVT::i64, 0,
+ 0,
+ 0,
+ 84,
+ OPC_RecordChild0,
+ OPC_Scope, 20,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitInteger, MVT::i64, 0,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0,
+ 1, MVT::i64, 3, 1, 0, 2,
+ 34,
+ OPC_CheckChild0Type, MVT::i8,
+ OPC_SwitchType , 8, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX16rr8), 0,
+ 1, MVT::i16, 1, 0,
+ 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rr8), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rr8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 24,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rr16), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rr16), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 0,
+ 96|128,2, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_Scope, 96|128,1,
+ OPC_MoveChild, 1,
+ OPC_Scope, 47,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8rCL), 0|OPFL_FlagInput,
+ 1, MVT::i8, 1, 0,
+ 11, MVT::i16,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16rCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 1, 0,
+ 11, MVT::i32,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32rCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 19,
+ OPC_CheckAndImm, 63,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64rCL), 0|OPFL_FlagInput,
+ 1, MVT::i64, 1, 0,
+ 47,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8r1), 0,
+ 1, MVT::i8, 1, 0,
+ 8, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16r1), 0,
+ 1, MVT::i16, 1, 0,
+ 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32r1), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64r1), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 103,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_Scope, 46,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVZX32rr8), 0,
+ 1, MVT::i32, 1, 4,
+ OPC_EmitInteger, MVT::i32, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i16, 2, 5, 6,
+ 46,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ OPC_EmitNode, TARGET_OPCODE(X86::MOVZX32_NOREXrr8), 0,
+ 1, MVT::i32, 1, 4,
+ OPC_EmitInteger, MVT::i32, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i16, 2, 5, 6,
+ 0,
+ 0,
+ 122,
+ OPC_RecordChild1,
+ OPC_Scope, 61,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8ri), 0,
+ 1, MVT::i8, 2, 0, 2,
+ 11, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16ri), 0,
+ 1, MVT::i16, 2, 0, 2,
+ 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64ri), 0,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 56,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8rCL), 0|OPFL_FlagInput,
+ 1, MVT::i8, 1, 0,
+ 11, MVT::i16,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16rCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 1, 0,
+ 11, MVT::i32,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32rCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 1, 0,
+ 11, MVT::i64,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64rCL), 0|OPFL_FlagInput,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 0,
+ 119|128,1, ISD::SRA,
+ OPC_RecordChild0,
+ OPC_Scope, 120,
+ OPC_MoveChild, 1,
+ OPC_Scope, 47,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8rCL), 0|OPFL_FlagInput,
+ 1, MVT::i8, 1, 0,
+ 11, MVT::i16,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16rCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 1, 0,
+ 11, MVT::i32,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32rCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 1, 0,
+ 0,
+ 19,
+ OPC_CheckAndImm, 63,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64rCL), 0|OPFL_FlagInput,
+ 1, MVT::i64, 1, 0,
+ 47,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8r1), 0,
+ 1, MVT::i8, 1, 0,
+ 8, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16r1), 0,
+ 1, MVT::i16, 1, 0,
+ 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32r1), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64r1), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 122,
+ OPC_RecordChild1,
+ OPC_Scope, 61,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8ri), 0,
+ 1, MVT::i8, 2, 0, 2,
+ 11, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16ri), 0,
+ 1, MVT::i16, 2, 0, 2,
+ 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64ri), 0,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 56,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8rCL), 0|OPFL_FlagInput,
+ 1, MVT::i8, 1, 0,
+ 11, MVT::i16,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16rCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 1, 0,
+ 11, MVT::i32,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32rCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 1, 0,
+ 11, MVT::i64,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64rCL), 0|OPFL_FlagInput,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 0,
+ 44, ISD::CALLSEQ_END,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TargetConstant,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::TargetConstant,
+ OPC_MoveParent,
+ OPC_Scope, 13,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADJCALLSTACKUP32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 2, 1, 2,
+ 13,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADJCALLSTACKUP64), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 2, 1, 2,
+ 0,
+ 22|128,1, X86ISD::TC_RETURN,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild1,
+ OPC_Scope, 100,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 46, ISD::TargetGlobalAddress,
+ OPC_SwitchType , 20, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TCRETURNdi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 1, 3,
+ 20, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TCRETURNdi64), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 1, 3,
+ 0,
+ 46, ISD::TargetExternalSymbol,
+ OPC_SwitchType , 20, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TCRETURNdi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 1, 3,
+ 20, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TCRETURNdi64), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 1, 3,
+ 0,
+ 0,
+ 21,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TCRETURNri), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 1, 3,
+ 21,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TCRETURNri64), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic2,
+ 0, 2, 1, 3,
+ 0,
+ 45|128,1, ISD::EXTRACT_VECTOR_ELT,
+ OPC_Scope, 31,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::EXTRACTPSrr), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 9|128,1,
+ OPC_RecordChild0,
+ OPC_Scope, 21,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 0, 1,
+ 21,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 0, 1,
+ 44,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_Scope, 17,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVPQIto64rr), 0,
+ 1, MVT::i64, 1, 0,
+ 21,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PEXTRQrr), 0,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 44,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_Scope, 17,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVPDI2DIrr), 0,
+ 1, MVT::i32, 1, 0,
+ 21,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PEXTRDrr), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
+ 0,
+ 0,
+ 30, X86ISD::VASTART_SAVE_XMM_REGS,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_MoveChild, 3,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::VASTART_SAVE_XMM_REGS), 0|OPFL_Chain|OPFL_Variadic3,
+ 0, 3, 1, 4, 5,
+ 36, X86ISD::RET_FLAG,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_Scope, 14,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RET), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic1,
+ 0, 0,
+ 16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TargetConstant,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RETI), 0|OPFL_Chain|OPFL_FlagInput|OPFL_Variadic1,
+ 0, 1, 1,
+ 0,
+ 43|128,2, X86ISD::BRCOND,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BasicBlock,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_Scope, 17,
+ OPC_CheckInteger, 13,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JO_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 10,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JNO_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JB_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JAE_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JE_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 9,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JNE_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JBE_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JA_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 15,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JS_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 12,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JNS_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 14,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JP_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 11,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JNP_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 7,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JL_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JGE_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JLE_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 17,
+ OPC_CheckInteger, 5,
+ OPC_MoveParent,
+ OPC_RecordChild3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 2, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JG_4), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 1, 1,
+ 0,
+ 48|128,1, ISD::ROTL,
+ OPC_RecordChild0,
+ OPC_Scope, 49,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL8r1), 0,
+ 1, MVT::i8, 1, 0,
+ 8, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL16r1), 0,
+ 1, MVT::i16, 1, 0,
+ 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL32r1), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL64r1), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 122,
+ OPC_RecordChild1,
+ OPC_Scope, 61,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL8ri), 0,
+ 1, MVT::i8, 2, 0, 2,
+ 11, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL16ri), 0,
+ 1, MVT::i16, 2, 0, 2,
+ 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL32ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL64ri), 0,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 56,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL8rCL), 0|OPFL_FlagInput,
+ 1, MVT::i8, 1, 0,
+ 11, MVT::i16,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL16rCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 1, 0,
+ 11, MVT::i32,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL32rCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 1, 0,
+ 11, MVT::i64,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL64rCL), 0|OPFL_FlagInput,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 0,
+ 48|128,1, ISD::ROTR,
+ OPC_RecordChild0,
+ OPC_Scope, 49,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR8r1), 0,
+ 1, MVT::i8, 1, 0,
+ 8, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR16r1), 0,
+ 1, MVT::i16, 1, 0,
+ 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR32r1), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR64r1), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 122,
+ OPC_RecordChild1,
+ OPC_Scope, 61,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR8ri), 0,
+ 1, MVT::i8, 2, 0, 2,
+ 11, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR16ri), 0,
+ 1, MVT::i16, 2, 0, 2,
+ 11, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR32ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 11, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR64ri), 0,
+ 1, MVT::i64, 2, 0, 2,
+ 0,
+ 56,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_SwitchType , 11, MVT::i8,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR8rCL), 0|OPFL_FlagInput,
+ 1, MVT::i8, 1, 0,
+ 11, MVT::i16,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR16rCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 1, 0,
+ 11, MVT::i32,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR32rCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 1, 0,
+ 11, MVT::i64,
+ OPC_EmitCopyToReg, 1, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR64rCL), 0|OPFL_FlagInput,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 0,
+ 56, X86ISD::SETCC_CARRY,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 10, MVT::i8,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETB_C8r), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 10, MVT::i16,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETB_C16r), 0|OPFL_FlagInput,
+ 1, MVT::i16, 0,
+ 10, MVT::i32,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETB_C32r), 0|OPFL_FlagInput,
+ 1, MVT::i32, 0,
+ 10, MVT::i64,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETB_C64r), 0|OPFL_FlagInput,
+ 1, MVT::i64, 0,
+ 0,
+ 116|128,1, X86ISD::SETCC,
+ OPC_MoveChild, 0,
+ OPC_Scope, 14,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETEr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNEr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 7,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETLr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETGEr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETLEr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 5,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETGr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETBr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETAEr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETBEr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETAr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 15,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETSr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 12,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNSr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 14,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETPr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 11,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNPr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 13,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETOr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 14,
+ OPC_CheckInteger, 10,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_EmitCopyToReg, 0, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNOr), 0|OPFL_FlagInput,
+ 1, MVT::i8, 0,
+ 0,
+ 29, X86ISD::FSRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 5, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLDQri), 0,
+ 1, MVT::v2f64, 2, 0, 3,
+ 35, ISD::CALLSEQ_START,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TargetConstant,
+ OPC_MoveParent,
+ OPC_Scope, 12,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADJCALLSTACKDOWN32), 0|OPFL_Chain|OPFL_FlagOutput,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADJCALLSTACKDOWN64), 0|OPFL_Chain|OPFL_FlagOutput,
+ 0, 1, 1,
+ 0,
+ 104, X86ISD::SHLD,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_Scope, 51,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rri8), 0,
+ 1, MVT::i32, 3, 0, 1, 3,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rri8), 0,
+ 1, MVT::i16, 3, 0, 1, 3,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64rri8), 0,
+ 1, MVT::i64, 3, 0, 1, 3,
+ 0,
+ 46,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_SwitchType , 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 104, X86ISD::SHRD,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_Scope, 51,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 12, MVT::i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rri8), 0,
+ 1, MVT::i32, 3, 0, 1, 3,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rri8), 0,
+ 1, MVT::i16, 3, 0, 1, 3,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64rri8), 0,
+ 1, MVT::i64, 3, 0, 1, 3,
+ 0,
+ 46,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_SwitchType , 12, MVT::i32,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i32, 2, 0, 1,
+ 12, MVT::i16,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i16, 2, 0, 1,
+ 12, MVT::i64,
+ OPC_EmitCopyToReg, 2, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64rrCL), 0|OPFL_FlagInput,
+ 1, MVT::i64, 2, 0, 1,
+ 0,
+ 0,
+ 22|128,2, X86ISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 50, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32ri), 0,
+ 1, MVT::i32, 1, 0,
+ 35, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 20,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri), 0,
+ 1, MVT::i64, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 21,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri64i32), 0,
+ 1, MVT::i64, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 22,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri32), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 50, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32ri), 0,
+ 1, MVT::i32, 1, 0,
+ 35, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 20,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri), 0,
+ 1, MVT::i64, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 21,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri64i32), 0,
+ 1, MVT::i64, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 22,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri32), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 11, ISD::TargetGlobalTLSAddress,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32ri), 0,
+ 1, MVT::i32, 1, 0,
+ 50, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32ri), 0,
+ 1, MVT::i32, 1, 0,
+ 35, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 20,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri), 0,
+ 1, MVT::i64, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 21,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri64i32), 0,
+ 1, MVT::i64, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 22,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri32), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 50, ISD::TargetExternalSymbol,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32ri), 0,
+ 1, MVT::i32, 1, 0,
+ 35, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 20,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri), 0,
+ 1, MVT::i64, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 21,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri64i32), 0,
+ 1, MVT::i64, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 22,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri32), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 50, ISD::TargetBlockAddress,
+ OPC_MoveParent,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32ri), 0,
+ 1, MVT::i32, 1, 0,
+ 35, MVT::i64,
+ OPC_Scope, 10,
+ OPC_CheckPatternPredicate, 20,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri), 0,
+ 1, MVT::i64, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 21,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri64i32), 0,
+ 1, MVT::i64, 1, 0,
+ 10,
+ OPC_CheckPatternPredicate, 22,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri32), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 0,
+ 0,
+ 1|128,1, ISD::Constant,
+ OPC_Scope, 40,
+ OPC_CheckInteger, 0,
+ OPC_SwitchType , 7, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64r0), 0,
+ 1, MVT::i64, 0,
+ 7, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8r0), 0,
+ 1, MVT::i8, 0,
+ 7, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16r0), 0,
+ 1, MVT::i16, 0,
+ 7, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32r0), 0,
+ 1, MVT::i32, 0,
+ 0,
+ 85,
+ OPC_RecordNode,
+ OPC_Scope, 14,
+ OPC_CheckPredicate, 69,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri64i32), 0,
+ 1, MVT::i64, 1, 1,
+ 14,
+ OPC_CheckPredicate, 12,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri32), 0,
+ 1, MVT::i64, 1, 1,
+ 12,
+ OPC_CheckType, MVT::i8,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8ri), 0,
+ 1, MVT::i8, 1, 1,
+ 12,
+ OPC_CheckType, MVT::i16,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16ri), 0,
+ 1, MVT::i16, 1, 1,
+ 12,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32ri), 0,
+ 1, MVT::i32, 1, 1,
+ 12,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri), 0,
+ 1, MVT::i64, 1, 1,
+ 0,
+ 0,
+ 42, X86ISD::VSHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 16, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 5, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSLLDQri), 0,
+ 1, MVT::v2i64, 2, 0, 3,
+ 11, MVT::v1i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSLLQri), 0,
+ 1, MVT::v1i64, 2, 0, 2,
+ 0,
+ 42, X86ISD::VSRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 16, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitNodeXForm, 5, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PSRLDQri), 0,
+ 1, MVT::v2i64, 2, 0, 3,
+ 11, MVT::v1i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSRLQri), 0,
+ 1, MVT::v1i64, 2, 0, 2,
+ 0,
+ 47, X86ISD::PEXTRW,
+ OPC_RecordChild0,
+ OPC_Scope, 21,
+ OPC_CheckChild0Type, MVT::v8i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PEXTRWri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 21,
+ OPC_CheckChild0Type, MVT::v4i16,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PEXTRWri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
+ 22, X86ISD::PEXTRB,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v16i8,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckPatternPredicate, 4,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PEXTRBrr), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 110|128,1, ISD::ConstantFP,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 109,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp032), 0,
+ 1, MVT::f32, 0,
+ 13,
+ OPC_CheckPredicate, 110,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp132), 0,
+ 1, MVT::f32, 0,
+ 13,
+ OPC_CheckPredicate, 109,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp064), 0,
+ 1, MVT::f64, 0,
+ 13,
+ OPC_CheckPredicate, 110,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp164), 0,
+ 1, MVT::f64, 0,
+ 11,
+ OPC_CheckPredicate, 109,
+ OPC_CheckType, MVT::f80,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp080), 0,
+ 1, MVT::f80, 0,
+ 11,
+ OPC_CheckPredicate, 110,
+ OPC_CheckType, MVT::f80,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp180), 0,
+ 1, MVT::f80, 0,
+ 13,
+ OPC_CheckPredicate, 111,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsFLD0SS), 0,
+ 1, MVT::f32, 0,
+ 13,
+ OPC_CheckPredicate, 109,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsFLD0SD), 0,
+ 1, MVT::f64, 0,
+ 21,
+ OPC_CheckPredicate, 112,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp032), 0,
+ 1, MVT::f32, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp32), 0,
+ 1, MVT::f32, 1, 0,
+ 21,
+ OPC_CheckPredicate, 113,
+ OPC_CheckType, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp132), 0,
+ 1, MVT::f32, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp32), 0,
+ 1, MVT::f32, 1, 0,
+ 21,
+ OPC_CheckPredicate, 112,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp064), 0,
+ 1, MVT::f64, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp64), 0,
+ 1, MVT::f64, 1, 0,
+ 21,
+ OPC_CheckPredicate, 113,
+ OPC_CheckType, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp164), 0,
+ 1, MVT::f64, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp64), 0,
+ 1, MVT::f64, 1, 0,
+ 19,
+ OPC_CheckPredicate, 112,
+ OPC_CheckType, MVT::f80,
+ OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp080), 0,
+ 1, MVT::f80, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp80), 0,
+ 1, MVT::f80, 1, 0,
+ 19,
+ OPC_CheckPredicate, 113,
+ OPC_CheckType, MVT::f80,
+ OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp180), 0,
+ 1, MVT::f80, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp80), 0,
+ 1, MVT::f80, 1, 0,
+ 0,
+ 15|128,1, ISD::BUILD_VECTOR,
+ OPC_Scope, 60,
+ OPC_CheckPredicate, 44,
+ OPC_SwitchType , 9, MVT::v4i32,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::V_SET0), 0,
+ 1, MVT::v4i32, 0,
+ 7, MVT::v2i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::V_SET0), 0,
+ 1, MVT::v2i64, 0,
+ 7, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::V_SET0), 0,
+ 1, MVT::v8i16, 0,
+ 7, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::V_SET0), 0,
+ 1, MVT::v16i8, 0,
+ 7, MVT::v2f64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::V_SET0), 0,
+ 1, MVT::v2f64, 0,
+ 7, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::V_SET0), 0,
+ 1, MVT::v4f32, 0,
+ 0,
+ 13,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::V_SETALLONES), 0,
+ 1, MVT::v4i32, 0,
+ 13,
+ OPC_CheckPredicate, 44,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_V_SET0), 0,
+ 1, MVT::v2i32, 0,
+ 13,
+ OPC_CheckPredicate, 67,
+ OPC_CheckType, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_V_SETALLONES), 0,
+ 1, MVT::v2i32, 0,
+ 37,
+ OPC_CheckPredicate, 44,
+ OPC_SwitchType , 9, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_V_SET0), 0,
+ 1, MVT::v1i64, 0,
+ 9, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_V_SET0), 0,
+ 1, MVT::v4i16, 0,
+ 9, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_V_SET0), 0,
+ 1, MVT::v8i8, 0,
+ 0,
+ 0,
+ 37, ISD::FNEG,
+ OPC_RecordChild0,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp32), 0,
+ 1, MVT::f32, 1, 0,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp64), 0,
+ 1, MVT::f64, 1, 0,
+ 8, MVT::f80,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp80), 0,
+ 1, MVT::f80, 1, 0,
+ 0,
+ 37, ISD::FABS,
+ OPC_RecordChild0,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ABS_Fp32), 0,
+ 1, MVT::f32, 1, 0,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ABS_Fp64), 0,
+ 1, MVT::f64, 1, 0,
+ 8, MVT::f80,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ABS_Fp80), 0,
+ 1, MVT::f80, 1, 0,
+ 0,
+ 37, ISD::FSIN,
+ OPC_RecordChild0,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SIN_Fp32), 0,
+ 1, MVT::f32, 1, 0,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SIN_Fp64), 0,
+ 1, MVT::f64, 1, 0,
+ 8, MVT::f80,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SIN_Fp80), 0,
+ 1, MVT::f80, 1, 0,
+ 0,
+ 37, ISD::FCOS,
+ OPC_RecordChild0,
+ OPC_SwitchType , 10, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::COS_Fp32), 0,
+ 1, MVT::f32, 1, 0,
+ 10, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::COS_Fp64), 0,
+ 1, MVT::f64, 1, 0,
+ 8, MVT::f80,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::COS_Fp80), 0,
+ 1, MVT::f80, 1, 0,
+ 0,
+ 93, X86ISD::INC,
+ OPC_RecordChild0,
+ OPC_Scope, 30,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_CheckType, MVT::i16,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC16r), 0,
+ 2, MVT::i16, MVT::i32, 1, 0,
+ 11,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_16r), 0,
+ 2, MVT::i16, MVT::i32, 1, 0,
+ 0,
+ 30,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC32r), 0,
+ 2, MVT::i32, MVT::i32, 1, 0,
+ 11,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_32r), 0,
+ 2, MVT::i32, MVT::i32, 1, 0,
+ 0,
+ 13,
+ OPC_CheckChild0Type, MVT::i8,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC8r), 0,
+ 2, MVT::i8, MVT::i32, 1, 0,
+ 13,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64r), 0,
+ 2, MVT::i64, MVT::i32, 1, 0,
+ 0,
+ 93, X86ISD::DEC,
+ OPC_RecordChild0,
+ OPC_Scope, 30,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_CheckType, MVT::i16,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC16r), 0,
+ 2, MVT::i16, MVT::i32, 1, 0,
+ 11,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_16r), 0,
+ 2, MVT::i16, MVT::i32, 1, 0,
+ 0,
+ 30,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 11,
+ OPC_CheckPatternPredicate, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC32r), 0,
+ 2, MVT::i32, MVT::i32, 1, 0,
+ 11,
+ OPC_CheckPatternPredicate, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_32r), 0,
+ 2, MVT::i32, MVT::i32, 1, 0,
+ 0,
+ 13,
+ OPC_CheckChild0Type, MVT::i8,
+ OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC8r), 0,
+ 2, MVT::i8, MVT::i32, 1, 0,
+ 13,
+ OPC_CheckChild0Type, MVT::i64,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64r), 0,
+ 2, MVT::i64, MVT::i32, 1, 0,
+ 0,
+ 17, ISD::BR,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BasicBlock,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::JMP_4), 0|OPFL_Chain,
+ 0, 1, 1,
+ 23, ISD::BSWAP,
+ OPC_RecordChild0,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSWAP32r), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::BSWAP64r), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 58, X86ISD::REP_MOVS,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_MoveChild, 1,
+ OPC_Scope, 12,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::REP_MOVSB), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 0,
+ 12,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::REP_MOVSW), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 0,
+ 12,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::REP_MOVSD), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 0,
+ 12,
+ OPC_CheckValueType, MVT::i64,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::REP_MOVSQ), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 0,
+ 0,
+ 58, X86ISD::REP_STOS,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_MoveChild, 1,
+ OPC_Scope, 12,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::REP_STOSB), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 0,
+ 12,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::REP_STOSW), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 0,
+ 12,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::REP_STOSD), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 0,
+ 12,
+ OPC_CheckValueType, MVT::i64,
+ OPC_MoveParent,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::REP_STOSQ), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 0,
+ 0,
+ 10, X86ISD::RDTSC_DAG,
+ OPC_RecordNode,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::RDTSC), 0|OPFL_Chain|OPFL_FlagOutput,
+ 0, 0,
+ 10, ISD::TRAP,
+ OPC_RecordNode,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TRAP), 0|OPFL_Chain,
+ 0, 0,
+ 76, ISD::SIGN_EXTEND,
+ OPC_RecordChild0,
+ OPC_Scope, 34,
+ OPC_CheckChild0Type, MVT::i8,
+ OPC_SwitchType , 8, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX16rr8), 0,
+ 1, MVT::i16, 1, 0,
+ 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rr8), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rr8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 24,
+ OPC_CheckChild0Type, MVT::i16,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rr16), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rr16), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 12,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rr32), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 30, X86ISD::EH_RETURN,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 12,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::EH_RETURN), 0|OPFL_Chain,
+ 0, 1, 1,
+ 12,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::EH_RETURN64), 0|OPFL_Chain,
+ 0, 1, 1,
+ 0,
+ 108|128,1, ISD::SIGN_EXTEND_INREG,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_Scope, 25,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_EmitInteger, MVT::i32, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rr16), 0,
+ 1, MVT::i32, 1, 2,
+ 25,
+ OPC_CheckValueType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitInteger, MVT::i32, 4,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i32, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rr32), 0,
+ 1, MVT::i64, 1, 2,
+ 25,
+ OPC_CheckValueType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_EmitInteger, MVT::i32, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rr16), 0,
+ 1, MVT::i64, 1, 2,
+ 23|128,1,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_SwitchType , 20, MVT::i64,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rr8), 0,
+ 1, MVT::i64, 1, 2,
+ 60, MVT::i32,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rr8), 0,
+ 1, MVT::i32, 1, 2,
+ 34,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, X86::GR32_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i32, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rr8), 0,
+ 1, MVT::i32, 1, 4,
+ 0,
+ 60, MVT::i16,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX16rr8), 0,
+ 1, MVT::i16, 1, 2,
+ 34,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 2, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX16rr8), 0,
+ 1, MVT::i16, 1, 4,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+ }; // Total Array size is 79144 bytes
+
+ #undef TARGET_OPCODE
+ return SelectCodeCommon(N, MatcherTable,sizeof(MatcherTable));
+}
+
+bool CheckPatternPredicate(unsigned PredNo) const {
+ switch (PredNo) {
+ default: assert(0 && "Invalid predicate in table?");
+ case 0: return (Subtarget->hasSSE1());
+ case 1: return (Subtarget->hasSSE2());
+ case 2: return (!Subtarget->is64Bit());
+ case 3: return (Subtarget->is64Bit());
+ case 4: return (Subtarget->hasSSE41());
+ case 5: return (TM.getCodeModel() == CodeModel::Small ||TM.getCodeModel() == CodeModel::Kernel) && (TM.getRelocationModel() == Reloc::Static);
+ case 6: return (!Subtarget->hasSSE1());
+ case 7: return (!Subtarget->hasSSE2());
+ case 8: return (Subtarget->hasMMX());
+ case 9: return (Subtarget->hasSSE3());
+ case 10: return (!OptForSize) && (Subtarget->hasSSE2());
+ case 11: return (Subtarget->hasSSSE3());
+ case 12: return (Subtarget->hasSSE2()) && (OptForSize);
+ case 13: return (Subtarget->hasSSE2()) && (!OptForSize);
+ case 14: return (Subtarget->hasSSE42());
+ case 15: return (Subtarget->hasMMX()) && (Subtarget->is64Bit());
+ case 16: return (!Subtarget->isTargetWin64());
+ case 17: return (Subtarget->isTargetWin64());
+ case 18: return (Subtarget->IsLegalToCallImmediateAddr(TM));
+ case 19: return (Subtarget->hasSSE1()) && (OptForSize);
+ case 20: return (TM.getCodeModel() != CodeModel::Small &&TM.getCodeModel() != CodeModel::Kernel);
+ case 21: return (TM.getCodeModel() == CodeModel::Small);
+ case 22: return (TM.getCodeModel() == CodeModel::Kernel);
+ }
+}
+
+bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {
+ switch (PredNo) {
+ default: assert(0 && "Invalid predicate in table?");
+ case 0: { // Predicate_alignednontemporalstore
+ SDNode *N = Node;
+
+ if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
+ return ST->isNonTemporal() && !ST->isTruncatingStore() &&
+ ST->getAddressingMode() == ISD::UNINDEXED &&
+ ST->getAlignment() >= 16;
+ return false;
-SDNode *Select_X86ISD_FILD_f80(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N->getOperand(2);
-
- // Pattern: (X86fild:f80 addr:iPTR:$src, i16:Other)
- // Emits: (ILD_Fp16m80:f80 addr:iPTR:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_286(N, X86::ILD_Fp16m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
-
- // Pattern: (X86fild:f80 addr:iPTR:$src, i32:Other)
- // Emits: (ILD_Fp32m80:f80 addr:iPTR:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_286(N, X86::ILD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
-
- // Pattern: (X86fild:f80 addr:iPTR:$src, i64:Other)
- // Emits: (ILD_Fp64m80:f80 addr:iPTR:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i64) {
- SDNode *Result = Emit_286(N, X86::ILD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
}
+ case 1: { // Predicate_nontemporalstore
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
+ return ST->isNonTemporal();
+ return false;
-DISABLE_INLINE SDNode *Emit_287(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 6);
- Chain = SDValue(ResNode, 1);
- SDValue InFlag(ResNode, 2);
- const SDValue Froms[] = {
- SDValue(N, 2),
- SDValue(N, 1)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_X86ISD_FILD_FLAG_f64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N->getOperand(2);
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i64) {
- SDNode *Result = Emit_287(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
}
+ case 2: { // Predicate_unindexedstore
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
-SDNode *Select_X86ISD_FLD_f32(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N->getOperand(2);
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::f32) {
- SDNode *Result = Emit_286(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
}
+ case 3: { // Predicate_store
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
-SDNode *Select_X86ISD_FLD_f64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N->getOperand(2);
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::f64) {
- SDNode *Result = Emit_286(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
}
+ case 4: { // Predicate_unindexedload
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
-SDNode *Select_X86ISD_FLD_f80(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N->getOperand(2);
- if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::f80) {
- SDNode *Result = Emit_286(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
}
+ case 5: { // Predicate_loadi32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ LoadSDNode *LD = cast<LoadSDNode>(N);
+ if (const Value *Src = LD->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ ISD::LoadExtType ExtType = LD->getExtensionType();
+ if (ExtType == ISD::NON_EXTLOAD)
+ return true;
+ if (ExtType == ISD::EXTLOAD)
+ return LD->getAlignment() >= 4 && !LD->isVolatile();
+ return false;
-SDNode *Select_X86ISD_FMAX_f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (X86fmax:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MAXSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MAXSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fmax:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (MAXSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MAXSSrr, MVT::f32);
- return Result;
}
+ case 6: { // Predicate_loadi16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ LoadSDNode *LD = cast<LoadSDNode>(N);
+ if (const Value *Src = LD->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ ISD::LoadExtType ExtType = LD->getExtensionType();
+ if (ExtType == ISD::NON_EXTLOAD)
+ return true;
+ if (ExtType == ISD::EXTLOAD)
+ return LD->getAlignment() >= 2 && !LD->isVolatile();
+ return false;
-SDNode *Select_X86ISD_FMAX_f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (X86fmax:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MAXSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MAXSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fmax:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (MAXSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MAXSDrr, MVT::f64);
- return Result;
}
+ case 7: { // Predicate_shrd
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ assert(N->getOpcode() == ISD::OR);
+ return N->getOperand(0).getOpcode() == ISD::SRL &&
+ N->getOperand(1).getOpcode() == ISD::SHL &&
+ isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
+ isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
+ N->getOperand(0).getConstantOperandVal(1) ==
+ N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
-SDNode *Select_X86ISD_FMAX_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (X86fmax:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MAXPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MAXPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fmax:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (MAXPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MAXPSrr, MVT::v4f32);
- return Result;
}
+ case 8: { // Predicate_shld
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ assert(N->getOpcode() == ISD::OR);
+ return N->getOperand(0).getOpcode() == ISD::SHL &&
+ N->getOperand(1).getOpcode() == ISD::SRL &&
+ isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
+ isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
+ N->getOperand(0).getConstantOperandVal(1) ==
+ N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
-SDNode *Select_X86ISD_FMAX_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (X86fmax:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MAXPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MAXPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fmax:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (MAXPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MAXPDrr, MVT::v2f64);
- return Result;
}
+ case 9: { // Predicate_load
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
-SDNode *Select_X86ISD_FMIN_f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (X86fmin:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MINSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MINSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fmin:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (MINSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MINSSrr, MVT::f32);
- return Result;
}
+ case 10: { // Predicate_dsload
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ return true;
-SDNode *Select_X86ISD_FMIN_f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (X86fmin:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MINSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MINSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fmin:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (MINSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MINSDrr, MVT::f64);
- return Result;
}
+ case 11: { // Predicate_immSext8
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ return N->getSExtValue() == (int8_t)N->getSExtValue();
-SDNode *Select_X86ISD_FMIN_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (X86fmin:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MINPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MINPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fmin:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (MINPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MINPSrr, MVT::v4f32);
- return Result;
}
+ case 12: { // Predicate_i64immSExt32
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
+ // sign extended field.
+ return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
-SDNode *Select_X86ISD_FMIN_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (X86fmin:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MINPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MINPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fmin:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (MINPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MINPDrr, MVT::v2f64);
- return Result;
}
+ case 13: { // Predicate_movlp
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
-DISABLE_INLINE SDNode *Emit_288(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
-}
-SDNode *Select_X86ISD_FNSTCW16m(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_288(N, X86::FNSTCW16m, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
}
+ case 14: { // Predicate_unpckh
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_FOR_f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86for:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (FsORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::FsORPSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86for:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
- // Emits: (FsORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::FsORPSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86for:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (FsORPSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::FsORPSrr, MVT::f32);
- return Result;
}
+ case 15: { // Predicate_trunc_su
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return N->hasOneUse();
-SDNode *Select_X86ISD_FOR_f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86for:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (FsORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::FsORPDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86for:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
- // Emits: (FsORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::FsORPDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86for:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (FsORPDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::FsORPDrr, MVT::f64);
- return Result;
}
+ case 16: { // Predicate_srl_su
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return N->hasOneUse();
-DISABLE_INLINE SDNode *Emit_289(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
-}
-SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(SDNode *N) {
- if ((Subtarget->hasSSE3())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (X86fp_to_i16mem:isVoid RFP32:f32:$src, addr:iPTR:$op)
- // Emits: (ISTT_Fp16m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_289(N, X86::ISTT_Fp16m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fp_to_i16mem:isVoid RFP64:f64:$src, addr:iPTR:$op)
- // Emits: (ISTT_Fp16m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_289(N, X86::ISTT_Fp16m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fp_to_i16mem:isVoid RFP80:f80:$src, addr:iPTR:$op)
- // Emits: (ISTT_Fp16m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_289(N, X86::ISTT_Fp16m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (X86fp_to_i16mem:isVoid RFP32:f32:$src, addr:iPTR:$dst)
- // Emits: (FP32_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
- // Pattern complexity = 21 cost = 11 size = 3
- if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_289(N, X86::FP32_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fp_to_i16mem:isVoid RFP64:f64:$src, addr:iPTR:$dst)
- // Emits: (FP64_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
- // Pattern complexity = 21 cost = 11 size = 3
- if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_289(N, X86::FP64_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fp_to_i16mem:isVoid RFP80:f80:$src, addr:iPTR:$dst)
- // Emits: (FP80_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
- // Pattern complexity = 21 cost = 11 size = 3
- if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_289(N, X86::FP80_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
}
+ case 17: { // Predicate_truncstore
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<StoreSDNode>(N)->isTruncatingStore();
-SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(SDNode *N) {
- if ((Subtarget->hasSSE3())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (X86fp_to_i32mem:isVoid RFP32:f32:$src, addr:iPTR:$op)
- // Emits: (ISTT_Fp32m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_289(N, X86::ISTT_Fp32m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fp_to_i32mem:isVoid RFP64:f64:$src, addr:iPTR:$op)
- // Emits: (ISTT_Fp32m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_289(N, X86::ISTT_Fp32m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fp_to_i32mem:isVoid RFP80:f80:$src, addr:iPTR:$op)
- // Emits: (ISTT_Fp32m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_289(N, X86::ISTT_Fp32m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (X86fp_to_i32mem:isVoid RFP32:f32:$src, addr:iPTR:$dst)
- // Emits: (FP32_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
- // Pattern complexity = 21 cost = 11 size = 3
- if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_289(N, X86::FP32_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fp_to_i32mem:isVoid RFP64:f64:$src, addr:iPTR:$dst)
- // Emits: (FP64_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
- // Pattern complexity = 21 cost = 11 size = 3
- if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_289(N, X86::FP64_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fp_to_i32mem:isVoid RFP80:f80:$src, addr:iPTR:$dst)
- // Emits: (FP80_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
- // Pattern complexity = 21 cost = 11 size = 3
- if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_289(N, X86::FP80_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
}
+ case 18: { // Predicate_truncstorei16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
-SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(SDNode *N) {
- if ((Subtarget->hasSSE3())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (X86fp_to_i64mem:isVoid RFP32:f32:$src, addr:iPTR:$op)
- // Emits: (ISTT_Fp64m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_289(N, X86::ISTT_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fp_to_i64mem:isVoid RFP64:f64:$src, addr:iPTR:$op)
- // Emits: (ISTT_Fp64m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_289(N, X86::ISTT_Fp64m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fp_to_i64mem:isVoid RFP80:f80:$src, addr:iPTR:$op)
- // Emits: (ISTT_Fp64m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_289(N, X86::ISTT_Fp64m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
- }
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
-
- // Pattern: (X86fp_to_i64mem:isVoid RFP32:f32:$src, addr:iPTR:$dst)
- // Emits: (FP32_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
- // Pattern complexity = 21 cost = 11 size = 3
- if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_289(N, X86::FP32_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fp_to_i64mem:isVoid RFP64:f64:$src, addr:iPTR:$dst)
- // Emits: (FP64_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
- // Pattern complexity = 21 cost = 11 size = 3
- if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_289(N, X86::FP64_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fp_to_i64mem:isVoid RFP80:f80:$src, addr:iPTR:$dst)
- // Emits: (FP80_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
- // Pattern complexity = 21 cost = 11 size = 3
- if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_289(N, X86::FP80_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
}
+ case 19: { // Predicate_truncstoref32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_FRCP_f32(SDNode *N) {
-
- // Pattern: (X86frcp:f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (RCPSSm:f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1()) && (OptForSize)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::RCPSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
- // Pattern: (X86frcp:f32 FR32:f32:$src)
- // Emits: (RCPSSr:f32 FR32:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_72(N, X86::RCPSSr, MVT::f32);
- return Result;
}
+ case 20: { // Predicate_truncstoref64
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
-SDNode *Select_X86ISD_FRCP_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (X86frcp:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (RCPPSm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::RCPPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86frcp:v4f32 VR128:v4f32:$src)
- // Emits: (RCPPSr:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_72(N, X86::RCPPSr, MVT::v4f32);
- return Result;
}
+ case 21: { // Predicate_alignedstore
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_FRSQRT_f32(SDNode *N) {
-
- // Pattern: (X86frsqrt:f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (RSQRTSSm:f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1()) && (OptForSize)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::RSQRTSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
+ return cast<StoreSDNode>(N)->getAlignment() >= 16;
- // Pattern: (X86frsqrt:f32 FR32:f32:$src)
- // Emits: (RSQRTSSr:f32 FR32:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_72(N, X86::RSQRTSSr, MVT::f32);
- return Result;
}
+ case 22: { // Predicate_movlhps
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_FRSQRT_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (X86frsqrt:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (RSQRTPSm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::RSQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86frsqrt:v4f32 VR128:v4f32:$src)
- // Emits: (RSQRTPSr:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_72(N, X86::RSQRTPSr, MVT::v4f32);
- return Result;
}
+ case 23: { // Predicate_movshdup
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
-DISABLE_INLINE SDNode *Emit_290(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_BYTE_imm(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
-}
-SDNode *Select_X86ISD_FSRL_v2f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N1.getNode()) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_290(N, X86::PSRLDQri, MVT::v2f64);
- return Result;
- }
}
+ case 24: { // Predicate_memop
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return Subtarget->hasVectorUAMem()
+ || cast<LoadSDNode>(N)->getAlignment() >= 16;
-DISABLE_INLINE SDNode *Emit_291(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue InFlag = N->getOperand(4);
- SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1, Chain, InFlag };
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
-}
-SDNode *Select_X86ISD_FST(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDValue N3 = N->getOperand(3);
- if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f32) {
-
- // Pattern: (X86fst:isVoid RFP32:f32:$src, addr:iPTR:$op, f32:Other)
- // Emits: (ST_Fp32m:isVoid addr:iPTR:$op, RFP32:f32:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_291(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fst:isVoid RFP64:f64:$src, addr:iPTR:$op, f32:Other)
- // Emits: (ST_Fp64m32:isVoid addr:iPTR:$op, RFP64:f64:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_291(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
- }
-
- // Pattern: (X86fst:isVoid RFP64:f64:$src, addr:iPTR:$op, f64:Other)
- // Emits: (ST_Fp64m:isVoid addr:iPTR:$op, RFP64:f64:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f64 &&
- N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_291(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fst:isVoid RFP80:f80:$src, addr:iPTR:$op, f32:Other)
- // Emits: (ST_Fp80m32:isVoid addr:iPTR:$op, RFP80:f80:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f32 &&
- N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_291(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fst:isVoid RFP80:f80:$src, addr:iPTR:$op, f64:Other)
- // Emits: (ST_Fp80m64:isVoid addr:iPTR:$op, RFP80:f80:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f64 &&
- N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_291(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
-
- // Pattern: (X86fst:isVoid RFP80:f80:$src, addr:iPTR:$op, f80:Other)
- // Emits: (ST_FpP80m:isVoid addr:iPTR:$op, RFP80:f80:$src)
- // Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f80 &&
- N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_291(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
- return Result;
- }
}
+ case 25: { // Predicate_movsldup
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_FXOR_f32(SDNode *N) {
- if ((Subtarget->hasSSE1())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86fxor:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (FsXORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::FsXORPSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fxor:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
- // Emits: (FsXORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::FsXORPSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fxor:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (FsXORPSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::FsXORPSrr, MVT::f32);
- return Result;
}
+ case 26: { // Predicate_pshufd
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_FXOR_f64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86fxor:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (FsXORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::FsXORPDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fxor:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
- // Emits: (FsXORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::FsXORPDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86fxor:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (FsXORPDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::FsXORPDrr, MVT::f64);
- return Result;
}
+ case 27: { // Predicate_movddup
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_INC_i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_252(N, X86::INC8r, MVT::i8);
- return Result;
}
+ case 28: { // Predicate_unpckl
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_INC_i16(SDNode *N) {
-
- // Pattern: (X86inc_flag:i16 GR16:i16:$src)
- // Emits: (INC16r:i16 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 1
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_252(N, X86::INC16r, MVT::i16);
- return Result;
- }
- }
+ return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
- // Pattern: (X86inc_flag:i16 GR16:i16:$src)
- // Emits: (INC64_16r:i16 GR16:i16:$src)
- // Pattern complexity = 3 cost = 1 size = 2
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_252(N, X86::INC64_16r, MVT::i16);
- return Result;
- }
}
+ case 29: { // Predicate_pshufhw
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_INC_i32(SDNode *N) {
-
- // Pattern: (X86inc_flag:i32 GR32:i32:$src)
- // Emits: (INC32r:i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 1
- if ((!Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_252(N, X86::INC32r, MVT::i32);
- return Result;
- }
- }
+ return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
- // Pattern: (X86inc_flag:i32 GR32:i32:$src)
- // Emits: (INC64_32r:i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 2
- if ((Subtarget->is64Bit())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_252(N, X86::INC64_32r, MVT::i32);
- return Result;
- }
}
+ case 30: { // Predicate_pshuflw
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_INC_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_252(N, X86::INC64r, MVT::i64);
- return Result;
}
+ case 31: { // Predicate_mmx_pshufw
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
-DISABLE_INLINE SDNode *Emit_292(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp2, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_X86ISD_INSERTPS_v4f32(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86insrtps:v4f32 VR128:v4f32:$src1, (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>), (imm:iPTR):$src3)
- // Emits: (INSERTPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 31 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadf32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::f32) {
- SDNode *Result = Emit_292(N, X86::INSERTPSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (X86insrtps:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:iPTR):$src3)
- // Emits: (INSERTPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_98(N, X86::INSERTPSrr, MVT::v4f32);
- return Result;
- }
}
+ case 32: { // Predicate_shufp
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
-DISABLE_INLINE SDNode *Emit_293(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 7);
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_X86ISD_LCMPXCHG8_DAG(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_293(N, X86::LCMPXCHG8B, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
}
+ case 33: { // Predicate_mmx_unpckh
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
-DISABLE_INLINE SDNode *Emit_294(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SDValue InFlag = N->getOperand(4);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, N2, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_X86ISD_LCMPXCHG_DAG(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N3.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cas:isVoid addr:iPTR:$ptr, GR32:i32:$swap, 4:i8)
- // Emits: (LCMPXCHG32:isVoid addr:iPTR:$ptr, GR32:i32:$swap)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(4) &&
- N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_294(N, X86::LCMPXCHG32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
-
- // Pattern: (X86cas:isVoid addr:iPTR:$ptr, GR16:i16:$swap, 2:i8)
- // Emits: (LCMPXCHG16:isVoid addr:iPTR:$ptr, GR16:i16:$swap)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(2) &&
- N2.getValueType() == MVT::i16) {
- SDNode *Result = Emit_294(N, X86::LCMPXCHG16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
-
- // Pattern: (X86cas:isVoid addr:iPTR:$ptr, GR8:i8:$swap, 1:i8)
- // Emits: (LCMPXCHG8:isVoid addr:iPTR:$ptr, GR8:i8:$swap)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(1) &&
- N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_294(N, X86::LCMPXCHG8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
-
- // Pattern: (X86cas:isVoid addr:iPTR:$ptr, GR64:i64:$swap, 8:i8)
- // Emits: (LCMPXCHG64:isVoid addr:iPTR:$ptr, GR64:i64:$swap)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(8) &&
- N2.getValueType() == MVT::i64) {
- SDNode *Result = Emit_294(N, X86::LCMPXCHG64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
- }
- }
}
+ case 34: { // Predicate_mmx_unpckl
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
-DISABLE_INLINE SDNode *Emit_295(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0001_0, SDValue &CPTmpN0001_1, SDValue &CPTmpN0001_2, SDValue &CPTmpN0001_3, SDValue &CPTmpN0001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue Chain000 = N000.getNode()->getOperand(0);
- SDValue N0001 = N000.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N000.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4, Chain000 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N000.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_X86ISD_MOVQ2DQ_v2i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (MMX_X86movq2dq:v2i64 (bitconvert:v1i64 (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
- // Emits: (MOVDI2PDIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 31 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N00.hasOneUse()) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::LOAD &&
- N000.hasOneUse() &&
- IsLegalAndProfitableToFold(N000.getNode(), N00.getNode(), N)) {
- SDValue Chain000 = N000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N000.getNode()) &&
- Predicate_loadi32(N000.getNode())) {
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue CPTmpN0001_0;
- SDValue CPTmpN0001_1;
- SDValue CPTmpN0001_2;
- SDValue CPTmpN0001_3;
- SDValue CPTmpN0001_4;
- if (SelectAddr(N, N0001, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4) &&
- N00.getValueType() == MVT::v2i32 &&
- N000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_295(N, X86::MOVDI2PDIrm, MVT::v2i64, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (MMX_X86movq2dq:v2i64 (ld:v1i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MOVQI2PQIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::MOVQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
}
+ case 35: { // Predicate_movhlps_undef
+ SDNode *N = Node;
- // Pattern: (MMX_X86movq2dq:v2i64 VR64:v1i64:$src)
- // Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_72(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
- return Result;
-}
-
-SDNode *Select_X86ISD_MUL_IMM_i32(SDNode *N) {
-
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA64_32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
- }
+ return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
- // Pattern: lea32addr:i32:$src
- // Emits: (LEA32r:i32 lea32addr:i32:$src)
- // Pattern complexity = 15 cost = 1 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
- }
}
+ case 36: { // Predicate_movhlps
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_MUL_IMM_i64(SDNode *N) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
}
+ case 37: { // Predicate_movl
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_OR_i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86or_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (OR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::OR8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86or_flag:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1)
- // Emits: (OR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi8(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::OR8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (X86or_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (OR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_3(N, X86::OR8ri, MVT::i8);
- return Result;
- }
}
+ case 38: { // Predicate_immAllZerosV_bc
+ SDNode *N = Node;
- // Pattern: (X86or_flag:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (OR8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::OR8rr, MVT::i8);
- return Result;
-}
+ return ISD::isBuildVectorAllZeros(N);
-SDNode *Select_X86ISD_OR_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86or_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (OR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::OR16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86or_flag:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
- // Emits: (OR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::OR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86or_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (OR16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::OR16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86or_flag:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (OR16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::OR16ri, MVT::i16);
- return Result;
- }
}
+ case 39: { // Predicate_unpckl_undef
+ SDNode *N = Node;
- // Pattern: (X86or_flag:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (OR16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::OR16rr, MVT::i16);
- return Result;
-}
+ return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_OR_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86or_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (OR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::OR32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86or_flag:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
- // Emits: (OR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::OR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86or_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (OR32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::OR32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86or_flag:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (OR32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::OR32ri, MVT::i32);
- return Result;
- }
}
+ case 40: { // Predicate_unpckh_undef
+ SDNode *N = Node;
- // Pattern: (X86or_flag:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (OR32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::OR32rr, MVT::i32);
- return Result;
-}
+ return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_OR_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86or_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (OR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::OR64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86or_flag:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1)
- // Emits: (OR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::OR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86or_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (OR64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::OR64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86or_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (OR64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::OR64ri32, MVT::i64);
- return Result;
- }
- }
}
+ case 41: { // Predicate_splat_lo
+ SDNode *N = Node;
- // Pattern: (X86or_flag:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (OR64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::OR64rr, MVT::i64);
- return Result;
-}
+ ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
+ return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
-SDNode *Select_X86ISD_PCMPEQB_v8i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86pcmpeqb:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPEQBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (X86pcmpeqb:v8i8 (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PCMPEQBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
}
+ case 42: { // Predicate_mmx_unpckl_undef
+ SDNode *N = Node;
- // Pattern: (X86pcmpeqb:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PCMPEQBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PCMPEQBrr, MVT::v8i8);
- return Result;
-}
+ return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_PCMPEQB_v16i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86pcmpeqb:v16i8 VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PCMPEQBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PCMPEQBrm, MVT::v16i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86pcmpeqb:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v16i8:$src1)
- // Emits: (PCMPEQBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PCMPEQBrm, MVT::v16i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
}
+ case 43: { // Predicate_mmx_unpckh_undef
+ SDNode *N = Node;
- // Pattern: (X86pcmpeqb:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PCMPEQBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PCMPEQBrr, MVT::v16i8);
- return Result;
-}
+ return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_PCMPEQD_v2i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86pcmpeqd:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPEQDrm:v2i32 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (X86pcmpeqd:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
- // Emits: (MMX_PCMPEQDrm:v2i32 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
}
+ case 44: { // Predicate_immAllZerosV
+ SDNode *N = Node;
- // Pattern: (X86pcmpeqd:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (MMX_PCMPEQDrr:v2i32 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PCMPEQDrr, MVT::v2i32);
- return Result;
-}
+ return ISD::isBuildVectorAllZeros(N);
-SDNode *Select_X86ISD_PCMPEQD_v4i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86pcmpeqd:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PCMPEQDrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PCMPEQDrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86pcmpeqd:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4i32:$src1)
- // Emits: (PCMPEQDrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PCMPEQDrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
}
+ case 45: { // Predicate_palign
+ SDNode *N = Node;
- // Pattern: (X86pcmpeqd:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PCMPEQDrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PCMPEQDrr, MVT::v4i32);
- return Result;
-}
+ return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
-SDNode *Select_X86ISD_PCMPEQQ_v2i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86pcmpeqq:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PCMPEQQrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86pcmpeqq:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
- // Emits: (PCMPEQQrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
}
+ case 46: { // Predicate_gsload
+ SDNode *N = Node;
- // Pattern: (X86pcmpeqq:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PCMPEQQrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PCMPEQQrr, MVT::v2i64);
- return Result;
-}
+ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ return PT->getAddressSpace() == 256;
+ return false;
-SDNode *Select_X86ISD_PCMPEQW_v4i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86pcmpeqw:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPEQWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (X86pcmpeqw:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PCMPEQWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
}
+ case 47: { // Predicate_fsload
+ SDNode *N = Node;
- // Pattern: (X86pcmpeqw:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PCMPEQWrr:v4i16 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PCMPEQWrr, MVT::v4i16);
- return Result;
-}
+ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ return PT->getAddressSpace() == 257;
+ return false;
-SDNode *Select_X86ISD_PCMPEQW_v8i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86pcmpeqw:v8i16 VR128:v8i16:$src1, (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PCMPEQWrm:v8i16 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PCMPEQWrm, MVT::v8i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86pcmpeqw:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v8i16:$src1)
- // Emits: (PCMPEQWrm:v8i16 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PCMPEQWrm, MVT::v8i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
}
+ case 48: { // Predicate_extload
+ SDNode *N = Node;
- // Pattern: (X86pcmpeqw:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PCMPEQWrr:v8i16 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PCMPEQWrr, MVT::v8i16);
- return Result;
-}
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
-SDNode *Select_X86ISD_PCMPGTB_v8i8(SDNode *N) {
-
- // Pattern: (X86pcmpgtb:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPGTBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PCMPGTBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
}
+ case 49: { // Predicate_extloadf32
+ SDNode *N = Node;
- // Pattern: (X86pcmpgtb:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PCMPGTBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PCMPGTBrr, MVT::v8i8);
- return Result;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
-SDNode *Select_X86ISD_PCMPGTB_v16i8(SDNode *N) {
-
- // Pattern: (X86pcmpgtb:v16i8 VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PCMPGTBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PCMPGTBrm, MVT::v16i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
}
+ case 50: { // Predicate_extloadf64
+ SDNode *N = Node;
- // Pattern: (X86pcmpgtb:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PCMPGTBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PCMPGTBrr, MVT::v16i8);
- return Result;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
-SDNode *Select_X86ISD_PCMPGTD_v2i32(SDNode *N) {
-
- // Pattern: (X86pcmpgtd:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPGTDrm:v2i32 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PCMPGTDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
}
+ case 51: { // Predicate_sextload
+ SDNode *N = Node;
- // Pattern: (X86pcmpgtd:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (MMX_PCMPGTDrr:v2i32 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PCMPGTDrr, MVT::v2i32);
- return Result;
-}
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
-SDNode *Select_X86ISD_PCMPGTD_v4i32(SDNode *N) {
-
- // Pattern: (X86pcmpgtd:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PCMPGTDrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PCMPGTDrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
}
+ case 52: { // Predicate_sextloadi8
+ SDNode *N = Node;
- // Pattern: (X86pcmpgtd:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PCMPGTDrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PCMPGTDrr, MVT::v4i32);
- return Result;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
-SDNode *Select_X86ISD_PCMPGTQ_v2i64(SDNode *N) {
-
- // Pattern: (X86pcmpgtq:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PCMPGTQrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PCMPGTQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
}
+ case 53: { // Predicate_sextloadi16
+ SDNode *N = Node;
- // Pattern: (X86pcmpgtq:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PCMPGTQrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PCMPGTQrr, MVT::v2i64);
- return Result;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
-SDNode *Select_X86ISD_PCMPGTW_v4i16(SDNode *N) {
-
- // Pattern: (X86pcmpgtw:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPGTWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PCMPGTWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
}
+ case 54: { // Predicate_zextload
+ SDNode *N = Node;
- // Pattern: (X86pcmpgtw:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PCMPGTWrr:v4i16 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::MMX_PCMPGTWrr, MVT::v4i16);
- return Result;
-}
+ return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
-SDNode *Select_X86ISD_PCMPGTW_v8i16(SDNode *N) {
-
- // Pattern: (X86pcmpgtw:v8i16 VR128:v8i16:$src1, (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PCMPGTWrm:v8i16 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PCMPGTWrm, MVT::v8i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
}
+ case 55: { // Predicate_zextloadi8
+ SDNode *N = Node;
- // Pattern: (X86pcmpgtw:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PCMPGTWrr:v8i16 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PCMPGTWrr, MVT::v8i16);
- return Result;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
-SDNode *Select_X86ISD_PEXTRB_i32(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_94(N, X86::PEXTRBrr, MVT::i32);
- return Result;
- }
}
+ case 56: { // Predicate_zextloadi16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_296(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
-}
-SDNode *Select_X86ISD_PEXTRW_i32(SDNode *N) {
-
- // Pattern: (X86pextrw:i32 VR128:v8i16:$src1, (imm:iPTR):$src2)
- // Emits: (PEXTRWri:i32 VR128:v8i16:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_94(N, X86::PEXTRWri, MVT::i32);
- return Result;
- }
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
- // Pattern: (MMX_X86pextrw:i32 VR64:v4i16:$src1, (imm:iPTR):$src2)
- // Emits: (MMX_PEXTRWri:i32 VR64:v4i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i16 &&
- N1.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_296(N, X86::MMX_PEXTRWri, MVT::i32);
- return Result;
- }
}
+ case 57: { // Predicate_zextloadi1
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
-SDNode *Select_X86ISD_PINSRB_v16i8(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86pinsrb:v16i8 VR128:v16i8:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, (imm:iPTR):$src3)
- // Emits: (PINSRBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_extload(N1.getNode()) &&
- Predicate_extloadi8(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_99(N, X86::PINSRBrm, MVT::v16i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86pinsrb:v16i8 VR128:v16i8:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
- // Emits: (PINSRBrr:v16i8 VR128:v16i8:$src1, GR32:i32:$src2, (imm:i32):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_98(N, X86::PINSRBrr, MVT::v16i8);
- return Result;
- }
}
+ case 58: { // Predicate_extloadi1
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
-DISABLE_INLINE SDNode *Emit_297(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i16);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_298(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N10 = N1.getNode()->getOperand(0);
- SDValue Chain10 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i16);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
- SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp2, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-SDNode *Select_X86ISD_PINSRW_v4i16(SDNode *N) {
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (MMX_X86pinsrw:v4i16 VR64:v4i16:$src1, (anyext:i32 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), (imm:iPTR):$src3)
- // Emits: (MMX_PINSRWrmi:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2, (imm:i16):$src3)
- // Pattern complexity = 31 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ANY_EXTEND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i16 &&
- N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::i16 &&
- N2.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_298(N, X86::MMX_PINSRWrmi, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (MMX_X86pinsrw:v4i16 VR64:v4i16:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
- // Emits: (MMX_PINSRWrri:v4i16 VR64:v4i16:$src1, GR32:i32:$src2, (imm:i16):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4i16 &&
- N1.getValueType() == MVT::i32 &&
- N2.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_297(N, X86::MMX_PINSRWrri, MVT::v4i16);
- return Result;
- }
}
+ case 59: { // Predicate_extloadi8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
-SDNode *Select_X86ISD_PINSRW_v8i16(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86pinsrw:v8i16 VR128:v8i16:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, (imm:iPTR):$src3)
- // Emits: (PINSRWrmi:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_extload(N1.getNode()) &&
- Predicate_extloadi16(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_99(N, X86::PINSRWrmi, MVT::v8i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86pinsrw:v8i16 VR128:v8i16:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
- // Emits: (PINSRWrri:v8i16 VR128:v8i16:$src1, GR32:i32:$src2, (imm:i32):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_98(N, X86::PINSRWrri, MVT::v8i16);
- return Result;
- }
}
+ case 60: { // Predicate_extloadi16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
-SDNode *Select_X86ISD_PSHUFB_v16i8(SDNode *N) {
- if ((Subtarget->hasSSSE3())) {
-
- // Pattern: (X86pshufb:v16i8 VR128:v16i8:$src, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$mask)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSHUFBrm128:v16i8 VR128:v16i8:$src, addr:iPTR:$mask)
- // Pattern complexity = 28 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PSHUFBrm128, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (X86pshufb:v16i8 VR128:v16i8:$src, VR128:v16i8:$mask)
- // Emits: (PSHUFBrr128:v16i8 VR128:v16i8:$src, VR128:v16i8:$mask)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_15(N, X86::PSHUFBrr128, MVT::v16i8);
- return Result;
}
+ case 61: { // Predicate_sextloadi32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
-SDNode *Select_X86ISD_PTEST(SDNode *N) {
- if ((Subtarget->hasSSE41())) {
-
- // Pattern: (X86ptest:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (PTESTrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_277(N, X86::PTESTrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86ptest:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (PTESTrr:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_254(N, X86::PTESTrr);
- return Result;
}
+ case 62: { // Predicate_zextloadi32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_299(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Chain);
- Chain = SDValue(ResNode, 0);
- SDValue InFlag(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_X86ISD_RDTSC_DAG(SDNode *N) {
- SDNode *Result = Emit_299(N, X86::RDTSC);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_300(SDNode *N, unsigned Opc0) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue InFlag = N->getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Chain, InFlag);
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_X86ISD_REP_MOVS(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86rep_movs:isVoid i8:Other)
- // Emits: (REP_MOVSB:isVoid)
- // Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_300(N, X86::REP_MOVSB);
- return Result;
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
- // Pattern: (X86rep_movs:isVoid i16:Other)
- // Emits: (REP_MOVSW:isVoid)
- // Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_300(N, X86::REP_MOVSW);
- return Result;
}
+ case 63: { // Predicate_alignedload
+ SDNode *N = Node;
- // Pattern: (X86rep_movs:isVoid i32:Other)
- // Emits: (REP_MOVSD:isVoid)
- // Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_300(N, X86::REP_MOVSD);
- return Result;
- }
+ return cast<LoadSDNode>(N)->getAlignment() >= 16;
- // Pattern: (X86rep_movs:isVoid i64:Other)
- // Emits: (REP_MOVSQ:isVoid)
- // Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i64) {
- SDNode *Result = Emit_300(N, X86::REP_MOVSQ);
- return Result;
}
+ case 64: { // Predicate_extloadi32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_REP_STOS(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86rep_stos:isVoid i8:Other)
- // Emits: (REP_STOSB:isVoid)
- // Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_300(N, X86::REP_STOSB);
- return Result;
- }
+ return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
- // Pattern: (X86rep_stos:isVoid i16:Other)
- // Emits: (REP_STOSW:isVoid)
- // Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_300(N, X86::REP_STOSW);
- return Result;
}
+ case 65: { // Predicate_loadi16_anyext
+ SDNode *N = Node;
- // Pattern: (X86rep_stos:isVoid i32:Other)
- // Emits: (REP_STOSD:isVoid)
- // Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_300(N, X86::REP_STOSD);
- return Result;
- }
+ LoadSDNode *LD = cast<LoadSDNode>(N);
+ if (const Value *Src = LD->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ if (PT->getAddressSpace() > 255)
+ return false;
+ ISD::LoadExtType ExtType = LD->getExtensionType();
+ if (ExtType == ISD::EXTLOAD)
+ return LD->getAlignment() >= 2 && !LD->isVolatile();
+ return false;
- // Pattern: (X86rep_stos:isVoid i64:Other)
- // Emits: (REP_STOSQ:isVoid)
- // Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i64) {
- SDNode *Result = Emit_300(N, X86::REP_STOSQ);
- return Result;
}
+ case 66: { // Predicate_memop64
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_301(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
-}
-DISABLE_INLINE SDNode *Emit_302(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(N1);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
-}
-SDNode *Select_X86ISD_RET_FLAG(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86retflag:isVoid 0:i16)
- // Emits: (RET:isVoid)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_301(N, X86::RET, 1);
- return Result;
- }
- }
- }
+ return cast<LoadSDNode>(N)->getAlignment() >= 8;
- // Pattern: (X86retflag:isVoid (timm:i16):$amt)
- // Emits: (RETI:isVoid (timm:i16):$amt)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_302(N, X86::RETI, 1);
- return Result;
}
+ case 67: { // Predicate_immAllOnesV
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return ISD::isBuildVectorAllOnes(N);
-DISABLE_INLINE SDNode *Emit_303(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EFLAGS, N1, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, InFlag);
-}
-SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86setcc:i8 4:i8, EFLAGS:i32)
- // Emits: (SETEr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_303(N, X86::SETEr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 9:i8, EFLAGS:i32)
- // Emits: (SETNEr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_303(N, X86::SETNEr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 7:i8, EFLAGS:i32)
- // Emits: (SETLr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_303(N, X86::SETLr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 6:i8, EFLAGS:i32)
- // Emits: (SETGEr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_303(N, X86::SETGEr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 8:i8, EFLAGS:i32)
- // Emits: (SETLEr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_303(N, X86::SETLEr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 5:i8, EFLAGS:i32)
- // Emits: (SETGr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_303(N, X86::SETGr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 2:i8, EFLAGS:i32)
- // Emits: (SETBr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_303(N, X86::SETBr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 1:i8, EFLAGS:i32)
- // Emits: (SETAEr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_303(N, X86::SETAEr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 3:i8, EFLAGS:i32)
- // Emits: (SETBEr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_303(N, X86::SETBEr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 0:i8, EFLAGS:i32)
- // Emits: (SETAr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_303(N, X86::SETAr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 15:i8, EFLAGS:i32)
- // Emits: (SETSr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_303(N, X86::SETSr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 12:i8, EFLAGS:i32)
- // Emits: (SETNSr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_303(N, X86::SETNSr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 14:i8, EFLAGS:i32)
- // Emits: (SETPr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_303(N, X86::SETPr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 11:i8, EFLAGS:i32)
- // Emits: (SETNPr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_303(N, X86::SETNPr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 13:i8, EFLAGS:i32)
- // Emits: (SETOr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_303(N, X86::SETOr, MVT::i8);
- return Result;
- }
-
- // Pattern: (X86setcc:i8 10:i8, EFLAGS:i32)
- // Emits: (SETNOr:i8)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_303(N, X86::SETNOr, MVT::i8);
- return Result;
- }
}
+ case 68: { // Predicate_immAllOnesV_bc
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return ISD::isBuildVectorAllOnes(N);
-SDNode *Select_X86ISD_SETCC_CARRY_i8(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_303(N, X86::SETB_C8r, MVT::i8);
- return Result;
- }
}
+ case 69: { // Predicate_i64immZExt32
+ ConstantSDNode*N = cast<ConstantSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
+ // unsignedsign extended field.
+ return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
-SDNode *Select_X86ISD_SETCC_CARRY_i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_303(N, X86::SETB_C16r, MVT::i16);
- return Result;
- }
}
+ case 70: { // Predicate_and_su
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
+ return N->hasOneUse();
-SDNode *Select_X86ISD_SETCC_CARRY_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_303(N, X86::SETB_C32r, MVT::i32);
- return Result;
- }
}
+ case 71: { // Predicate_or_is_add
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_SETCC_CARRY_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_303(N, X86::SETB_C64r, MVT::i64);
- return Result;
- }
+ if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
+ return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
+ else {
+ unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
+ APInt Mask = APInt::getAllOnesValue(BitWidth);
+ APInt KnownZero0, KnownOne0;
+ CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
+ APInt KnownZero1, KnownOne1;
+ CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
+ return (~KnownZero0 & ~KnownZero1) == 0;
}
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_304(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::CL, N2, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, InFlag);
-}
-SDNode *Select_X86ISD_SHLD_i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
-
- // Pattern: (X86shld:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$src3)
- // Emits: (SHLD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_284(N, X86::SHLD16rri8, MVT::i16);
- return Result;
}
+ case 72: { // Predicate_atomic_swap_32
+ SDNode *N = Node;
- // Pattern: (X86shld:i16 GR16:i16:$src1, GR16:i16:$src2, CL:i8)
- // Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_304(N, X86::SHLD16rrCL, MVT::i16);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 73: { // Predicate_atomic_swap_16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_SHLD_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
-
- // Pattern: (X86shld:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$src3)
- // Emits: (SHLD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_284(N, X86::SHLD32rri8, MVT::i32);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 74: { // Predicate_atomic_swap_8
+ SDNode *N = Node;
- // Pattern: (X86shld:i32 GR32:i32:$src1, GR32:i32:$src2, CL:i8)
- // Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_304(N, X86::SHLD32rrCL, MVT::i32);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 75: { // Predicate_atomic_swap_64
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_SHLD_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
-
- // Pattern: (X86shld:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$src3)
- // Emits: (SHLD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_284(N, X86::SHLD64rri8, MVT::i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 76: { // Predicate_atomic_load_add_32
+ SDNode *N = Node;
- // Pattern: (X86shld:i64 GR64:i64:$src1, GR64:i64:$src2, CL:i8)
- // Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_304(N, X86::SHLD64rrCL, MVT::i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 77: { // Predicate_atomic_load_add_16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_SHRD_i16(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
-
- // Pattern: (X86shrd:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$src3)
- // Emits: (SHRD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_284(N, X86::SHRD16rri8, MVT::i16);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 78: { // Predicate_atomic_load_add_8
+ SDNode *N = Node;
- // Pattern: (X86shrd:i16 GR16:i16:$src1, GR16:i16:$src2, CL:i8)
- // Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_304(N, X86::SHRD16rrCL, MVT::i16);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 79: { // Predicate_atomic_load_add_64
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_SHRD_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
-
- // Pattern: (X86shrd:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$src3)
- // Emits: (SHRD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_284(N, X86::SHRD32rri8, MVT::i32);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 80: { // Predicate_atomic_load_and_32
+ SDNode *N = Node;
- // Pattern: (X86shrd:i32 GR32:i32:$src1, GR32:i32:$src2, CL:i8)
- // Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_304(N, X86::SHRD32rrCL, MVT::i32);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 81: { // Predicate_atomic_load_and_16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_SHRD_i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
-
- // Pattern: (X86shrd:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$src3)
- // Emits: (SHRD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_284(N, X86::SHRD64rri8, MVT::i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 82: { // Predicate_atomic_load_and_8
+ SDNode *N = Node;
- // Pattern: (X86shrd:i64 GR64:i64:$src1, GR64:i64:$src2, CL:i8)
- // Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_304(N, X86::SHRD64rrCL, MVT::i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 83: { // Predicate_atomic_load_and_64
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_305(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, N0);
-}
-SDNode *Select_X86ISD_SMUL_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86smul_flag:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (IMUL16rmi8:i16 addr:iPTR:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_146(N, X86::IMUL16rmi8, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86smul_flag:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2)
- // Emits: (IMUL16rmi:i16 addr:iPTR:$src1, (imm:i16):$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- SDNode *Result = Emit_146(N, X86::IMUL16rmi, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86smul_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (IMUL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::IMUL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86smul_flag:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
- // Emits: (IMUL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::IMUL16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86smul_flag:i16 GR16:i16:$src1, 2:i16)
- // Emits: (ADD16rr:i16 GR16:i16:$src1, GR16:i16:$src1)
- // Pattern complexity = 10 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_305(N, X86::ADD16rr, MVT::i16);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86smul_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (IMUL16rri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::IMUL16rri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86smul_flag:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (IMUL16rri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::IMUL16rri, MVT::i16);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 84: { // Predicate_atomic_load_or_32
+ SDNode *N = Node;
- // Pattern: (X86smul_flag:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (IMUL16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::IMUL16rr, MVT::i16);
- return Result;
-}
-
-SDNode *Select_X86ISD_SMUL_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86smul_flag:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (IMUL32rmi8:i32 addr:iPTR:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_147(N, X86::IMUL32rmi8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86smul_flag:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2)
- // Emits: (IMUL32rmi:i32 addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- SDNode *Result = Emit_147(N, X86::IMUL32rmi, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86smul_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (IMUL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::IMUL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86smul_flag:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
- // Emits: (IMUL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::IMUL32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86smul_flag:i32 GR32:i32:$src1, 2:i32)
- // Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src1)
- // Pattern complexity = 10 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_305(N, X86::ADD32rr, MVT::i32);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86smul_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (IMUL32rri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::IMUL32rri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86smul_flag:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (IMUL32rri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::IMUL32rri, MVT::i32);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 85: { // Predicate_atomic_load_or_16
+ SDNode *N = Node;
- // Pattern: (X86smul_flag:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (IMUL32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::IMUL32rr, MVT::i32);
- return Result;
-}
-
-SDNode *Select_X86ISD_SMUL_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86smul_flag:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (IMUL64rmi8:i64 addr:iPTR:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_148(N, X86::IMUL64rmi8, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
- // Pattern: (X86smul_flag:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (IMUL64rmi32:i64 addr:iPTR:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_148(N, X86::IMUL64rmi32, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (X86smul_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (IMUL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::IMUL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86smul_flag:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1)
- // Emits: (IMUL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::IMUL64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86smul_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (IMUL64rri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::IMUL64rri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86smul_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (IMUL64rri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::IMUL64rri32, MVT::i64);
- return Result;
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 86: { // Predicate_atomic_load_or_8
+ SDNode *N = Node;
- // Pattern: (X86smul_flag:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (IMUL64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::IMUL64rr, MVT::i64);
- return Result;
-}
-
-SDNode *Select_X86ISD_SUB_i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86sub_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (SUB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::SUB8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
-
- // Pattern: (X86sub_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (SUB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_3(N, X86::SUB8ri, MVT::i8);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 87: { // Predicate_atomic_load_or_64
+ SDNode *N = Node;
- // Pattern: (X86sub_flag:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (SUB8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::SUB8rr, MVT::i8);
- return Result;
-}
-
-SDNode *Select_X86ISD_SUB_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86sub_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (SUB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::SUB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86sub_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (SUB16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::SUB16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86sub_flag:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (SUB16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::SUB16ri, MVT::i16);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 88: { // Predicate_atomic_load_xor_32
+ SDNode *N = Node;
- // Pattern: (X86sub_flag:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (SUB16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::SUB16rr, MVT::i16);
- return Result;
-}
-
-SDNode *Select_X86ISD_SUB_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86sub_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::SUB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86sub_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (SUB32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::SUB32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86sub_flag:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (SUB32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::SUB32ri, MVT::i32);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 89: { // Predicate_atomic_load_xor_16
+ SDNode *N = Node;
- // Pattern: (X86sub_flag:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (SUB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::SUB32rr, MVT::i32);
- return Result;
-}
-
-SDNode *Select_X86ISD_SUB_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86sub_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::SUB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86sub_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (SUB64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::SUB64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86sub_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (SUB64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::SUB64ri32, MVT::i64);
- return Result;
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 90: { // Predicate_atomic_load_xor_8
+ SDNode *N = Node;
- // Pattern: (X86sub_flag:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (SUB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::SUB64rr, MVT::i64);
- return Result;
-}
-
-DISABLE_INLINE SDNode *Emit_306(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SmallVector<SDValue, 8> Ops0;
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- Ops0.push_back(N1);
- Ops0.push_back(Tmp1);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- if (HasInFlag)
- Ops0.push_back(InFlag);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
-}
-SDNode *Select_X86ISD_TC_RETURN(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (X86tcret:isVoid (tglobaladdr:i64):$dst, (imm:i32):$off)
- // Emits: (TCRETURNdi64:isVoid (tglobaladdr:i64):$dst, (imm:i32):$off)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_306(N, X86::TCRETURNdi64, 2);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 91: { // Predicate_atomic_load_xor_64
+ SDNode *N = Node;
- // Pattern: (X86tcret:isVoid (texternalsym:i64):$dst, (imm:i32):$off)
- // Emits: (TCRETURNdi64:isVoid (texternalsym:i64):$dst, (imm:i32):$off)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_306(N, X86::TCRETURNdi64, 2);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 92: { // Predicate_atomic_load_nand_32
+ SDNode *N = Node;
- // Pattern: (X86tcret:isVoid (tglobaladdr:i32):$dst, (imm:i32):$off)
- // Emits: (TCRETURNdi:isVoid (texternalsym:i32):$dst, (imm:i32):$off)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, X86::TCRETURNdi, 2);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 93: { // Predicate_atomic_load_nand_16
+ SDNode *N = Node;
- // Pattern: (X86tcret:isVoid (texternalsym:i32):$dst, (imm:i32):$off)
- // Emits: (TCRETURNdi:isVoid (texternalsym:i32):$dst, (imm:i32):$off)
- // Pattern complexity = 9 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, X86::TCRETURNdi, 2);
- return Result;
- }
- }
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86tcret:isVoid GR64:i64:$dst, (imm:i32):$off)
- // Emits: (TCRETURNri64:isVoid GR64:i64:$dst, (imm:i32):$off)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_306(N, X86::TCRETURNri64, 2);
- return Result;
- }
-
- // Pattern: (X86tcret:isVoid GR32:i32:$dst, (imm:i32):$off)
- // Emits: (TCRETURNri:isVoid GR32:i32:$dst, (imm:i32):$off)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, X86::TCRETURNri, 2);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 94: { // Predicate_atomic_load_nand_8
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_307(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
- SDValue InFlag(0, 0);
- if (HasInFlag) {
- InFlag = N->getOperand(N->getNumOperands()-1);
- }
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 6 : 5);
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- const SDValue Froms[] = {
- SDValue(N, 1),
- SDValue(N, 0)
- };
- const SDValue Tos[] = {
- InFlag,
- SDValue(Chain.getNode(), Chain.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-SDNode *Select_X86ISD_TLSADDR(SDNode *N) {
-
- // Pattern: (X86tlsaddr:isVoid tls32addr:i32:$sym)
- // Emits: (TLS_addr32:isVoid tls32addr:i32:$sym)
- // Pattern complexity = 18 cost = 1 size = 3
- if ((!Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- if (SelectTLSADDRAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3) &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_307(N, X86::TLS_addr32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+
}
+ case 95: { // Predicate_atomic_load_nand_64
+ SDNode *N = Node;
- // Pattern: (X86tlsaddr:isVoid tls64addr:i64:$sym)
- // Emits: (TLS_addr64:isVoid tls64addr:i64:$sym)
- // Pattern complexity = 18 cost = 1 size = 3
- if ((Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- if (SelectTLSADDRAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3) &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_307(N, X86::TLS_addr64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 96: { // Predicate_atomic_load_min_32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_UCOMI(SDNode *N) {
-
- // Pattern: (X86ucomi:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_UCOMISSrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_277(N, X86::Int_UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 97: { // Predicate_atomic_load_min_16
+ SDNode *N = Node;
- // Pattern: (X86ucomi:isVoid VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_UCOMISDrm:isVoid VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_277(N, X86::Int_UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 98: { // Predicate_atomic_load_min_64
+ SDNode *N = Node;
- // Pattern: (X86ucomi:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (Int_UCOMISSrr:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_254(N, X86::Int_UCOMISSrr);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 99: { // Predicate_atomic_load_max_32
+ SDNode *N = Node;
- // Pattern: (X86ucomi:isVoid VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (Int_UCOMISDrr:isVoid VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_254(N, X86::Int_UCOMISDrr);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 100: { // Predicate_atomic_load_max_16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_308(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- SmallVector<SDValue, 8> Ops0;
- SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i64);
- SDValue Tmp2 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i64);
- Ops0.push_back(N1);
- Ops0.push_back(Tmp1);
- Ops0.push_back(Tmp2);
- for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands(); i != e; ++i) {
- Ops0.push_back(N->getOperand(i));
- }
- Ops0.push_back(Chain);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
-}
-SDNode *Select_X86ISD_VASTART_SAVE_XMM_REGS(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_308(N, X86::VASTART_SAVE_XMM_REGS, 3);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 101: { // Predicate_atomic_load_max_64
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_VSHL_v1i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::MMX_PSLLQri, MVT::v1i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 102: { // Predicate_atomic_load_umin_32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_VSHL_v2i64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_290(N, X86::PSLLDQri, MVT::v2i64);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 103: { // Predicate_atomic_load_umin_16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_VSRL_v1i64(SDNode *N) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::MMX_PSRLQri, MVT::v1i64);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 104: { // Predicate_atomic_load_umin_64
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_VSRL_v2i64(SDNode *N) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_290(N, X86::PSRLDQri, MVT::v2i64);
- return Result;
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 105: { // Predicate_atomic_load_umax_32
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_309(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
-}
-SDNode *Select_X86ISD_VZEXT_LOAD_v2i64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_309(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+
}
+ case 106: { // Predicate_atomic_load_umax_16
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_X86ISD_VZEXT_LOAD_v2f64(SDNode *N) {
- SDValue Chain = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_309(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
- return Result;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+
}
+ case 107: { // Predicate_atomic_load_umax_64
+ SDNode *N = Node;
- CannotYetSelect(N);
- return NULL;
-}
-
-DISABLE_INLINE SDNode *Emit_310(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Chain00 = N00.getNode()->getOperand(0);
- SDValue N001 = N00.getNode()->getOperand(1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
- SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
- ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_311(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp1(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, N0, Tmp1);
-}
-SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(SDNode *N) {
-
- // Pattern: (X86vzmovl:v2i32 (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))
- // Emits: (MMX_MOVZDI2PDIrm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_loadi32(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
- N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_310(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
+ return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+
}
+ case 108: { // Predicate_def32
+ SDNode *N = Node;
- // Pattern: (X86vzmovl:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_MOVZDI2PDIrm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
- N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_310(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
+ return N->getOpcode() != ISD::TRUNCATE &&
+ N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
+ N->getOpcode() != ISD::CopyFromReg &&
+ N->getOpcode() != X86ISD::CMOV;
- // Pattern: (X86vzmovl:v2i32 (scalar_to_vector:v2i32 GR32:i32:$src))
- // Emits: (MMX_MOVZDI2PDIrr:v2i32 GR32:i32:$src)
- // Pattern complexity = 21 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_160(N, X86::MMX_MOVZDI2PDIrr, MVT::v2i32);
- return Result;
- }
- }
}
+ case 109: { // Predicate_fpimm0
+ ConstantFPSDNode*N = cast<ConstantFPSDNode>(Node);
- // Pattern: (X86vzmovl:v2i32 VR64:v2i32:$src)
- // Emits: (MMX_PUNPCKLDQrr:v2i32 VR64:v8i8:$src, (MMX_V_SET0:v8i8))
- // Pattern complexity = 18 cost = 2 size = 6
- SDNode *Result = Emit_311(N, X86::MMX_V_SET0, X86::MMX_PUNPCKLDQrr, MVT::v8i8, MVT::v2i32);
- return Result;
-}
+ return N->isExactlyValue(+0.0);
-DISABLE_INLINE SDNode *Emit_312(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp0, N0);
-}
-SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(SDNode *N) {
-
- // Pattern: (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))
- // Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_loadi32(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
- N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_310(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
-
- // Pattern: (X86vzmovl:v4i32 (bitconvert:v4i32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if (N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_310(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
-
- // Pattern: (X86vzmovl:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if (N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_310(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (X86vzmovl:v4i32 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 45 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
}
+ case 110: { // Predicate_fpimm1
+ ConstantFPSDNode*N = cast<ConstantFPSDNode>(Node);
- // Pattern: (X86vzmovl:v4i32 (scalar_to_vector:v4i32 GR32:i32:$src))
- // Emits: (MOVZDI2PDIrr:v4i32 GR32:i32:$src)
- // Pattern complexity = 21 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_160(N, X86::MOVZDI2PDIrr, MVT::v4i32);
- return Result;
- }
- }
- }
+ return N->isExactlyValue(+1.0);
- // Pattern: (X86vzmovl:v4i32 VR128:v4i32:$src)
- // Emits: (MOVLPSrr:v4i32 (V_SET0:v16i8), VR128:v16i8:$src)
- // Pattern complexity = 18 cost = 2 size = 6
- if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_312(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4i32);
- return Result;
}
+ case 111: { // Predicate_fp32imm0
+ ConstantFPSDNode*N = cast<ConstantFPSDNode>(Node);
- CannotYetSelect(N);
- return NULL;
-}
+ return N->isExactlyValue(+0.0);
-SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(SDNode *N) {
-
- // Pattern: (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))
- // Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_loadi64(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
- N00.getValueType() == MVT::i64) {
- SDNode *Result = Emit_310(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
-
- // Pattern: (X86vzmovl:v2i64 (bitconvert:v2i64 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if (N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_310(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
-
- // Pattern: (X86vzmovl:v2i64 (bitconvert:v2i64 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MOVZPQILo2PQIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if (N00.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_310(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
}
+ case 112: { // Predicate_fpimmneg0
+ ConstantFPSDNode*N = cast<ConstantFPSDNode>(Node);
- // Pattern: (X86vzmovl:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MOVZPQILo2PQIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 45 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
+ return N->isExactlyValue(-0.0);
- // Pattern: (X86vzmovl:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 45 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
}
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (X86vzmovl:v2i64 (scalar_to_vector:v2i64 GR64:i64:$src))
- // Emits: (MOVZQI2PQIrr:v2i64 GR64:i64:$src)
- // Pattern complexity = 21 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getValueType() == MVT::i64) {
- SDNode *Result = Emit_160(N, X86::MOVZQI2PQIrr, MVT::v2i64);
- return Result;
- }
- }
- }
-
- // Pattern: (X86vzmovl:v2i64 VR128:v2i64:$src)
- // Emits: (MOVZPQILo2PQIrr:v2i64 VR128:v2i64:$src)
- // Pattern complexity = 18 cost = 1 size = 3
- SDNode *Result = Emit_72(N, X86::MOVZPQILo2PQIrr, MVT::v2i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
+ case 113: { // Predicate_fpimmneg1
+ ConstantFPSDNode*N = cast<ConstantFPSDNode>(Node);
-DISABLE_INLINE SDNode *Emit_313(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N->getOperand(0);
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
- return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp0, N00);
-}
-SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(SDNode *N) {
-
- // Pattern: (X86vzmovl:v4f32 (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>))
- // Emits: (MOVZSS2PSrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_loadf32(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
- N00.getValueType() == MVT::f32) {
- SDNode *Result = Emit_310(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
+ return N->isExactlyValue(-1.0);
- // Pattern: (X86vzmovl:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MOVZSS2PSrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
}
- if ((Subtarget->hasSSE1())) {
-
- // Pattern: (X86vzmovl:v4f32 (scalar_to_vector:v4f32 FR32:f32:$src))
- // Emits: (MOVLSS2PSrr:v4f32 (V_SET0:v16i8), FR32:f32:$src)
- // Pattern complexity = 21 cost = 2 size = 6
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getValueType() == MVT::f32) {
- SDNode *Result = Emit_313(N, X86::V_SET0, X86::MOVLSS2PSrr, MVT::v16i8, MVT::v4f32);
- return Result;
- }
- }
- }
-
- // Pattern: (X86vzmovl:v4f32 VR128:v4f32:$src)
- // Emits: (MOVLPSrr:v4f32 (V_SET0:v16i8), VR128:v16i8:$src)
- // Pattern complexity = 18 cost = 2 size = 6
- SDNode *Result = Emit_312(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4f32);
- return Result;
}
-
- CannotYetSelect(N);
- return NULL;
}
-SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(SDNode *N) {
-
- // Pattern: (X86vzmovl:v2f64 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))
- // Emits: (MOVZSD2PDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_loadf64(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
- N00.getValueType() == MVT::f64) {
- SDNode *Result = Emit_310(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86vzmovl:v2f64 (bitconvert:v2f64 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MOVZSD2PDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
- N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_310(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86vzmovl:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MOVZSD2PDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 45 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (X86vzmovl:v2f64 (scalar_to_vector:v2f64 FR64:f64:$src))
- // Emits: (MOVLSD2PDrr:v2f64 (V_SET0:v16i8), FR64:f64:$src)
- // Pattern complexity = 21 cost = 2 size = 6
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getValueType() == MVT::f64) {
- SDNode *Result = Emit_313(N, X86::V_SET0, X86::MOVLSD2PDrr, MVT::v16i8, MVT::v2f64);
- return Result;
- }
- }
- }
-
- // Pattern: (X86vzmovl:v2f64 VR128:v2f64:$src)
- // Emits: (MOVZPQILo2PQIrr:v2f64 VR128:v16i8:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_72(N, X86::MOVZPQILo2PQIrr, MVT::v2f64);
- return Result;
+bool CheckComplexPattern(SDNode *Root, SDValue N,
+ unsigned PatternNo, SmallVectorImpl<SDValue> &Result) {
+ switch (PatternNo) {
+ default: assert(0 && "Invalid pattern # in table?");
+ case 0:
+ Result.resize(Result.size()+5);
+ return SelectAddr(Root, N, Result[Result.size()-5], Result[Result.size()-4], Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 1:
+ Result.resize(Result.size()+6);
+ return SelectScalarSSELoad(Root, N, Result[Result.size()-6], Result[Result.size()-5], Result[Result.size()-4], Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 2:
+ Result.resize(Result.size()+6);
+ return SelectScalarSSELoad(Root, N, Result[Result.size()-6], Result[Result.size()-5], Result[Result.size()-4], Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 3:
+ Result.resize(Result.size()+4);
+ return SelectLEAAddr(Root, N, Result[Result.size()-4], Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 4:
+ Result.resize(Result.size()+4);
+ return SelectLEAAddr(Root, N, Result[Result.size()-4], Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 5:
+ Result.resize(Result.size()+4);
+ return SelectTLSADDRAddr(Root, N, Result[Result.size()-4], Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
+ case 6:
+ Result.resize(Result.size()+4);
+ return SelectTLSADDRAddr(Root, N, Result[Result.size()-4], Result[Result.size()-3], Result[Result.size()-2], Result[Result.size()-1]);
}
-
- CannotYetSelect(N);
- return NULL;
}
-SDNode *Select_X86ISD_Wrapper_i32(SDNode *N) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86Wrapper:i32 (tconstpool:i32):$dst)
- // Emits: (MOV32ri:i32 (tconstpool:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_72(N, X86::MOV32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i32 (tjumptable:i32):$dst)
- // Emits: (MOV32ri:i32 (tjumptable:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDNode *Result = Emit_72(N, X86::MOV32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i32 (tglobaltlsaddr:i32):$dst)
- // Emits: (MOV32ri:i32 (tglobaltlsaddr:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalTLSAddress) {
- SDNode *Result = Emit_72(N, X86::MOV32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i32 (tglobaladdr:i32):$dst)
- // Emits: (MOV32ri:i32 (tglobaladdr:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_72(N, X86::MOV32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i32 (texternalsym:i32):$dst)
- // Emits: (MOV32ri:i32 (texternalsym:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_72(N, X86::MOV32ri, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i32 (tblockaddress:i32):$dst)
- // Emits: (MOV32ri:i32 (tblockaddress:i32):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDNode *Result = Emit_72(N, X86::MOV32ri, MVT::i32);
- return Result;
- }
+SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
+ switch (XFormNo) {
+ default: assert(0 && "Invalid xform # in table?");
+ case 0: {
+ SDNode *N = V.getNode();
- CannotYetSelect(N);
- return NULL;
-}
+ return getI8Imm(X86::getShuffleSHUFImmediate(N));
-SDNode *Select_X86ISD_Wrapper_i64(SDNode *N) {
- if ((TM.getCodeModel() != CodeModel::Small &&TM.getCodeModel() != CodeModel::Kernel)) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86Wrapper:i64 (tconstpool:i64):$dst)
- // Emits: (MOV64ri:i64 (tconstpool:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_72(N, X86::MOV64ri, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i64 (tjumptable:i64):$dst)
- // Emits: (MOV64ri:i64 (tjumptable:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDNode *Result = Emit_72(N, X86::MOV64ri, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i64 (tglobaladdr:i64):$dst)
- // Emits: (MOV64ri:i64 (tglobaladdr:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_72(N, X86::MOV64ri, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i64 (texternalsym:i64):$dst)
- // Emits: (MOV64ri:i64 (texternalsym:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_72(N, X86::MOV64ri, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i64 (tblockaddress:i64):$dst)
- // Emits: (MOV64ri:i64 (tblockaddress:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDNode *Result = Emit_72(N, X86::MOV64ri, MVT::i64);
- return Result;
- }
- }
- if ((TM.getCodeModel() == CodeModel::Small)) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86Wrapper:i64 (tconstpool:i64):$dst)
- // Emits: (MOV64ri64i32:i64 (tconstpool:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_72(N, X86::MOV64ri64i32, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i64 (tjumptable:i64):$dst)
- // Emits: (MOV64ri64i32:i64 (tjumptable:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDNode *Result = Emit_72(N, X86::MOV64ri64i32, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i64 (tglobaladdr:i64):$dst)
- // Emits: (MOV64ri64i32:i64 (tglobaladdr:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_72(N, X86::MOV64ri64i32, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i64 (texternalsym:i64):$dst)
- // Emits: (MOV64ri64i32:i64 (texternalsym:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_72(N, X86::MOV64ri64i32, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i64 (tblockaddress:i64):$dst)
- // Emits: (MOV64ri64i32:i64 (tblockaddress:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDNode *Result = Emit_72(N, X86::MOV64ri64i32, MVT::i64);
- return Result;
- }
- }
- if ((TM.getCodeModel() == CodeModel::Kernel)) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86Wrapper:i64 (tconstpool:i64):$dst)
- // Emits: (MOV64ri32:i64 (tconstpool:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_72(N, X86::MOV64ri32, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i64 (tjumptable:i64):$dst)
- // Emits: (MOV64ri32:i64 (tjumptable:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
- SDNode *Result = Emit_72(N, X86::MOV64ri32, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i64 (tglobaladdr:i64):$dst)
- // Emits: (MOV64ri32:i64 (tglobaladdr:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_72(N, X86::MOV64ri32, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i64 (texternalsym:i64):$dst)
- // Emits: (MOV64ri32:i64 (texternalsym:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_72(N, X86::MOV64ri32, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86Wrapper:i64 (tblockaddress:i64):$dst)
- // Emits: (MOV64ri32:i64 (tblockaddress:i64):$dst)
- // Pattern complexity = 6 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
- SDNode *Result = Emit_72(N, X86::MOV64ri32, MVT::i64);
- return Result;
- }
}
+ case 1: {
+ SDNode *N = V.getNode();
- CannotYetSelect(N);
- return NULL;
-}
+ return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
-SDNode *Select_X86ISD_WrapperRIP_i64(SDNode *N) {
- SDValue CPTmpN_0;
- SDValue CPTmpN_1;
- SDValue CPTmpN_2;
- SDValue CPTmpN_3;
- if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
- SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
- return Result;
}
+ case 2: {
+ SDNode *N = V.getNode();
- CannotYetSelect(N);
- return NULL;
-}
+ return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
-SDNode *Select_X86ISD_XOR_i8(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86xor_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (XOR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::XOR8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86xor_flag:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1)
- // Emits: (XOR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi8(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::XOR8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (X86xor_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (XOR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_3(N, X86::XOR8ri, MVT::i8);
- return Result;
- }
}
+ case 3: {
+ SDNode *N = V.getNode();
- // Pattern: (X86xor_flag:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Emits: (XOR8rr:i8 GR8:i8:$src1, GR8:i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::XOR8rr, MVT::i8);
- return Result;
-}
+ return getI8Imm(X86::getShuffleSHUFImmediate(N));
-SDNode *Select_X86ISD_XOR_i16(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86xor_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (XOR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::XOR16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86xor_flag:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
- // Emits: (XOR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::XOR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86xor_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (XOR16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_5(N, X86::XOR16ri8, MVT::i16);
- return Result;
- }
-
- // Pattern: (X86xor_flag:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Emits: (XOR16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_5(N, X86::XOR16ri, MVT::i16);
- return Result;
- }
}
+ case 4: {
+ SDNode *N = V.getNode();
- // Pattern: (X86xor_flag:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Emits: (XOR16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::XOR16rr, MVT::i16);
- return Result;
-}
+ return getI8Imm(X86::getShufflePALIGNRImmediate(N));
-SDNode *Select_X86ISD_XOR_i32(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86xor_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (XOR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::XOR32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86xor_flag:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
- // Emits: (XOR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::XOR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86xor_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (XOR32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_8(N, X86::XOR32ri8, MVT::i32);
- return Result;
- }
-
- // Pattern: (X86xor_flag:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Emits: (XOR32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- SDNode *Result = Emit_8(N, X86::XOR32ri, MVT::i32);
- return Result;
- }
}
+ case 5: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (X86xor_flag:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Emits: (XOR32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::XOR32rr, MVT::i32);
- return Result;
-}
+ // Transformation function: imm >> 3
+ return getI32Imm(N->getZExtValue() >> 3);
-SDNode *Select_X86ISD_XOR_i64(SDNode *N) {
- {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86xor_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (XOR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::XOR64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86xor_flag:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1)
- // Emits: (XOR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_4(N, X86::XOR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86xor_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (XOR64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::XOR64ri8, MVT::i64);
- return Result;
- }
-
- // Pattern: (X86xor_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (XOR64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_12(N, X86::XOR64ri32, MVT::i64);
- return Result;
- }
- }
}
+ case 6: {
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
- // Pattern: (X86xor_flag:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Emits: (XOR64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_1(N, X86::XOR64rr, MVT::i64);
- return Result;
-}
+ // Transformation function: get the low 32 bits.
+ return getI32Imm((unsigned)N->getZExtValue());
-// The main instruction selector code.
-SDNode *SelectCode(SDNode *N) {
- MVT::SimpleValueType NVT = N->getValueType(0).getSimpleVT().SimpleTy;
- switch (N->getOpcode()) {
- default:
- assert(!N->isMachineOpcode() && "Node already selected!");
- break;
- case ISD::EntryToken: // These nodes remain the same.
- case ISD::BasicBlock:
- case ISD::Register:
- case ISD::HANDLENODE:
- case ISD::TargetConstant:
- case ISD::TargetConstantFP:
- case ISD::TargetConstantPool:
- case ISD::TargetFrameIndex:
- case ISD::TargetExternalSymbol:
- case ISD::TargetBlockAddress:
- case ISD::TargetJumpTable:
- case ISD::TargetGlobalTLSAddress:
- case ISD::TargetGlobalAddress:
- case ISD::TokenFactor:
- case ISD::CopyFromReg:
- case ISD::CopyToReg: {
- return NULL;
- }
- case ISD::AssertSext:
- case ISD::AssertZext: {
- ReplaceUses(SDValue(N, 0), N->getOperand(0));
- return NULL;
- }
- case ISD::INLINEASM: return Select_INLINEASM(N);
- case ISD::EH_LABEL: return Select_EH_LABEL(N);
- case ISD::UNDEF: return Select_UNDEF(N);
- case ISD::ADD: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_ADD_i8(N);
- case MVT::i16:
- return Select_ISD_ADD_i16(N);
- case MVT::i32:
- return Select_ISD_ADD_i32(N);
- case MVT::i64:
- return Select_ISD_ADD_i64(N);
- case MVT::v8i8:
- return Select_ISD_ADD_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_ADD_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_ADD_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_ADD_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_ADD_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_ADD_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_ADD_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_ADD_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ADDC: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_ADDC_i32(N);
- case MVT::i64:
- return Select_ISD_ADDC_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ADDE: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_ADDE_i8(N);
- case MVT::i16:
- return Select_ISD_ADDE_i16(N);
- case MVT::i32:
- return Select_ISD_ADDE_i32(N);
- case MVT::i64:
- return Select_ISD_ADDE_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::AND: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_AND_i8(N);
- case MVT::i16:
- return Select_ISD_AND_i16(N);
- case MVT::i32:
- return Select_ISD_AND_i32(N);
- case MVT::i64:
- return Select_ISD_AND_i64(N);
- case MVT::v1i64:
- return Select_ISD_AND_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_AND_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ANY_EXTEND: {
- switch (NVT) {
- case MVT::i16:
- return Select_ISD_ANY_EXTEND_i16(N);
- case MVT::i32:
- return Select_ISD_ANY_EXTEND_i32(N);
- case MVT::i64:
- return Select_ISD_ANY_EXTEND_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_ADD: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_ATOMIC_LOAD_ADD_i8(N);
- case MVT::i16:
- return Select_ISD_ATOMIC_LOAD_ADD_i16(N);
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_ADD_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_ADD_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_AND: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_ATOMIC_LOAD_AND_i8(N);
- case MVT::i16:
- return Select_ISD_ATOMIC_LOAD_AND_i16(N);
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_AND_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_AND_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_MAX: {
- switch (NVT) {
- case MVT::i16:
- return Select_ISD_ATOMIC_LOAD_MAX_i16(N);
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_MAX_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_MAX_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_MIN: {
- switch (NVT) {
- case MVT::i16:
- return Select_ISD_ATOMIC_LOAD_MIN_i16(N);
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_MIN_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_MIN_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_NAND: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_ATOMIC_LOAD_NAND_i8(N);
- case MVT::i16:
- return Select_ISD_ATOMIC_LOAD_NAND_i16(N);
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_NAND_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_NAND_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_OR: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_ATOMIC_LOAD_OR_i8(N);
- case MVT::i16:
- return Select_ISD_ATOMIC_LOAD_OR_i16(N);
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_OR_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_OR_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_UMAX: {
- switch (NVT) {
- case MVT::i16:
- return Select_ISD_ATOMIC_LOAD_UMAX_i16(N);
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_UMAX_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_UMAX_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_UMIN: {
- switch (NVT) {
- case MVT::i16:
- return Select_ISD_ATOMIC_LOAD_UMIN_i16(N);
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_UMIN_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_UMIN_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_LOAD_XOR: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_ATOMIC_LOAD_XOR_i8(N);
- case MVT::i16:
- return Select_ISD_ATOMIC_LOAD_XOR_i16(N);
- case MVT::i32:
- return Select_ISD_ATOMIC_LOAD_XOR_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_LOAD_XOR_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ATOMIC_SWAP: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_ATOMIC_SWAP_i8(N);
- case MVT::i16:
- return Select_ISD_ATOMIC_SWAP_i16(N);
- case MVT::i32:
- return Select_ISD_ATOMIC_SWAP_i32(N);
- case MVT::i64:
- return Select_ISD_ATOMIC_SWAP_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::BIT_CONVERT: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_BIT_CONVERT_i32(N);
- case MVT::i64:
- return Select_ISD_BIT_CONVERT_i64(N);
- case MVT::f32:
- return Select_ISD_BIT_CONVERT_f32(N);
- case MVT::f64:
- return Select_ISD_BIT_CONVERT_f64(N);
- case MVT::v8i8:
- return Select_ISD_BIT_CONVERT_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_BIT_CONVERT_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_BIT_CONVERT_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_BIT_CONVERT_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_BIT_CONVERT_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_BIT_CONVERT_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_BIT_CONVERT_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_BIT_CONVERT_v2i64(N);
- case MVT::v2f32:
- return Select_ISD_BIT_CONVERT_v2f32(N);
- case MVT::v4f32:
- return Select_ISD_BIT_CONVERT_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_BIT_CONVERT_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::BR: {
- return Select_ISD_BR(N);
- break;
- }
- case ISD::BRIND: {
- return Select_ISD_BRIND(N);
- break;
- }
- case ISD::BSWAP: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_BSWAP_i32(N);
- case MVT::i64:
- return Select_ISD_BSWAP_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::BUILD_VECTOR: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ISD_BUILD_VECTOR_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_BUILD_VECTOR_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_BUILD_VECTOR_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_BUILD_VECTOR_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_BUILD_VECTOR_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_BUILD_VECTOR_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_BUILD_VECTOR_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_BUILD_VECTOR_v2i64(N);
- case MVT::v4f32:
- return Select_ISD_BUILD_VECTOR_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_BUILD_VECTOR_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::CALLSEQ_END: {
- return Select_ISD_CALLSEQ_END(N);
- break;
- }
- case ISD::CALLSEQ_START: {
- return Select_ISD_CALLSEQ_START(N);
- break;
- }
- case ISD::Constant: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_Constant_i8(N);
- case MVT::i16:
- return Select_ISD_Constant_i16(N);
- case MVT::i32:
- return Select_ISD_Constant_i32(N);
- case MVT::i64:
- return Select_ISD_Constant_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ConstantFP: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_ConstantFP_f32(N);
- case MVT::f64:
- return Select_ISD_ConstantFP_f64(N);
- case MVT::f80:
- return Select_ISD_ConstantFP_f80(N);
- default:
- break;
- }
- break;
- }
- case ISD::EXTRACT_VECTOR_ELT: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_EXTRACT_VECTOR_ELT_i32(N);
- case MVT::i64:
- return Select_ISD_EXTRACT_VECTOR_ELT_i64(N);
- case MVT::f32:
- return Select_ISD_EXTRACT_VECTOR_ELT_f32(N);
- case MVT::f64:
- return Select_ISD_EXTRACT_VECTOR_ELT_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FABS: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FABS_f32(N);
- case MVT::f64:
- return Select_ISD_FABS_f64(N);
- case MVT::f80:
- return Select_ISD_FABS_f80(N);
- default:
- break;
- }
- break;
- }
- case ISD::FADD: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FADD_f32(N);
- case MVT::f64:
- return Select_ISD_FADD_f64(N);
- case MVT::f80:
- return Select_ISD_FADD_f80(N);
- case MVT::v4f32:
- return Select_ISD_FADD_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_FADD_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FCOS: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FCOS_f32(N);
- case MVT::f64:
- return Select_ISD_FCOS_f64(N);
- case MVT::f80:
- return Select_ISD_FCOS_f80(N);
- default:
- break;
- }
- break;
- }
- case ISD::FDIV: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FDIV_f32(N);
- case MVT::f64:
- return Select_ISD_FDIV_f64(N);
- case MVT::f80:
- return Select_ISD_FDIV_f80(N);
- case MVT::v4f32:
- return Select_ISD_FDIV_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_FDIV_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FMUL: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FMUL_f32(N);
- case MVT::f64:
- return Select_ISD_FMUL_f64(N);
- case MVT::f80:
- return Select_ISD_FMUL_f80(N);
- case MVT::v4f32:
- return Select_ISD_FMUL_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_FMUL_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FNEG: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FNEG_f32(N);
- case MVT::f64:
- return Select_ISD_FNEG_f64(N);
- case MVT::f80:
- return Select_ISD_FNEG_f80(N);
- default:
- break;
- }
- break;
- }
- case ISD::FP_EXTEND: {
- switch (NVT) {
- case MVT::f64:
- return Select_ISD_FP_EXTEND_f64(N);
- case MVT::f80:
- return Select_ISD_FP_EXTEND_f80(N);
- default:
- break;
- }
- break;
- }
- case ISD::FP_ROUND: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FP_ROUND_f32(N);
- case MVT::f64:
- return Select_ISD_FP_ROUND_f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FP_TO_SINT: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_FP_TO_SINT_i32(N);
- case MVT::i64:
- return Select_ISD_FP_TO_SINT_i64(N);
- case MVT::v2i32:
- return Select_ISD_FP_TO_SINT_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_FP_TO_SINT_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::FSIN: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FSIN_f32(N);
- case MVT::f64:
- return Select_ISD_FSIN_f64(N);
- case MVT::f80:
- return Select_ISD_FSIN_f80(N);
- default:
- break;
- }
- break;
- }
- case ISD::FSQRT: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FSQRT_f32(N);
- case MVT::f64:
- return Select_ISD_FSQRT_f64(N);
- case MVT::f80:
- return Select_ISD_FSQRT_f80(N);
- case MVT::v4f32:
- return Select_ISD_FSQRT_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_FSQRT_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FSUB: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_FSUB_f32(N);
- case MVT::f64:
- return Select_ISD_FSUB_f64(N);
- case MVT::f80:
- return Select_ISD_FSUB_f80(N);
- case MVT::v4f32:
- return Select_ISD_FSUB_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_FSUB_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::FrameIndex: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_FrameIndex_i32(N);
- case MVT::i64:
- return Select_ISD_FrameIndex_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::INSERT_VECTOR_ELT: {
- switch (NVT) {
- case MVT::v4i32:
- return Select_ISD_INSERT_VECTOR_ELT_v4i32(N);
- case MVT::v2i64:
- return Select_ISD_INSERT_VECTOR_ELT_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::INTRINSIC_VOID: {
- return Select_ISD_INTRINSIC_VOID(N);
- break;
- }
- case ISD::INTRINSIC_WO_CHAIN: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_INTRINSIC_WO_CHAIN_i32(N);
- case MVT::i64:
- return Select_ISD_INTRINSIC_WO_CHAIN_i64(N);
- case MVT::v8i8:
- return Select_ISD_INTRINSIC_WO_CHAIN_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_INTRINSIC_WO_CHAIN_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_INTRINSIC_WO_CHAIN_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_INTRINSIC_WO_CHAIN_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_INTRINSIC_WO_CHAIN_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_INTRINSIC_WO_CHAIN_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_INTRINSIC_WO_CHAIN_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_INTRINSIC_WO_CHAIN_v2i64(N);
- case MVT::v4f32:
- return Select_ISD_INTRINSIC_WO_CHAIN_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_INTRINSIC_WO_CHAIN_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::INTRINSIC_W_CHAIN: {
- switch (NVT) {
- case MVT::v16i8:
- return Select_ISD_INTRINSIC_W_CHAIN_v16i8(N);
- case MVT::v2i64:
- return Select_ISD_INTRINSIC_W_CHAIN_v2i64(N);
- case MVT::v4f32:
- return Select_ISD_INTRINSIC_W_CHAIN_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_INTRINSIC_W_CHAIN_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::LOAD: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_LOAD_i8(N);
- case MVT::i16:
- return Select_ISD_LOAD_i16(N);
- case MVT::i32:
- return Select_ISD_LOAD_i32(N);
- case MVT::i64:
- return Select_ISD_LOAD_i64(N);
- case MVT::f32:
- return Select_ISD_LOAD_f32(N);
- case MVT::f64:
- return Select_ISD_LOAD_f64(N);
- case MVT::f80:
- return Select_ISD_LOAD_f80(N);
- case MVT::v4i32:
- return Select_ISD_LOAD_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_LOAD_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_LOAD_v2i64(N);
- case MVT::v4f32:
- return Select_ISD_LOAD_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_LOAD_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::MEMBARRIER: {
- return Select_ISD_MEMBARRIER(N);
- break;
- }
- case ISD::MUL: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_MUL_i8(N);
- case MVT::i16:
- return Select_ISD_MUL_i16(N);
- case MVT::i32:
- return Select_ISD_MUL_i32(N);
- case MVT::i64:
- return Select_ISD_MUL_i64(N);
- case MVT::v16i8:
- return Select_ISD_MUL_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_MUL_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_MUL_v8i16(N);
- case MVT::v4i32:
- return Select_ISD_MUL_v4i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::OR: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_OR_i8(N);
- case MVT::i16:
- return Select_ISD_OR_i16(N);
- case MVT::i32:
- return Select_ISD_OR_i32(N);
- case MVT::i64:
- return Select_ISD_OR_i64(N);
- case MVT::v1i64:
- return Select_ISD_OR_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_OR_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::PREFETCH: {
- return Select_ISD_PREFETCH(N);
- break;
- }
- case ISD::ROTL: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_ROTL_i8(N);
- case MVT::i16:
- return Select_ISD_ROTL_i16(N);
- case MVT::i32:
- return Select_ISD_ROTL_i32(N);
- case MVT::i64:
- return Select_ISD_ROTL_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ROTR: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_ROTR_i8(N);
- case MVT::i16:
- return Select_ISD_ROTR_i16(N);
- case MVT::i32:
- return Select_ISD_ROTR_i32(N);
- case MVT::i64:
- return Select_ISD_ROTR_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SCALAR_TO_VECTOR: {
- switch (NVT) {
- case MVT::v2i32:
- return Select_ISD_SCALAR_TO_VECTOR_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_SCALAR_TO_VECTOR_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_SCALAR_TO_VECTOR_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_SCALAR_TO_VECTOR_v2i64(N);
- case MVT::v4f32:
- return Select_ISD_SCALAR_TO_VECTOR_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_SCALAR_TO_VECTOR_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SHL: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_SHL_i8(N);
- case MVT::i16:
- return Select_ISD_SHL_i16(N);
- case MVT::i32:
- return Select_ISD_SHL_i32(N);
- case MVT::i64:
- return Select_ISD_SHL_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SIGN_EXTEND: {
- switch (NVT) {
- case MVT::i16:
- return Select_ISD_SIGN_EXTEND_i16(N);
- case MVT::i32:
- return Select_ISD_SIGN_EXTEND_i32(N);
- case MVT::i64:
- return Select_ISD_SIGN_EXTEND_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SIGN_EXTEND_INREG: {
- switch (NVT) {
- case MVT::i16:
- return Select_ISD_SIGN_EXTEND_INREG_i16(N);
- case MVT::i32:
- return Select_ISD_SIGN_EXTEND_INREG_i32(N);
- case MVT::i64:
- return Select_ISD_SIGN_EXTEND_INREG_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SINT_TO_FP: {
- switch (NVT) {
- case MVT::f32:
- return Select_ISD_SINT_TO_FP_f32(N);
- case MVT::f64:
- return Select_ISD_SINT_TO_FP_f64(N);
- case MVT::v4f32:
- return Select_ISD_SINT_TO_FP_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_SINT_TO_FP_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SRA: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_SRA_i8(N);
- case MVT::i16:
- return Select_ISD_SRA_i16(N);
- case MVT::i32:
- return Select_ISD_SRA_i32(N);
- case MVT::i64:
- return Select_ISD_SRA_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SRL: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_SRL_i8(N);
- case MVT::i16:
- return Select_ISD_SRL_i16(N);
- case MVT::i32:
- return Select_ISD_SRL_i32(N);
- case MVT::i64:
- return Select_ISD_SRL_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::STORE: {
- return Select_ISD_STORE(N);
- break;
- }
- case ISD::SUB: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_SUB_i8(N);
- case MVT::i16:
- return Select_ISD_SUB_i16(N);
- case MVT::i32:
- return Select_ISD_SUB_i32(N);
- case MVT::i64:
- return Select_ISD_SUB_i64(N);
- case MVT::v8i8:
- return Select_ISD_SUB_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_SUB_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_SUB_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_SUB_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_SUB_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_SUB_v4i32(N);
- case MVT::v1i64:
- return Select_ISD_SUB_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_SUB_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SUBC: {
- switch (NVT) {
- case MVT::i32:
- return Select_ISD_SUBC_i32(N);
- case MVT::i64:
- return Select_ISD_SUBC_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::SUBE: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_SUBE_i8(N);
- case MVT::i16:
- return Select_ISD_SUBE_i16(N);
- case MVT::i32:
- return Select_ISD_SUBE_i32(N);
- case MVT::i64:
- return Select_ISD_SUBE_i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::TRAP: {
- return Select_ISD_TRAP(N);
- break;
- }
- case ISD::TRUNCATE: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_TRUNCATE_i8(N);
- case MVT::i16:
- return Select_ISD_TRUNCATE_i16(N);
- case MVT::i32:
- return Select_ISD_TRUNCATE_i32(N);
- default:
- break;
- }
- break;
- }
- case ISD::VECTOR_SHUFFLE: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_ISD_VECTOR_SHUFFLE_v8i8(N);
- case MVT::v16i8:
- return Select_ISD_VECTOR_SHUFFLE_v16i8(N);
- case MVT::v4i16:
- return Select_ISD_VECTOR_SHUFFLE_v4i16(N);
- case MVT::v8i16:
- return Select_ISD_VECTOR_SHUFFLE_v8i16(N);
- case MVT::v2i32:
- return Select_ISD_VECTOR_SHUFFLE_v2i32(N);
- case MVT::v4i32:
- return Select_ISD_VECTOR_SHUFFLE_v4i32(N);
- case MVT::v2i64:
- return Select_ISD_VECTOR_SHUFFLE_v2i64(N);
- case MVT::v4f32:
- return Select_ISD_VECTOR_SHUFFLE_v4f32(N);
- case MVT::v2f64:
- return Select_ISD_VECTOR_SHUFFLE_v2f64(N);
- default:
- break;
- }
- break;
- }
- case ISD::XOR: {
- switch (NVT) {
- case MVT::i8:
- return Select_ISD_XOR_i8(N);
- case MVT::i16:
- return Select_ISD_XOR_i16(N);
- case MVT::i32:
- return Select_ISD_XOR_i32(N);
- case MVT::i64:
- return Select_ISD_XOR_i64(N);
- case MVT::v1i64:
- return Select_ISD_XOR_v1i64(N);
- case MVT::v2i64:
- return Select_ISD_XOR_v2i64(N);
- default:
- break;
- }
- break;
- }
- case ISD::ZERO_EXTEND: {
- switch (NVT) {
- case MVT::i16:
- return Select_ISD_ZERO_EXTEND_i16(N);
- case MVT::i32:
- return Select_ISD_ZERO_EXTEND_i32(N);
- case MVT::i64:
- return Select_ISD_ZERO_EXTEND_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::ADD: {
- switch (NVT) {
- case MVT::i8:
- return Select_X86ISD_ADD_i8(N);
- case MVT::i16:
- return Select_X86ISD_ADD_i16(N);
- case MVT::i32:
- return Select_X86ISD_ADD_i32(N);
- case MVT::i64:
- return Select_X86ISD_ADD_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::AND: {
- switch (NVT) {
- case MVT::i8:
- return Select_X86ISD_AND_i8(N);
- case MVT::i16:
- return Select_X86ISD_AND_i16(N);
- case MVT::i32:
- return Select_X86ISD_AND_i32(N);
- case MVT::i64:
- return Select_X86ISD_AND_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::BRCOND: {
- return Select_X86ISD_BRCOND(N);
- break;
- }
- case X86ISD::BSF: {
- switch (NVT) {
- case MVT::i16:
- return Select_X86ISD_BSF_i16(N);
- case MVT::i32:
- return Select_X86ISD_BSF_i32(N);
- case MVT::i64:
- return Select_X86ISD_BSF_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::BSR: {
- switch (NVT) {
- case MVT::i16:
- return Select_X86ISD_BSR_i16(N);
- case MVT::i32:
- return Select_X86ISD_BSR_i32(N);
- case MVT::i64:
- return Select_X86ISD_BSR_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::BT: {
- return Select_X86ISD_BT(N);
- break;
- }
- case X86ISD::CALL: {
- return Select_X86ISD_CALL(N);
- break;
- }
- case X86ISD::CMOV: {
- switch (NVT) {
- case MVT::i8:
- return Select_X86ISD_CMOV_i8(N);
- case MVT::i16:
- return Select_X86ISD_CMOV_i16(N);
- case MVT::i32:
- return Select_X86ISD_CMOV_i32(N);
- case MVT::i64:
- return Select_X86ISD_CMOV_i64(N);
- case MVT::f32:
- return Select_X86ISD_CMOV_f32(N);
- case MVT::f64:
- return Select_X86ISD_CMOV_f64(N);
- case MVT::f80:
- return Select_X86ISD_CMOV_f80(N);
- case MVT::v1i64:
- return Select_X86ISD_CMOV_v1i64(N);
- case MVT::v2i64:
- return Select_X86ISD_CMOV_v2i64(N);
- case MVT::v4f32:
- return Select_X86ISD_CMOV_v4f32(N);
- case MVT::v2f64:
- return Select_X86ISD_CMOV_v2f64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::CMP: {
- return Select_X86ISD_CMP(N);
- break;
- }
- case X86ISD::CMPPD: {
- switch (NVT) {
- case MVT::v2i64:
- return Select_X86ISD_CMPPD_v2i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::CMPPS: {
- switch (NVT) {
- case MVT::v4i32:
- return Select_X86ISD_CMPPS_v4i32(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::COMI: {
- return Select_X86ISD_COMI(N);
- break;
- }
- case X86ISD::DEC: {
- switch (NVT) {
- case MVT::i8:
- return Select_X86ISD_DEC_i8(N);
- case MVT::i16:
- return Select_X86ISD_DEC_i16(N);
- case MVT::i32:
- return Select_X86ISD_DEC_i32(N);
- case MVT::i64:
- return Select_X86ISD_DEC_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::EH_RETURN: {
- return Select_X86ISD_EH_RETURN(N);
- break;
- }
- case X86ISD::FAND: {
- switch (NVT) {
- case MVT::f32:
- return Select_X86ISD_FAND_f32(N);
- case MVT::f64:
- return Select_X86ISD_FAND_f64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::FILD: {
- switch (NVT) {
- case MVT::f32:
- return Select_X86ISD_FILD_f32(N);
- case MVT::f64:
- return Select_X86ISD_FILD_f64(N);
- case MVT::f80:
- return Select_X86ISD_FILD_f80(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::FILD_FLAG: {
- switch (NVT) {
- case MVT::f64:
- return Select_X86ISD_FILD_FLAG_f64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::FLD: {
- switch (NVT) {
- case MVT::f32:
- return Select_X86ISD_FLD_f32(N);
- case MVT::f64:
- return Select_X86ISD_FLD_f64(N);
- case MVT::f80:
- return Select_X86ISD_FLD_f80(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::FMAX: {
- switch (NVT) {
- case MVT::f32:
- return Select_X86ISD_FMAX_f32(N);
- case MVT::f64:
- return Select_X86ISD_FMAX_f64(N);
- case MVT::v4f32:
- return Select_X86ISD_FMAX_v4f32(N);
- case MVT::v2f64:
- return Select_X86ISD_FMAX_v2f64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::FMIN: {
- switch (NVT) {
- case MVT::f32:
- return Select_X86ISD_FMIN_f32(N);
- case MVT::f64:
- return Select_X86ISD_FMIN_f64(N);
- case MVT::v4f32:
- return Select_X86ISD_FMIN_v4f32(N);
- case MVT::v2f64:
- return Select_X86ISD_FMIN_v2f64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::FNSTCW16m: {
- return Select_X86ISD_FNSTCW16m(N);
- break;
- }
- case X86ISD::FOR: {
- switch (NVT) {
- case MVT::f32:
- return Select_X86ISD_FOR_f32(N);
- case MVT::f64:
- return Select_X86ISD_FOR_f64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::FP_TO_INT16_IN_MEM: {
- return Select_X86ISD_FP_TO_INT16_IN_MEM(N);
- break;
- }
- case X86ISD::FP_TO_INT32_IN_MEM: {
- return Select_X86ISD_FP_TO_INT32_IN_MEM(N);
- break;
- }
- case X86ISD::FP_TO_INT64_IN_MEM: {
- return Select_X86ISD_FP_TO_INT64_IN_MEM(N);
- break;
- }
- case X86ISD::FRCP: {
- switch (NVT) {
- case MVT::f32:
- return Select_X86ISD_FRCP_f32(N);
- case MVT::v4f32:
- return Select_X86ISD_FRCP_v4f32(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::FRSQRT: {
- switch (NVT) {
- case MVT::f32:
- return Select_X86ISD_FRSQRT_f32(N);
- case MVT::v4f32:
- return Select_X86ISD_FRSQRT_v4f32(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::FSRL: {
- switch (NVT) {
- case MVT::v2f64:
- return Select_X86ISD_FSRL_v2f64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::FST: {
- return Select_X86ISD_FST(N);
- break;
- }
- case X86ISD::FXOR: {
- switch (NVT) {
- case MVT::f32:
- return Select_X86ISD_FXOR_f32(N);
- case MVT::f64:
- return Select_X86ISD_FXOR_f64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::INC: {
- switch (NVT) {
- case MVT::i8:
- return Select_X86ISD_INC_i8(N);
- case MVT::i16:
- return Select_X86ISD_INC_i16(N);
- case MVT::i32:
- return Select_X86ISD_INC_i32(N);
- case MVT::i64:
- return Select_X86ISD_INC_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::INSERTPS: {
- switch (NVT) {
- case MVT::v4f32:
- return Select_X86ISD_INSERTPS_v4f32(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::LCMPXCHG8_DAG: {
- return Select_X86ISD_LCMPXCHG8_DAG(N);
- break;
- }
- case X86ISD::LCMPXCHG_DAG: {
- return Select_X86ISD_LCMPXCHG_DAG(N);
- break;
- }
- case X86ISD::MOVQ2DQ: {
- switch (NVT) {
- case MVT::v2i64:
- return Select_X86ISD_MOVQ2DQ_v2i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::MUL_IMM: {
- switch (NVT) {
- case MVT::i32:
- return Select_X86ISD_MUL_IMM_i32(N);
- case MVT::i64:
- return Select_X86ISD_MUL_IMM_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::OR: {
- switch (NVT) {
- case MVT::i8:
- return Select_X86ISD_OR_i8(N);
- case MVT::i16:
- return Select_X86ISD_OR_i16(N);
- case MVT::i32:
- return Select_X86ISD_OR_i32(N);
- case MVT::i64:
- return Select_X86ISD_OR_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PCMPEQB: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_X86ISD_PCMPEQB_v8i8(N);
- case MVT::v16i8:
- return Select_X86ISD_PCMPEQB_v16i8(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PCMPEQD: {
- switch (NVT) {
- case MVT::v2i32:
- return Select_X86ISD_PCMPEQD_v2i32(N);
- case MVT::v4i32:
- return Select_X86ISD_PCMPEQD_v4i32(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PCMPEQQ: {
- switch (NVT) {
- case MVT::v2i64:
- return Select_X86ISD_PCMPEQQ_v2i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PCMPEQW: {
- switch (NVT) {
- case MVT::v4i16:
- return Select_X86ISD_PCMPEQW_v4i16(N);
- case MVT::v8i16:
- return Select_X86ISD_PCMPEQW_v8i16(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PCMPGTB: {
- switch (NVT) {
- case MVT::v8i8:
- return Select_X86ISD_PCMPGTB_v8i8(N);
- case MVT::v16i8:
- return Select_X86ISD_PCMPGTB_v16i8(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PCMPGTD: {
- switch (NVT) {
- case MVT::v2i32:
- return Select_X86ISD_PCMPGTD_v2i32(N);
- case MVT::v4i32:
- return Select_X86ISD_PCMPGTD_v4i32(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PCMPGTQ: {
- switch (NVT) {
- case MVT::v2i64:
- return Select_X86ISD_PCMPGTQ_v2i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PCMPGTW: {
- switch (NVT) {
- case MVT::v4i16:
- return Select_X86ISD_PCMPGTW_v4i16(N);
- case MVT::v8i16:
- return Select_X86ISD_PCMPGTW_v8i16(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PEXTRB: {
- switch (NVT) {
- case MVT::i32:
- return Select_X86ISD_PEXTRB_i32(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PEXTRW: {
- switch (NVT) {
- case MVT::i32:
- return Select_X86ISD_PEXTRW_i32(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PINSRB: {
- switch (NVT) {
- case MVT::v16i8:
- return Select_X86ISD_PINSRB_v16i8(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PINSRW: {
- switch (NVT) {
- case MVT::v4i16:
- return Select_X86ISD_PINSRW_v4i16(N);
- case MVT::v8i16:
- return Select_X86ISD_PINSRW_v8i16(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PSHUFB: {
- switch (NVT) {
- case MVT::v16i8:
- return Select_X86ISD_PSHUFB_v16i8(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::PTEST: {
- return Select_X86ISD_PTEST(N);
- break;
- }
- case X86ISD::RDTSC_DAG: {
- return Select_X86ISD_RDTSC_DAG(N);
- break;
- }
- case X86ISD::REP_MOVS: {
- return Select_X86ISD_REP_MOVS(N);
- break;
- }
- case X86ISD::REP_STOS: {
- return Select_X86ISD_REP_STOS(N);
- break;
- }
- case X86ISD::RET_FLAG: {
- return Select_X86ISD_RET_FLAG(N);
- break;
- }
- case X86ISD::SETCC: {
- switch (NVT) {
- case MVT::i8:
- return Select_X86ISD_SETCC_i8(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::SETCC_CARRY: {
- switch (NVT) {
- case MVT::i8:
- return Select_X86ISD_SETCC_CARRY_i8(N);
- case MVT::i16:
- return Select_X86ISD_SETCC_CARRY_i16(N);
- case MVT::i32:
- return Select_X86ISD_SETCC_CARRY_i32(N);
- case MVT::i64:
- return Select_X86ISD_SETCC_CARRY_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::SHLD: {
- switch (NVT) {
- case MVT::i16:
- return Select_X86ISD_SHLD_i16(N);
- case MVT::i32:
- return Select_X86ISD_SHLD_i32(N);
- case MVT::i64:
- return Select_X86ISD_SHLD_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::SHRD: {
- switch (NVT) {
- case MVT::i16:
- return Select_X86ISD_SHRD_i16(N);
- case MVT::i32:
- return Select_X86ISD_SHRD_i32(N);
- case MVT::i64:
- return Select_X86ISD_SHRD_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::SMUL: {
- switch (NVT) {
- case MVT::i16:
- return Select_X86ISD_SMUL_i16(N);
- case MVT::i32:
- return Select_X86ISD_SMUL_i32(N);
- case MVT::i64:
- return Select_X86ISD_SMUL_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::SUB: {
- switch (NVT) {
- case MVT::i8:
- return Select_X86ISD_SUB_i8(N);
- case MVT::i16:
- return Select_X86ISD_SUB_i16(N);
- case MVT::i32:
- return Select_X86ISD_SUB_i32(N);
- case MVT::i64:
- return Select_X86ISD_SUB_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::TC_RETURN: {
- return Select_X86ISD_TC_RETURN(N);
- break;
- }
- case X86ISD::TLSADDR: {
- return Select_X86ISD_TLSADDR(N);
- break;
- }
- case X86ISD::UCOMI: {
- return Select_X86ISD_UCOMI(N);
- break;
- }
- case X86ISD::VASTART_SAVE_XMM_REGS: {
- return Select_X86ISD_VASTART_SAVE_XMM_REGS(N);
- break;
- }
- case X86ISD::VSHL: {
- switch (NVT) {
- case MVT::v1i64:
- return Select_X86ISD_VSHL_v1i64(N);
- case MVT::v2i64:
- return Select_X86ISD_VSHL_v2i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::VSRL: {
- switch (NVT) {
- case MVT::v1i64:
- return Select_X86ISD_VSRL_v1i64(N);
- case MVT::v2i64:
- return Select_X86ISD_VSRL_v2i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::VZEXT_LOAD: {
- switch (NVT) {
- case MVT::v2i64:
- return Select_X86ISD_VZEXT_LOAD_v2i64(N);
- case MVT::v2f64:
- return Select_X86ISD_VZEXT_LOAD_v2f64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::VZEXT_MOVL: {
- switch (NVT) {
- case MVT::v2i32:
- return Select_X86ISD_VZEXT_MOVL_v2i32(N);
- case MVT::v4i32:
- return Select_X86ISD_VZEXT_MOVL_v4i32(N);
- case MVT::v2i64:
- return Select_X86ISD_VZEXT_MOVL_v2i64(N);
- case MVT::v4f32:
- return Select_X86ISD_VZEXT_MOVL_v4f32(N);
- case MVT::v2f64:
- return Select_X86ISD_VZEXT_MOVL_v2f64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::Wrapper: {
- switch (NVT) {
- case MVT::i32:
- return Select_X86ISD_Wrapper_i32(N);
- case MVT::i64:
- return Select_X86ISD_Wrapper_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::WrapperRIP: {
- switch (NVT) {
- case MVT::i64:
- return Select_X86ISD_WrapperRIP_i64(N);
- default:
- break;
- }
- break;
- }
- case X86ISD::XOR: {
- switch (NVT) {
- case MVT::i8:
- return Select_X86ISD_XOR_i8(N);
- case MVT::i16:
- return Select_X86ISD_XOR_i16(N);
- case MVT::i32:
- return Select_X86ISD_XOR_i32(N);
- case MVT::i64:
- return Select_X86ISD_XOR_i64(N);
- default:
- break;
- }
- break;
}
- } // end of big switch.
-
- if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
- N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
- N->getOpcode() != ISD::INTRINSIC_VOID) {
- CannotYetSelect(N);
- } else {
- CannotYetSelectIntrinsic(N);
}
- return NULL;
}
diff --git a/libclamav/c++/X86GenFastISel.inc b/libclamav/c++/X86GenFastISel.inc
index f1bea70..dc171fc 100644
--- a/libclamav/c++/X86GenFastISel.inc
+++ b/libclamav/c++/X86GenFastISel.inc
@@ -704,30 +704,10 @@ switch (RetVT.SimpleTy) {
}
}
-unsigned FastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0) {
- if (RetVT.SimpleTy != MVT::v4f32)
- return 0;
- if ((Subtarget->hasSSE1())) {
- return FastEmitInst_r(X86::MOVSS2PSrr, X86::VR128RegisterClass, Op0);
- }
- return 0;
-}
-
-unsigned FastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(MVT RetVT, unsigned Op0) {
- if (RetVT.SimpleTy != MVT::v2f64)
- return 0;
- if ((Subtarget->hasSSE2())) {
- return FastEmitInst_r(X86::MOVSD2PDrr, X86::VR128RegisterClass, Op0);
- }
- return 0;
-}
-
unsigned FastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) {
switch (VT.SimpleTy) {
case MVT::i32: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
case MVT::i64: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(RetVT, Op0);
- case MVT::f32: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
- case MVT::f64: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(RetVT, Op0);
default: return 0;
}
}
diff --git a/libclamav/c++/X86GenInstrInfo.inc b/libclamav/c++/X86GenInstrInfo.inc
index a352932..98269ea 100644
--- a/libclamav/c++/X86GenInstrInfo.inc
+++ b/libclamav/c++/X86GenInstrInfo.inc
@@ -35,7 +35,7 @@ static const unsigned ImplicitList18[] = { X86::EAX, X86::EDX, X86::EFLAGS, 0 };
static const unsigned ImplicitList19[] = { X86::RAX, X86::RDX, 0 };
static const unsigned ImplicitList20[] = { X86::AX, X86::DX, 0 };
static const unsigned ImplicitList21[] = { X86::AX, X86::DX, X86::EFLAGS, 0 };
-static const unsigned ImplicitList22[] = { X86::AL, X86::AH, X86::EFLAGS, 0 };
+static const unsigned ImplicitList22[] = { X86::AL, X86::EFLAGS, X86::AX, 0 };
static const TargetRegisterClass* Barriers7[] = { &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, NULL };
static const unsigned ImplicitList23[] = { X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 0 };
static const unsigned ImplicitList24[] = { X86::ST0, 0 };
@@ -237,46 +237,42 @@ static const TargetOperandInfo OperandInfo161[] = { { X86::GR8_NOREXRegClassID,
static const TargetOperandInfo OperandInfo162[] = { { X86::GR8_NOREXRegClassID, 0, 0 }, { X86::GR8_NOREXRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo163[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo164[] = { { X86::VR128RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo165[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo166[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo167[] = { { X86::FR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo168[] = { { X86::FR32RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo169[] = { { X86::VR128RegClassID, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo170[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo171[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo172[] = { { X86::VR128RegClassID, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo173[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo174[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo175[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo176[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo177[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo178[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo179[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo180[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo181[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo182[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo183[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo184[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo185[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo186[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo187[] = { { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo188[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo189[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo190[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo191[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo192[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo193[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo194[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo195[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo196[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo197[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo198[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo199[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo200[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo201[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo202[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo203[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo204[] = { { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo165[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo166[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo167[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo168[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::FR32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo169[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo170[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo171[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo172[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo173[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo174[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo175[] = { { X86::GR32_NOREXRegClassID, 0, 0 }, { X86::GR8RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo176[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo177[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo178[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo179[] = { { X86::RFP80RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo180[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo181[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP80RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo182[] = { { X86::VR64RegClassID, 0, 0 }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::VR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo183[] = { { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo184[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo185[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo186[] = { { X86::GR64RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo187[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo188[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo189[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo190[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo191[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo192[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo193[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo194[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo195[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo196[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo197[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo198[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo199[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo200[] = { { X86::VR128RegClassID, 0, 0 }, };
static const TargetInstrDesc X86Insts[] = {
{ 0, 0, 0, 0, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #0 = PHI
@@ -288,7 +284,7 @@ static const TargetInstrDesc X86Insts[] = {
{ 6, 3, 1, 0, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo76 }, // Inst #6 = EXTRACT_SUBREG
{ 7, 4, 1, 0, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo116 }, // Inst #7 = INSERT_SUBREG
{ 8, 1, 1, 0, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #8 = IMPLICIT_DEF
- { 9, 4, 1, 0, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo200 }, // Inst #9 = SUBREG_TO_REG
+ { 9, 4, 1, 0, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo196 }, // Inst #9 = SUBREG_TO_REG
{ 10, 3, 1, 0, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo76 }, // Inst #10 = COPY_TO_REGCLASS
{ 11, 0, 0, 0, "DBG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DBG_VALUE
{ 12, 0, 0, 0, "ABS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(225<<24), NULL, NULL, NULL, 0 }, // Inst #12 = ABS_F
@@ -1627,1189 +1623,1181 @@ static const TargetInstrDesc X86Insts[] = {
{ 1345, 3, 1, 0, "MOVLHPSrr", 0, 0|5|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1345 = MOVLHPSrr
{ 1346, 6, 0, 0, "MOVLPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1346 = MOVLPDmr
{ 1347, 7, 1, 0, "MOVLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1347 = MOVLPDrm
- { 1348, 3, 1, 0, "MOVLPDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1348 = MOVLPDrr
- { 1349, 6, 0, 0, "MOVLPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1349 = MOVLPSmr
- { 1350, 7, 1, 0, "MOVLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1350 = MOVLPSrm
- { 1351, 3, 1, 0, "MOVLPSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1351 = MOVLPSrr
- { 1352, 6, 0, 0, "MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1352 = MOVLQ128mr
- { 1353, 3, 1, 0, "MOVLSD2PDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1353 = MOVLSD2PDrr
- { 1354, 3, 1, 0, "MOVLSS2PSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1354 = MOVLSS2PSrr
- { 1355, 2, 1, 0, "MOVMSKPDrr", 0, 0|5|(1<<6)|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1355 = MOVMSKPDrr
- { 1356, 2, 1, 0, "MOVMSKPSrr", 0, 0|5|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1356 = MOVMSKPSrr
- { 1357, 6, 1, 0, "MOVNTDQArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1357 = MOVNTDQArm
- { 1358, 6, 0, 0, "MOVNTDQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1358 = MOVNTDQmr
- { 1359, 6, 0, 0, "MOVNTImr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1359 = MOVNTImr
- { 1360, 6, 0, 0, "MOVNTPDmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1360 = MOVNTPDmr
- { 1361, 6, 0, 0, "MOVNTPSmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1361 = MOVNTPSmr
- { 1362, 2, 1, 0, "MOVPC32r", 0|(1<<TID::NotDuplicable), 0|(4<<13)|(232<<24), ImplicitList2, NULL, NULL, OperandInfo55 }, // Inst #1362 = MOVPC32r
- { 1363, 6, 0, 0, "MOVPD2SDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1363 = MOVPD2SDmr
- { 1364, 2, 1, 0, "MOVPD2SDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1364 = MOVPD2SDrr
+ { 1348, 6, 0, 0, "MOVLPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1348 = MOVLPSmr
+ { 1349, 7, 1, 0, "MOVLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1349 = MOVLPSrm
+ { 1350, 6, 0, 0, "MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1350 = MOVLQ128mr
+ { 1351, 2, 1, 0, "MOVMSKPDrr", 0, 0|5|(1<<6)|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1351 = MOVMSKPDrr
+ { 1352, 2, 1, 0, "MOVMSKPSrr", 0, 0|5|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1352 = MOVMSKPSrr
+ { 1353, 6, 1, 0, "MOVNTDQArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1353 = MOVNTDQArm
+ { 1354, 6, 0, 0, "MOVNTDQ_64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1354 = MOVNTDQ_64mr
+ { 1355, 6, 0, 0, "MOVNTDQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1355 = MOVNTDQmr
+ { 1356, 6, 0, 0, "MOVNTDQmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1356 = MOVNTDQmr_Int
+ { 1357, 6, 0, 0, "MOVNTI_64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(195<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1357 = MOVNTI_64mr
+ { 1358, 6, 0, 0, "MOVNTImr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1358 = MOVNTImr
+ { 1359, 6, 0, 0, "MOVNTImr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1359 = MOVNTImr_Int
+ { 1360, 6, 0, 0, "MOVNTPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1360 = MOVNTPDmr
+ { 1361, 6, 0, 0, "MOVNTPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1361 = MOVNTPDmr_Int
+ { 1362, 6, 0, 0, "MOVNTPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1362 = MOVNTPSmr
+ { 1363, 6, 0, 0, "MOVNTPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1363 = MOVNTPSmr_Int
+ { 1364, 2, 1, 0, "MOVPC32r", 0|(1<<TID::NotDuplicable), 0|(4<<13)|(232<<24), ImplicitList2, NULL, NULL, OperandInfo55 }, // Inst #1364 = MOVPC32r
{ 1365, 6, 0, 0, "MOVPDI2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1365 = MOVPDI2DImr
{ 1366, 2, 1, 0, "MOVPDI2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1366 = MOVPDI2DIrr
{ 1367, 6, 0, 0, "MOVPQI2QImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1367 = MOVPQI2QImr
{ 1368, 2, 1, 0, "MOVPQIto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1368 = MOVPQIto64rr
- { 1369, 6, 0, 0, "MOVPS2SSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1369 = MOVPS2SSmr
- { 1370, 2, 1, 0, "MOVPS2SSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1370 = MOVPS2SSrr
- { 1371, 6, 1, 0, "MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1371 = MOVQI2PQIrm
- { 1372, 2, 1, 0, "MOVQxrxr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1372 = MOVQxrxr
- { 1373, 0, 0, 0, "MOVSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(164<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1373 = MOVSB
- { 1374, 0, 0, 0, "MOVSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(165<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1374 = MOVSD
- { 1375, 6, 1, 0, "MOVSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1375 = MOVSD2PDrm
- { 1376, 2, 1, 0, "MOVSD2PDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1376 = MOVSD2PDrr
- { 1377, 6, 0, 0, "MOVSDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1377 = MOVSDmr
- { 1378, 6, 1, 0, "MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1378 = MOVSDrm
- { 1379, 2, 1, 0, "MOVSDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #1379 = MOVSDrr
- { 1380, 6, 0, 0, "MOVSDto64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1380 = MOVSDto64mr
- { 1381, 2, 1, 0, "MOVSDto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #1381 = MOVSDto64rr
- { 1382, 6, 1, 0, "MOVSHDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1382 = MOVSHDUPrm
- { 1383, 2, 1, 0, "MOVSHDUPrr", 0, 0|5|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1383 = MOVSHDUPrr
- { 1384, 6, 1, 0, "MOVSLDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1384 = MOVSLDUPrm
- { 1385, 2, 1, 0, "MOVSLDUPrr", 0, 0|5|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1385 = MOVSLDUPrr
- { 1386, 6, 0, 0, "MOVSS2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1386 = MOVSS2DImr
- { 1387, 2, 1, 0, "MOVSS2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #1387 = MOVSS2DIrr
- { 1388, 6, 1, 0, "MOVSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1388 = MOVSS2PSrm
- { 1389, 2, 1, 0, "MOVSS2PSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1389 = MOVSS2PSrr
- { 1390, 6, 0, 0, "MOVSSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1390 = MOVSSmr
- { 1391, 6, 1, 0, "MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1391 = MOVSSrm
- { 1392, 2, 1, 0, "MOVSSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1392 = MOVSSrr
- { 1393, 0, 0, 0, "MOVSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(165<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1393 = MOVSW
- { 1394, 6, 1, 0, "MOVSX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1394 = MOVSX16rm8
- { 1395, 6, 1, 0, "MOVSX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1395 = MOVSX16rm8W
- { 1396, 2, 1, 0, "MOVSX16rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1396 = MOVSX16rr8
- { 1397, 2, 1, 0, "MOVSX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1397 = MOVSX16rr8W
- { 1398, 6, 1, 0, "MOVSX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1398 = MOVSX32rm16
- { 1399, 6, 1, 0, "MOVSX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1399 = MOVSX32rm8
- { 1400, 2, 1, 0, "MOVSX32rr16", 0, 0|5|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1400 = MOVSX32rr16
- { 1401, 2, 1, 0, "MOVSX32rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1401 = MOVSX32rr8
- { 1402, 6, 1, 0, "MOVSX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1402 = MOVSX64rm16
- { 1403, 6, 1, 0, "MOVSX64rm32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1403 = MOVSX64rm32
- { 1404, 6, 1, 0, "MOVSX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1404 = MOVSX64rm8
- { 1405, 2, 1, 0, "MOVSX64rr16", 0, 0|5|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1405 = MOVSX64rr16
- { 1406, 2, 1, 0, "MOVSX64rr32", 0, 0|5|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1406 = MOVSX64rr32
- { 1407, 2, 1, 0, "MOVSX64rr8", 0, 0|5|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1407 = MOVSX64rr8
- { 1408, 6, 0, 0, "MOVUPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1408 = MOVUPDmr
- { 1409, 6, 0, 0, "MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1409 = MOVUPDmr_Int
- { 1410, 6, 1, 0, "MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1410 = MOVUPDrm
- { 1411, 6, 1, 0, "MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1411 = MOVUPDrm_Int
- { 1412, 2, 1, 0, "MOVUPDrr", 0, 0|5|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1412 = MOVUPDrr
- { 1413, 6, 0, 0, "MOVUPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1413 = MOVUPSmr
- { 1414, 6, 0, 0, "MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1414 = MOVUPSmr_Int
- { 1415, 6, 1, 0, "MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1415 = MOVUPSrm
- { 1416, 6, 1, 0, "MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1416 = MOVUPSrm_Int
- { 1417, 2, 1, 0, "MOVUPSrr", 0, 0|5|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1417 = MOVUPSrr
- { 1418, 6, 1, 0, "MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1418 = MOVZDI2PDIrm
- { 1419, 2, 1, 0, "MOVZDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1419 = MOVZDI2PDIrr
- { 1420, 6, 1, 0, "MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1420 = MOVZPQILo2PQIrm
- { 1421, 2, 1, 0, "MOVZPQILo2PQIrr", 0, 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1421 = MOVZPQILo2PQIrr
- { 1422, 6, 1, 0, "MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1422 = MOVZQI2PQIrm
- { 1423, 2, 1, 0, "MOVZQI2PQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1423 = MOVZQI2PQIrr
- { 1424, 6, 1, 0, "MOVZSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1424 = MOVZSD2PDrm
- { 1425, 6, 1, 0, "MOVZSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1425 = MOVZSS2PSrm
- { 1426, 6, 1, 0, "MOVZX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1426 = MOVZX16rm8
- { 1427, 6, 1, 0, "MOVZX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1427 = MOVZX16rm8W
- { 1428, 2, 1, 0, "MOVZX16rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1428 = MOVZX16rr8
- { 1429, 2, 1, 0, "MOVZX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1429 = MOVZX16rr8W
- { 1430, 6, 1, 0, "MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1430 = MOVZX32_NOREXrm8
- { 1431, 2, 1, 0, "MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1431 = MOVZX32_NOREXrr8
- { 1432, 6, 1, 0, "MOVZX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1432 = MOVZX32rm16
- { 1433, 6, 1, 0, "MOVZX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1433 = MOVZX32rm8
- { 1434, 2, 1, 0, "MOVZX32rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1434 = MOVZX32rr16
- { 1435, 2, 1, 0, "MOVZX32rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1435 = MOVZX32rr8
- { 1436, 6, 1, 0, "MOVZX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1436 = MOVZX64rm16
- { 1437, 6, 1, 0, "MOVZX64rm16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1437 = MOVZX64rm16_Q
- { 1438, 6, 1, 0, "MOVZX64rm32", 0|(1<<TID::MayLoad), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1438 = MOVZX64rm32
- { 1439, 6, 1, 0, "MOVZX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1439 = MOVZX64rm8
- { 1440, 6, 1, 0, "MOVZX64rm8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1440 = MOVZX64rm8_Q
- { 1441, 2, 1, 0, "MOVZX64rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1441 = MOVZX64rr16
- { 1442, 2, 1, 0, "MOVZX64rr16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1442 = MOVZX64rr16_Q
- { 1443, 2, 1, 0, "MOVZX64rr32", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1443 = MOVZX64rr32
- { 1444, 2, 1, 0, "MOVZX64rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1444 = MOVZX64rr8
- { 1445, 2, 1, 0, "MOVZX64rr8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1445 = MOVZX64rr8_Q
- { 1446, 2, 1, 0, "MOV_Fp3232", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #1446 = MOV_Fp3232
- { 1447, 2, 1, 0, "MOV_Fp3264", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo180 }, // Inst #1447 = MOV_Fp3264
- { 1448, 2, 1, 0, "MOV_Fp3280", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo181 }, // Inst #1448 = MOV_Fp3280
- { 1449, 2, 1, 0, "MOV_Fp6432", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo182 }, // Inst #1449 = MOV_Fp6432
- { 1450, 2, 1, 0, "MOV_Fp6464", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #1450 = MOV_Fp6464
- { 1451, 2, 1, 0, "MOV_Fp6480", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo183 }, // Inst #1451 = MOV_Fp6480
- { 1452, 2, 1, 0, "MOV_Fp8032", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo184 }, // Inst #1452 = MOV_Fp8032
- { 1453, 2, 1, 0, "MOV_Fp8064", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo185 }, // Inst #1453 = MOV_Fp8064
- { 1454, 2, 1, 0, "MOV_Fp8080", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #1454 = MOV_Fp8080
- { 1455, 8, 1, 0, "MPSADBWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1455 = MPSADBWrmi
- { 1456, 4, 1, 0, "MPSADBWrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1456 = MPSADBWrri
- { 1457, 5, 0, 0, "MUL16m", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #1457 = MUL16m
- { 1458, 1, 0, 0, "MUL16r", 0, 0|20|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #1458 = MUL16r
- { 1459, 5, 0, 0, "MUL32m", 0|(1<<TID::MayLoad), 0|28|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #1459 = MUL32m
- { 1460, 1, 0, 0, "MUL32r", 0, 0|20|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #1460 = MUL32r
- { 1461, 5, 0, 0, "MUL64m", 0|(1<<TID::MayLoad), 0|28|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #1461 = MUL64m
- { 1462, 1, 0, 0, "MUL64r", 0, 0|20|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #1462 = MUL64r
- { 1463, 5, 0, 0, "MUL8m", 0|(1<<TID::MayLoad), 0|28|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #1463 = MUL8m
- { 1464, 1, 0, 0, "MUL8r", 0, 0|20|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #1464 = MUL8r
- { 1465, 7, 1, 0, "MULPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1465 = MULPDrm
- { 1466, 3, 1, 0, "MULPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1466 = MULPDrr
- { 1467, 7, 1, 0, "MULPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1467 = MULPSrm
- { 1468, 3, 1, 0, "MULPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1468 = MULPSrr
- { 1469, 7, 1, 0, "MULSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1469 = MULSDrm
- { 1470, 7, 1, 0, "MULSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1470 = MULSDrm_Int
- { 1471, 3, 1, 0, "MULSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1471 = MULSDrr
- { 1472, 3, 1, 0, "MULSDrr_Int", 0, 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1472 = MULSDrr_Int
- { 1473, 7, 1, 0, "MULSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1473 = MULSSrm
- { 1474, 7, 1, 0, "MULSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1474 = MULSSrm_Int
- { 1475, 3, 1, 0, "MULSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1475 = MULSSrr
- { 1476, 3, 1, 0, "MULSSrr_Int", 0, 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1476 = MULSSrr_Int
- { 1477, 5, 0, 0, "MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1477 = MUL_F32m
- { 1478, 5, 0, 0, "MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1478 = MUL_F64m
- { 1479, 5, 0, 0, "MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1479 = MUL_FI16m
- { 1480, 5, 0, 0, "MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1480 = MUL_FI32m
- { 1481, 1, 0, 0, "MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1481 = MUL_FPrST0
- { 1482, 1, 0, 0, "MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1482 = MUL_FST0r
- { 1483, 3, 1, 0, "MUL_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1483 = MUL_Fp32
- { 1484, 7, 1, 0, "MUL_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1484 = MUL_Fp32m
- { 1485, 3, 1, 0, "MUL_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1485 = MUL_Fp64
- { 1486, 7, 1, 0, "MUL_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1486 = MUL_Fp64m
- { 1487, 7, 1, 0, "MUL_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1487 = MUL_Fp64m32
- { 1488, 3, 1, 0, "MUL_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1488 = MUL_Fp80
- { 1489, 7, 1, 0, "MUL_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1489 = MUL_Fp80m32
- { 1490, 7, 1, 0, "MUL_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1490 = MUL_Fp80m64
- { 1491, 7, 1, 0, "MUL_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1491 = MUL_FpI16m32
- { 1492, 7, 1, 0, "MUL_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1492 = MUL_FpI16m64
- { 1493, 7, 1, 0, "MUL_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1493 = MUL_FpI16m80
- { 1494, 7, 1, 0, "MUL_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1494 = MUL_FpI32m32
- { 1495, 7, 1, 0, "MUL_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1495 = MUL_FpI32m64
- { 1496, 7, 1, 0, "MUL_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1496 = MUL_FpI32m80
- { 1497, 1, 0, 0, "MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1497 = MUL_FrST0
- { 1498, 0, 0, 0, "MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|38|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1498 = MWAIT
- { 1499, 5, 0, 0, "NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1499 = NEG16m
- { 1500, 2, 1, 0, "NEG16r", 0, 0|19|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1500 = NEG16r
- { 1501, 5, 0, 0, "NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1501 = NEG32m
- { 1502, 2, 1, 0, "NEG32r", 0, 0|19|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1502 = NEG32r
- { 1503, 5, 0, 0, "NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1503 = NEG64m
- { 1504, 2, 1, 0, "NEG64r", 0, 0|19|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1504 = NEG64r
- { 1505, 5, 0, 0, "NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1505 = NEG8m
- { 1506, 2, 1, 0, "NEG8r", 0, 0|19|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1506 = NEG8r
- { 1507, 0, 0, 0, "NOOP", 0, 0|1|(144<<24), NULL, NULL, NULL, 0 }, // Inst #1507 = NOOP
- { 1508, 5, 0, 0, "NOOPL", 0, 0|24|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1508 = NOOPL
- { 1509, 5, 0, 0, "NOOPW", 0, 0|24|(1<<6)|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1509 = NOOPW
- { 1510, 5, 0, 0, "NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1510 = NOT16m
- { 1511, 2, 1, 0, "NOT16r", 0, 0|18|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo91 }, // Inst #1511 = NOT16r
- { 1512, 5, 0, 0, "NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1512 = NOT32m
- { 1513, 2, 1, 0, "NOT32r", 0, 0|18|(247<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #1513 = NOT32r
- { 1514, 5, 0, 0, "NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1514 = NOT64m
- { 1515, 2, 1, 0, "NOT64r", 0, 0|18|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #1515 = NOT64r
- { 1516, 5, 0, 0, "NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(246<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1516 = NOT8m
- { 1517, 2, 1, 0, "NOT8r", 0, 0|18|(246<<24), NULL, NULL, NULL, OperandInfo92 }, // Inst #1517 = NOT8r
- { 1518, 1, 0, 0, "OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1518 = OR16i16
- { 1519, 6, 0, 0, "OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1519 = OR16mi
- { 1520, 6, 0, 0, "OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1520 = OR16mi8
- { 1521, 6, 0, 0, "OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1521 = OR16mr
- { 1522, 3, 1, 0, "OR16ri", 0, 0|17|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1522 = OR16ri
- { 1523, 3, 1, 0, "OR16ri8", 0, 0|17|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1523 = OR16ri8
- { 1524, 7, 1, 0, "OR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1524 = OR16rm
- { 1525, 3, 1, 0, "OR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1525 = OR16rr
- { 1526, 3, 1, 0, "OR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1526 = OR16rr_REV
- { 1527, 1, 0, 0, "OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1527 = OR32i32
- { 1528, 6, 0, 0, "OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1528 = OR32mi
- { 1529, 6, 0, 0, "OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1529 = OR32mi8
- { 1530, 6, 0, 0, "OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1530 = OR32mr
- { 1531, 3, 1, 0, "OR32ri", 0, 0|17|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1531 = OR32ri
- { 1532, 3, 1, 0, "OR32ri8", 0, 0|17|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1532 = OR32ri8
- { 1533, 7, 1, 0, "OR32rm", 0|(1<<TID::MayLoad), 0|6|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1533 = OR32rm
- { 1534, 3, 1, 0, "OR32rr", 0|(1<<TID::Commutable), 0|3|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1534 = OR32rr
- { 1535, 3, 1, 0, "OR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1535 = OR32rr_REV
- { 1536, 1, 0, 0, "OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1536 = OR64i32
- { 1537, 6, 0, 0, "OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1537 = OR64mi32
- { 1538, 6, 0, 0, "OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1538 = OR64mi8
- { 1539, 6, 0, 0, "OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1539 = OR64mr
- { 1540, 3, 1, 0, "OR64ri32", 0, 0|17|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1540 = OR64ri32
- { 1541, 3, 1, 0, "OR64ri8", 0, 0|17|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1541 = OR64ri8
- { 1542, 7, 1, 0, "OR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1542 = OR64rm
- { 1543, 3, 1, 0, "OR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1543 = OR64rr
- { 1544, 3, 1, 0, "OR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1544 = OR64rr_REV
- { 1545, 1, 0, 0, "OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(12<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1545 = OR8i8
- { 1546, 6, 0, 0, "OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1546 = OR8mi
- { 1547, 6, 0, 0, "OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1547 = OR8mr
- { 1548, 3, 1, 0, "OR8ri", 0, 0|17|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1548 = OR8ri
- { 1549, 7, 1, 0, "OR8rm", 0|(1<<TID::MayLoad), 0|6|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1549 = OR8rm
- { 1550, 3, 1, 0, "OR8rr", 0|(1<<TID::Commutable), 0|3|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1550 = OR8rr
- { 1551, 3, 1, 0, "OR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1551 = OR8rr_REV
- { 1552, 7, 1, 0, "ORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1552 = ORPDrm
- { 1553, 3, 1, 0, "ORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1553 = ORPDrr
- { 1554, 7, 1, 0, "ORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1554 = ORPSrm
- { 1555, 3, 1, 0, "ORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1555 = ORPSrr
- { 1556, 1, 0, 0, "OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(231<<24), ImplicitList12, NULL, NULL, OperandInfo5 }, // Inst #1556 = OUT16ir
- { 1557, 0, 0, 0, "OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(239<<24), ImplicitList39, NULL, NULL, 0 }, // Inst #1557 = OUT16rr
- { 1558, 1, 0, 0, "OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(231<<24), ImplicitList13, NULL, NULL, OperandInfo5 }, // Inst #1558 = OUT32ir
- { 1559, 0, 0, 0, "OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(239<<24), ImplicitList40, NULL, NULL, 0 }, // Inst #1559 = OUT32rr
- { 1560, 1, 0, 0, "OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(230<<24), ImplicitList11, NULL, NULL, OperandInfo5 }, // Inst #1560 = OUT8ir
- { 1561, 0, 0, 0, "OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(238<<24), ImplicitList41, NULL, NULL, 0 }, // Inst #1561 = OUT8rr
- { 1562, 0, 0, 0, "OUTSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(110<<24), NULL, NULL, NULL, 0 }, // Inst #1562 = OUTSB
- { 1563, 0, 0, 0, "OUTSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1563 = OUTSD
- { 1564, 0, 0, 0, "OUTSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1564 = OUTSW
- { 1565, 6, 1, 0, "PABSBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1565 = PABSBrm128
- { 1566, 6, 1, 0, "PABSBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1566 = PABSBrm64
- { 1567, 2, 1, 0, "PABSBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1567 = PABSBrr128
- { 1568, 2, 1, 0, "PABSBrr64", 0, 0|5|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1568 = PABSBrr64
- { 1569, 6, 1, 0, "PABSDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1569 = PABSDrm128
- { 1570, 6, 1, 0, "PABSDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1570 = PABSDrm64
- { 1571, 2, 1, 0, "PABSDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1571 = PABSDrr128
- { 1572, 2, 1, 0, "PABSDrr64", 0, 0|5|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1572 = PABSDrr64
- { 1573, 6, 1, 0, "PABSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1573 = PABSWrm128
- { 1574, 6, 1, 0, "PABSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1574 = PABSWrm64
- { 1575, 2, 1, 0, "PABSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1575 = PABSWrr128
- { 1576, 2, 1, 0, "PABSWrr64", 0, 0|5|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1576 = PABSWrr64
- { 1577, 7, 1, 0, "PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1577 = PACKSSDWrm
- { 1578, 3, 1, 0, "PACKSSDWrr", 0, 0|5|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1578 = PACKSSDWrr
- { 1579, 7, 1, 0, "PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1579 = PACKSSWBrm
- { 1580, 3, 1, 0, "PACKSSWBrr", 0, 0|5|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1580 = PACKSSWBrr
- { 1581, 7, 1, 0, "PACKUSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1581 = PACKUSDWrm
- { 1582, 3, 1, 0, "PACKUSDWrr", 0, 0|5|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1582 = PACKUSDWrr
- { 1583, 7, 1, 0, "PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1583 = PACKUSWBrm
- { 1584, 3, 1, 0, "PACKUSWBrr", 0, 0|5|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1584 = PACKUSWBrr
- { 1585, 7, 1, 0, "PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1585 = PADDBrm
- { 1586, 3, 1, 0, "PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1586 = PADDBrr
- { 1587, 7, 1, 0, "PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1587 = PADDDrm
- { 1588, 3, 1, 0, "PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1588 = PADDDrr
- { 1589, 7, 1, 0, "PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1589 = PADDQrm
- { 1590, 3, 1, 0, "PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1590 = PADDQrr
- { 1591, 7, 1, 0, "PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1591 = PADDSBrm
- { 1592, 3, 1, 0, "PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1592 = PADDSBrr
- { 1593, 7, 1, 0, "PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1593 = PADDSWrm
- { 1594, 3, 1, 0, "PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1594 = PADDSWrr
- { 1595, 7, 1, 0, "PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1595 = PADDUSBrm
- { 1596, 3, 1, 0, "PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1596 = PADDUSBrr
- { 1597, 7, 1, 0, "PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1597 = PADDUSWrm
- { 1598, 3, 1, 0, "PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1598 = PADDUSWrr
- { 1599, 7, 1, 0, "PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1599 = PADDWrm
- { 1600, 3, 1, 0, "PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1600 = PADDWrr
- { 1601, 8, 1, 0, "PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1601 = PALIGNR128rm
- { 1602, 4, 1, 0, "PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1602 = PALIGNR128rr
- { 1603, 8, 1, 0, "PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1603 = PALIGNR64rm
- { 1604, 4, 1, 0, "PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo186 }, // Inst #1604 = PALIGNR64rr
- { 1605, 7, 1, 0, "PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1605 = PANDNrm
- { 1606, 3, 1, 0, "PANDNrr", 0, 0|5|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1606 = PANDNrr
- { 1607, 7, 1, 0, "PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1607 = PANDrm
- { 1608, 3, 1, 0, "PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1608 = PANDrr
- { 1609, 7, 1, 0, "PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1609 = PAVGBrm
- { 1610, 3, 1, 0, "PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1610 = PAVGBrr
- { 1611, 7, 1, 0, "PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1611 = PAVGWrm
- { 1612, 3, 1, 0, "PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1612 = PAVGWrr
- { 1613, 7, 1, 0, "PBLENDVBrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #1613 = PBLENDVBrm0
- { 1614, 3, 1, 0, "PBLENDVBrr0", 0, 0|5|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #1614 = PBLENDVBrr0
- { 1615, 8, 1, 0, "PBLENDWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1615 = PBLENDWrmi
- { 1616, 4, 1, 0, "PBLENDWrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1616 = PBLENDWrri
- { 1617, 7, 1, 0, "PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1617 = PCMPEQBrm
- { 1618, 3, 1, 0, "PCMPEQBrr", 0, 0|5|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1618 = PCMPEQBrr
- { 1619, 7, 1, 0, "PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1619 = PCMPEQDrm
- { 1620, 3, 1, 0, "PCMPEQDrr", 0, 0|5|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1620 = PCMPEQDrr
- { 1621, 7, 1, 0, "PCMPEQQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1621 = PCMPEQQrm
- { 1622, 3, 1, 0, "PCMPEQQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1622 = PCMPEQQrr
- { 1623, 7, 1, 0, "PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1623 = PCMPEQWrm
- { 1624, 3, 1, 0, "PCMPEQWrr", 0, 0|5|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1624 = PCMPEQWrr
- { 1625, 7, 0, 0, "PCMPESTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1625 = PCMPESTRIArm
- { 1626, 3, 0, 0, "PCMPESTRIArr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1626 = PCMPESTRIArr
- { 1627, 7, 0, 0, "PCMPESTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1627 = PCMPESTRICrm
- { 1628, 3, 0, 0, "PCMPESTRICrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1628 = PCMPESTRICrr
- { 1629, 7, 0, 0, "PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1629 = PCMPESTRIOrm
- { 1630, 3, 0, 0, "PCMPESTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1630 = PCMPESTRIOrr
- { 1631, 7, 0, 0, "PCMPESTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1631 = PCMPESTRISrm
- { 1632, 3, 0, 0, "PCMPESTRISrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1632 = PCMPESTRISrr
- { 1633, 7, 0, 0, "PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1633 = PCMPESTRIZrm
- { 1634, 3, 0, 0, "PCMPESTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1634 = PCMPESTRIZrr
- { 1635, 7, 0, 0, "PCMPESTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1635 = PCMPESTRIrm
- { 1636, 3, 0, 0, "PCMPESTRIrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1636 = PCMPESTRIrr
- { 1637, 8, 1, 0, "PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1637 = PCMPESTRM128MEM
- { 1638, 4, 1, 0, "PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1638 = PCMPESTRM128REG
- { 1639, 7, 0, 0, "PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList43, Barriers1, OperandInfo187 }, // Inst #1639 = PCMPESTRM128rm
- { 1640, 3, 0, 0, "PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList43, Barriers1, OperandInfo188 }, // Inst #1640 = PCMPESTRM128rr
- { 1641, 7, 1, 0, "PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1641 = PCMPGTBrm
- { 1642, 3, 1, 0, "PCMPGTBrr", 0, 0|5|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1642 = PCMPGTBrr
- { 1643, 7, 1, 0, "PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1643 = PCMPGTDrm
- { 1644, 3, 1, 0, "PCMPGTDrr", 0, 0|5|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1644 = PCMPGTDrr
- { 1645, 7, 1, 0, "PCMPGTQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1645 = PCMPGTQrm
- { 1646, 3, 1, 0, "PCMPGTQrr", 0, 0|5|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1646 = PCMPGTQrr
- { 1647, 7, 1, 0, "PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1647 = PCMPGTWrm
- { 1648, 3, 1, 0, "PCMPGTWrr", 0, 0|5|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1648 = PCMPGTWrr
- { 1649, 7, 0, 0, "PCMPISTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1649 = PCMPISTRIArm
- { 1650, 3, 0, 0, "PCMPISTRIArr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1650 = PCMPISTRIArr
- { 1651, 7, 0, 0, "PCMPISTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1651 = PCMPISTRICrm
- { 1652, 3, 0, 0, "PCMPISTRICrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1652 = PCMPISTRICrr
- { 1653, 7, 0, 0, "PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1653 = PCMPISTRIOrm
- { 1654, 3, 0, 0, "PCMPISTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1654 = PCMPISTRIOrr
- { 1655, 7, 0, 0, "PCMPISTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1655 = PCMPISTRISrm
- { 1656, 3, 0, 0, "PCMPISTRISrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1656 = PCMPISTRISrr
- { 1657, 7, 0, 0, "PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1657 = PCMPISTRIZrm
- { 1658, 3, 0, 0, "PCMPISTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1658 = PCMPISTRIZrr
- { 1659, 7, 0, 0, "PCMPISTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1659 = PCMPISTRIrm
- { 1660, 3, 0, 0, "PCMPISTRIrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1660 = PCMPISTRIrr
- { 1661, 8, 1, 0, "PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1661 = PCMPISTRM128MEM
- { 1662, 4, 1, 0, "PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1662 = PCMPISTRM128REG
- { 1663, 7, 0, 0, "PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList43, Barriers1, OperandInfo187 }, // Inst #1663 = PCMPISTRM128rm
- { 1664, 3, 0, 0, "PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList43, Barriers1, OperandInfo188 }, // Inst #1664 = PCMPISTRM128rr
- { 1665, 7, 0, 0, "PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1665 = PEXTRBmr
- { 1666, 3, 1, 0, "PEXTRBrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1666 = PEXTRBrr
- { 1667, 7, 0, 0, "PEXTRDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1667 = PEXTRDmr
- { 1668, 3, 1, 0, "PEXTRDrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1668 = PEXTRDrr
- { 1669, 7, 0, 0, "PEXTRQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1669 = PEXTRQmr
- { 1670, 3, 1, 0, "PEXTRQrr", 0, 0|3|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo190 }, // Inst #1670 = PEXTRQrr
- { 1671, 7, 0, 0, "PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(21<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1671 = PEXTRWmr
- { 1672, 3, 1, 0, "PEXTRWri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1672 = PEXTRWri
- { 1673, 7, 1, 0, "PHADDDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1673 = PHADDDrm128
- { 1674, 7, 1, 0, "PHADDDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1674 = PHADDDrm64
- { 1675, 3, 1, 0, "PHADDDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1675 = PHADDDrr128
- { 1676, 3, 1, 0, "PHADDDrr64", 0, 0|5|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1676 = PHADDDrr64
- { 1677, 7, 1, 0, "PHADDSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1677 = PHADDSWrm128
- { 1678, 7, 1, 0, "PHADDSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1678 = PHADDSWrm64
- { 1679, 3, 1, 0, "PHADDSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1679 = PHADDSWrr128
- { 1680, 3, 1, 0, "PHADDSWrr64", 0, 0|5|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1680 = PHADDSWrr64
- { 1681, 7, 1, 0, "PHADDWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1681 = PHADDWrm128
- { 1682, 7, 1, 0, "PHADDWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1682 = PHADDWrm64
- { 1683, 3, 1, 0, "PHADDWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1683 = PHADDWrr128
- { 1684, 3, 1, 0, "PHADDWrr64", 0, 0|5|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1684 = PHADDWrr64
- { 1685, 6, 1, 0, "PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1685 = PHMINPOSUWrm128
- { 1686, 2, 1, 0, "PHMINPOSUWrr128", 0, 0|5|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1686 = PHMINPOSUWrr128
- { 1687, 7, 1, 0, "PHSUBDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1687 = PHSUBDrm128
- { 1688, 7, 1, 0, "PHSUBDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1688 = PHSUBDrm64
- { 1689, 3, 1, 0, "PHSUBDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1689 = PHSUBDrr128
- { 1690, 3, 1, 0, "PHSUBDrr64", 0, 0|5|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1690 = PHSUBDrr64
- { 1691, 7, 1, 0, "PHSUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1691 = PHSUBSWrm128
- { 1692, 7, 1, 0, "PHSUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1692 = PHSUBSWrm64
- { 1693, 3, 1, 0, "PHSUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1693 = PHSUBSWrr128
- { 1694, 3, 1, 0, "PHSUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1694 = PHSUBSWrr64
- { 1695, 7, 1, 0, "PHSUBWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1695 = PHSUBWrm128
- { 1696, 7, 1, 0, "PHSUBWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1696 = PHSUBWrm64
- { 1697, 3, 1, 0, "PHSUBWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1697 = PHSUBWrr128
- { 1698, 3, 1, 0, "PHSUBWrr64", 0, 0|5|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1698 = PHSUBWrr64
- { 1699, 8, 1, 0, "PINSRBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1699 = PINSRBrm
- { 1700, 4, 1, 0, "PINSRBrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1700 = PINSRBrr
- { 1701, 8, 1, 0, "PINSRDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1701 = PINSRDrm
- { 1702, 4, 1, 0, "PINSRDrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1702 = PINSRDrr
- { 1703, 8, 1, 0, "PINSRQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1703 = PINSRQrm
- { 1704, 4, 1, 0, "PINSRQrr", 0, 0|5|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo192 }, // Inst #1704 = PINSRQrr
- { 1705, 8, 1, 0, "PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1705 = PINSRWrmi
- { 1706, 4, 1, 0, "PINSRWrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1706 = PINSRWrri
- { 1707, 7, 1, 0, "PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1707 = PMADDUBSWrm128
- { 1708, 7, 1, 0, "PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1708 = PMADDUBSWrm64
- { 1709, 3, 1, 0, "PMADDUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1709 = PMADDUBSWrr128
- { 1710, 3, 1, 0, "PMADDUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1710 = PMADDUBSWrr64
- { 1711, 7, 1, 0, "PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1711 = PMADDWDrm
- { 1712, 3, 1, 0, "PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1712 = PMADDWDrr
- { 1713, 7, 1, 0, "PMAXSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1713 = PMAXSBrm
- { 1714, 3, 1, 0, "PMAXSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1714 = PMAXSBrr
- { 1715, 7, 1, 0, "PMAXSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1715 = PMAXSDrm
- { 1716, 3, 1, 0, "PMAXSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1716 = PMAXSDrr
- { 1717, 7, 1, 0, "PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1717 = PMAXSWrm
- { 1718, 3, 1, 0, "PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1718 = PMAXSWrr
- { 1719, 7, 1, 0, "PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1719 = PMAXUBrm
- { 1720, 3, 1, 0, "PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1720 = PMAXUBrr
- { 1721, 7, 1, 0, "PMAXUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1721 = PMAXUDrm
- { 1722, 3, 1, 0, "PMAXUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1722 = PMAXUDrr
- { 1723, 7, 1, 0, "PMAXUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1723 = PMAXUWrm
- { 1724, 3, 1, 0, "PMAXUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1724 = PMAXUWrr
- { 1725, 7, 1, 0, "PMINSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1725 = PMINSBrm
- { 1726, 3, 1, 0, "PMINSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1726 = PMINSBrr
- { 1727, 7, 1, 0, "PMINSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1727 = PMINSDrm
- { 1728, 3, 1, 0, "PMINSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1728 = PMINSDrr
- { 1729, 7, 1, 0, "PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1729 = PMINSWrm
- { 1730, 3, 1, 0, "PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1730 = PMINSWrr
- { 1731, 7, 1, 0, "PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1731 = PMINUBrm
- { 1732, 3, 1, 0, "PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1732 = PMINUBrr
- { 1733, 7, 1, 0, "PMINUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1733 = PMINUDrm
- { 1734, 3, 1, 0, "PMINUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1734 = PMINUDrr
- { 1735, 7, 1, 0, "PMINUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1735 = PMINUWrm
- { 1736, 3, 1, 0, "PMINUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1736 = PMINUWrr
- { 1737, 2, 1, 0, "PMOVMSKBrr", 0, 0|5|(1<<6)|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1737 = PMOVMSKBrr
- { 1738, 6, 1, 0, "PMOVSXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1738 = PMOVSXBDrm
- { 1739, 2, 1, 0, "PMOVSXBDrr", 0, 0|5|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1739 = PMOVSXBDrr
- { 1740, 6, 1, 0, "PMOVSXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1740 = PMOVSXBQrm
- { 1741, 2, 1, 0, "PMOVSXBQrr", 0, 0|5|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1741 = PMOVSXBQrr
- { 1742, 6, 1, 0, "PMOVSXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1742 = PMOVSXBWrm
- { 1743, 2, 1, 0, "PMOVSXBWrr", 0, 0|5|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1743 = PMOVSXBWrr
- { 1744, 6, 1, 0, "PMOVSXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1744 = PMOVSXDQrm
- { 1745, 2, 1, 0, "PMOVSXDQrr", 0, 0|5|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1745 = PMOVSXDQrr
- { 1746, 6, 1, 0, "PMOVSXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1746 = PMOVSXWDrm
- { 1747, 2, 1, 0, "PMOVSXWDrr", 0, 0|5|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1747 = PMOVSXWDrr
- { 1748, 6, 1, 0, "PMOVSXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1748 = PMOVSXWQrm
- { 1749, 2, 1, 0, "PMOVSXWQrr", 0, 0|5|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1749 = PMOVSXWQrr
- { 1750, 6, 1, 0, "PMOVZXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1750 = PMOVZXBDrm
- { 1751, 2, 1, 0, "PMOVZXBDrr", 0, 0|5|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1751 = PMOVZXBDrr
- { 1752, 6, 1, 0, "PMOVZXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1752 = PMOVZXBQrm
- { 1753, 2, 1, 0, "PMOVZXBQrr", 0, 0|5|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1753 = PMOVZXBQrr
- { 1754, 6, 1, 0, "PMOVZXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1754 = PMOVZXBWrm
- { 1755, 2, 1, 0, "PMOVZXBWrr", 0, 0|5|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1755 = PMOVZXBWrr
- { 1756, 6, 1, 0, "PMOVZXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1756 = PMOVZXDQrm
- { 1757, 2, 1, 0, "PMOVZXDQrr", 0, 0|5|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1757 = PMOVZXDQrr
- { 1758, 6, 1, 0, "PMOVZXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1758 = PMOVZXWDrm
- { 1759, 2, 1, 0, "PMOVZXWDrr", 0, 0|5|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1759 = PMOVZXWDrr
- { 1760, 6, 1, 0, "PMOVZXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1760 = PMOVZXWQrm
- { 1761, 2, 1, 0, "PMOVZXWQrr", 0, 0|5|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1761 = PMOVZXWQrr
- { 1762, 7, 1, 0, "PMULDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1762 = PMULDQrm
- { 1763, 3, 1, 0, "PMULDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1763 = PMULDQrr
- { 1764, 7, 1, 0, "PMULHRSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1764 = PMULHRSWrm128
- { 1765, 7, 1, 0, "PMULHRSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1765 = PMULHRSWrm64
- { 1766, 3, 1, 0, "PMULHRSWrr128", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1766 = PMULHRSWrr128
- { 1767, 3, 1, 0, "PMULHRSWrr64", 0|(1<<TID::Commutable), 0|5|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1767 = PMULHRSWrr64
- { 1768, 7, 1, 0, "PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1768 = PMULHUWrm
- { 1769, 3, 1, 0, "PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1769 = PMULHUWrr
- { 1770, 7, 1, 0, "PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1770 = PMULHWrm
- { 1771, 3, 1, 0, "PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1771 = PMULHWrr
- { 1772, 7, 1, 0, "PMULLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1772 = PMULLDrm
- { 1773, 7, 1, 0, "PMULLDrm_int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1773 = PMULLDrm_int
- { 1774, 3, 1, 0, "PMULLDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1774 = PMULLDrr
- { 1775, 3, 1, 0, "PMULLDrr_int", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1775 = PMULLDrr_int
- { 1776, 7, 1, 0, "PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1776 = PMULLWrm
- { 1777, 3, 1, 0, "PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1777 = PMULLWrr
- { 1778, 7, 1, 0, "PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1778 = PMULUDQrm
- { 1779, 3, 1, 0, "PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1779 = PMULUDQrr
- { 1780, 1, 1, 0, "POP16r", 0|(1<<TID::MayLoad), 0|2|(1<<6)|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1780 = POP16r
- { 1781, 5, 1, 0, "POP16rmm", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1781 = POP16rmm
- { 1782, 1, 1, 0, "POP16rmr", 0|(1<<TID::MayLoad), 0|16|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1782 = POP16rmr
- { 1783, 1, 1, 0, "POP32r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1783 = POP32r
- { 1784, 5, 1, 0, "POP32rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1784 = POP32rmm
- { 1785, 1, 1, 0, "POP32rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1785 = POP32rmr
- { 1786, 1, 1, 0, "POP64r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1786 = POP64r
- { 1787, 5, 1, 0, "POP64rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1787 = POP64rmm
- { 1788, 1, 1, 0, "POP64rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1788 = POP64rmr
- { 1789, 6, 1, 0, "POPCNT16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1789 = POPCNT16rm
- { 1790, 2, 1, 0, "POPCNT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1790 = POPCNT16rr
- { 1791, 6, 1, 0, "POPCNT32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1791 = POPCNT32rm
- { 1792, 2, 1, 0, "POPCNT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1792 = POPCNT32rr
- { 1793, 6, 1, 0, "POPCNT64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1793 = POPCNT64rm
- { 1794, 2, 1, 0, "POPCNT64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1794 = POPCNT64rr
- { 1795, 0, 0, 0, "POPF", 0|(1<<TID::MayLoad), 0|1|(1<<6)|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1795 = POPF
- { 1796, 0, 0, 0, "POPFD", 0|(1<<TID::MayLoad), 0|1|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1796 = POPFD
- { 1797, 0, 0, 0, "POPFQ", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(157<<24), ImplicitList4, ImplicitList5, Barriers1, 0 }, // Inst #1797 = POPFQ
- { 1798, 0, 0, 0, "POPFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1798 = POPFS16
- { 1799, 0, 0, 0, "POPFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1799 = POPFS32
- { 1800, 0, 0, 0, "POPFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1800 = POPFS64
- { 1801, 0, 0, 0, "POPGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1801 = POPGS16
- { 1802, 0, 0, 0, "POPGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1802 = POPGS32
- { 1803, 0, 0, 0, "POPGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1803 = POPGS64
- { 1804, 7, 1, 0, "PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1804 = PORrm
- { 1805, 3, 1, 0, "PORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1805 = PORrr
- { 1806, 5, 0, 0, "PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1806 = PREFETCHNTA
- { 1807, 5, 0, 0, "PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1807 = PREFETCHT0
- { 1808, 5, 0, 0, "PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1808 = PREFETCHT1
- { 1809, 5, 0, 0, "PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1809 = PREFETCHT2
- { 1810, 7, 1, 0, "PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1810 = PSADBWrm
- { 1811, 3, 1, 0, "PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1811 = PSADBWrr
- { 1812, 7, 1, 0, "PSHUFBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo24 }, // Inst #1812 = PSHUFBrm128
- { 1813, 7, 1, 0, "PSHUFBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo136 }, // Inst #1813 = PSHUFBrm64
- { 1814, 3, 1, 0, "PSHUFBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo25 }, // Inst #1814 = PSHUFBrr128
- { 1815, 3, 1, 0, "PSHUFBrr64", 0, 0|5|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo137 }, // Inst #1815 = PSHUFBrr64
- { 1816, 7, 1, 0, "PSHUFDmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1816 = PSHUFDmi
- { 1817, 3, 1, 0, "PSHUFDri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1817 = PSHUFDri
- { 1818, 7, 1, 0, "PSHUFHWmi", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1818 = PSHUFHWmi
- { 1819, 3, 1, 0, "PSHUFHWri", 0, 0|5|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1819 = PSHUFHWri
- { 1820, 7, 1, 0, "PSHUFLWmi", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1820 = PSHUFLWmi
- { 1821, 3, 1, 0, "PSHUFLWri", 0, 0|5|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1821 = PSHUFLWri
- { 1822, 7, 1, 0, "PSIGNBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1822 = PSIGNBrm128
- { 1823, 7, 1, 0, "PSIGNBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1823 = PSIGNBrm64
- { 1824, 3, 1, 0, "PSIGNBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1824 = PSIGNBrr128
- { 1825, 3, 1, 0, "PSIGNBrr64", 0, 0|5|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1825 = PSIGNBrr64
- { 1826, 7, 1, 0, "PSIGNDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1826 = PSIGNDrm128
- { 1827, 7, 1, 0, "PSIGNDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1827 = PSIGNDrm64
- { 1828, 3, 1, 0, "PSIGNDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1828 = PSIGNDrr128
- { 1829, 3, 1, 0, "PSIGNDrr64", 0, 0|5|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1829 = PSIGNDrr64
- { 1830, 7, 1, 0, "PSIGNWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1830 = PSIGNWrm128
- { 1831, 7, 1, 0, "PSIGNWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1831 = PSIGNWrm64
- { 1832, 3, 1, 0, "PSIGNWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1832 = PSIGNWrr128
- { 1833, 3, 1, 0, "PSIGNWrr64", 0, 0|5|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1833 = PSIGNWrr64
- { 1834, 3, 1, 0, "PSLLDQri", 0, 0|23|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1834 = PSLLDQri
- { 1835, 3, 1, 0, "PSLLDri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1835 = PSLLDri
- { 1836, 7, 1, 0, "PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1836 = PSLLDrm
- { 1837, 3, 1, 0, "PSLLDrr", 0, 0|5|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1837 = PSLLDrr
- { 1838, 3, 1, 0, "PSLLQri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1838 = PSLLQri
- { 1839, 7, 1, 0, "PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1839 = PSLLQrm
- { 1840, 3, 1, 0, "PSLLQrr", 0, 0|5|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1840 = PSLLQrr
- { 1841, 3, 1, 0, "PSLLWri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1841 = PSLLWri
- { 1842, 7, 1, 0, "PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1842 = PSLLWrm
- { 1843, 3, 1, 0, "PSLLWrr", 0, 0|5|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1843 = PSLLWrr
- { 1844, 3, 1, 0, "PSRADri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1844 = PSRADri
- { 1845, 7, 1, 0, "PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1845 = PSRADrm
- { 1846, 3, 1, 0, "PSRADrr", 0, 0|5|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1846 = PSRADrr
- { 1847, 3, 1, 0, "PSRAWri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1847 = PSRAWri
- { 1848, 7, 1, 0, "PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1848 = PSRAWrm
- { 1849, 3, 1, 0, "PSRAWrr", 0, 0|5|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1849 = PSRAWrr
- { 1850, 3, 1, 0, "PSRLDQri", 0, 0|19|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1850 = PSRLDQri
- { 1851, 3, 1, 0, "PSRLDri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1851 = PSRLDri
- { 1852, 7, 1, 0, "PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1852 = PSRLDrm
- { 1853, 3, 1, 0, "PSRLDrr", 0, 0|5|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1853 = PSRLDrr
- { 1854, 3, 1, 0, "PSRLQri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1854 = PSRLQri
- { 1855, 7, 1, 0, "PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1855 = PSRLQrm
- { 1856, 3, 1, 0, "PSRLQrr", 0, 0|5|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1856 = PSRLQrr
- { 1857, 3, 1, 0, "PSRLWri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1857 = PSRLWri
- { 1858, 7, 1, 0, "PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1858 = PSRLWrm
- { 1859, 3, 1, 0, "PSRLWrr", 0, 0|5|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1859 = PSRLWrr
- { 1860, 7, 1, 0, "PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1860 = PSUBBrm
- { 1861, 3, 1, 0, "PSUBBrr", 0, 0|5|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1861 = PSUBBrr
- { 1862, 7, 1, 0, "PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1862 = PSUBDrm
- { 1863, 3, 1, 0, "PSUBDrr", 0, 0|5|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1863 = PSUBDrr
- { 1864, 7, 1, 0, "PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1864 = PSUBQrm
- { 1865, 3, 1, 0, "PSUBQrr", 0, 0|5|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1865 = PSUBQrr
- { 1866, 7, 1, 0, "PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1866 = PSUBSBrm
- { 1867, 3, 1, 0, "PSUBSBrr", 0, 0|5|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1867 = PSUBSBrr
- { 1868, 7, 1, 0, "PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1868 = PSUBSWrm
- { 1869, 3, 1, 0, "PSUBSWrr", 0, 0|5|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1869 = PSUBSWrr
- { 1870, 7, 1, 0, "PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1870 = PSUBUSBrm
- { 1871, 3, 1, 0, "PSUBUSBrr", 0, 0|5|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1871 = PSUBUSBrr
- { 1872, 7, 1, 0, "PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1872 = PSUBUSWrm
- { 1873, 3, 1, 0, "PSUBUSWrr", 0, 0|5|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1873 = PSUBUSWrr
- { 1874, 7, 1, 0, "PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1874 = PSUBWrm
- { 1875, 3, 1, 0, "PSUBWrr", 0, 0|5|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1875 = PSUBWrr
- { 1876, 6, 0, 0, "PTESTrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #1876 = PTESTrm
- { 1877, 2, 0, 0, "PTESTrr", 0, 0|5|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #1877 = PTESTrr
- { 1878, 7, 1, 0, "PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1878 = PUNPCKHBWrm
- { 1879, 3, 1, 0, "PUNPCKHBWrr", 0, 0|5|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1879 = PUNPCKHBWrr
- { 1880, 7, 1, 0, "PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1880 = PUNPCKHDQrm
- { 1881, 3, 1, 0, "PUNPCKHDQrr", 0, 0|5|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1881 = PUNPCKHDQrr
- { 1882, 7, 1, 0, "PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1882 = PUNPCKHQDQrm
- { 1883, 3, 1, 0, "PUNPCKHQDQrr", 0, 0|5|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1883 = PUNPCKHQDQrr
- { 1884, 7, 1, 0, "PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1884 = PUNPCKHWDrm
- { 1885, 3, 1, 0, "PUNPCKHWDrr", 0, 0|5|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1885 = PUNPCKHWDrr
- { 1886, 7, 1, 0, "PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1886 = PUNPCKLBWrm
- { 1887, 3, 1, 0, "PUNPCKLBWrr", 0, 0|5|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1887 = PUNPCKLBWrr
- { 1888, 7, 1, 0, "PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1888 = PUNPCKLDQrm
- { 1889, 3, 1, 0, "PUNPCKLDQrr", 0, 0|5|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1889 = PUNPCKLDQrr
- { 1890, 7, 1, 0, "PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1890 = PUNPCKLQDQrm
- { 1891, 3, 1, 0, "PUNPCKLQDQrr", 0, 0|5|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1891 = PUNPCKLQDQrr
- { 1892, 7, 1, 0, "PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1892 = PUNPCKLWDrm
- { 1893, 3, 1, 0, "PUNPCKLWDrr", 0, 0|5|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1893 = PUNPCKLWDrr
- { 1894, 1, 0, 0, "PUSH16r", 0|(1<<TID::MayStore), 0|2|(1<<6)|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1894 = PUSH16r
- { 1895, 5, 0, 0, "PUSH16rmm", 0|(1<<TID::MayStore), 0|30|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1895 = PUSH16rmm
- { 1896, 1, 0, 0, "PUSH16rmr", 0|(1<<TID::MayStore), 0|22|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1896 = PUSH16rmr
- { 1897, 1, 0, 0, "PUSH32i16", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1897 = PUSH32i16
- { 1898, 1, 0, 0, "PUSH32i32", 0|(1<<TID::MayStore), 0|1|(4<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1898 = PUSH32i32
- { 1899, 1, 0, 0, "PUSH32i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1899 = PUSH32i8
- { 1900, 1, 0, 0, "PUSH32r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1900 = PUSH32r
- { 1901, 5, 0, 0, "PUSH32rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1901 = PUSH32rmm
- { 1902, 1, 0, 0, "PUSH32rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1902 = PUSH32rmr
- { 1903, 1, 0, 0, "PUSH64i16", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1903 = PUSH64i16
- { 1904, 1, 0, 0, "PUSH64i32", 0|(1<<TID::MayStore), 0|1|(4<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1904 = PUSH64i32
- { 1905, 1, 0, 0, "PUSH64i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1905 = PUSH64i8
- { 1906, 1, 0, 0, "PUSH64r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1906 = PUSH64r
- { 1907, 5, 0, 0, "PUSH64rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1907 = PUSH64rmm
- { 1908, 1, 0, 0, "PUSH64rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1908 = PUSH64rmr
- { 1909, 0, 0, 0, "PUSHF", 0|(1<<TID::MayStore), 0|1|(1<<6)|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1909 = PUSHF
- { 1910, 0, 0, 0, "PUSHFD", 0|(1<<TID::MayStore), 0|1|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1910 = PUSHFD
- { 1911, 0, 0, 0, "PUSHFQ64", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(156<<24), ImplicitList5, ImplicitList4, NULL, 0 }, // Inst #1911 = PUSHFQ64
- { 1912, 0, 0, 0, "PUSHFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1912 = PUSHFS16
- { 1913, 0, 0, 0, "PUSHFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1913 = PUSHFS32
- { 1914, 0, 0, 0, "PUSHFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1914 = PUSHFS64
- { 1915, 0, 0, 0, "PUSHGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1915 = PUSHGS16
- { 1916, 0, 0, 0, "PUSHGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1916 = PUSHGS32
- { 1917, 0, 0, 0, "PUSHGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1917 = PUSHGS64
- { 1918, 7, 1, 0, "PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1918 = PXORrm
- { 1919, 3, 1, 0, "PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1919 = PXORrr
- { 1920, 5, 0, 0, "RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1920 = RCL16m1
- { 1921, 5, 0, 0, "RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1921 = RCL16mCL
- { 1922, 6, 0, 0, "RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1922 = RCL16mi
- { 1923, 2, 1, 0, "RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1923 = RCL16r1
- { 1924, 2, 1, 0, "RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1924 = RCL16rCL
- { 1925, 3, 1, 0, "RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1925 = RCL16ri
- { 1926, 5, 0, 0, "RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1926 = RCL32m1
- { 1927, 5, 0, 0, "RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1927 = RCL32mCL
- { 1928, 6, 0, 0, "RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1928 = RCL32mi
- { 1929, 2, 1, 0, "RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1929 = RCL32r1
- { 1930, 2, 1, 0, "RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1930 = RCL32rCL
- { 1931, 3, 1, 0, "RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1931 = RCL32ri
- { 1932, 5, 0, 0, "RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1932 = RCL64m1
- { 1933, 5, 0, 0, "RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1933 = RCL64mCL
- { 1934, 6, 0, 0, "RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1934 = RCL64mi
- { 1935, 2, 1, 0, "RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1935 = RCL64r1
- { 1936, 2, 1, 0, "RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1936 = RCL64rCL
- { 1937, 3, 1, 0, "RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1937 = RCL64ri
- { 1938, 5, 0, 0, "RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1938 = RCL8m1
- { 1939, 5, 0, 0, "RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1939 = RCL8mCL
- { 1940, 6, 0, 0, "RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1940 = RCL8mi
- { 1941, 2, 1, 0, "RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1941 = RCL8r1
- { 1942, 2, 1, 0, "RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1942 = RCL8rCL
- { 1943, 3, 1, 0, "RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1943 = RCL8ri
- { 1944, 6, 1, 0, "RCPPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1944 = RCPPSm
- { 1945, 6, 1, 0, "RCPPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1945 = RCPPSm_Int
- { 1946, 2, 1, 0, "RCPPSr", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1946 = RCPPSr
- { 1947, 2, 1, 0, "RCPPSr_Int", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1947 = RCPPSr_Int
- { 1948, 6, 1, 0, "RCPSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1948 = RCPSSm
- { 1949, 6, 1, 0, "RCPSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1949 = RCPSSm_Int
- { 1950, 2, 1, 0, "RCPSSr", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1950 = RCPSSr
- { 1951, 2, 1, 0, "RCPSSr_Int", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1951 = RCPSSr_Int
- { 1952, 5, 0, 0, "RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1952 = RCR16m1
- { 1953, 5, 0, 0, "RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1953 = RCR16mCL
- { 1954, 6, 0, 0, "RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1954 = RCR16mi
- { 1955, 2, 1, 0, "RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1955 = RCR16r1
- { 1956, 2, 1, 0, "RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1956 = RCR16rCL
- { 1957, 3, 1, 0, "RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1957 = RCR16ri
- { 1958, 5, 0, 0, "RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1958 = RCR32m1
- { 1959, 5, 0, 0, "RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1959 = RCR32mCL
- { 1960, 6, 0, 0, "RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1960 = RCR32mi
- { 1961, 2, 1, 0, "RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1961 = RCR32r1
- { 1962, 2, 1, 0, "RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1962 = RCR32rCL
- { 1963, 3, 1, 0, "RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1963 = RCR32ri
- { 1964, 5, 0, 0, "RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1964 = RCR64m1
- { 1965, 5, 0, 0, "RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1965 = RCR64mCL
- { 1966, 6, 0, 0, "RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1966 = RCR64mi
- { 1967, 2, 1, 0, "RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1967 = RCR64r1
- { 1968, 2, 1, 0, "RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1968 = RCR64rCL
- { 1969, 3, 1, 0, "RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1969 = RCR64ri
- { 1970, 5, 0, 0, "RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1970 = RCR8m1
- { 1971, 5, 0, 0, "RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1971 = RCR8mCL
- { 1972, 6, 0, 0, "RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1972 = RCR8mi
- { 1973, 2, 1, 0, "RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1973 = RCR8r1
- { 1974, 2, 1, 0, "RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1974 = RCR8rCL
- { 1975, 3, 1, 0, "RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1975 = RCR8ri
- { 1976, 0, 0, 0, "RDMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(50<<24), NULL, NULL, NULL, 0 }, // Inst #1976 = RDMSR
- { 1977, 0, 0, 0, "RDPMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(51<<24), NULL, NULL, NULL, 0 }, // Inst #1977 = RDPMC
- { 1978, 0, 0, 0, "RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(49<<24), NULL, ImplicitList19, NULL, 0 }, // Inst #1978 = RDTSC
- { 1979, 0, 0, 0, "RDTSCP", 0|(1<<TID::UnmodeledSideEffects), 0|42|(1<<8)|(1<<24), NULL, ImplicitList45, NULL, 0 }, // Inst #1979 = RDTSCP
- { 1980, 0, 0, 0, "REPNE_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(242<<24), ImplicitList42, ImplicitList27, NULL, 0 }, // Inst #1980 = REPNE_PREFIX
- { 1981, 0, 0, 0, "REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(164<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1981 = REP_MOVSB
- { 1982, 0, 0, 0, "REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(165<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1982 = REP_MOVSD
- { 1983, 0, 0, 0, "REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(165<<24), ImplicitList47, ImplicitList47, NULL, 0 }, // Inst #1983 = REP_MOVSQ
- { 1984, 0, 0, 0, "REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(165<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1984 = REP_MOVSW
- { 1985, 0, 0, 0, "REP_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(243<<24), ImplicitList42, ImplicitList27, NULL, 0 }, // Inst #1985 = REP_PREFIX
- { 1986, 0, 0, 0, "REP_STOSB", 0|(1<<TID::MayStore), 0|1|(2<<8)|(170<<24), ImplicitList48, ImplicitList49, NULL, 0 }, // Inst #1986 = REP_STOSB
- { 1987, 0, 0, 0, "REP_STOSD", 0|(1<<TID::MayStore), 0|1|(2<<8)|(171<<24), ImplicitList50, ImplicitList49, NULL, 0 }, // Inst #1987 = REP_STOSD
- { 1988, 0, 0, 0, "REP_STOSQ", 0|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(171<<24), ImplicitList51, ImplicitList52, NULL, 0 }, // Inst #1988 = REP_STOSQ
- { 1989, 0, 0, 0, "REP_STOSW", 0|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(171<<24), ImplicitList53, ImplicitList49, NULL, 0 }, // Inst #1989 = REP_STOSW
- { 1990, 0, 0, 0, "RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(7<<16)|(195<<24), NULL, NULL, NULL, 0 }, // Inst #1990 = RET
- { 1991, 1, 0, 0, "RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(3<<13)|(7<<16)|(194<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1991 = RETI
- { 1992, 5, 0, 0, "ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1992 = ROL16m1
- { 1993, 5, 0, 0, "ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1993 = ROL16mCL
- { 1994, 6, 0, 0, "ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1994 = ROL16mi
- { 1995, 2, 1, 0, "ROL16r1", 0, 0|16|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1995 = ROL16r1
- { 1996, 2, 1, 0, "ROL16rCL", 0, 0|16|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1996 = ROL16rCL
- { 1997, 3, 1, 0, "ROL16ri", 0, 0|16|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1997 = ROL16ri
- { 1998, 5, 0, 0, "ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1998 = ROL32m1
- { 1999, 5, 0, 0, "ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1999 = ROL32mCL
- { 2000, 6, 0, 0, "ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2000 = ROL32mi
- { 2001, 2, 1, 0, "ROL32r1", 0, 0|16|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2001 = ROL32r1
- { 2002, 2, 1, 0, "ROL32rCL", 0, 0|16|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2002 = ROL32rCL
- { 2003, 3, 1, 0, "ROL32ri", 0, 0|16|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2003 = ROL32ri
- { 2004, 5, 0, 0, "ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2004 = ROL64m1
- { 2005, 5, 0, 0, "ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2005 = ROL64mCL
- { 2006, 6, 0, 0, "ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2006 = ROL64mi
- { 2007, 2, 1, 0, "ROL64r1", 0, 0|16|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2007 = ROL64r1
- { 2008, 2, 1, 0, "ROL64rCL", 0, 0|16|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2008 = ROL64rCL
- { 2009, 3, 1, 0, "ROL64ri", 0, 0|16|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2009 = ROL64ri
- { 2010, 5, 0, 0, "ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2010 = ROL8m1
- { 2011, 5, 0, 0, "ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2011 = ROL8mCL
- { 2012, 6, 0, 0, "ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2012 = ROL8mi
- { 2013, 2, 1, 0, "ROL8r1", 0, 0|16|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2013 = ROL8r1
- { 2014, 2, 1, 0, "ROL8rCL", 0, 0|16|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2014 = ROL8rCL
- { 2015, 3, 1, 0, "ROL8ri", 0, 0|16|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2015 = ROL8ri
- { 2016, 5, 0, 0, "ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2016 = ROR16m1
- { 2017, 5, 0, 0, "ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2017 = ROR16mCL
- { 2018, 6, 0, 0, "ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2018 = ROR16mi
- { 2019, 2, 1, 0, "ROR16r1", 0, 0|17|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2019 = ROR16r1
- { 2020, 2, 1, 0, "ROR16rCL", 0, 0|17|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2020 = ROR16rCL
- { 2021, 3, 1, 0, "ROR16ri", 0, 0|17|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2021 = ROR16ri
- { 2022, 5, 0, 0, "ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2022 = ROR32m1
- { 2023, 5, 0, 0, "ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2023 = ROR32mCL
- { 2024, 6, 0, 0, "ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2024 = ROR32mi
- { 2025, 2, 1, 0, "ROR32r1", 0, 0|17|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2025 = ROR32r1
- { 2026, 2, 1, 0, "ROR32rCL", 0, 0|17|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2026 = ROR32rCL
- { 2027, 3, 1, 0, "ROR32ri", 0, 0|17|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2027 = ROR32ri
- { 2028, 5, 0, 0, "ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2028 = ROR64m1
- { 2029, 5, 0, 0, "ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2029 = ROR64mCL
- { 2030, 6, 0, 0, "ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2030 = ROR64mi
- { 2031, 2, 1, 0, "ROR64r1", 0, 0|17|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2031 = ROR64r1
- { 2032, 2, 1, 0, "ROR64rCL", 0, 0|17|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2032 = ROR64rCL
- { 2033, 3, 1, 0, "ROR64ri", 0, 0|17|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2033 = ROR64ri
- { 2034, 5, 0, 0, "ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2034 = ROR8m1
- { 2035, 5, 0, 0, "ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2035 = ROR8mCL
- { 2036, 6, 0, 0, "ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2036 = ROR8mi
- { 2037, 2, 1, 0, "ROR8r1", 0, 0|17|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2037 = ROR8r1
- { 2038, 2, 1, 0, "ROR8rCL", 0, 0|17|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2038 = ROR8rCL
- { 2039, 3, 1, 0, "ROR8ri", 0, 0|17|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2039 = ROR8ri
- { 2040, 7, 1, 0, "ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #2040 = ROUNDPDm_Int
- { 2041, 3, 1, 0, "ROUNDPDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #2041 = ROUNDPDr_Int
- { 2042, 7, 1, 0, "ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #2042 = ROUNDPSm_Int
- { 2043, 3, 1, 0, "ROUNDPSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #2043 = ROUNDPSr_Int
- { 2044, 8, 1, 0, "ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2044 = ROUNDSDm_Int
- { 2045, 4, 1, 0, "ROUNDSDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2045 = ROUNDSDr_Int
- { 2046, 8, 1, 0, "ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2046 = ROUNDSSm_Int
- { 2047, 4, 1, 0, "ROUNDSSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2047 = ROUNDSSr_Int
- { 2048, 0, 0, 0, "RSM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(170<<24), NULL, NULL, NULL, 0 }, // Inst #2048 = RSM
- { 2049, 6, 1, 0, "RSQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2049 = RSQRTPSm
- { 2050, 6, 1, 0, "RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2050 = RSQRTPSm_Int
- { 2051, 2, 1, 0, "RSQRTPSr", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2051 = RSQRTPSr
- { 2052, 2, 1, 0, "RSQRTPSr_Int", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2052 = RSQRTPSr_Int
- { 2053, 6, 1, 0, "RSQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2053 = RSQRTSSm
- { 2054, 6, 1, 0, "RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2054 = RSQRTSSm_Int
- { 2055, 2, 1, 0, "RSQRTSSr", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2055 = RSQRTSSr
- { 2056, 2, 1, 0, "RSQRTSSr_Int", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2056 = RSQRTSSr_Int
- { 2057, 0, 0, 0, "SAHF", 0, 0|1|(158<<24), ImplicitList28, ImplicitList1, Barriers1, 0 }, // Inst #2057 = SAHF
- { 2058, 5, 0, 0, "SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2058 = SAR16m1
- { 2059, 5, 0, 0, "SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2059 = SAR16mCL
- { 2060, 6, 0, 0, "SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2060 = SAR16mi
- { 2061, 2, 1, 0, "SAR16r1", 0, 0|23|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2061 = SAR16r1
- { 2062, 2, 1, 0, "SAR16rCL", 0, 0|23|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2062 = SAR16rCL
- { 2063, 3, 1, 0, "SAR16ri", 0, 0|23|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2063 = SAR16ri
- { 2064, 5, 0, 0, "SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2064 = SAR32m1
- { 2065, 5, 0, 0, "SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2065 = SAR32mCL
- { 2066, 6, 0, 0, "SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2066 = SAR32mi
- { 2067, 2, 1, 0, "SAR32r1", 0, 0|23|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2067 = SAR32r1
- { 2068, 2, 1, 0, "SAR32rCL", 0, 0|23|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2068 = SAR32rCL
- { 2069, 3, 1, 0, "SAR32ri", 0, 0|23|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2069 = SAR32ri
- { 2070, 5, 0, 0, "SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2070 = SAR64m1
- { 2071, 5, 0, 0, "SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2071 = SAR64mCL
- { 2072, 6, 0, 0, "SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2072 = SAR64mi
- { 2073, 2, 1, 0, "SAR64r1", 0, 0|23|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2073 = SAR64r1
- { 2074, 2, 1, 0, "SAR64rCL", 0, 0|23|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2074 = SAR64rCL
- { 2075, 3, 1, 0, "SAR64ri", 0, 0|23|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2075 = SAR64ri
- { 2076, 5, 0, 0, "SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2076 = SAR8m1
- { 2077, 5, 0, 0, "SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2077 = SAR8mCL
- { 2078, 6, 0, 0, "SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2078 = SAR8mi
- { 2079, 2, 1, 0, "SAR8r1", 0, 0|23|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2079 = SAR8r1
- { 2080, 2, 1, 0, "SAR8rCL", 0, 0|23|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2080 = SAR8rCL
- { 2081, 3, 1, 0, "SAR8ri", 0, 0|23|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2081 = SAR8ri
- { 2082, 1, 0, 0, "SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2082 = SBB16i16
- { 2083, 6, 0, 0, "SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2083 = SBB16mi
- { 2084, 6, 0, 0, "SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2084 = SBB16mi8
- { 2085, 6, 0, 0, "SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2085 = SBB16mr
- { 2086, 3, 1, 0, "SBB16ri", 0, 0|19|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2086 = SBB16ri
- { 2087, 3, 1, 0, "SBB16ri8", 0, 0|19|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2087 = SBB16ri8
- { 2088, 7, 1, 0, "SBB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2088 = SBB16rm
- { 2089, 3, 1, 0, "SBB16rr", 0, 0|3|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2089 = SBB16rr
- { 2090, 3, 1, 0, "SBB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2090 = SBB16rr_REV
- { 2091, 1, 0, 0, "SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2091 = SBB32i32
- { 2092, 6, 0, 0, "SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2092 = SBB32mi
- { 2093, 6, 0, 0, "SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2093 = SBB32mi8
- { 2094, 6, 0, 0, "SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2094 = SBB32mr
- { 2095, 3, 1, 0, "SBB32ri", 0, 0|19|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2095 = SBB32ri
- { 2096, 3, 1, 0, "SBB32ri8", 0, 0|19|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2096 = SBB32ri8
- { 2097, 7, 1, 0, "SBB32rm", 0|(1<<TID::MayLoad), 0|6|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2097 = SBB32rm
- { 2098, 3, 1, 0, "SBB32rr", 0, 0|3|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2098 = SBB32rr
- { 2099, 3, 1, 0, "SBB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2099 = SBB32rr_REV
- { 2100, 1, 0, 0, "SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2100 = SBB64i32
- { 2101, 6, 0, 0, "SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2101 = SBB64mi32
- { 2102, 6, 0, 0, "SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2102 = SBB64mi8
- { 2103, 6, 0, 0, "SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2103 = SBB64mr
- { 2104, 3, 1, 0, "SBB64ri32", 0, 0|19|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2104 = SBB64ri32
- { 2105, 3, 1, 0, "SBB64ri8", 0, 0|19|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2105 = SBB64ri8
- { 2106, 7, 1, 0, "SBB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2106 = SBB64rm
- { 2107, 3, 1, 0, "SBB64rr", 0, 0|3|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2107 = SBB64rr
- { 2108, 3, 1, 0, "SBB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2108 = SBB64rr_REV
- { 2109, 1, 0, 0, "SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(28<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2109 = SBB8i8
- { 2110, 6, 0, 0, "SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2110 = SBB8mi
- { 2111, 6, 0, 0, "SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2111 = SBB8mr
- { 2112, 3, 1, 0, "SBB8ri", 0, 0|19|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2112 = SBB8ri
- { 2113, 7, 1, 0, "SBB8rm", 0|(1<<TID::MayLoad), 0|6|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2113 = SBB8rm
- { 2114, 3, 1, 0, "SBB8rr", 0, 0|3|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2114 = SBB8rr
- { 2115, 3, 1, 0, "SBB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2115 = SBB8rr_REV
- { 2116, 0, 0, 0, "SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2116 = SCAS16
- { 2117, 0, 0, 0, "SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2117 = SCAS32
- { 2118, 0, 0, 0, "SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2118 = SCAS64
- { 2119, 0, 0, 0, "SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2119 = SCAS8
- { 2120, 5, 0, 0, "SETAEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2120 = SETAEm
- { 2121, 1, 1, 0, "SETAEr", 0, 0|16|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2121 = SETAEr
- { 2122, 5, 0, 0, "SETAm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2122 = SETAm
- { 2123, 1, 1, 0, "SETAr", 0, 0|16|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2123 = SETAr
- { 2124, 5, 0, 0, "SETBEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2124 = SETBEm
- { 2125, 1, 1, 0, "SETBEr", 0, 0|16|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2125 = SETBEr
- { 2126, 1, 1, 0, "SETB_C16r", 0, 0|32|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #2126 = SETB_C16r
- { 2127, 1, 1, 0, "SETB_C32r", 0, 0|32|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #2127 = SETB_C32r
- { 2128, 1, 1, 0, "SETB_C64r", 0, 0|32|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #2128 = SETB_C64r
- { 2129, 1, 1, 0, "SETB_C8r", 0, 0|32|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #2129 = SETB_C8r
- { 2130, 5, 0, 0, "SETBm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2130 = SETBm
- { 2131, 1, 1, 0, "SETBr", 0, 0|16|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2131 = SETBr
- { 2132, 5, 0, 0, "SETEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2132 = SETEm
- { 2133, 1, 1, 0, "SETEr", 0, 0|16|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2133 = SETEr
- { 2134, 5, 0, 0, "SETGEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2134 = SETGEm
- { 2135, 1, 1, 0, "SETGEr", 0, 0|16|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2135 = SETGEr
- { 2136, 5, 0, 0, "SETGm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2136 = SETGm
- { 2137, 1, 1, 0, "SETGr", 0, 0|16|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2137 = SETGr
- { 2138, 5, 0, 0, "SETLEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2138 = SETLEm
- { 2139, 1, 1, 0, "SETLEr", 0, 0|16|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2139 = SETLEr
- { 2140, 5, 0, 0, "SETLm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2140 = SETLm
- { 2141, 1, 1, 0, "SETLr", 0, 0|16|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2141 = SETLr
- { 2142, 5, 0, 0, "SETNEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2142 = SETNEm
- { 2143, 1, 1, 0, "SETNEr", 0, 0|16|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2143 = SETNEr
- { 2144, 5, 0, 0, "SETNOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2144 = SETNOm
- { 2145, 1, 1, 0, "SETNOr", 0, 0|16|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2145 = SETNOr
- { 2146, 5, 0, 0, "SETNPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2146 = SETNPm
- { 2147, 1, 1, 0, "SETNPr", 0, 0|16|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2147 = SETNPr
- { 2148, 5, 0, 0, "SETNSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2148 = SETNSm
- { 2149, 1, 1, 0, "SETNSr", 0, 0|16|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2149 = SETNSr
- { 2150, 5, 0, 0, "SETOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2150 = SETOm
- { 2151, 1, 1, 0, "SETOr", 0, 0|16|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2151 = SETOr
- { 2152, 5, 0, 0, "SETPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2152 = SETPm
- { 2153, 1, 1, 0, "SETPr", 0, 0|16|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2153 = SETPr
- { 2154, 5, 0, 0, "SETSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2154 = SETSm
- { 2155, 1, 1, 0, "SETSr", 0, 0|16|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2155 = SETSr
- { 2156, 0, 0, 0, "SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2156 = SFENCE
- { 2157, 5, 1, 0, "SGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2157 = SGDTm
- { 2158, 5, 0, 0, "SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2158 = SHL16m1
- { 2159, 5, 0, 0, "SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2159 = SHL16mCL
- { 2160, 6, 0, 0, "SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2160 = SHL16mi
- { 2161, 2, 1, 0, "SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2161 = SHL16r1
- { 2162, 2, 1, 0, "SHL16rCL", 0, 0|20|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2162 = SHL16rCL
- { 2163, 3, 1, 0, "SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2163 = SHL16ri
- { 2164, 5, 0, 0, "SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2164 = SHL32m1
- { 2165, 5, 0, 0, "SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2165 = SHL32mCL
- { 2166, 6, 0, 0, "SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2166 = SHL32mi
- { 2167, 2, 1, 0, "SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2167 = SHL32r1
- { 2168, 2, 1, 0, "SHL32rCL", 0, 0|20|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2168 = SHL32rCL
- { 2169, 3, 1, 0, "SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2169 = SHL32ri
- { 2170, 5, 0, 0, "SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2170 = SHL64m1
- { 2171, 5, 0, 0, "SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2171 = SHL64mCL
- { 2172, 6, 0, 0, "SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2172 = SHL64mi
- { 2173, 2, 1, 0, "SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2173 = SHL64r1
- { 2174, 2, 1, 0, "SHL64rCL", 0, 0|20|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2174 = SHL64rCL
- { 2175, 3, 1, 0, "SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2175 = SHL64ri
- { 2176, 5, 0, 0, "SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2176 = SHL8m1
- { 2177, 5, 0, 0, "SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2177 = SHL8mCL
- { 2178, 6, 0, 0, "SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2178 = SHL8mi
- { 2179, 2, 1, 0, "SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2179 = SHL8r1
- { 2180, 2, 1, 0, "SHL8rCL", 0, 0|20|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2180 = SHL8rCL
- { 2181, 3, 1, 0, "SHL8ri", 0, 0|20|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2181 = SHL8ri
- { 2182, 6, 0, 0, "SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2182 = SHLD16mrCL
- { 2183, 7, 0, 0, "SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #2183 = SHLD16mri8
- { 2184, 3, 1, 0, "SHLD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2184 = SHLD16rrCL
- { 2185, 4, 1, 0, "SHLD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #2185 = SHLD16rri8
- { 2186, 6, 0, 0, "SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2186 = SHLD32mrCL
- { 2187, 7, 0, 0, "SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo196 }, // Inst #2187 = SHLD32mri8
- { 2188, 3, 1, 0, "SHLD32rrCL", 0, 0|3|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2188 = SHLD32rrCL
- { 2189, 4, 1, 0, "SHLD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo197 }, // Inst #2189 = SHLD32rri8
- { 2190, 6, 0, 0, "SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2190 = SHLD64mrCL
- { 2191, 7, 0, 0, "SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo198 }, // Inst #2191 = SHLD64mri8
- { 2192, 3, 1, 0, "SHLD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2192 = SHLD64rrCL
- { 2193, 4, 1, 0, "SHLD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo199 }, // Inst #2193 = SHLD64rri8
- { 2194, 5, 0, 0, "SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2194 = SHR16m1
- { 2195, 5, 0, 0, "SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2195 = SHR16mCL
- { 2196, 6, 0, 0, "SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2196 = SHR16mi
- { 2197, 2, 1, 0, "SHR16r1", 0, 0|21|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2197 = SHR16r1
- { 2198, 2, 1, 0, "SHR16rCL", 0, 0|21|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2198 = SHR16rCL
- { 2199, 3, 1, 0, "SHR16ri", 0, 0|21|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2199 = SHR16ri
- { 2200, 5, 0, 0, "SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2200 = SHR32m1
- { 2201, 5, 0, 0, "SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2201 = SHR32mCL
- { 2202, 6, 0, 0, "SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2202 = SHR32mi
- { 2203, 2, 1, 0, "SHR32r1", 0, 0|21|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2203 = SHR32r1
- { 2204, 2, 1, 0, "SHR32rCL", 0, 0|21|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2204 = SHR32rCL
- { 2205, 3, 1, 0, "SHR32ri", 0, 0|21|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2205 = SHR32ri
- { 2206, 5, 0, 0, "SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2206 = SHR64m1
- { 2207, 5, 0, 0, "SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2207 = SHR64mCL
- { 2208, 6, 0, 0, "SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2208 = SHR64mi
- { 2209, 2, 1, 0, "SHR64r1", 0, 0|21|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2209 = SHR64r1
- { 2210, 2, 1, 0, "SHR64rCL", 0, 0|21|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2210 = SHR64rCL
- { 2211, 3, 1, 0, "SHR64ri", 0, 0|21|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2211 = SHR64ri
- { 2212, 5, 0, 0, "SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2212 = SHR8m1
- { 2213, 5, 0, 0, "SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2213 = SHR8mCL
- { 2214, 6, 0, 0, "SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2214 = SHR8mi
- { 2215, 2, 1, 0, "SHR8r1", 0, 0|21|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2215 = SHR8r1
- { 2216, 2, 1, 0, "SHR8rCL", 0, 0|21|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2216 = SHR8rCL
- { 2217, 3, 1, 0, "SHR8ri", 0, 0|21|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2217 = SHR8ri
- { 2218, 6, 0, 0, "SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2218 = SHRD16mrCL
- { 2219, 7, 0, 0, "SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #2219 = SHRD16mri8
- { 2220, 3, 1, 0, "SHRD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2220 = SHRD16rrCL
- { 2221, 4, 1, 0, "SHRD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #2221 = SHRD16rri8
- { 2222, 6, 0, 0, "SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2222 = SHRD32mrCL
- { 2223, 7, 0, 0, "SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo196 }, // Inst #2223 = SHRD32mri8
- { 2224, 3, 1, 0, "SHRD32rrCL", 0, 0|3|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2224 = SHRD32rrCL
- { 2225, 4, 1, 0, "SHRD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo197 }, // Inst #2225 = SHRD32rri8
- { 2226, 6, 0, 0, "SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2226 = SHRD64mrCL
- { 2227, 7, 0, 0, "SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo198 }, // Inst #2227 = SHRD64mri8
- { 2228, 3, 1, 0, "SHRD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2228 = SHRD64rrCL
- { 2229, 4, 1, 0, "SHRD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo199 }, // Inst #2229 = SHRD64rri8
- { 2230, 8, 1, 0, "SHUFPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2230 = SHUFPDrmi
- { 2231, 4, 1, 0, "SHUFPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2231 = SHUFPDrri
- { 2232, 8, 1, 0, "SHUFPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2232 = SHUFPSrmi
- { 2233, 4, 1, 0, "SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0|5|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2233 = SHUFPSrri
- { 2234, 5, 1, 0, "SIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2234 = SIDTm
- { 2235, 0, 0, 0, "SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(254<<24), NULL, NULL, NULL, 0 }, // Inst #2235 = SIN_F
- { 2236, 2, 1, 0, "SIN_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2236 = SIN_Fp32
- { 2237, 2, 1, 0, "SIN_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2237 = SIN_Fp64
- { 2238, 2, 1, 0, "SIN_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2238 = SIN_Fp80
- { 2239, 5, 1, 0, "SLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2239 = SLDT16m
- { 2240, 1, 1, 0, "SLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2240 = SLDT16r
- { 2241, 5, 1, 0, "SLDT64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo30 }, // Inst #2241 = SLDT64m
- { 2242, 1, 1, 0, "SLDT64r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo58 }, // Inst #2242 = SLDT64r
- { 2243, 5, 1, 0, "SMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2243 = SMSW16m
- { 2244, 1, 1, 0, "SMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2244 = SMSW16r
- { 2245, 1, 1, 0, "SMSW32r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2245 = SMSW32r
- { 2246, 1, 1, 0, "SMSW64r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<12)|(1<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2246 = SMSW64r
- { 2247, 6, 1, 0, "SQRTPDm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2247 = SQRTPDm
- { 2248, 6, 1, 0, "SQRTPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2248 = SQRTPDm_Int
- { 2249, 2, 1, 0, "SQRTPDr", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2249 = SQRTPDr
- { 2250, 2, 1, 0, "SQRTPDr_Int", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2250 = SQRTPDr_Int
- { 2251, 6, 1, 0, "SQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2251 = SQRTPSm
- { 2252, 6, 1, 0, "SQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2252 = SQRTPSm_Int
- { 2253, 2, 1, 0, "SQRTPSr", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2253 = SQRTPSr
- { 2254, 2, 1, 0, "SQRTPSr_Int", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2254 = SQRTPSr_Int
- { 2255, 6, 1, 0, "SQRTSDm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #2255 = SQRTSDm
- { 2256, 6, 1, 0, "SQRTSDm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2256 = SQRTSDm_Int
- { 2257, 2, 1, 0, "SQRTSDr", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #2257 = SQRTSDr
- { 2258, 2, 1, 0, "SQRTSDr_Int", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2258 = SQRTSDr_Int
- { 2259, 6, 1, 0, "SQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2259 = SQRTSSm
- { 2260, 6, 1, 0, "SQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2260 = SQRTSSm_Int
- { 2261, 2, 1, 0, "SQRTSSr", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2261 = SQRTSSr
- { 2262, 2, 1, 0, "SQRTSSr_Int", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2262 = SQRTSSr_Int
- { 2263, 0, 0, 0, "SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(250<<24), NULL, NULL, NULL, 0 }, // Inst #2263 = SQRT_F
- { 2264, 2, 1, 0, "SQRT_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2264 = SQRT_Fp32
- { 2265, 2, 1, 0, "SQRT_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2265 = SQRT_Fp64
- { 2266, 2, 1, 0, "SQRT_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2266 = SQRT_Fp80
- { 2267, 0, 0, 0, "SS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(54<<24), NULL, NULL, NULL, 0 }, // Inst #2267 = SS_PREFIX
- { 2268, 0, 0, 0, "STC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(249<<24), NULL, NULL, NULL, 0 }, // Inst #2268 = STC
- { 2269, 0, 0, 0, "STD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(253<<24), NULL, NULL, NULL, 0 }, // Inst #2269 = STD
- { 2270, 0, 0, 0, "STI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(251<<24), NULL, NULL, NULL, 0 }, // Inst #2270 = STI
- { 2271, 5, 0, 0, "STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2271 = STMXCSR
- { 2272, 0, 0, 0, "STOSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(170<<24), ImplicitList54, ImplicitList35, NULL, 0 }, // Inst #2272 = STOSB
- { 2273, 0, 0, 0, "STOSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(171<<24), ImplicitList55, ImplicitList35, NULL, 0 }, // Inst #2273 = STOSD
- { 2274, 0, 0, 0, "STOSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(171<<24), ImplicitList56, ImplicitList35, NULL, 0 }, // Inst #2274 = STOSW
- { 2275, 5, 1, 0, "STRm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2275 = STRm
- { 2276, 1, 1, 0, "STRr", 0|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2276 = STRr
- { 2277, 5, 0, 0, "ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2277 = ST_F32m
- { 2278, 5, 0, 0, "ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2278 = ST_F64m
- { 2279, 5, 0, 0, "ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2279 = ST_FP32m
- { 2280, 5, 0, 0, "ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2280 = ST_FP64m
- { 2281, 5, 0, 0, "ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2281 = ST_FP80m
- { 2282, 1, 0, 0, "ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2282 = ST_FPrr
- { 2283, 6, 0, 0, "ST_Fp32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2283 = ST_Fp32m
- { 2284, 6, 0, 0, "ST_Fp64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2284 = ST_Fp64m
- { 2285, 6, 0, 0, "ST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2285 = ST_Fp64m32
- { 2286, 6, 0, 0, "ST_Fp80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2286 = ST_Fp80m32
- { 2287, 6, 0, 0, "ST_Fp80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2287 = ST_Fp80m64
- { 2288, 6, 0, 0, "ST_FpP32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2288 = ST_FpP32m
- { 2289, 6, 0, 0, "ST_FpP64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2289 = ST_FpP64m
- { 2290, 6, 0, 0, "ST_FpP64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2290 = ST_FpP64m32
- { 2291, 6, 0, 0, "ST_FpP80m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2291 = ST_FpP80m
- { 2292, 6, 0, 0, "ST_FpP80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2292 = ST_FpP80m32
- { 2293, 6, 0, 0, "ST_FpP80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2293 = ST_FpP80m64
- { 2294, 1, 0, 0, "ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2294 = ST_Frr
- { 2295, 1, 0, 0, "SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2295 = SUB16i16
- { 2296, 6, 0, 0, "SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2296 = SUB16mi
- { 2297, 6, 0, 0, "SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2297 = SUB16mi8
- { 2298, 6, 0, 0, "SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2298 = SUB16mr
- { 2299, 3, 1, 0, "SUB16ri", 0, 0|21|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2299 = SUB16ri
- { 2300, 3, 1, 0, "SUB16ri8", 0, 0|21|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2300 = SUB16ri8
- { 2301, 7, 1, 0, "SUB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2301 = SUB16rm
- { 2302, 3, 1, 0, "SUB16rr", 0, 0|3|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2302 = SUB16rr
- { 2303, 3, 1, 0, "SUB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2303 = SUB16rr_REV
- { 2304, 1, 0, 0, "SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2304 = SUB32i32
- { 2305, 6, 0, 0, "SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2305 = SUB32mi
- { 2306, 6, 0, 0, "SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2306 = SUB32mi8
- { 2307, 6, 0, 0, "SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2307 = SUB32mr
- { 2308, 3, 1, 0, "SUB32ri", 0, 0|21|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2308 = SUB32ri
- { 2309, 3, 1, 0, "SUB32ri8", 0, 0|21|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2309 = SUB32ri8
- { 2310, 7, 1, 0, "SUB32rm", 0|(1<<TID::MayLoad), 0|6|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2310 = SUB32rm
- { 2311, 3, 1, 0, "SUB32rr", 0, 0|3|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2311 = SUB32rr
- { 2312, 3, 1, 0, "SUB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2312 = SUB32rr_REV
- { 2313, 1, 0, 0, "SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2313 = SUB64i32
- { 2314, 6, 0, 0, "SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2314 = SUB64mi32
- { 2315, 6, 0, 0, "SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2315 = SUB64mi8
- { 2316, 6, 0, 0, "SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2316 = SUB64mr
- { 2317, 3, 1, 0, "SUB64ri32", 0, 0|21|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2317 = SUB64ri32
- { 2318, 3, 1, 0, "SUB64ri8", 0, 0|21|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2318 = SUB64ri8
- { 2319, 7, 1, 0, "SUB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2319 = SUB64rm
- { 2320, 3, 1, 0, "SUB64rr", 0, 0|3|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2320 = SUB64rr
- { 2321, 3, 1, 0, "SUB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2321 = SUB64rr_REV
- { 2322, 1, 0, 0, "SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(44<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2322 = SUB8i8
- { 2323, 6, 0, 0, "SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2323 = SUB8mi
- { 2324, 6, 0, 0, "SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2324 = SUB8mr
- { 2325, 3, 1, 0, "SUB8ri", 0, 0|21|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2325 = SUB8ri
- { 2326, 7, 1, 0, "SUB8rm", 0|(1<<TID::MayLoad), 0|6|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2326 = SUB8rm
- { 2327, 3, 1, 0, "SUB8rr", 0, 0|3|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2327 = SUB8rr
- { 2328, 3, 1, 0, "SUB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2328 = SUB8rr_REV
- { 2329, 7, 1, 0, "SUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2329 = SUBPDrm
- { 2330, 3, 1, 0, "SUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2330 = SUBPDrr
- { 2331, 7, 1, 0, "SUBPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2331 = SUBPSrm
- { 2332, 3, 1, 0, "SUBPSrr", 0, 0|5|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2332 = SUBPSrr
- { 2333, 5, 0, 0, "SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2333 = SUBR_F32m
- { 2334, 5, 0, 0, "SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2334 = SUBR_F64m
- { 2335, 5, 0, 0, "SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2335 = SUBR_FI16m
- { 2336, 5, 0, 0, "SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2336 = SUBR_FI32m
- { 2337, 1, 0, 0, "SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2337 = SUBR_FPrST0
- { 2338, 1, 0, 0, "SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2338 = SUBR_FST0r
- { 2339, 7, 1, 0, "SUBR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2339 = SUBR_Fp32m
- { 2340, 7, 1, 0, "SUBR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2340 = SUBR_Fp64m
- { 2341, 7, 1, 0, "SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2341 = SUBR_Fp64m32
- { 2342, 7, 1, 0, "SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2342 = SUBR_Fp80m32
- { 2343, 7, 1, 0, "SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2343 = SUBR_Fp80m64
- { 2344, 7, 1, 0, "SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2344 = SUBR_FpI16m32
- { 2345, 7, 1, 0, "SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2345 = SUBR_FpI16m64
- { 2346, 7, 1, 0, "SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2346 = SUBR_FpI16m80
- { 2347, 7, 1, 0, "SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2347 = SUBR_FpI32m32
- { 2348, 7, 1, 0, "SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2348 = SUBR_FpI32m64
- { 2349, 7, 1, 0, "SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2349 = SUBR_FpI32m80
- { 2350, 1, 0, 0, "SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2350 = SUBR_FrST0
- { 2351, 7, 1, 0, "SUBSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #2351 = SUBSDrm
- { 2352, 7, 1, 0, "SUBSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2352 = SUBSDrm_Int
- { 2353, 3, 1, 0, "SUBSDrr", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #2353 = SUBSDrr
- { 2354, 3, 1, 0, "SUBSDrr_Int", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2354 = SUBSDrr_Int
- { 2355, 7, 1, 0, "SUBSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #2355 = SUBSSrm
- { 2356, 7, 1, 0, "SUBSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2356 = SUBSSrm_Int
- { 2357, 3, 1, 0, "SUBSSrr", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2357 = SUBSSrr
- { 2358, 3, 1, 0, "SUBSSrr_Int", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2358 = SUBSSrr_Int
- { 2359, 5, 0, 0, "SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2359 = SUB_F32m
- { 2360, 5, 0, 0, "SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2360 = SUB_F64m
- { 2361, 5, 0, 0, "SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2361 = SUB_FI16m
- { 2362, 5, 0, 0, "SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2362 = SUB_FI32m
- { 2363, 1, 0, 0, "SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2363 = SUB_FPrST0
- { 2364, 1, 0, 0, "SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2364 = SUB_FST0r
- { 2365, 3, 1, 0, "SUB_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2365 = SUB_Fp32
- { 2366, 7, 1, 0, "SUB_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2366 = SUB_Fp32m
- { 2367, 3, 1, 0, "SUB_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2367 = SUB_Fp64
- { 2368, 7, 1, 0, "SUB_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2368 = SUB_Fp64m
- { 2369, 7, 1, 0, "SUB_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2369 = SUB_Fp64m32
- { 2370, 3, 1, 0, "SUB_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2370 = SUB_Fp80
- { 2371, 7, 1, 0, "SUB_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2371 = SUB_Fp80m32
- { 2372, 7, 1, 0, "SUB_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2372 = SUB_Fp80m64
- { 2373, 7, 1, 0, "SUB_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2373 = SUB_FpI16m32
- { 2374, 7, 1, 0, "SUB_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2374 = SUB_FpI16m64
- { 2375, 7, 1, 0, "SUB_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2375 = SUB_FpI16m80
- { 2376, 7, 1, 0, "SUB_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2376 = SUB_FpI32m32
- { 2377, 7, 1, 0, "SUB_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2377 = SUB_FpI32m64
- { 2378, 7, 1, 0, "SUB_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2378 = SUB_FpI32m80
- { 2379, 1, 0, 0, "SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2379 = SUB_FrST0
- { 2380, 0, 0, 0, "SWAPGS", 0|(1<<TID::UnmodeledSideEffects), 0|41|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2380 = SWAPGS
- { 2381, 0, 0, 0, "SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(5<<24), NULL, NULL, NULL, 0 }, // Inst #2381 = SYSCALL
- { 2382, 0, 0, 0, "SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(52<<24), NULL, NULL, NULL, 0 }, // Inst #2382 = SYSENTER
- { 2383, 0, 0, 0, "SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2383 = SYSEXIT
- { 2384, 0, 0, 0, "SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<12)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2384 = SYSEXIT64
- { 2385, 0, 0, 0, "SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(7<<24), NULL, NULL, NULL, 0 }, // Inst #2385 = SYSRET
- { 2386, 1, 0, 0, "TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #2386 = TAILJMPd
- { 2387, 5, 0, 0, "TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2387 = TAILJMPm
- { 2388, 1, 0, 0, "TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2388 = TAILJMPr
- { 2389, 1, 0, 0, "TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2389 = TAILJMPr64
- { 2390, 2, 0, 0, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2390 = TCRETURNdi
- { 2391, 2, 0, 0, "TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2391 = TCRETURNdi64
- { 2392, 2, 0, 0, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo55 }, // Inst #2392 = TCRETURNri
- { 2393, 2, 0, 0, "TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo56 }, // Inst #2393 = TCRETURNri64
- { 2394, 1, 0, 0, "TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2394 = TEST16i16
- { 2395, 6, 0, 0, "TEST16mi", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2395 = TEST16mi
- { 2396, 2, 0, 0, "TEST16ri", 0, 0|16|(1<<6)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #2396 = TEST16ri
- { 2397, 6, 0, 0, "TEST16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #2397 = TEST16rm
- { 2398, 2, 0, 0, "TEST16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #2398 = TEST16rr
- { 2399, 1, 0, 0, "TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2399 = TEST32i32
- { 2400, 6, 0, 0, "TEST32mi", 0|(1<<TID::MayLoad), 0|24|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2400 = TEST32mi
- { 2401, 2, 0, 0, "TEST32ri", 0, 0|16|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #2401 = TEST32ri
- { 2402, 6, 0, 0, "TEST32rm", 0|(1<<TID::MayLoad), 0|6|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #2402 = TEST32rm
- { 2403, 2, 0, 0, "TEST32rr", 0|(1<<TID::Commutable), 0|3|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #2403 = TEST32rr
- { 2404, 1, 0, 0, "TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2404 = TEST64i32
- { 2405, 6, 0, 0, "TEST64mi32", 0|(1<<TID::MayLoad), 0|24|(1<<12)|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2405 = TEST64mi32
- { 2406, 2, 0, 0, "TEST64ri32", 0, 0|16|(1<<12)|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #2406 = TEST64ri32
- { 2407, 6, 0, 0, "TEST64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #2407 = TEST64rm
- { 2408, 2, 0, 0, "TEST64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #2408 = TEST64rr
- { 2409, 1, 0, 0, "TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(168<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2409 = TEST8i8
- { 2410, 6, 0, 0, "TEST8mi", 0|(1<<TID::MayLoad), 0|24|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2410 = TEST8mi
- { 2411, 2, 0, 0, "TEST8ri", 0, 0|16|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #2411 = TEST8ri
- { 2412, 6, 0, 0, "TEST8rm", 0|(1<<TID::MayLoad), 0|6|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #2412 = TEST8rm
- { 2413, 2, 0, 0, "TEST8rr", 0|(1<<TID::Commutable), 0|3|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #2413 = TEST8rr
- { 2414, 4, 0, 0, "TLS_addr32", 0, 0, ImplicitList2, ImplicitList9, Barriers3, OperandInfo201 }, // Inst #2414 = TLS_addr32
- { 2415, 4, 0, 0, "TLS_addr64", 0, 0, ImplicitList4, ImplicitList10, Barriers4, OperandInfo202 }, // Inst #2415 = TLS_addr64
- { 2416, 0, 0, 0, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(11<<24), NULL, NULL, NULL, 0 }, // Inst #2416 = TRAP
- { 2417, 0, 0, 0, "TST_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(228<<24), NULL, NULL, NULL, 0 }, // Inst #2417 = TST_F
- { 2418, 1, 0, 0, "TST_Fp32", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #2418 = TST_Fp32
- { 2419, 1, 0, 0, "TST_Fp64", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #2419 = TST_Fp64
- { 2420, 1, 0, 0, "TST_Fp80", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #2420 = TST_Fp80
- { 2421, 6, 0, 0, "UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo82 }, // Inst #2421 = UCOMISDrm
- { 2422, 2, 0, 0, "UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo105 }, // Inst #2422 = UCOMISDrr
- { 2423, 6, 0, 0, "UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo80 }, // Inst #2423 = UCOMISSrm
- { 2424, 2, 0, 0, "UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo106 }, // Inst #2424 = UCOMISSrr
- { 2425, 1, 0, 0, "UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2425 = UCOM_FIPr
- { 2426, 1, 0, 0, "UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2426 = UCOM_FIr
- { 2427, 0, 0, 0, "UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(5<<8)|(233<<24), ImplicitList24, ImplicitList1, Barriers1, 0 }, // Inst #2427 = UCOM_FPPr
- { 2428, 1, 0, 0, "UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2428 = UCOM_FPr
- { 2429, 2, 0, 0, "UCOM_FpIr32", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2429 = UCOM_FpIr32
- { 2430, 2, 0, 0, "UCOM_FpIr64", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2430 = UCOM_FpIr64
- { 2431, 2, 0, 0, "UCOM_FpIr80", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2431 = UCOM_FpIr80
- { 2432, 2, 0, 0, "UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2432 = UCOM_Fpr32
- { 2433, 2, 0, 0, "UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2433 = UCOM_Fpr64
- { 2434, 2, 0, 0, "UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2434 = UCOM_Fpr80
- { 2435, 1, 0, 0, "UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(224<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2435 = UCOM_Fr
- { 2436, 7, 1, 0, "UNPCKHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2436 = UNPCKHPDrm
- { 2437, 3, 1, 0, "UNPCKHPDrr", 0, 0|5|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2437 = UNPCKHPDrr
- { 2438, 7, 1, 0, "UNPCKHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2438 = UNPCKHPSrm
- { 2439, 3, 1, 0, "UNPCKHPSrr", 0, 0|5|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2439 = UNPCKHPSrr
- { 2440, 7, 1, 0, "UNPCKLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2440 = UNPCKLPDrm
- { 2441, 3, 1, 0, "UNPCKLPDrr", 0, 0|5|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2441 = UNPCKLPDrr
- { 2442, 7, 1, 0, "UNPCKLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2442 = UNPCKLPSrm
- { 2443, 3, 1, 0, "UNPCKLPSrr", 0, 0|5|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2443 = UNPCKLPSrr
- { 2444, 3, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0, NULL, NULL, NULL, OperandInfo203 }, // Inst #2444 = VASTART_SAVE_XMM_REGS
- { 2445, 5, 0, 0, "VERRm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2445 = VERRm
- { 2446, 1, 0, 0, "VERRr", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2446 = VERRr
- { 2447, 5, 0, 0, "VERWm", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2447 = VERWm
- { 2448, 1, 0, 0, "VERWr", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2448 = VERWr
- { 2449, 0, 0, 0, "VMCALL", 0|(1<<TID::UnmodeledSideEffects), 0|33|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2449 = VMCALL
- { 2450, 5, 0, 0, "VMCLEARm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2450 = VMCLEARm
- { 2451, 0, 0, 0, "VMLAUNCH", 0|(1<<TID::UnmodeledSideEffects), 0|34|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2451 = VMLAUNCH
- { 2452, 5, 0, 0, "VMPTRLDm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2452 = VMPTRLDm
- { 2453, 5, 1, 0, "VMPTRSTm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2453 = VMPTRSTm
- { 2454, 6, 1, 0, "VMREAD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2454 = VMREAD32rm
- { 2455, 2, 1, 0, "VMREAD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2455 = VMREAD32rr
- { 2456, 6, 1, 0, "VMREAD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2456 = VMREAD64rm
- { 2457, 2, 1, 0, "VMREAD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2457 = VMREAD64rr
- { 2458, 0, 0, 0, "VMRESUME", 0|(1<<TID::UnmodeledSideEffects), 0|35|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2458 = VMRESUME
- { 2459, 6, 1, 0, "VMWRITE32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #2459 = VMWRITE32rm
- { 2460, 2, 1, 0, "VMWRITE32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2460 = VMWRITE32rr
- { 2461, 6, 1, 0, "VMWRITE64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #2461 = VMWRITE64rm
- { 2462, 2, 1, 0, "VMWRITE64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2462 = VMWRITE64rr
- { 2463, 0, 0, 0, "VMXOFF", 0|(1<<TID::UnmodeledSideEffects), 0|36|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2463 = VMXOFF
- { 2464, 5, 0, 0, "VMXON", 0|(1<<TID::UnmodeledSideEffects), 0|30|(11<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2464 = VMXON
- { 2465, 1, 1, 0, "V_SET0", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo204 }, // Inst #2465 = V_SET0
- { 2466, 1, 1, 0, "V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo204 }, // Inst #2466 = V_SETALLONES
- { 2467, 0, 0, 0, "WAIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(155<<24), NULL, NULL, NULL, 0 }, // Inst #2467 = WAIT
- { 2468, 0, 0, 0, "WBINVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(9<<24), NULL, NULL, NULL, 0 }, // Inst #2468 = WBINVD
- { 2469, 5, 0, 0, "WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo30 }, // Inst #2469 = WINCALL64m
- { 2470, 1, 0, 0, "WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(232<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo5 }, // Inst #2470 = WINCALL64pcrel32
- { 2471, 1, 0, 0, "WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo58 }, // Inst #2471 = WINCALL64r
- { 2472, 0, 0, 0, "WRMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(48<<24), NULL, NULL, NULL, 0 }, // Inst #2472 = WRMSR
- { 2473, 6, 0, 0, "XADD16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #2473 = XADD16rm
- { 2474, 2, 1, 0, "XADD16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #2474 = XADD16rr
- { 2475, 6, 0, 0, "XADD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2475 = XADD32rm
- { 2476, 2, 1, 0, "XADD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2476 = XADD32rr
- { 2477, 6, 0, 0, "XADD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2477 = XADD64rm
- { 2478, 2, 1, 0, "XADD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2478 = XADD64rr
- { 2479, 6, 0, 0, "XADD8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #2479 = XADD8rm
- { 2480, 2, 1, 0, "XADD8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #2480 = XADD8rr
- { 2481, 1, 0, 0, "XCHG16ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<6)|(144<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2481 = XCHG16ar
- { 2482, 7, 1, 0, "XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo9 }, // Inst #2482 = XCHG16rm
- { 2483, 3, 1, 0, "XCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo10 }, // Inst #2483 = XCHG16rr
- { 2484, 1, 0, 0, "XCHG32ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(144<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2484 = XCHG32ar
- { 2485, 7, 1, 0, "XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(135<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #2485 = XCHG32rm
- { 2486, 3, 1, 0, "XCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(135<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #2486 = XCHG32rr
- { 2487, 1, 0, 0, "XCHG64ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<12)|(144<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2487 = XCHG64ar
- { 2488, 7, 1, 0, "XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #2488 = XCHG64rm
- { 2489, 3, 1, 0, "XCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #2489 = XCHG64rr
- { 2490, 7, 1, 0, "XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(134<<24), NULL, NULL, NULL, OperandInfo22 }, // Inst #2490 = XCHG8rm
- { 2491, 3, 1, 0, "XCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(134<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2491 = XCHG8rr
- { 2492, 1, 0, 0, "XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2492 = XCH_F
- { 2493, 0, 0, 0, "XLAT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(215<<24), NULL, NULL, NULL, 0 }, // Inst #2493 = XLAT
- { 2494, 1, 0, 0, "XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2494 = XOR16i16
- { 2495, 6, 0, 0, "XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2495 = XOR16mi
- { 2496, 6, 0, 0, "XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2496 = XOR16mi8
- { 2497, 6, 0, 0, "XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2497 = XOR16mr
- { 2498, 3, 1, 0, "XOR16ri", 0, 0|22|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2498 = XOR16ri
- { 2499, 3, 1, 0, "XOR16ri8", 0, 0|22|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2499 = XOR16ri8
- { 2500, 7, 1, 0, "XOR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2500 = XOR16rm
- { 2501, 3, 1, 0, "XOR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2501 = XOR16rr
- { 2502, 3, 1, 0, "XOR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2502 = XOR16rr_REV
- { 2503, 1, 0, 0, "XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2503 = XOR32i32
- { 2504, 6, 0, 0, "XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2504 = XOR32mi
- { 2505, 6, 0, 0, "XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2505 = XOR32mi8
- { 2506, 6, 0, 0, "XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2506 = XOR32mr
- { 2507, 3, 1, 0, "XOR32ri", 0, 0|22|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2507 = XOR32ri
- { 2508, 3, 1, 0, "XOR32ri8", 0, 0|22|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2508 = XOR32ri8
- { 2509, 7, 1, 0, "XOR32rm", 0|(1<<TID::MayLoad), 0|6|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2509 = XOR32rm
- { 2510, 3, 1, 0, "XOR32rr", 0|(1<<TID::Commutable), 0|3|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2510 = XOR32rr
- { 2511, 3, 1, 0, "XOR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2511 = XOR32rr_REV
- { 2512, 1, 0, 0, "XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2512 = XOR64i32
- { 2513, 6, 0, 0, "XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2513 = XOR64mi32
- { 2514, 6, 0, 0, "XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2514 = XOR64mi8
- { 2515, 6, 0, 0, "XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2515 = XOR64mr
- { 2516, 3, 1, 0, "XOR64ri32", 0, 0|22|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2516 = XOR64ri32
- { 2517, 3, 1, 0, "XOR64ri8", 0, 0|22|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2517 = XOR64ri8
- { 2518, 7, 1, 0, "XOR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2518 = XOR64rm
- { 2519, 3, 1, 0, "XOR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2519 = XOR64rr
- { 2520, 3, 1, 0, "XOR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2520 = XOR64rr_REV
- { 2521, 1, 0, 0, "XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(52<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2521 = XOR8i8
- { 2522, 6, 0, 0, "XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2522 = XOR8mi
- { 2523, 6, 0, 0, "XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2523 = XOR8mr
- { 2524, 3, 1, 0, "XOR8ri", 0, 0|22|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2524 = XOR8ri
- { 2525, 7, 1, 0, "XOR8rm", 0|(1<<TID::MayLoad), 0|6|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2525 = XOR8rm
- { 2526, 3, 1, 0, "XOR8rr", 0|(1<<TID::Commutable), 0|3|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2526 = XOR8rr
- { 2527, 3, 1, 0, "XOR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2527 = XOR8rr_REV
- { 2528, 7, 1, 0, "XORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2528 = XORPDrm
- { 2529, 3, 1, 0, "XORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2529 = XORPDrr
- { 2530, 7, 1, 0, "XORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2530 = XORPSrm
- { 2531, 3, 1, 0, "XORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2531 = XORPSrr
+ { 1369, 6, 1, 0, "MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1369 = MOVQI2PQIrm
+ { 1370, 2, 1, 0, "MOVQxrxr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1370 = MOVQxrxr
+ { 1371, 0, 0, 0, "MOVSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(164<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1371 = MOVSB
+ { 1372, 0, 0, 0, "MOVSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(165<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1372 = MOVSD
+ { 1373, 6, 0, 0, "MOVSDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1373 = MOVSDmr
+ { 1374, 6, 1, 0, "MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1374 = MOVSDrm
+ { 1375, 3, 1, 0, "MOVSDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1375 = MOVSDrr
+ { 1376, 6, 0, 0, "MOVSDto64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1376 = MOVSDto64mr
+ { 1377, 2, 1, 0, "MOVSDto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #1377 = MOVSDto64rr
+ { 1378, 6, 1, 0, "MOVSHDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1378 = MOVSHDUPrm
+ { 1379, 2, 1, 0, "MOVSHDUPrr", 0, 0|5|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1379 = MOVSHDUPrr
+ { 1380, 6, 1, 0, "MOVSLDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1380 = MOVSLDUPrm
+ { 1381, 2, 1, 0, "MOVSLDUPrr", 0, 0|5|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1381 = MOVSLDUPrr
+ { 1382, 6, 0, 0, "MOVSS2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1382 = MOVSS2DImr
+ { 1383, 2, 1, 0, "MOVSS2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #1383 = MOVSS2DIrr
+ { 1384, 6, 0, 0, "MOVSSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1384 = MOVSSmr
+ { 1385, 6, 1, 0, "MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1385 = MOVSSrm
+ { 1386, 3, 1, 0, "MOVSSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1386 = MOVSSrr
+ { 1387, 0, 0, 0, "MOVSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(165<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1387 = MOVSW
+ { 1388, 6, 1, 0, "MOVSX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1388 = MOVSX16rm8
+ { 1389, 6, 1, 0, "MOVSX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1389 = MOVSX16rm8W
+ { 1390, 2, 1, 0, "MOVSX16rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1390 = MOVSX16rr8
+ { 1391, 2, 1, 0, "MOVSX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1391 = MOVSX16rr8W
+ { 1392, 6, 1, 0, "MOVSX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1392 = MOVSX32rm16
+ { 1393, 6, 1, 0, "MOVSX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1393 = MOVSX32rm8
+ { 1394, 2, 1, 0, "MOVSX32rr16", 0, 0|5|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1394 = MOVSX32rr16
+ { 1395, 2, 1, 0, "MOVSX32rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1395 = MOVSX32rr8
+ { 1396, 6, 1, 0, "MOVSX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1396 = MOVSX64rm16
+ { 1397, 6, 1, 0, "MOVSX64rm32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1397 = MOVSX64rm32
+ { 1398, 6, 1, 0, "MOVSX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1398 = MOVSX64rm8
+ { 1399, 2, 1, 0, "MOVSX64rr16", 0, 0|5|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1399 = MOVSX64rr16
+ { 1400, 2, 1, 0, "MOVSX64rr32", 0, 0|5|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1400 = MOVSX64rr32
+ { 1401, 2, 1, 0, "MOVSX64rr8", 0, 0|5|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1401 = MOVSX64rr8
+ { 1402, 6, 0, 0, "MOVUPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1402 = MOVUPDmr
+ { 1403, 6, 0, 0, "MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1403 = MOVUPDmr_Int
+ { 1404, 6, 1, 0, "MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1404 = MOVUPDrm
+ { 1405, 6, 1, 0, "MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1405 = MOVUPDrm_Int
+ { 1406, 2, 1, 0, "MOVUPDrr", 0, 0|5|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1406 = MOVUPDrr
+ { 1407, 6, 0, 0, "MOVUPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1407 = MOVUPSmr
+ { 1408, 6, 0, 0, "MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1408 = MOVUPSmr_Int
+ { 1409, 6, 1, 0, "MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1409 = MOVUPSrm
+ { 1410, 6, 1, 0, "MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1410 = MOVUPSrm_Int
+ { 1411, 2, 1, 0, "MOVUPSrr", 0, 0|5|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1411 = MOVUPSrr
+ { 1412, 6, 1, 0, "MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1412 = MOVZDI2PDIrm
+ { 1413, 2, 1, 0, "MOVZDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1413 = MOVZDI2PDIrr
+ { 1414, 6, 1, 0, "MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1414 = MOVZPQILo2PQIrm
+ { 1415, 2, 1, 0, "MOVZPQILo2PQIrr", 0, 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1415 = MOVZPQILo2PQIrr
+ { 1416, 6, 1, 0, "MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1416 = MOVZQI2PQIrm
+ { 1417, 2, 1, 0, "MOVZQI2PQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1417 = MOVZQI2PQIrr
+ { 1418, 6, 1, 0, "MOVZX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1418 = MOVZX16rm8
+ { 1419, 6, 1, 0, "MOVZX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1419 = MOVZX16rm8W
+ { 1420, 2, 1, 0, "MOVZX16rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1420 = MOVZX16rr8
+ { 1421, 2, 1, 0, "MOVZX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1421 = MOVZX16rr8W
+ { 1422, 6, 1, 0, "MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1422 = MOVZX32_NOREXrm8
+ { 1423, 2, 1, 0, "MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1423 = MOVZX32_NOREXrr8
+ { 1424, 6, 1, 0, "MOVZX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1424 = MOVZX32rm16
+ { 1425, 6, 1, 0, "MOVZX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1425 = MOVZX32rm8
+ { 1426, 2, 1, 0, "MOVZX32rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1426 = MOVZX32rr16
+ { 1427, 2, 1, 0, "MOVZX32rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1427 = MOVZX32rr8
+ { 1428, 6, 1, 0, "MOVZX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1428 = MOVZX64rm16
+ { 1429, 6, 1, 0, "MOVZX64rm16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1429 = MOVZX64rm16_Q
+ { 1430, 6, 1, 0, "MOVZX64rm32", 0|(1<<TID::MayLoad), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1430 = MOVZX64rm32
+ { 1431, 6, 1, 0, "MOVZX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1431 = MOVZX64rm8
+ { 1432, 6, 1, 0, "MOVZX64rm8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1432 = MOVZX64rm8_Q
+ { 1433, 2, 1, 0, "MOVZX64rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1433 = MOVZX64rr16
+ { 1434, 2, 1, 0, "MOVZX64rr16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1434 = MOVZX64rr16_Q
+ { 1435, 2, 1, 0, "MOVZX64rr32", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1435 = MOVZX64rr32
+ { 1436, 2, 1, 0, "MOVZX64rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1436 = MOVZX64rr8
+ { 1437, 2, 1, 0, "MOVZX64rr8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1437 = MOVZX64rr8_Q
+ { 1438, 2, 1, 0, "MOV_Fp3232", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #1438 = MOV_Fp3232
+ { 1439, 2, 1, 0, "MOV_Fp3264", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo176 }, // Inst #1439 = MOV_Fp3264
+ { 1440, 2, 1, 0, "MOV_Fp3280", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo177 }, // Inst #1440 = MOV_Fp3280
+ { 1441, 2, 1, 0, "MOV_Fp6432", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo178 }, // Inst #1441 = MOV_Fp6432
+ { 1442, 2, 1, 0, "MOV_Fp6464", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #1442 = MOV_Fp6464
+ { 1443, 2, 1, 0, "MOV_Fp6480", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo179 }, // Inst #1443 = MOV_Fp6480
+ { 1444, 2, 1, 0, "MOV_Fp8032", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo180 }, // Inst #1444 = MOV_Fp8032
+ { 1445, 2, 1, 0, "MOV_Fp8064", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo181 }, // Inst #1445 = MOV_Fp8064
+ { 1446, 2, 1, 0, "MOV_Fp8080", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #1446 = MOV_Fp8080
+ { 1447, 8, 1, 0, "MPSADBWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1447 = MPSADBWrmi
+ { 1448, 4, 1, 0, "MPSADBWrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1448 = MPSADBWrri
+ { 1449, 5, 0, 0, "MUL16m", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #1449 = MUL16m
+ { 1450, 1, 0, 0, "MUL16r", 0, 0|20|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #1450 = MUL16r
+ { 1451, 5, 0, 0, "MUL32m", 0|(1<<TID::MayLoad), 0|28|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #1451 = MUL32m
+ { 1452, 1, 0, 0, "MUL32r", 0, 0|20|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #1452 = MUL32r
+ { 1453, 5, 0, 0, "MUL64m", 0|(1<<TID::MayLoad), 0|28|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #1453 = MUL64m
+ { 1454, 1, 0, 0, "MUL64r", 0, 0|20|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #1454 = MUL64r
+ { 1455, 5, 0, 0, "MUL8m", 0|(1<<TID::MayLoad), 0|28|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #1455 = MUL8m
+ { 1456, 1, 0, 0, "MUL8r", 0, 0|20|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #1456 = MUL8r
+ { 1457, 7, 1, 0, "MULPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1457 = MULPDrm
+ { 1458, 3, 1, 0, "MULPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1458 = MULPDrr
+ { 1459, 7, 1, 0, "MULPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1459 = MULPSrm
+ { 1460, 3, 1, 0, "MULPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1460 = MULPSrr
+ { 1461, 7, 1, 0, "MULSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1461 = MULSDrm
+ { 1462, 7, 1, 0, "MULSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1462 = MULSDrm_Int
+ { 1463, 3, 1, 0, "MULSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1463 = MULSDrr
+ { 1464, 3, 1, 0, "MULSDrr_Int", 0, 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1464 = MULSDrr_Int
+ { 1465, 7, 1, 0, "MULSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1465 = MULSSrm
+ { 1466, 7, 1, 0, "MULSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1466 = MULSSrm_Int
+ { 1467, 3, 1, 0, "MULSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1467 = MULSSrr
+ { 1468, 3, 1, 0, "MULSSrr_Int", 0, 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1468 = MULSSrr_Int
+ { 1469, 5, 0, 0, "MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1469 = MUL_F32m
+ { 1470, 5, 0, 0, "MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1470 = MUL_F64m
+ { 1471, 5, 0, 0, "MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1471 = MUL_FI16m
+ { 1472, 5, 0, 0, "MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1472 = MUL_FI32m
+ { 1473, 1, 0, 0, "MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1473 = MUL_FPrST0
+ { 1474, 1, 0, 0, "MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1474 = MUL_FST0r
+ { 1475, 3, 1, 0, "MUL_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1475 = MUL_Fp32
+ { 1476, 7, 1, 0, "MUL_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1476 = MUL_Fp32m
+ { 1477, 3, 1, 0, "MUL_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1477 = MUL_Fp64
+ { 1478, 7, 1, 0, "MUL_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1478 = MUL_Fp64m
+ { 1479, 7, 1, 0, "MUL_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1479 = MUL_Fp64m32
+ { 1480, 3, 1, 0, "MUL_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1480 = MUL_Fp80
+ { 1481, 7, 1, 0, "MUL_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1481 = MUL_Fp80m32
+ { 1482, 7, 1, 0, "MUL_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1482 = MUL_Fp80m64
+ { 1483, 7, 1, 0, "MUL_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1483 = MUL_FpI16m32
+ { 1484, 7, 1, 0, "MUL_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1484 = MUL_FpI16m64
+ { 1485, 7, 1, 0, "MUL_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1485 = MUL_FpI16m80
+ { 1486, 7, 1, 0, "MUL_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1486 = MUL_FpI32m32
+ { 1487, 7, 1, 0, "MUL_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1487 = MUL_FpI32m64
+ { 1488, 7, 1, 0, "MUL_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1488 = MUL_FpI32m80
+ { 1489, 1, 0, 0, "MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1489 = MUL_FrST0
+ { 1490, 0, 0, 0, "MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|38|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1490 = MWAIT
+ { 1491, 5, 0, 0, "NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1491 = NEG16m
+ { 1492, 2, 1, 0, "NEG16r", 0, 0|19|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1492 = NEG16r
+ { 1493, 5, 0, 0, "NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1493 = NEG32m
+ { 1494, 2, 1, 0, "NEG32r", 0, 0|19|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1494 = NEG32r
+ { 1495, 5, 0, 0, "NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1495 = NEG64m
+ { 1496, 2, 1, 0, "NEG64r", 0, 0|19|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1496 = NEG64r
+ { 1497, 5, 0, 0, "NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1497 = NEG8m
+ { 1498, 2, 1, 0, "NEG8r", 0, 0|19|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1498 = NEG8r
+ { 1499, 0, 0, 0, "NOOP", 0, 0|1|(144<<24), NULL, NULL, NULL, 0 }, // Inst #1499 = NOOP
+ { 1500, 5, 0, 0, "NOOPL", 0, 0|24|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1500 = NOOPL
+ { 1501, 5, 0, 0, "NOOPW", 0, 0|24|(1<<6)|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1501 = NOOPW
+ { 1502, 5, 0, 0, "NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1502 = NOT16m
+ { 1503, 2, 1, 0, "NOT16r", 0, 0|18|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo91 }, // Inst #1503 = NOT16r
+ { 1504, 5, 0, 0, "NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1504 = NOT32m
+ { 1505, 2, 1, 0, "NOT32r", 0, 0|18|(247<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #1505 = NOT32r
+ { 1506, 5, 0, 0, "NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1506 = NOT64m
+ { 1507, 2, 1, 0, "NOT64r", 0, 0|18|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #1507 = NOT64r
+ { 1508, 5, 0, 0, "NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(246<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1508 = NOT8m
+ { 1509, 2, 1, 0, "NOT8r", 0, 0|18|(246<<24), NULL, NULL, NULL, OperandInfo92 }, // Inst #1509 = NOT8r
+ { 1510, 1, 0, 0, "OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1510 = OR16i16
+ { 1511, 6, 0, 0, "OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1511 = OR16mi
+ { 1512, 6, 0, 0, "OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1512 = OR16mi8
+ { 1513, 6, 0, 0, "OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1513 = OR16mr
+ { 1514, 3, 1, 0, "OR16ri", 0, 0|17|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1514 = OR16ri
+ { 1515, 3, 1, 0, "OR16ri8", 0, 0|17|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1515 = OR16ri8
+ { 1516, 7, 1, 0, "OR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1516 = OR16rm
+ { 1517, 3, 1, 0, "OR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1517 = OR16rr
+ { 1518, 3, 1, 0, "OR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1518 = OR16rr_REV
+ { 1519, 1, 0, 0, "OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1519 = OR32i32
+ { 1520, 6, 0, 0, "OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1520 = OR32mi
+ { 1521, 6, 0, 0, "OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1521 = OR32mi8
+ { 1522, 6, 0, 0, "OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1522 = OR32mr
+ { 1523, 3, 1, 0, "OR32ri", 0, 0|17|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1523 = OR32ri
+ { 1524, 3, 1, 0, "OR32ri8", 0, 0|17|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1524 = OR32ri8
+ { 1525, 7, 1, 0, "OR32rm", 0|(1<<TID::MayLoad), 0|6|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1525 = OR32rm
+ { 1526, 3, 1, 0, "OR32rr", 0|(1<<TID::Commutable), 0|3|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1526 = OR32rr
+ { 1527, 3, 1, 0, "OR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1527 = OR32rr_REV
+ { 1528, 1, 0, 0, "OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1528 = OR64i32
+ { 1529, 6, 0, 0, "OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1529 = OR64mi32
+ { 1530, 6, 0, 0, "OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1530 = OR64mi8
+ { 1531, 6, 0, 0, "OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1531 = OR64mr
+ { 1532, 3, 1, 0, "OR64ri32", 0, 0|17|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1532 = OR64ri32
+ { 1533, 3, 1, 0, "OR64ri8", 0, 0|17|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1533 = OR64ri8
+ { 1534, 7, 1, 0, "OR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1534 = OR64rm
+ { 1535, 3, 1, 0, "OR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1535 = OR64rr
+ { 1536, 3, 1, 0, "OR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1536 = OR64rr_REV
+ { 1537, 1, 0, 0, "OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(12<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1537 = OR8i8
+ { 1538, 6, 0, 0, "OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1538 = OR8mi
+ { 1539, 6, 0, 0, "OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1539 = OR8mr
+ { 1540, 3, 1, 0, "OR8ri", 0, 0|17|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1540 = OR8ri
+ { 1541, 7, 1, 0, "OR8rm", 0|(1<<TID::MayLoad), 0|6|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1541 = OR8rm
+ { 1542, 3, 1, 0, "OR8rr", 0|(1<<TID::Commutable), 0|3|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1542 = OR8rr
+ { 1543, 3, 1, 0, "OR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1543 = OR8rr_REV
+ { 1544, 7, 1, 0, "ORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1544 = ORPDrm
+ { 1545, 3, 1, 0, "ORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1545 = ORPDrr
+ { 1546, 7, 1, 0, "ORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1546 = ORPSrm
+ { 1547, 3, 1, 0, "ORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1547 = ORPSrr
+ { 1548, 1, 0, 0, "OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(231<<24), ImplicitList12, NULL, NULL, OperandInfo5 }, // Inst #1548 = OUT16ir
+ { 1549, 0, 0, 0, "OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(239<<24), ImplicitList39, NULL, NULL, 0 }, // Inst #1549 = OUT16rr
+ { 1550, 1, 0, 0, "OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(231<<24), ImplicitList13, NULL, NULL, OperandInfo5 }, // Inst #1550 = OUT32ir
+ { 1551, 0, 0, 0, "OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(239<<24), ImplicitList40, NULL, NULL, 0 }, // Inst #1551 = OUT32rr
+ { 1552, 1, 0, 0, "OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(230<<24), ImplicitList11, NULL, NULL, OperandInfo5 }, // Inst #1552 = OUT8ir
+ { 1553, 0, 0, 0, "OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(238<<24), ImplicitList41, NULL, NULL, 0 }, // Inst #1553 = OUT8rr
+ { 1554, 0, 0, 0, "OUTSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(110<<24), NULL, NULL, NULL, 0 }, // Inst #1554 = OUTSB
+ { 1555, 0, 0, 0, "OUTSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1555 = OUTSD
+ { 1556, 0, 0, 0, "OUTSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1556 = OUTSW
+ { 1557, 6, 1, 0, "PABSBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1557 = PABSBrm128
+ { 1558, 6, 1, 0, "PABSBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1558 = PABSBrm64
+ { 1559, 2, 1, 0, "PABSBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1559 = PABSBrr128
+ { 1560, 2, 1, 0, "PABSBrr64", 0, 0|5|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1560 = PABSBrr64
+ { 1561, 6, 1, 0, "PABSDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1561 = PABSDrm128
+ { 1562, 6, 1, 0, "PABSDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1562 = PABSDrm64
+ { 1563, 2, 1, 0, "PABSDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1563 = PABSDrr128
+ { 1564, 2, 1, 0, "PABSDrr64", 0, 0|5|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1564 = PABSDrr64
+ { 1565, 6, 1, 0, "PABSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1565 = PABSWrm128
+ { 1566, 6, 1, 0, "PABSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1566 = PABSWrm64
+ { 1567, 2, 1, 0, "PABSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1567 = PABSWrr128
+ { 1568, 2, 1, 0, "PABSWrr64", 0, 0|5|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1568 = PABSWrr64
+ { 1569, 7, 1, 0, "PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1569 = PACKSSDWrm
+ { 1570, 3, 1, 0, "PACKSSDWrr", 0, 0|5|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1570 = PACKSSDWrr
+ { 1571, 7, 1, 0, "PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1571 = PACKSSWBrm
+ { 1572, 3, 1, 0, "PACKSSWBrr", 0, 0|5|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1572 = PACKSSWBrr
+ { 1573, 7, 1, 0, "PACKUSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1573 = PACKUSDWrm
+ { 1574, 3, 1, 0, "PACKUSDWrr", 0, 0|5|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1574 = PACKUSDWrr
+ { 1575, 7, 1, 0, "PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1575 = PACKUSWBrm
+ { 1576, 3, 1, 0, "PACKUSWBrr", 0, 0|5|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1576 = PACKUSWBrr
+ { 1577, 7, 1, 0, "PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1577 = PADDBrm
+ { 1578, 3, 1, 0, "PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1578 = PADDBrr
+ { 1579, 7, 1, 0, "PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1579 = PADDDrm
+ { 1580, 3, 1, 0, "PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1580 = PADDDrr
+ { 1581, 7, 1, 0, "PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1581 = PADDQrm
+ { 1582, 3, 1, 0, "PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1582 = PADDQrr
+ { 1583, 7, 1, 0, "PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1583 = PADDSBrm
+ { 1584, 3, 1, 0, "PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1584 = PADDSBrr
+ { 1585, 7, 1, 0, "PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1585 = PADDSWrm
+ { 1586, 3, 1, 0, "PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1586 = PADDSWrr
+ { 1587, 7, 1, 0, "PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1587 = PADDUSBrm
+ { 1588, 3, 1, 0, "PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1588 = PADDUSBrr
+ { 1589, 7, 1, 0, "PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1589 = PADDUSWrm
+ { 1590, 3, 1, 0, "PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1590 = PADDUSWrr
+ { 1591, 7, 1, 0, "PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1591 = PADDWrm
+ { 1592, 3, 1, 0, "PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1592 = PADDWrr
+ { 1593, 8, 1, 0, "PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1593 = PALIGNR128rm
+ { 1594, 4, 1, 0, "PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1594 = PALIGNR128rr
+ { 1595, 8, 1, 0, "PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1595 = PALIGNR64rm
+ { 1596, 4, 1, 0, "PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo182 }, // Inst #1596 = PALIGNR64rr
+ { 1597, 7, 1, 0, "PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1597 = PANDNrm
+ { 1598, 3, 1, 0, "PANDNrr", 0, 0|5|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1598 = PANDNrr
+ { 1599, 7, 1, 0, "PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1599 = PANDrm
+ { 1600, 3, 1, 0, "PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1600 = PANDrr
+ { 1601, 7, 1, 0, "PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1601 = PAVGBrm
+ { 1602, 3, 1, 0, "PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1602 = PAVGBrr
+ { 1603, 7, 1, 0, "PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1603 = PAVGWrm
+ { 1604, 3, 1, 0, "PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1604 = PAVGWrr
+ { 1605, 7, 1, 0, "PBLENDVBrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #1605 = PBLENDVBrm0
+ { 1606, 3, 1, 0, "PBLENDVBrr0", 0, 0|5|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #1606 = PBLENDVBrr0
+ { 1607, 8, 1, 0, "PBLENDWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1607 = PBLENDWrmi
+ { 1608, 4, 1, 0, "PBLENDWrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1608 = PBLENDWrri
+ { 1609, 7, 1, 0, "PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1609 = PCMPEQBrm
+ { 1610, 3, 1, 0, "PCMPEQBrr", 0, 0|5|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1610 = PCMPEQBrr
+ { 1611, 7, 1, 0, "PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1611 = PCMPEQDrm
+ { 1612, 3, 1, 0, "PCMPEQDrr", 0, 0|5|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1612 = PCMPEQDrr
+ { 1613, 7, 1, 0, "PCMPEQQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1613 = PCMPEQQrm
+ { 1614, 3, 1, 0, "PCMPEQQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1614 = PCMPEQQrr
+ { 1615, 7, 1, 0, "PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1615 = PCMPEQWrm
+ { 1616, 3, 1, 0, "PCMPEQWrr", 0, 0|5|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1616 = PCMPEQWrr
+ { 1617, 7, 0, 0, "PCMPESTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1617 = PCMPESTRIArm
+ { 1618, 3, 0, 0, "PCMPESTRIArr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1618 = PCMPESTRIArr
+ { 1619, 7, 0, 0, "PCMPESTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1619 = PCMPESTRICrm
+ { 1620, 3, 0, 0, "PCMPESTRICrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1620 = PCMPESTRICrr
+ { 1621, 7, 0, 0, "PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1621 = PCMPESTRIOrm
+ { 1622, 3, 0, 0, "PCMPESTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1622 = PCMPESTRIOrr
+ { 1623, 7, 0, 0, "PCMPESTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1623 = PCMPESTRISrm
+ { 1624, 3, 0, 0, "PCMPESTRISrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1624 = PCMPESTRISrr
+ { 1625, 7, 0, 0, "PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1625 = PCMPESTRIZrm
+ { 1626, 3, 0, 0, "PCMPESTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1626 = PCMPESTRIZrr
+ { 1627, 7, 0, 0, "PCMPESTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1627 = PCMPESTRIrm
+ { 1628, 3, 0, 0, "PCMPESTRIrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1628 = PCMPESTRIrr
+ { 1629, 8, 1, 0, "PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1629 = PCMPESTRM128MEM
+ { 1630, 4, 1, 0, "PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1630 = PCMPESTRM128REG
+ { 1631, 7, 0, 0, "PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList43, Barriers1, OperandInfo183 }, // Inst #1631 = PCMPESTRM128rm
+ { 1632, 3, 0, 0, "PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList43, Barriers1, OperandInfo184 }, // Inst #1632 = PCMPESTRM128rr
+ { 1633, 7, 1, 0, "PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1633 = PCMPGTBrm
+ { 1634, 3, 1, 0, "PCMPGTBrr", 0, 0|5|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1634 = PCMPGTBrr
+ { 1635, 7, 1, 0, "PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1635 = PCMPGTDrm
+ { 1636, 3, 1, 0, "PCMPGTDrr", 0, 0|5|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1636 = PCMPGTDrr
+ { 1637, 7, 1, 0, "PCMPGTQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1637 = PCMPGTQrm
+ { 1638, 3, 1, 0, "PCMPGTQrr", 0, 0|5|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1638 = PCMPGTQrr
+ { 1639, 7, 1, 0, "PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1639 = PCMPGTWrm
+ { 1640, 3, 1, 0, "PCMPGTWrr", 0, 0|5|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1640 = PCMPGTWrr
+ { 1641, 7, 0, 0, "PCMPISTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1641 = PCMPISTRIArm
+ { 1642, 3, 0, 0, "PCMPISTRIArr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1642 = PCMPISTRIArr
+ { 1643, 7, 0, 0, "PCMPISTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1643 = PCMPISTRICrm
+ { 1644, 3, 0, 0, "PCMPISTRICrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1644 = PCMPISTRICrr
+ { 1645, 7, 0, 0, "PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1645 = PCMPISTRIOrm
+ { 1646, 3, 0, 0, "PCMPISTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1646 = PCMPISTRIOrr
+ { 1647, 7, 0, 0, "PCMPISTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1647 = PCMPISTRISrm
+ { 1648, 3, 0, 0, "PCMPISTRISrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1648 = PCMPISTRISrr
+ { 1649, 7, 0, 0, "PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1649 = PCMPISTRIZrm
+ { 1650, 3, 0, 0, "PCMPISTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1650 = PCMPISTRIZrr
+ { 1651, 7, 0, 0, "PCMPISTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1651 = PCMPISTRIrm
+ { 1652, 3, 0, 0, "PCMPISTRIrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1652 = PCMPISTRIrr
+ { 1653, 8, 1, 0, "PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1653 = PCMPISTRM128MEM
+ { 1654, 4, 1, 0, "PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1654 = PCMPISTRM128REG
+ { 1655, 7, 0, 0, "PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList43, Barriers1, OperandInfo183 }, // Inst #1655 = PCMPISTRM128rm
+ { 1656, 3, 0, 0, "PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList43, Barriers1, OperandInfo184 }, // Inst #1656 = PCMPISTRM128rr
+ { 1657, 7, 0, 0, "PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1657 = PEXTRBmr
+ { 1658, 3, 1, 0, "PEXTRBrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1658 = PEXTRBrr
+ { 1659, 7, 0, 0, "PEXTRDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1659 = PEXTRDmr
+ { 1660, 3, 1, 0, "PEXTRDrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1660 = PEXTRDrr
+ { 1661, 7, 0, 0, "PEXTRQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1661 = PEXTRQmr
+ { 1662, 3, 1, 0, "PEXTRQrr", 0, 0|3|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo186 }, // Inst #1662 = PEXTRQrr
+ { 1663, 7, 0, 0, "PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(21<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1663 = PEXTRWmr
+ { 1664, 3, 1, 0, "PEXTRWri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1664 = PEXTRWri
+ { 1665, 7, 1, 0, "PHADDDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1665 = PHADDDrm128
+ { 1666, 7, 1, 0, "PHADDDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1666 = PHADDDrm64
+ { 1667, 3, 1, 0, "PHADDDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1667 = PHADDDrr128
+ { 1668, 3, 1, 0, "PHADDDrr64", 0, 0|5|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1668 = PHADDDrr64
+ { 1669, 7, 1, 0, "PHADDSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1669 = PHADDSWrm128
+ { 1670, 7, 1, 0, "PHADDSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1670 = PHADDSWrm64
+ { 1671, 3, 1, 0, "PHADDSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1671 = PHADDSWrr128
+ { 1672, 3, 1, 0, "PHADDSWrr64", 0, 0|5|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1672 = PHADDSWrr64
+ { 1673, 7, 1, 0, "PHADDWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1673 = PHADDWrm128
+ { 1674, 7, 1, 0, "PHADDWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1674 = PHADDWrm64
+ { 1675, 3, 1, 0, "PHADDWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1675 = PHADDWrr128
+ { 1676, 3, 1, 0, "PHADDWrr64", 0, 0|5|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1676 = PHADDWrr64
+ { 1677, 6, 1, 0, "PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1677 = PHMINPOSUWrm128
+ { 1678, 2, 1, 0, "PHMINPOSUWrr128", 0, 0|5|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1678 = PHMINPOSUWrr128
+ { 1679, 7, 1, 0, "PHSUBDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1679 = PHSUBDrm128
+ { 1680, 7, 1, 0, "PHSUBDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1680 = PHSUBDrm64
+ { 1681, 3, 1, 0, "PHSUBDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1681 = PHSUBDrr128
+ { 1682, 3, 1, 0, "PHSUBDrr64", 0, 0|5|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1682 = PHSUBDrr64
+ { 1683, 7, 1, 0, "PHSUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1683 = PHSUBSWrm128
+ { 1684, 7, 1, 0, "PHSUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1684 = PHSUBSWrm64
+ { 1685, 3, 1, 0, "PHSUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1685 = PHSUBSWrr128
+ { 1686, 3, 1, 0, "PHSUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1686 = PHSUBSWrr64
+ { 1687, 7, 1, 0, "PHSUBWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1687 = PHSUBWrm128
+ { 1688, 7, 1, 0, "PHSUBWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1688 = PHSUBWrm64
+ { 1689, 3, 1, 0, "PHSUBWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1689 = PHSUBWrr128
+ { 1690, 3, 1, 0, "PHSUBWrr64", 0, 0|5|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1690 = PHSUBWrr64
+ { 1691, 8, 1, 0, "PINSRBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1691 = PINSRBrm
+ { 1692, 4, 1, 0, "PINSRBrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1692 = PINSRBrr
+ { 1693, 8, 1, 0, "PINSRDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1693 = PINSRDrm
+ { 1694, 4, 1, 0, "PINSRDrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1694 = PINSRDrr
+ { 1695, 8, 1, 0, "PINSRQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1695 = PINSRQrm
+ { 1696, 4, 1, 0, "PINSRQrr", 0, 0|5|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1696 = PINSRQrr
+ { 1697, 8, 1, 0, "PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1697 = PINSRWrmi
+ { 1698, 4, 1, 0, "PINSRWrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1698 = PINSRWrri
+ { 1699, 7, 1, 0, "PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1699 = PMADDUBSWrm128
+ { 1700, 7, 1, 0, "PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1700 = PMADDUBSWrm64
+ { 1701, 3, 1, 0, "PMADDUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1701 = PMADDUBSWrr128
+ { 1702, 3, 1, 0, "PMADDUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1702 = PMADDUBSWrr64
+ { 1703, 7, 1, 0, "PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1703 = PMADDWDrm
+ { 1704, 3, 1, 0, "PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1704 = PMADDWDrr
+ { 1705, 7, 1, 0, "PMAXSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1705 = PMAXSBrm
+ { 1706, 3, 1, 0, "PMAXSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1706 = PMAXSBrr
+ { 1707, 7, 1, 0, "PMAXSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1707 = PMAXSDrm
+ { 1708, 3, 1, 0, "PMAXSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1708 = PMAXSDrr
+ { 1709, 7, 1, 0, "PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1709 = PMAXSWrm
+ { 1710, 3, 1, 0, "PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1710 = PMAXSWrr
+ { 1711, 7, 1, 0, "PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1711 = PMAXUBrm
+ { 1712, 3, 1, 0, "PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1712 = PMAXUBrr
+ { 1713, 7, 1, 0, "PMAXUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1713 = PMAXUDrm
+ { 1714, 3, 1, 0, "PMAXUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1714 = PMAXUDrr
+ { 1715, 7, 1, 0, "PMAXUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1715 = PMAXUWrm
+ { 1716, 3, 1, 0, "PMAXUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1716 = PMAXUWrr
+ { 1717, 7, 1, 0, "PMINSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1717 = PMINSBrm
+ { 1718, 3, 1, 0, "PMINSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1718 = PMINSBrr
+ { 1719, 7, 1, 0, "PMINSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1719 = PMINSDrm
+ { 1720, 3, 1, 0, "PMINSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1720 = PMINSDrr
+ { 1721, 7, 1, 0, "PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1721 = PMINSWrm
+ { 1722, 3, 1, 0, "PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1722 = PMINSWrr
+ { 1723, 7, 1, 0, "PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1723 = PMINUBrm
+ { 1724, 3, 1, 0, "PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1724 = PMINUBrr
+ { 1725, 7, 1, 0, "PMINUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1725 = PMINUDrm
+ { 1726, 3, 1, 0, "PMINUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1726 = PMINUDrr
+ { 1727, 7, 1, 0, "PMINUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1727 = PMINUWrm
+ { 1728, 3, 1, 0, "PMINUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1728 = PMINUWrr
+ { 1729, 2, 1, 0, "PMOVMSKBrr", 0, 0|5|(1<<6)|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1729 = PMOVMSKBrr
+ { 1730, 6, 1, 0, "PMOVSXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1730 = PMOVSXBDrm
+ { 1731, 2, 1, 0, "PMOVSXBDrr", 0, 0|5|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1731 = PMOVSXBDrr
+ { 1732, 6, 1, 0, "PMOVSXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1732 = PMOVSXBQrm
+ { 1733, 2, 1, 0, "PMOVSXBQrr", 0, 0|5|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1733 = PMOVSXBQrr
+ { 1734, 6, 1, 0, "PMOVSXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1734 = PMOVSXBWrm
+ { 1735, 2, 1, 0, "PMOVSXBWrr", 0, 0|5|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1735 = PMOVSXBWrr
+ { 1736, 6, 1, 0, "PMOVSXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1736 = PMOVSXDQrm
+ { 1737, 2, 1, 0, "PMOVSXDQrr", 0, 0|5|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1737 = PMOVSXDQrr
+ { 1738, 6, 1, 0, "PMOVSXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1738 = PMOVSXWDrm
+ { 1739, 2, 1, 0, "PMOVSXWDrr", 0, 0|5|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1739 = PMOVSXWDrr
+ { 1740, 6, 1, 0, "PMOVSXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1740 = PMOVSXWQrm
+ { 1741, 2, 1, 0, "PMOVSXWQrr", 0, 0|5|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1741 = PMOVSXWQrr
+ { 1742, 6, 1, 0, "PMOVZXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1742 = PMOVZXBDrm
+ { 1743, 2, 1, 0, "PMOVZXBDrr", 0, 0|5|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1743 = PMOVZXBDrr
+ { 1744, 6, 1, 0, "PMOVZXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1744 = PMOVZXBQrm
+ { 1745, 2, 1, 0, "PMOVZXBQrr", 0, 0|5|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1745 = PMOVZXBQrr
+ { 1746, 6, 1, 0, "PMOVZXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1746 = PMOVZXBWrm
+ { 1747, 2, 1, 0, "PMOVZXBWrr", 0, 0|5|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1747 = PMOVZXBWrr
+ { 1748, 6, 1, 0, "PMOVZXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1748 = PMOVZXDQrm
+ { 1749, 2, 1, 0, "PMOVZXDQrr", 0, 0|5|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1749 = PMOVZXDQrr
+ { 1750, 6, 1, 0, "PMOVZXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1750 = PMOVZXWDrm
+ { 1751, 2, 1, 0, "PMOVZXWDrr", 0, 0|5|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1751 = PMOVZXWDrr
+ { 1752, 6, 1, 0, "PMOVZXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1752 = PMOVZXWQrm
+ { 1753, 2, 1, 0, "PMOVZXWQrr", 0, 0|5|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1753 = PMOVZXWQrr
+ { 1754, 7, 1, 0, "PMULDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1754 = PMULDQrm
+ { 1755, 3, 1, 0, "PMULDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1755 = PMULDQrr
+ { 1756, 7, 1, 0, "PMULHRSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1756 = PMULHRSWrm128
+ { 1757, 7, 1, 0, "PMULHRSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1757 = PMULHRSWrm64
+ { 1758, 3, 1, 0, "PMULHRSWrr128", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1758 = PMULHRSWrr128
+ { 1759, 3, 1, 0, "PMULHRSWrr64", 0|(1<<TID::Commutable), 0|5|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1759 = PMULHRSWrr64
+ { 1760, 7, 1, 0, "PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1760 = PMULHUWrm
+ { 1761, 3, 1, 0, "PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1761 = PMULHUWrr
+ { 1762, 7, 1, 0, "PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1762 = PMULHWrm
+ { 1763, 3, 1, 0, "PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1763 = PMULHWrr
+ { 1764, 7, 1, 0, "PMULLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1764 = PMULLDrm
+ { 1765, 7, 1, 0, "PMULLDrm_int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1765 = PMULLDrm_int
+ { 1766, 3, 1, 0, "PMULLDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1766 = PMULLDrr
+ { 1767, 3, 1, 0, "PMULLDrr_int", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1767 = PMULLDrr_int
+ { 1768, 7, 1, 0, "PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1768 = PMULLWrm
+ { 1769, 3, 1, 0, "PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1769 = PMULLWrr
+ { 1770, 7, 1, 0, "PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1770 = PMULUDQrm
+ { 1771, 3, 1, 0, "PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1771 = PMULUDQrr
+ { 1772, 1, 1, 0, "POP16r", 0|(1<<TID::MayLoad), 0|2|(1<<6)|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1772 = POP16r
+ { 1773, 5, 1, 0, "POP16rmm", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1773 = POP16rmm
+ { 1774, 1, 1, 0, "POP16rmr", 0|(1<<TID::MayLoad), 0|16|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1774 = POP16rmr
+ { 1775, 1, 1, 0, "POP32r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1775 = POP32r
+ { 1776, 5, 1, 0, "POP32rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1776 = POP32rmm
+ { 1777, 1, 1, 0, "POP32rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1777 = POP32rmr
+ { 1778, 1, 1, 0, "POP64r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1778 = POP64r
+ { 1779, 5, 1, 0, "POP64rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1779 = POP64rmm
+ { 1780, 1, 1, 0, "POP64rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1780 = POP64rmr
+ { 1781, 6, 1, 0, "POPCNT16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1781 = POPCNT16rm
+ { 1782, 2, 1, 0, "POPCNT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1782 = POPCNT16rr
+ { 1783, 6, 1, 0, "POPCNT32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1783 = POPCNT32rm
+ { 1784, 2, 1, 0, "POPCNT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1784 = POPCNT32rr
+ { 1785, 6, 1, 0, "POPCNT64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1785 = POPCNT64rm
+ { 1786, 2, 1, 0, "POPCNT64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1786 = POPCNT64rr
+ { 1787, 0, 0, 0, "POPF", 0|(1<<TID::MayLoad), 0|1|(1<<6)|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1787 = POPF
+ { 1788, 0, 0, 0, "POPFD", 0|(1<<TID::MayLoad), 0|1|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1788 = POPFD
+ { 1789, 0, 0, 0, "POPFQ", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(157<<24), ImplicitList4, ImplicitList5, Barriers1, 0 }, // Inst #1789 = POPFQ
+ { 1790, 0, 0, 0, "POPFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1790 = POPFS16
+ { 1791, 0, 0, 0, "POPFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1791 = POPFS32
+ { 1792, 0, 0, 0, "POPFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1792 = POPFS64
+ { 1793, 0, 0, 0, "POPGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1793 = POPGS16
+ { 1794, 0, 0, 0, "POPGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1794 = POPGS32
+ { 1795, 0, 0, 0, "POPGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1795 = POPGS64
+ { 1796, 7, 1, 0, "PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1796 = PORrm
+ { 1797, 3, 1, 0, "PORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1797 = PORrr
+ { 1798, 5, 0, 0, "PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1798 = PREFETCHNTA
+ { 1799, 5, 0, 0, "PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1799 = PREFETCHT0
+ { 1800, 5, 0, 0, "PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1800 = PREFETCHT1
+ { 1801, 5, 0, 0, "PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1801 = PREFETCHT2
+ { 1802, 7, 1, 0, "PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1802 = PSADBWrm
+ { 1803, 3, 1, 0, "PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1803 = PSADBWrr
+ { 1804, 7, 1, 0, "PSHUFBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo24 }, // Inst #1804 = PSHUFBrm128
+ { 1805, 7, 1, 0, "PSHUFBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo136 }, // Inst #1805 = PSHUFBrm64
+ { 1806, 3, 1, 0, "PSHUFBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo25 }, // Inst #1806 = PSHUFBrr128
+ { 1807, 3, 1, 0, "PSHUFBrr64", 0, 0|5|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo137 }, // Inst #1807 = PSHUFBrr64
+ { 1808, 7, 1, 0, "PSHUFDmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1808 = PSHUFDmi
+ { 1809, 3, 1, 0, "PSHUFDri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1809 = PSHUFDri
+ { 1810, 7, 1, 0, "PSHUFHWmi", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1810 = PSHUFHWmi
+ { 1811, 3, 1, 0, "PSHUFHWri", 0, 0|5|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1811 = PSHUFHWri
+ { 1812, 7, 1, 0, "PSHUFLWmi", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1812 = PSHUFLWmi
+ { 1813, 3, 1, 0, "PSHUFLWri", 0, 0|5|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1813 = PSHUFLWri
+ { 1814, 7, 1, 0, "PSIGNBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1814 = PSIGNBrm128
+ { 1815, 7, 1, 0, "PSIGNBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1815 = PSIGNBrm64
+ { 1816, 3, 1, 0, "PSIGNBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1816 = PSIGNBrr128
+ { 1817, 3, 1, 0, "PSIGNBrr64", 0, 0|5|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1817 = PSIGNBrr64
+ { 1818, 7, 1, 0, "PSIGNDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1818 = PSIGNDrm128
+ { 1819, 7, 1, 0, "PSIGNDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1819 = PSIGNDrm64
+ { 1820, 3, 1, 0, "PSIGNDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1820 = PSIGNDrr128
+ { 1821, 3, 1, 0, "PSIGNDrr64", 0, 0|5|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1821 = PSIGNDrr64
+ { 1822, 7, 1, 0, "PSIGNWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1822 = PSIGNWrm128
+ { 1823, 7, 1, 0, "PSIGNWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1823 = PSIGNWrm64
+ { 1824, 3, 1, 0, "PSIGNWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1824 = PSIGNWrr128
+ { 1825, 3, 1, 0, "PSIGNWrr64", 0, 0|5|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1825 = PSIGNWrr64
+ { 1826, 3, 1, 0, "PSLLDQri", 0, 0|23|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1826 = PSLLDQri
+ { 1827, 3, 1, 0, "PSLLDri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1827 = PSLLDri
+ { 1828, 7, 1, 0, "PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1828 = PSLLDrm
+ { 1829, 3, 1, 0, "PSLLDrr", 0, 0|5|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1829 = PSLLDrr
+ { 1830, 3, 1, 0, "PSLLQri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1830 = PSLLQri
+ { 1831, 7, 1, 0, "PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1831 = PSLLQrm
+ { 1832, 3, 1, 0, "PSLLQrr", 0, 0|5|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1832 = PSLLQrr
+ { 1833, 3, 1, 0, "PSLLWri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1833 = PSLLWri
+ { 1834, 7, 1, 0, "PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1834 = PSLLWrm
+ { 1835, 3, 1, 0, "PSLLWrr", 0, 0|5|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1835 = PSLLWrr
+ { 1836, 3, 1, 0, "PSRADri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1836 = PSRADri
+ { 1837, 7, 1, 0, "PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1837 = PSRADrm
+ { 1838, 3, 1, 0, "PSRADrr", 0, 0|5|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1838 = PSRADrr
+ { 1839, 3, 1, 0, "PSRAWri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1839 = PSRAWri
+ { 1840, 7, 1, 0, "PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1840 = PSRAWrm
+ { 1841, 3, 1, 0, "PSRAWrr", 0, 0|5|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1841 = PSRAWrr
+ { 1842, 3, 1, 0, "PSRLDQri", 0, 0|19|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1842 = PSRLDQri
+ { 1843, 3, 1, 0, "PSRLDri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1843 = PSRLDri
+ { 1844, 7, 1, 0, "PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1844 = PSRLDrm
+ { 1845, 3, 1, 0, "PSRLDrr", 0, 0|5|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1845 = PSRLDrr
+ { 1846, 3, 1, 0, "PSRLQri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1846 = PSRLQri
+ { 1847, 7, 1, 0, "PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1847 = PSRLQrm
+ { 1848, 3, 1, 0, "PSRLQrr", 0, 0|5|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1848 = PSRLQrr
+ { 1849, 3, 1, 0, "PSRLWri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1849 = PSRLWri
+ { 1850, 7, 1, 0, "PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1850 = PSRLWrm
+ { 1851, 3, 1, 0, "PSRLWrr", 0, 0|5|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1851 = PSRLWrr
+ { 1852, 7, 1, 0, "PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1852 = PSUBBrm
+ { 1853, 3, 1, 0, "PSUBBrr", 0, 0|5|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1853 = PSUBBrr
+ { 1854, 7, 1, 0, "PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1854 = PSUBDrm
+ { 1855, 3, 1, 0, "PSUBDrr", 0, 0|5|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1855 = PSUBDrr
+ { 1856, 7, 1, 0, "PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1856 = PSUBQrm
+ { 1857, 3, 1, 0, "PSUBQrr", 0, 0|5|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1857 = PSUBQrr
+ { 1858, 7, 1, 0, "PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1858 = PSUBSBrm
+ { 1859, 3, 1, 0, "PSUBSBrr", 0, 0|5|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1859 = PSUBSBrr
+ { 1860, 7, 1, 0, "PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1860 = PSUBSWrm
+ { 1861, 3, 1, 0, "PSUBSWrr", 0, 0|5|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1861 = PSUBSWrr
+ { 1862, 7, 1, 0, "PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1862 = PSUBUSBrm
+ { 1863, 3, 1, 0, "PSUBUSBrr", 0, 0|5|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1863 = PSUBUSBrr
+ { 1864, 7, 1, 0, "PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1864 = PSUBUSWrm
+ { 1865, 3, 1, 0, "PSUBUSWrr", 0, 0|5|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1865 = PSUBUSWrr
+ { 1866, 7, 1, 0, "PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1866 = PSUBWrm
+ { 1867, 3, 1, 0, "PSUBWrr", 0, 0|5|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1867 = PSUBWrr
+ { 1868, 6, 0, 0, "PTESTrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #1868 = PTESTrm
+ { 1869, 2, 0, 0, "PTESTrr", 0, 0|5|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #1869 = PTESTrr
+ { 1870, 7, 1, 0, "PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1870 = PUNPCKHBWrm
+ { 1871, 3, 1, 0, "PUNPCKHBWrr", 0, 0|5|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1871 = PUNPCKHBWrr
+ { 1872, 7, 1, 0, "PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1872 = PUNPCKHDQrm
+ { 1873, 3, 1, 0, "PUNPCKHDQrr", 0, 0|5|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1873 = PUNPCKHDQrr
+ { 1874, 7, 1, 0, "PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1874 = PUNPCKHQDQrm
+ { 1875, 3, 1, 0, "PUNPCKHQDQrr", 0, 0|5|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1875 = PUNPCKHQDQrr
+ { 1876, 7, 1, 0, "PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1876 = PUNPCKHWDrm
+ { 1877, 3, 1, 0, "PUNPCKHWDrr", 0, 0|5|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1877 = PUNPCKHWDrr
+ { 1878, 7, 1, 0, "PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1878 = PUNPCKLBWrm
+ { 1879, 3, 1, 0, "PUNPCKLBWrr", 0, 0|5|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1879 = PUNPCKLBWrr
+ { 1880, 7, 1, 0, "PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1880 = PUNPCKLDQrm
+ { 1881, 3, 1, 0, "PUNPCKLDQrr", 0, 0|5|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1881 = PUNPCKLDQrr
+ { 1882, 7, 1, 0, "PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1882 = PUNPCKLQDQrm
+ { 1883, 3, 1, 0, "PUNPCKLQDQrr", 0, 0|5|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1883 = PUNPCKLQDQrr
+ { 1884, 7, 1, 0, "PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1884 = PUNPCKLWDrm
+ { 1885, 3, 1, 0, "PUNPCKLWDrr", 0, 0|5|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1885 = PUNPCKLWDrr
+ { 1886, 1, 0, 0, "PUSH16r", 0|(1<<TID::MayStore), 0|2|(1<<6)|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1886 = PUSH16r
+ { 1887, 5, 0, 0, "PUSH16rmm", 0|(1<<TID::MayStore), 0|30|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1887 = PUSH16rmm
+ { 1888, 1, 0, 0, "PUSH16rmr", 0|(1<<TID::MayStore), 0|22|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1888 = PUSH16rmr
+ { 1889, 1, 0, 0, "PUSH32i16", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1889 = PUSH32i16
+ { 1890, 1, 0, 0, "PUSH32i32", 0|(1<<TID::MayStore), 0|1|(4<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1890 = PUSH32i32
+ { 1891, 1, 0, 0, "PUSH32i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1891 = PUSH32i8
+ { 1892, 1, 0, 0, "PUSH32r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1892 = PUSH32r
+ { 1893, 5, 0, 0, "PUSH32rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1893 = PUSH32rmm
+ { 1894, 1, 0, 0, "PUSH32rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1894 = PUSH32rmr
+ { 1895, 1, 0, 0, "PUSH64i16", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1895 = PUSH64i16
+ { 1896, 1, 0, 0, "PUSH64i32", 0|(1<<TID::MayStore), 0|1|(4<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1896 = PUSH64i32
+ { 1897, 1, 0, 0, "PUSH64i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1897 = PUSH64i8
+ { 1898, 1, 0, 0, "PUSH64r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1898 = PUSH64r
+ { 1899, 5, 0, 0, "PUSH64rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1899 = PUSH64rmm
+ { 1900, 1, 0, 0, "PUSH64rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1900 = PUSH64rmr
+ { 1901, 0, 0, 0, "PUSHF", 0|(1<<TID::MayStore), 0|1|(1<<6)|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1901 = PUSHF
+ { 1902, 0, 0, 0, "PUSHFD", 0|(1<<TID::MayStore), 0|1|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1902 = PUSHFD
+ { 1903, 0, 0, 0, "PUSHFQ64", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(156<<24), ImplicitList5, ImplicitList4, NULL, 0 }, // Inst #1903 = PUSHFQ64
+ { 1904, 0, 0, 0, "PUSHFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1904 = PUSHFS16
+ { 1905, 0, 0, 0, "PUSHFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1905 = PUSHFS32
+ { 1906, 0, 0, 0, "PUSHFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1906 = PUSHFS64
+ { 1907, 0, 0, 0, "PUSHGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1907 = PUSHGS16
+ { 1908, 0, 0, 0, "PUSHGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1908 = PUSHGS32
+ { 1909, 0, 0, 0, "PUSHGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1909 = PUSHGS64
+ { 1910, 7, 1, 0, "PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1910 = PXORrm
+ { 1911, 3, 1, 0, "PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1911 = PXORrr
+ { 1912, 5, 0, 0, "RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1912 = RCL16m1
+ { 1913, 5, 0, 0, "RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1913 = RCL16mCL
+ { 1914, 6, 0, 0, "RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1914 = RCL16mi
+ { 1915, 2, 1, 0, "RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1915 = RCL16r1
+ { 1916, 2, 1, 0, "RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1916 = RCL16rCL
+ { 1917, 3, 1, 0, "RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1917 = RCL16ri
+ { 1918, 5, 0, 0, "RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1918 = RCL32m1
+ { 1919, 5, 0, 0, "RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1919 = RCL32mCL
+ { 1920, 6, 0, 0, "RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1920 = RCL32mi
+ { 1921, 2, 1, 0, "RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1921 = RCL32r1
+ { 1922, 2, 1, 0, "RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1922 = RCL32rCL
+ { 1923, 3, 1, 0, "RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1923 = RCL32ri
+ { 1924, 5, 0, 0, "RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1924 = RCL64m1
+ { 1925, 5, 0, 0, "RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1925 = RCL64mCL
+ { 1926, 6, 0, 0, "RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1926 = RCL64mi
+ { 1927, 2, 1, 0, "RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1927 = RCL64r1
+ { 1928, 2, 1, 0, "RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1928 = RCL64rCL
+ { 1929, 3, 1, 0, "RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1929 = RCL64ri
+ { 1930, 5, 0, 0, "RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1930 = RCL8m1
+ { 1931, 5, 0, 0, "RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1931 = RCL8mCL
+ { 1932, 6, 0, 0, "RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1932 = RCL8mi
+ { 1933, 2, 1, 0, "RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1933 = RCL8r1
+ { 1934, 2, 1, 0, "RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1934 = RCL8rCL
+ { 1935, 3, 1, 0, "RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1935 = RCL8ri
+ { 1936, 6, 1, 0, "RCPPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1936 = RCPPSm
+ { 1937, 6, 1, 0, "RCPPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1937 = RCPPSm_Int
+ { 1938, 2, 1, 0, "RCPPSr", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1938 = RCPPSr
+ { 1939, 2, 1, 0, "RCPPSr_Int", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1939 = RCPPSr_Int
+ { 1940, 6, 1, 0, "RCPSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1940 = RCPSSm
+ { 1941, 6, 1, 0, "RCPSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1941 = RCPSSm_Int
+ { 1942, 2, 1, 0, "RCPSSr", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1942 = RCPSSr
+ { 1943, 2, 1, 0, "RCPSSr_Int", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1943 = RCPSSr_Int
+ { 1944, 5, 0, 0, "RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1944 = RCR16m1
+ { 1945, 5, 0, 0, "RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1945 = RCR16mCL
+ { 1946, 6, 0, 0, "RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1946 = RCR16mi
+ { 1947, 2, 1, 0, "RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1947 = RCR16r1
+ { 1948, 2, 1, 0, "RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1948 = RCR16rCL
+ { 1949, 3, 1, 0, "RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1949 = RCR16ri
+ { 1950, 5, 0, 0, "RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1950 = RCR32m1
+ { 1951, 5, 0, 0, "RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1951 = RCR32mCL
+ { 1952, 6, 0, 0, "RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1952 = RCR32mi
+ { 1953, 2, 1, 0, "RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1953 = RCR32r1
+ { 1954, 2, 1, 0, "RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1954 = RCR32rCL
+ { 1955, 3, 1, 0, "RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1955 = RCR32ri
+ { 1956, 5, 0, 0, "RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1956 = RCR64m1
+ { 1957, 5, 0, 0, "RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1957 = RCR64mCL
+ { 1958, 6, 0, 0, "RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1958 = RCR64mi
+ { 1959, 2, 1, 0, "RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1959 = RCR64r1
+ { 1960, 2, 1, 0, "RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1960 = RCR64rCL
+ { 1961, 3, 1, 0, "RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1961 = RCR64ri
+ { 1962, 5, 0, 0, "RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1962 = RCR8m1
+ { 1963, 5, 0, 0, "RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1963 = RCR8mCL
+ { 1964, 6, 0, 0, "RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1964 = RCR8mi
+ { 1965, 2, 1, 0, "RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1965 = RCR8r1
+ { 1966, 2, 1, 0, "RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1966 = RCR8rCL
+ { 1967, 3, 1, 0, "RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1967 = RCR8ri
+ { 1968, 0, 0, 0, "RDMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(50<<24), NULL, NULL, NULL, 0 }, // Inst #1968 = RDMSR
+ { 1969, 0, 0, 0, "RDPMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(51<<24), NULL, NULL, NULL, 0 }, // Inst #1969 = RDPMC
+ { 1970, 0, 0, 0, "RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(49<<24), NULL, ImplicitList19, NULL, 0 }, // Inst #1970 = RDTSC
+ { 1971, 0, 0, 0, "RDTSCP", 0|(1<<TID::UnmodeledSideEffects), 0|42|(1<<8)|(1<<24), NULL, ImplicitList45, NULL, 0 }, // Inst #1971 = RDTSCP
+ { 1972, 0, 0, 0, "REPNE_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(242<<24), ImplicitList42, ImplicitList27, NULL, 0 }, // Inst #1972 = REPNE_PREFIX
+ { 1973, 0, 0, 0, "REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(164<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1973 = REP_MOVSB
+ { 1974, 0, 0, 0, "REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(165<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1974 = REP_MOVSD
+ { 1975, 0, 0, 0, "REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(165<<24), ImplicitList47, ImplicitList47, NULL, 0 }, // Inst #1975 = REP_MOVSQ
+ { 1976, 0, 0, 0, "REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(165<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1976 = REP_MOVSW
+ { 1977, 0, 0, 0, "REP_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(243<<24), ImplicitList42, ImplicitList27, NULL, 0 }, // Inst #1977 = REP_PREFIX
+ { 1978, 0, 0, 0, "REP_STOSB", 0|(1<<TID::MayStore), 0|1|(2<<8)|(170<<24), ImplicitList48, ImplicitList49, NULL, 0 }, // Inst #1978 = REP_STOSB
+ { 1979, 0, 0, 0, "REP_STOSD", 0|(1<<TID::MayStore), 0|1|(2<<8)|(171<<24), ImplicitList50, ImplicitList49, NULL, 0 }, // Inst #1979 = REP_STOSD
+ { 1980, 0, 0, 0, "REP_STOSQ", 0|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(171<<24), ImplicitList51, ImplicitList52, NULL, 0 }, // Inst #1980 = REP_STOSQ
+ { 1981, 0, 0, 0, "REP_STOSW", 0|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(171<<24), ImplicitList53, ImplicitList49, NULL, 0 }, // Inst #1981 = REP_STOSW
+ { 1982, 0, 0, 0, "RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(7<<16)|(195<<24), NULL, NULL, NULL, 0 }, // Inst #1982 = RET
+ { 1983, 1, 0, 0, "RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(3<<13)|(7<<16)|(194<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1983 = RETI
+ { 1984, 5, 0, 0, "ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1984 = ROL16m1
+ { 1985, 5, 0, 0, "ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1985 = ROL16mCL
+ { 1986, 6, 0, 0, "ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1986 = ROL16mi
+ { 1987, 2, 1, 0, "ROL16r1", 0, 0|16|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1987 = ROL16r1
+ { 1988, 2, 1, 0, "ROL16rCL", 0, 0|16|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1988 = ROL16rCL
+ { 1989, 3, 1, 0, "ROL16ri", 0, 0|16|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1989 = ROL16ri
+ { 1990, 5, 0, 0, "ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1990 = ROL32m1
+ { 1991, 5, 0, 0, "ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1991 = ROL32mCL
+ { 1992, 6, 0, 0, "ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1992 = ROL32mi
+ { 1993, 2, 1, 0, "ROL32r1", 0, 0|16|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1993 = ROL32r1
+ { 1994, 2, 1, 0, "ROL32rCL", 0, 0|16|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1994 = ROL32rCL
+ { 1995, 3, 1, 0, "ROL32ri", 0, 0|16|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1995 = ROL32ri
+ { 1996, 5, 0, 0, "ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1996 = ROL64m1
+ { 1997, 5, 0, 0, "ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1997 = ROL64mCL
+ { 1998, 6, 0, 0, "ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1998 = ROL64mi
+ { 1999, 2, 1, 0, "ROL64r1", 0, 0|16|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1999 = ROL64r1
+ { 2000, 2, 1, 0, "ROL64rCL", 0, 0|16|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2000 = ROL64rCL
+ { 2001, 3, 1, 0, "ROL64ri", 0, 0|16|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2001 = ROL64ri
+ { 2002, 5, 0, 0, "ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2002 = ROL8m1
+ { 2003, 5, 0, 0, "ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2003 = ROL8mCL
+ { 2004, 6, 0, 0, "ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2004 = ROL8mi
+ { 2005, 2, 1, 0, "ROL8r1", 0, 0|16|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2005 = ROL8r1
+ { 2006, 2, 1, 0, "ROL8rCL", 0, 0|16|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2006 = ROL8rCL
+ { 2007, 3, 1, 0, "ROL8ri", 0, 0|16|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2007 = ROL8ri
+ { 2008, 5, 0, 0, "ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2008 = ROR16m1
+ { 2009, 5, 0, 0, "ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2009 = ROR16mCL
+ { 2010, 6, 0, 0, "ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2010 = ROR16mi
+ { 2011, 2, 1, 0, "ROR16r1", 0, 0|17|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2011 = ROR16r1
+ { 2012, 2, 1, 0, "ROR16rCL", 0, 0|17|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2012 = ROR16rCL
+ { 2013, 3, 1, 0, "ROR16ri", 0, 0|17|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2013 = ROR16ri
+ { 2014, 5, 0, 0, "ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2014 = ROR32m1
+ { 2015, 5, 0, 0, "ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2015 = ROR32mCL
+ { 2016, 6, 0, 0, "ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2016 = ROR32mi
+ { 2017, 2, 1, 0, "ROR32r1", 0, 0|17|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2017 = ROR32r1
+ { 2018, 2, 1, 0, "ROR32rCL", 0, 0|17|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2018 = ROR32rCL
+ { 2019, 3, 1, 0, "ROR32ri", 0, 0|17|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2019 = ROR32ri
+ { 2020, 5, 0, 0, "ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2020 = ROR64m1
+ { 2021, 5, 0, 0, "ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2021 = ROR64mCL
+ { 2022, 6, 0, 0, "ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2022 = ROR64mi
+ { 2023, 2, 1, 0, "ROR64r1", 0, 0|17|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2023 = ROR64r1
+ { 2024, 2, 1, 0, "ROR64rCL", 0, 0|17|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2024 = ROR64rCL
+ { 2025, 3, 1, 0, "ROR64ri", 0, 0|17|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2025 = ROR64ri
+ { 2026, 5, 0, 0, "ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2026 = ROR8m1
+ { 2027, 5, 0, 0, "ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2027 = ROR8mCL
+ { 2028, 6, 0, 0, "ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2028 = ROR8mi
+ { 2029, 2, 1, 0, "ROR8r1", 0, 0|17|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2029 = ROR8r1
+ { 2030, 2, 1, 0, "ROR8rCL", 0, 0|17|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2030 = ROR8rCL
+ { 2031, 3, 1, 0, "ROR8ri", 0, 0|17|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2031 = ROR8ri
+ { 2032, 7, 1, 0, "ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #2032 = ROUNDPDm_Int
+ { 2033, 3, 1, 0, "ROUNDPDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #2033 = ROUNDPDr_Int
+ { 2034, 7, 1, 0, "ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #2034 = ROUNDPSm_Int
+ { 2035, 3, 1, 0, "ROUNDPSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #2035 = ROUNDPSr_Int
+ { 2036, 8, 1, 0, "ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2036 = ROUNDSDm_Int
+ { 2037, 4, 1, 0, "ROUNDSDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2037 = ROUNDSDr_Int
+ { 2038, 8, 1, 0, "ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2038 = ROUNDSSm_Int
+ { 2039, 4, 1, 0, "ROUNDSSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2039 = ROUNDSSr_Int
+ { 2040, 0, 0, 0, "RSM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(170<<24), NULL, NULL, NULL, 0 }, // Inst #2040 = RSM
+ { 2041, 6, 1, 0, "RSQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2041 = RSQRTPSm
+ { 2042, 6, 1, 0, "RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2042 = RSQRTPSm_Int
+ { 2043, 2, 1, 0, "RSQRTPSr", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2043 = RSQRTPSr
+ { 2044, 2, 1, 0, "RSQRTPSr_Int", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2044 = RSQRTPSr_Int
+ { 2045, 6, 1, 0, "RSQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2045 = RSQRTSSm
+ { 2046, 6, 1, 0, "RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2046 = RSQRTSSm_Int
+ { 2047, 2, 1, 0, "RSQRTSSr", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2047 = RSQRTSSr
+ { 2048, 2, 1, 0, "RSQRTSSr_Int", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2048 = RSQRTSSr_Int
+ { 2049, 0, 0, 0, "SAHF", 0, 0|1|(158<<24), ImplicitList28, ImplicitList1, Barriers1, 0 }, // Inst #2049 = SAHF
+ { 2050, 5, 0, 0, "SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2050 = SAR16m1
+ { 2051, 5, 0, 0, "SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2051 = SAR16mCL
+ { 2052, 6, 0, 0, "SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2052 = SAR16mi
+ { 2053, 2, 1, 0, "SAR16r1", 0, 0|23|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2053 = SAR16r1
+ { 2054, 2, 1, 0, "SAR16rCL", 0, 0|23|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2054 = SAR16rCL
+ { 2055, 3, 1, 0, "SAR16ri", 0, 0|23|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2055 = SAR16ri
+ { 2056, 5, 0, 0, "SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2056 = SAR32m1
+ { 2057, 5, 0, 0, "SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2057 = SAR32mCL
+ { 2058, 6, 0, 0, "SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2058 = SAR32mi
+ { 2059, 2, 1, 0, "SAR32r1", 0, 0|23|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2059 = SAR32r1
+ { 2060, 2, 1, 0, "SAR32rCL", 0, 0|23|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2060 = SAR32rCL
+ { 2061, 3, 1, 0, "SAR32ri", 0, 0|23|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2061 = SAR32ri
+ { 2062, 5, 0, 0, "SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2062 = SAR64m1
+ { 2063, 5, 0, 0, "SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2063 = SAR64mCL
+ { 2064, 6, 0, 0, "SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2064 = SAR64mi
+ { 2065, 2, 1, 0, "SAR64r1", 0, 0|23|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2065 = SAR64r1
+ { 2066, 2, 1, 0, "SAR64rCL", 0, 0|23|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2066 = SAR64rCL
+ { 2067, 3, 1, 0, "SAR64ri", 0, 0|23|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2067 = SAR64ri
+ { 2068, 5, 0, 0, "SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2068 = SAR8m1
+ { 2069, 5, 0, 0, "SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2069 = SAR8mCL
+ { 2070, 6, 0, 0, "SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2070 = SAR8mi
+ { 2071, 2, 1, 0, "SAR8r1", 0, 0|23|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2071 = SAR8r1
+ { 2072, 2, 1, 0, "SAR8rCL", 0, 0|23|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2072 = SAR8rCL
+ { 2073, 3, 1, 0, "SAR8ri", 0, 0|23|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2073 = SAR8ri
+ { 2074, 1, 0, 0, "SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2074 = SBB16i16
+ { 2075, 6, 0, 0, "SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2075 = SBB16mi
+ { 2076, 6, 0, 0, "SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2076 = SBB16mi8
+ { 2077, 6, 0, 0, "SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2077 = SBB16mr
+ { 2078, 3, 1, 0, "SBB16ri", 0, 0|19|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2078 = SBB16ri
+ { 2079, 3, 1, 0, "SBB16ri8", 0, 0|19|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2079 = SBB16ri8
+ { 2080, 7, 1, 0, "SBB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2080 = SBB16rm
+ { 2081, 3, 1, 0, "SBB16rr", 0, 0|3|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2081 = SBB16rr
+ { 2082, 3, 1, 0, "SBB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2082 = SBB16rr_REV
+ { 2083, 1, 0, 0, "SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2083 = SBB32i32
+ { 2084, 6, 0, 0, "SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2084 = SBB32mi
+ { 2085, 6, 0, 0, "SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2085 = SBB32mi8
+ { 2086, 6, 0, 0, "SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2086 = SBB32mr
+ { 2087, 3, 1, 0, "SBB32ri", 0, 0|19|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2087 = SBB32ri
+ { 2088, 3, 1, 0, "SBB32ri8", 0, 0|19|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2088 = SBB32ri8
+ { 2089, 7, 1, 0, "SBB32rm", 0|(1<<TID::MayLoad), 0|6|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2089 = SBB32rm
+ { 2090, 3, 1, 0, "SBB32rr", 0, 0|3|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2090 = SBB32rr
+ { 2091, 3, 1, 0, "SBB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2091 = SBB32rr_REV
+ { 2092, 1, 0, 0, "SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2092 = SBB64i32
+ { 2093, 6, 0, 0, "SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2093 = SBB64mi32
+ { 2094, 6, 0, 0, "SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2094 = SBB64mi8
+ { 2095, 6, 0, 0, "SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2095 = SBB64mr
+ { 2096, 3, 1, 0, "SBB64ri32", 0, 0|19|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2096 = SBB64ri32
+ { 2097, 3, 1, 0, "SBB64ri8", 0, 0|19|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2097 = SBB64ri8
+ { 2098, 7, 1, 0, "SBB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2098 = SBB64rm
+ { 2099, 3, 1, 0, "SBB64rr", 0, 0|3|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2099 = SBB64rr
+ { 2100, 3, 1, 0, "SBB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2100 = SBB64rr_REV
+ { 2101, 1, 0, 0, "SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(28<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2101 = SBB8i8
+ { 2102, 6, 0, 0, "SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2102 = SBB8mi
+ { 2103, 6, 0, 0, "SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2103 = SBB8mr
+ { 2104, 3, 1, 0, "SBB8ri", 0, 0|19|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2104 = SBB8ri
+ { 2105, 7, 1, 0, "SBB8rm", 0|(1<<TID::MayLoad), 0|6|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2105 = SBB8rm
+ { 2106, 3, 1, 0, "SBB8rr", 0, 0|3|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2106 = SBB8rr
+ { 2107, 3, 1, 0, "SBB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2107 = SBB8rr_REV
+ { 2108, 0, 0, 0, "SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2108 = SCAS16
+ { 2109, 0, 0, 0, "SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2109 = SCAS32
+ { 2110, 0, 0, 0, "SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2110 = SCAS64
+ { 2111, 0, 0, 0, "SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2111 = SCAS8
+ { 2112, 5, 0, 0, "SETAEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2112 = SETAEm
+ { 2113, 1, 1, 0, "SETAEr", 0, 0|16|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2113 = SETAEr
+ { 2114, 5, 0, 0, "SETAm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2114 = SETAm
+ { 2115, 1, 1, 0, "SETAr", 0, 0|16|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2115 = SETAr
+ { 2116, 5, 0, 0, "SETBEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2116 = SETBEm
+ { 2117, 1, 1, 0, "SETBEr", 0, 0|16|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2117 = SETBEr
+ { 2118, 1, 1, 0, "SETB_C16r", 0, 0|32|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #2118 = SETB_C16r
+ { 2119, 1, 1, 0, "SETB_C32r", 0, 0|32|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #2119 = SETB_C32r
+ { 2120, 1, 1, 0, "SETB_C64r", 0, 0|32|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #2120 = SETB_C64r
+ { 2121, 1, 1, 0, "SETB_C8r", 0, 0|32|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #2121 = SETB_C8r
+ { 2122, 5, 0, 0, "SETBm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2122 = SETBm
+ { 2123, 1, 1, 0, "SETBr", 0, 0|16|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2123 = SETBr
+ { 2124, 5, 0, 0, "SETEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2124 = SETEm
+ { 2125, 1, 1, 0, "SETEr", 0, 0|16|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2125 = SETEr
+ { 2126, 5, 0, 0, "SETGEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2126 = SETGEm
+ { 2127, 1, 1, 0, "SETGEr", 0, 0|16|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2127 = SETGEr
+ { 2128, 5, 0, 0, "SETGm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2128 = SETGm
+ { 2129, 1, 1, 0, "SETGr", 0, 0|16|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2129 = SETGr
+ { 2130, 5, 0, 0, "SETLEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2130 = SETLEm
+ { 2131, 1, 1, 0, "SETLEr", 0, 0|16|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2131 = SETLEr
+ { 2132, 5, 0, 0, "SETLm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2132 = SETLm
+ { 2133, 1, 1, 0, "SETLr", 0, 0|16|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2133 = SETLr
+ { 2134, 5, 0, 0, "SETNEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2134 = SETNEm
+ { 2135, 1, 1, 0, "SETNEr", 0, 0|16|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2135 = SETNEr
+ { 2136, 5, 0, 0, "SETNOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2136 = SETNOm
+ { 2137, 1, 1, 0, "SETNOr", 0, 0|16|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2137 = SETNOr
+ { 2138, 5, 0, 0, "SETNPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2138 = SETNPm
+ { 2139, 1, 1, 0, "SETNPr", 0, 0|16|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2139 = SETNPr
+ { 2140, 5, 0, 0, "SETNSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2140 = SETNSm
+ { 2141, 1, 1, 0, "SETNSr", 0, 0|16|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2141 = SETNSr
+ { 2142, 5, 0, 0, "SETOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2142 = SETOm
+ { 2143, 1, 1, 0, "SETOr", 0, 0|16|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2143 = SETOr
+ { 2144, 5, 0, 0, "SETPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2144 = SETPm
+ { 2145, 1, 1, 0, "SETPr", 0, 0|16|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2145 = SETPr
+ { 2146, 5, 0, 0, "SETSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2146 = SETSm
+ { 2147, 1, 1, 0, "SETSr", 0, 0|16|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2147 = SETSr
+ { 2148, 0, 0, 0, "SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2148 = SFENCE
+ { 2149, 5, 1, 0, "SGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2149 = SGDTm
+ { 2150, 5, 0, 0, "SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2150 = SHL16m1
+ { 2151, 5, 0, 0, "SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2151 = SHL16mCL
+ { 2152, 6, 0, 0, "SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2152 = SHL16mi
+ { 2153, 2, 1, 0, "SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2153 = SHL16r1
+ { 2154, 2, 1, 0, "SHL16rCL", 0, 0|20|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2154 = SHL16rCL
+ { 2155, 3, 1, 0, "SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2155 = SHL16ri
+ { 2156, 5, 0, 0, "SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2156 = SHL32m1
+ { 2157, 5, 0, 0, "SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2157 = SHL32mCL
+ { 2158, 6, 0, 0, "SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2158 = SHL32mi
+ { 2159, 2, 1, 0, "SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2159 = SHL32r1
+ { 2160, 2, 1, 0, "SHL32rCL", 0, 0|20|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2160 = SHL32rCL
+ { 2161, 3, 1, 0, "SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2161 = SHL32ri
+ { 2162, 5, 0, 0, "SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2162 = SHL64m1
+ { 2163, 5, 0, 0, "SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2163 = SHL64mCL
+ { 2164, 6, 0, 0, "SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2164 = SHL64mi
+ { 2165, 2, 1, 0, "SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2165 = SHL64r1
+ { 2166, 2, 1, 0, "SHL64rCL", 0, 0|20|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2166 = SHL64rCL
+ { 2167, 3, 1, 0, "SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2167 = SHL64ri
+ { 2168, 5, 0, 0, "SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2168 = SHL8m1
+ { 2169, 5, 0, 0, "SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2169 = SHL8mCL
+ { 2170, 6, 0, 0, "SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2170 = SHL8mi
+ { 2171, 2, 1, 0, "SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2171 = SHL8r1
+ { 2172, 2, 1, 0, "SHL8rCL", 0, 0|20|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2172 = SHL8rCL
+ { 2173, 3, 1, 0, "SHL8ri", 0, 0|20|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2173 = SHL8ri
+ { 2174, 6, 0, 0, "SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2174 = SHLD16mrCL
+ { 2175, 7, 0, 0, "SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo190 }, // Inst #2175 = SHLD16mri8
+ { 2176, 3, 1, 0, "SHLD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2176 = SHLD16rrCL
+ { 2177, 4, 1, 0, "SHLD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo191 }, // Inst #2177 = SHLD16rri8
+ { 2178, 6, 0, 0, "SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2178 = SHLD32mrCL
+ { 2179, 7, 0, 0, "SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo192 }, // Inst #2179 = SHLD32mri8
+ { 2180, 3, 1, 0, "SHLD32rrCL", 0, 0|3|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2180 = SHLD32rrCL
+ { 2181, 4, 1, 0, "SHLD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo193 }, // Inst #2181 = SHLD32rri8
+ { 2182, 6, 0, 0, "SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2182 = SHLD64mrCL
+ { 2183, 7, 0, 0, "SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #2183 = SHLD64mri8
+ { 2184, 3, 1, 0, "SHLD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2184 = SHLD64rrCL
+ { 2185, 4, 1, 0, "SHLD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #2185 = SHLD64rri8
+ { 2186, 5, 0, 0, "SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2186 = SHR16m1
+ { 2187, 5, 0, 0, "SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2187 = SHR16mCL
+ { 2188, 6, 0, 0, "SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2188 = SHR16mi
+ { 2189, 2, 1, 0, "SHR16r1", 0, 0|21|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2189 = SHR16r1
+ { 2190, 2, 1, 0, "SHR16rCL", 0, 0|21|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2190 = SHR16rCL
+ { 2191, 3, 1, 0, "SHR16ri", 0, 0|21|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2191 = SHR16ri
+ { 2192, 5, 0, 0, "SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2192 = SHR32m1
+ { 2193, 5, 0, 0, "SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2193 = SHR32mCL
+ { 2194, 6, 0, 0, "SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2194 = SHR32mi
+ { 2195, 2, 1, 0, "SHR32r1", 0, 0|21|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2195 = SHR32r1
+ { 2196, 2, 1, 0, "SHR32rCL", 0, 0|21|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2196 = SHR32rCL
+ { 2197, 3, 1, 0, "SHR32ri", 0, 0|21|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2197 = SHR32ri
+ { 2198, 5, 0, 0, "SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2198 = SHR64m1
+ { 2199, 5, 0, 0, "SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2199 = SHR64mCL
+ { 2200, 6, 0, 0, "SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2200 = SHR64mi
+ { 2201, 2, 1, 0, "SHR64r1", 0, 0|21|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2201 = SHR64r1
+ { 2202, 2, 1, 0, "SHR64rCL", 0, 0|21|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2202 = SHR64rCL
+ { 2203, 3, 1, 0, "SHR64ri", 0, 0|21|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2203 = SHR64ri
+ { 2204, 5, 0, 0, "SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2204 = SHR8m1
+ { 2205, 5, 0, 0, "SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2205 = SHR8mCL
+ { 2206, 6, 0, 0, "SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2206 = SHR8mi
+ { 2207, 2, 1, 0, "SHR8r1", 0, 0|21|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2207 = SHR8r1
+ { 2208, 2, 1, 0, "SHR8rCL", 0, 0|21|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2208 = SHR8rCL
+ { 2209, 3, 1, 0, "SHR8ri", 0, 0|21|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2209 = SHR8ri
+ { 2210, 6, 0, 0, "SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2210 = SHRD16mrCL
+ { 2211, 7, 0, 0, "SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo190 }, // Inst #2211 = SHRD16mri8
+ { 2212, 3, 1, 0, "SHRD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2212 = SHRD16rrCL
+ { 2213, 4, 1, 0, "SHRD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo191 }, // Inst #2213 = SHRD16rri8
+ { 2214, 6, 0, 0, "SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2214 = SHRD32mrCL
+ { 2215, 7, 0, 0, "SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo192 }, // Inst #2215 = SHRD32mri8
+ { 2216, 3, 1, 0, "SHRD32rrCL", 0, 0|3|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2216 = SHRD32rrCL
+ { 2217, 4, 1, 0, "SHRD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo193 }, // Inst #2217 = SHRD32rri8
+ { 2218, 6, 0, 0, "SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2218 = SHRD64mrCL
+ { 2219, 7, 0, 0, "SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #2219 = SHRD64mri8
+ { 2220, 3, 1, 0, "SHRD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2220 = SHRD64rrCL
+ { 2221, 4, 1, 0, "SHRD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #2221 = SHRD64rri8
+ { 2222, 8, 1, 0, "SHUFPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2222 = SHUFPDrmi
+ { 2223, 4, 1, 0, "SHUFPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2223 = SHUFPDrri
+ { 2224, 8, 1, 0, "SHUFPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2224 = SHUFPSrmi
+ { 2225, 4, 1, 0, "SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0|5|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2225 = SHUFPSrri
+ { 2226, 5, 1, 0, "SIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2226 = SIDTm
+ { 2227, 0, 0, 0, "SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(254<<24), NULL, NULL, NULL, 0 }, // Inst #2227 = SIN_F
+ { 2228, 2, 1, 0, "SIN_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2228 = SIN_Fp32
+ { 2229, 2, 1, 0, "SIN_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2229 = SIN_Fp64
+ { 2230, 2, 1, 0, "SIN_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2230 = SIN_Fp80
+ { 2231, 5, 1, 0, "SLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2231 = SLDT16m
+ { 2232, 1, 1, 0, "SLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2232 = SLDT16r
+ { 2233, 5, 1, 0, "SLDT64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo30 }, // Inst #2233 = SLDT64m
+ { 2234, 1, 1, 0, "SLDT64r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo58 }, // Inst #2234 = SLDT64r
+ { 2235, 5, 1, 0, "SMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2235 = SMSW16m
+ { 2236, 1, 1, 0, "SMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2236 = SMSW16r
+ { 2237, 1, 1, 0, "SMSW32r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2237 = SMSW32r
+ { 2238, 1, 1, 0, "SMSW64r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<12)|(1<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2238 = SMSW64r
+ { 2239, 6, 1, 0, "SQRTPDm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2239 = SQRTPDm
+ { 2240, 6, 1, 0, "SQRTPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2240 = SQRTPDm_Int
+ { 2241, 2, 1, 0, "SQRTPDr", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2241 = SQRTPDr
+ { 2242, 2, 1, 0, "SQRTPDr_Int", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2242 = SQRTPDr_Int
+ { 2243, 6, 1, 0, "SQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2243 = SQRTPSm
+ { 2244, 6, 1, 0, "SQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2244 = SQRTPSm_Int
+ { 2245, 2, 1, 0, "SQRTPSr", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2245 = SQRTPSr
+ { 2246, 2, 1, 0, "SQRTPSr_Int", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2246 = SQRTPSr_Int
+ { 2247, 6, 1, 0, "SQRTSDm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #2247 = SQRTSDm
+ { 2248, 6, 1, 0, "SQRTSDm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2248 = SQRTSDm_Int
+ { 2249, 2, 1, 0, "SQRTSDr", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #2249 = SQRTSDr
+ { 2250, 2, 1, 0, "SQRTSDr_Int", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2250 = SQRTSDr_Int
+ { 2251, 6, 1, 0, "SQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2251 = SQRTSSm
+ { 2252, 6, 1, 0, "SQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2252 = SQRTSSm_Int
+ { 2253, 2, 1, 0, "SQRTSSr", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2253 = SQRTSSr
+ { 2254, 2, 1, 0, "SQRTSSr_Int", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2254 = SQRTSSr_Int
+ { 2255, 0, 0, 0, "SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(250<<24), NULL, NULL, NULL, 0 }, // Inst #2255 = SQRT_F
+ { 2256, 2, 1, 0, "SQRT_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2256 = SQRT_Fp32
+ { 2257, 2, 1, 0, "SQRT_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2257 = SQRT_Fp64
+ { 2258, 2, 1, 0, "SQRT_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2258 = SQRT_Fp80
+ { 2259, 0, 0, 0, "SS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(54<<24), NULL, NULL, NULL, 0 }, // Inst #2259 = SS_PREFIX
+ { 2260, 0, 0, 0, "STC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(249<<24), NULL, NULL, NULL, 0 }, // Inst #2260 = STC
+ { 2261, 0, 0, 0, "STD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(253<<24), NULL, NULL, NULL, 0 }, // Inst #2261 = STD
+ { 2262, 0, 0, 0, "STI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(251<<24), NULL, NULL, NULL, 0 }, // Inst #2262 = STI
+ { 2263, 5, 0, 0, "STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2263 = STMXCSR
+ { 2264, 0, 0, 0, "STOSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(170<<24), ImplicitList54, ImplicitList35, NULL, 0 }, // Inst #2264 = STOSB
+ { 2265, 0, 0, 0, "STOSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(171<<24), ImplicitList55, ImplicitList35, NULL, 0 }, // Inst #2265 = STOSD
+ { 2266, 0, 0, 0, "STOSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(171<<24), ImplicitList56, ImplicitList35, NULL, 0 }, // Inst #2266 = STOSW
+ { 2267, 5, 1, 0, "STRm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2267 = STRm
+ { 2268, 1, 1, 0, "STRr", 0|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2268 = STRr
+ { 2269, 5, 0, 0, "ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2269 = ST_F32m
+ { 2270, 5, 0, 0, "ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2270 = ST_F64m
+ { 2271, 5, 0, 0, "ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2271 = ST_FP32m
+ { 2272, 5, 0, 0, "ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2272 = ST_FP64m
+ { 2273, 5, 0, 0, "ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2273 = ST_FP80m
+ { 2274, 1, 0, 0, "ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2274 = ST_FPrr
+ { 2275, 6, 0, 0, "ST_Fp32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2275 = ST_Fp32m
+ { 2276, 6, 0, 0, "ST_Fp64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2276 = ST_Fp64m
+ { 2277, 6, 0, 0, "ST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2277 = ST_Fp64m32
+ { 2278, 6, 0, 0, "ST_Fp80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2278 = ST_Fp80m32
+ { 2279, 6, 0, 0, "ST_Fp80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2279 = ST_Fp80m64
+ { 2280, 6, 0, 0, "ST_FpP32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2280 = ST_FpP32m
+ { 2281, 6, 0, 0, "ST_FpP64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2281 = ST_FpP64m
+ { 2282, 6, 0, 0, "ST_FpP64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2282 = ST_FpP64m32
+ { 2283, 6, 0, 0, "ST_FpP80m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2283 = ST_FpP80m
+ { 2284, 6, 0, 0, "ST_FpP80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2284 = ST_FpP80m32
+ { 2285, 6, 0, 0, "ST_FpP80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2285 = ST_FpP80m64
+ { 2286, 1, 0, 0, "ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2286 = ST_Frr
+ { 2287, 1, 0, 0, "SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2287 = SUB16i16
+ { 2288, 6, 0, 0, "SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2288 = SUB16mi
+ { 2289, 6, 0, 0, "SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2289 = SUB16mi8
+ { 2290, 6, 0, 0, "SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2290 = SUB16mr
+ { 2291, 3, 1, 0, "SUB16ri", 0, 0|21|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2291 = SUB16ri
+ { 2292, 3, 1, 0, "SUB16ri8", 0, 0|21|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2292 = SUB16ri8
+ { 2293, 7, 1, 0, "SUB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2293 = SUB16rm
+ { 2294, 3, 1, 0, "SUB16rr", 0, 0|3|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2294 = SUB16rr
+ { 2295, 3, 1, 0, "SUB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2295 = SUB16rr_REV
+ { 2296, 1, 0, 0, "SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2296 = SUB32i32
+ { 2297, 6, 0, 0, "SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2297 = SUB32mi
+ { 2298, 6, 0, 0, "SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2298 = SUB32mi8
+ { 2299, 6, 0, 0, "SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2299 = SUB32mr
+ { 2300, 3, 1, 0, "SUB32ri", 0, 0|21|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2300 = SUB32ri
+ { 2301, 3, 1, 0, "SUB32ri8", 0, 0|21|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2301 = SUB32ri8
+ { 2302, 7, 1, 0, "SUB32rm", 0|(1<<TID::MayLoad), 0|6|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2302 = SUB32rm
+ { 2303, 3, 1, 0, "SUB32rr", 0, 0|3|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2303 = SUB32rr
+ { 2304, 3, 1, 0, "SUB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2304 = SUB32rr_REV
+ { 2305, 1, 0, 0, "SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2305 = SUB64i32
+ { 2306, 6, 0, 0, "SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2306 = SUB64mi32
+ { 2307, 6, 0, 0, "SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2307 = SUB64mi8
+ { 2308, 6, 0, 0, "SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2308 = SUB64mr
+ { 2309, 3, 1, 0, "SUB64ri32", 0, 0|21|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2309 = SUB64ri32
+ { 2310, 3, 1, 0, "SUB64ri8", 0, 0|21|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2310 = SUB64ri8
+ { 2311, 7, 1, 0, "SUB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2311 = SUB64rm
+ { 2312, 3, 1, 0, "SUB64rr", 0, 0|3|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2312 = SUB64rr
+ { 2313, 3, 1, 0, "SUB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2313 = SUB64rr_REV
+ { 2314, 1, 0, 0, "SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(44<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2314 = SUB8i8
+ { 2315, 6, 0, 0, "SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2315 = SUB8mi
+ { 2316, 6, 0, 0, "SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2316 = SUB8mr
+ { 2317, 3, 1, 0, "SUB8ri", 0, 0|21|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2317 = SUB8ri
+ { 2318, 7, 1, 0, "SUB8rm", 0|(1<<TID::MayLoad), 0|6|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2318 = SUB8rm
+ { 2319, 3, 1, 0, "SUB8rr", 0, 0|3|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2319 = SUB8rr
+ { 2320, 3, 1, 0, "SUB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2320 = SUB8rr_REV
+ { 2321, 7, 1, 0, "SUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2321 = SUBPDrm
+ { 2322, 3, 1, 0, "SUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2322 = SUBPDrr
+ { 2323, 7, 1, 0, "SUBPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2323 = SUBPSrm
+ { 2324, 3, 1, 0, "SUBPSrr", 0, 0|5|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2324 = SUBPSrr
+ { 2325, 5, 0, 0, "SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2325 = SUBR_F32m
+ { 2326, 5, 0, 0, "SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2326 = SUBR_F64m
+ { 2327, 5, 0, 0, "SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2327 = SUBR_FI16m
+ { 2328, 5, 0, 0, "SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2328 = SUBR_FI32m
+ { 2329, 1, 0, 0, "SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2329 = SUBR_FPrST0
+ { 2330, 1, 0, 0, "SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2330 = SUBR_FST0r
+ { 2331, 7, 1, 0, "SUBR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2331 = SUBR_Fp32m
+ { 2332, 7, 1, 0, "SUBR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2332 = SUBR_Fp64m
+ { 2333, 7, 1, 0, "SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2333 = SUBR_Fp64m32
+ { 2334, 7, 1, 0, "SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2334 = SUBR_Fp80m32
+ { 2335, 7, 1, 0, "SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2335 = SUBR_Fp80m64
+ { 2336, 7, 1, 0, "SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2336 = SUBR_FpI16m32
+ { 2337, 7, 1, 0, "SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2337 = SUBR_FpI16m64
+ { 2338, 7, 1, 0, "SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2338 = SUBR_FpI16m80
+ { 2339, 7, 1, 0, "SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2339 = SUBR_FpI32m32
+ { 2340, 7, 1, 0, "SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2340 = SUBR_FpI32m64
+ { 2341, 7, 1, 0, "SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2341 = SUBR_FpI32m80
+ { 2342, 1, 0, 0, "SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2342 = SUBR_FrST0
+ { 2343, 7, 1, 0, "SUBSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #2343 = SUBSDrm
+ { 2344, 7, 1, 0, "SUBSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2344 = SUBSDrm_Int
+ { 2345, 3, 1, 0, "SUBSDrr", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #2345 = SUBSDrr
+ { 2346, 3, 1, 0, "SUBSDrr_Int", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2346 = SUBSDrr_Int
+ { 2347, 7, 1, 0, "SUBSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #2347 = SUBSSrm
+ { 2348, 7, 1, 0, "SUBSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2348 = SUBSSrm_Int
+ { 2349, 3, 1, 0, "SUBSSrr", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2349 = SUBSSrr
+ { 2350, 3, 1, 0, "SUBSSrr_Int", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2350 = SUBSSrr_Int
+ { 2351, 5, 0, 0, "SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2351 = SUB_F32m
+ { 2352, 5, 0, 0, "SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2352 = SUB_F64m
+ { 2353, 5, 0, 0, "SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2353 = SUB_FI16m
+ { 2354, 5, 0, 0, "SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2354 = SUB_FI32m
+ { 2355, 1, 0, 0, "SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2355 = SUB_FPrST0
+ { 2356, 1, 0, 0, "SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2356 = SUB_FST0r
+ { 2357, 3, 1, 0, "SUB_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2357 = SUB_Fp32
+ { 2358, 7, 1, 0, "SUB_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2358 = SUB_Fp32m
+ { 2359, 3, 1, 0, "SUB_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2359 = SUB_Fp64
+ { 2360, 7, 1, 0, "SUB_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2360 = SUB_Fp64m
+ { 2361, 7, 1, 0, "SUB_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2361 = SUB_Fp64m32
+ { 2362, 3, 1, 0, "SUB_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2362 = SUB_Fp80
+ { 2363, 7, 1, 0, "SUB_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2363 = SUB_Fp80m32
+ { 2364, 7, 1, 0, "SUB_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2364 = SUB_Fp80m64
+ { 2365, 7, 1, 0, "SUB_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2365 = SUB_FpI16m32
+ { 2366, 7, 1, 0, "SUB_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2366 = SUB_FpI16m64
+ { 2367, 7, 1, 0, "SUB_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2367 = SUB_FpI16m80
+ { 2368, 7, 1, 0, "SUB_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2368 = SUB_FpI32m32
+ { 2369, 7, 1, 0, "SUB_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2369 = SUB_FpI32m64
+ { 2370, 7, 1, 0, "SUB_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2370 = SUB_FpI32m80
+ { 2371, 1, 0, 0, "SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2371 = SUB_FrST0
+ { 2372, 0, 0, 0, "SWAPGS", 0|(1<<TID::UnmodeledSideEffects), 0|41|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2372 = SWAPGS
+ { 2373, 0, 0, 0, "SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(5<<24), NULL, NULL, NULL, 0 }, // Inst #2373 = SYSCALL
+ { 2374, 0, 0, 0, "SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(52<<24), NULL, NULL, NULL, 0 }, // Inst #2374 = SYSENTER
+ { 2375, 0, 0, 0, "SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2375 = SYSEXIT
+ { 2376, 0, 0, 0, "SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<12)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2376 = SYSEXIT64
+ { 2377, 0, 0, 0, "SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(7<<24), NULL, NULL, NULL, 0 }, // Inst #2377 = SYSRET
+ { 2378, 1, 0, 0, "TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #2378 = TAILJMPd
+ { 2379, 5, 0, 0, "TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2379 = TAILJMPm
+ { 2380, 1, 0, 0, "TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2380 = TAILJMPr
+ { 2381, 1, 0, 0, "TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2381 = TAILJMPr64
+ { 2382, 2, 0, 0, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2382 = TCRETURNdi
+ { 2383, 2, 0, 0, "TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2383 = TCRETURNdi64
+ { 2384, 2, 0, 0, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo55 }, // Inst #2384 = TCRETURNri
+ { 2385, 2, 0, 0, "TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo56 }, // Inst #2385 = TCRETURNri64
+ { 2386, 1, 0, 0, "TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2386 = TEST16i16
+ { 2387, 6, 0, 0, "TEST16mi", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2387 = TEST16mi
+ { 2388, 2, 0, 0, "TEST16ri", 0, 0|16|(1<<6)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #2388 = TEST16ri
+ { 2389, 6, 0, 0, "TEST16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #2389 = TEST16rm
+ { 2390, 2, 0, 0, "TEST16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #2390 = TEST16rr
+ { 2391, 1, 0, 0, "TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2391 = TEST32i32
+ { 2392, 6, 0, 0, "TEST32mi", 0|(1<<TID::MayLoad), 0|24|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2392 = TEST32mi
+ { 2393, 2, 0, 0, "TEST32ri", 0, 0|16|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #2393 = TEST32ri
+ { 2394, 6, 0, 0, "TEST32rm", 0|(1<<TID::MayLoad), 0|6|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #2394 = TEST32rm
+ { 2395, 2, 0, 0, "TEST32rr", 0|(1<<TID::Commutable), 0|3|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #2395 = TEST32rr
+ { 2396, 1, 0, 0, "TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2396 = TEST64i32
+ { 2397, 6, 0, 0, "TEST64mi32", 0|(1<<TID::MayLoad), 0|24|(1<<12)|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2397 = TEST64mi32
+ { 2398, 2, 0, 0, "TEST64ri32", 0, 0|16|(1<<12)|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #2398 = TEST64ri32
+ { 2399, 6, 0, 0, "TEST64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #2399 = TEST64rm
+ { 2400, 2, 0, 0, "TEST64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #2400 = TEST64rr
+ { 2401, 1, 0, 0, "TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(168<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2401 = TEST8i8
+ { 2402, 6, 0, 0, "TEST8mi", 0|(1<<TID::MayLoad), 0|24|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2402 = TEST8mi
+ { 2403, 2, 0, 0, "TEST8ri", 0, 0|16|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #2403 = TEST8ri
+ { 2404, 6, 0, 0, "TEST8rm", 0|(1<<TID::MayLoad), 0|6|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #2404 = TEST8rm
+ { 2405, 2, 0, 0, "TEST8rr", 0|(1<<TID::Commutable), 0|3|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #2405 = TEST8rr
+ { 2406, 4, 0, 0, "TLS_addr32", 0, 0, ImplicitList2, ImplicitList9, Barriers3, OperandInfo197 }, // Inst #2406 = TLS_addr32
+ { 2407, 4, 0, 0, "TLS_addr64", 0, 0, ImplicitList4, ImplicitList10, Barriers4, OperandInfo198 }, // Inst #2407 = TLS_addr64
+ { 2408, 0, 0, 0, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(11<<24), NULL, NULL, NULL, 0 }, // Inst #2408 = TRAP
+ { 2409, 0, 0, 0, "TST_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(228<<24), NULL, NULL, NULL, 0 }, // Inst #2409 = TST_F
+ { 2410, 1, 0, 0, "TST_Fp32", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #2410 = TST_Fp32
+ { 2411, 1, 0, 0, "TST_Fp64", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #2411 = TST_Fp64
+ { 2412, 1, 0, 0, "TST_Fp80", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #2412 = TST_Fp80
+ { 2413, 6, 0, 0, "UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo82 }, // Inst #2413 = UCOMISDrm
+ { 2414, 2, 0, 0, "UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo105 }, // Inst #2414 = UCOMISDrr
+ { 2415, 6, 0, 0, "UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo80 }, // Inst #2415 = UCOMISSrm
+ { 2416, 2, 0, 0, "UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo106 }, // Inst #2416 = UCOMISSrr
+ { 2417, 1, 0, 0, "UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2417 = UCOM_FIPr
+ { 2418, 1, 0, 0, "UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2418 = UCOM_FIr
+ { 2419, 0, 0, 0, "UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(5<<8)|(233<<24), ImplicitList24, ImplicitList1, Barriers1, 0 }, // Inst #2419 = UCOM_FPPr
+ { 2420, 1, 0, 0, "UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2420 = UCOM_FPr
+ { 2421, 2, 0, 0, "UCOM_FpIr32", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2421 = UCOM_FpIr32
+ { 2422, 2, 0, 0, "UCOM_FpIr64", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2422 = UCOM_FpIr64
+ { 2423, 2, 0, 0, "UCOM_FpIr80", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2423 = UCOM_FpIr80
+ { 2424, 2, 0, 0, "UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2424 = UCOM_Fpr32
+ { 2425, 2, 0, 0, "UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2425 = UCOM_Fpr64
+ { 2426, 2, 0, 0, "UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2426 = UCOM_Fpr80
+ { 2427, 1, 0, 0, "UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(224<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2427 = UCOM_Fr
+ { 2428, 7, 1, 0, "UNPCKHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2428 = UNPCKHPDrm
+ { 2429, 3, 1, 0, "UNPCKHPDrr", 0, 0|5|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2429 = UNPCKHPDrr
+ { 2430, 7, 1, 0, "UNPCKHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2430 = UNPCKHPSrm
+ { 2431, 3, 1, 0, "UNPCKHPSrr", 0, 0|5|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2431 = UNPCKHPSrr
+ { 2432, 7, 1, 0, "UNPCKLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2432 = UNPCKLPDrm
+ { 2433, 3, 1, 0, "UNPCKLPDrr", 0, 0|5|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2433 = UNPCKLPDrr
+ { 2434, 7, 1, 0, "UNPCKLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2434 = UNPCKLPSrm
+ { 2435, 3, 1, 0, "UNPCKLPSrr", 0, 0|5|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2435 = UNPCKLPSrr
+ { 2436, 3, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0, NULL, NULL, NULL, OperandInfo199 }, // Inst #2436 = VASTART_SAVE_XMM_REGS
+ { 2437, 5, 0, 0, "VERRm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2437 = VERRm
+ { 2438, 1, 0, 0, "VERRr", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2438 = VERRr
+ { 2439, 5, 0, 0, "VERWm", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2439 = VERWm
+ { 2440, 1, 0, 0, "VERWr", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2440 = VERWr
+ { 2441, 0, 0, 0, "VMCALL", 0|(1<<TID::UnmodeledSideEffects), 0|33|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2441 = VMCALL
+ { 2442, 5, 0, 0, "VMCLEARm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2442 = VMCLEARm
+ { 2443, 0, 0, 0, "VMLAUNCH", 0|(1<<TID::UnmodeledSideEffects), 0|34|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2443 = VMLAUNCH
+ { 2444, 5, 0, 0, "VMPTRLDm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2444 = VMPTRLDm
+ { 2445, 5, 1, 0, "VMPTRSTm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2445 = VMPTRSTm
+ { 2446, 6, 1, 0, "VMREAD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2446 = VMREAD32rm
+ { 2447, 2, 1, 0, "VMREAD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2447 = VMREAD32rr
+ { 2448, 6, 1, 0, "VMREAD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2448 = VMREAD64rm
+ { 2449, 2, 1, 0, "VMREAD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2449 = VMREAD64rr
+ { 2450, 0, 0, 0, "VMRESUME", 0|(1<<TID::UnmodeledSideEffects), 0|35|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2450 = VMRESUME
+ { 2451, 6, 1, 0, "VMWRITE32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #2451 = VMWRITE32rm
+ { 2452, 2, 1, 0, "VMWRITE32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2452 = VMWRITE32rr
+ { 2453, 6, 1, 0, "VMWRITE64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #2453 = VMWRITE64rm
+ { 2454, 2, 1, 0, "VMWRITE64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2454 = VMWRITE64rr
+ { 2455, 0, 0, 0, "VMXOFF", 0|(1<<TID::UnmodeledSideEffects), 0|36|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2455 = VMXOFF
+ { 2456, 5, 0, 0, "VMXON", 0|(1<<TID::UnmodeledSideEffects), 0|30|(11<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2456 = VMXON
+ { 2457, 1, 1, 0, "V_SET0", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo200 }, // Inst #2457 = V_SET0
+ { 2458, 1, 1, 0, "V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo200 }, // Inst #2458 = V_SETALLONES
+ { 2459, 0, 0, 0, "WAIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(155<<24), NULL, NULL, NULL, 0 }, // Inst #2459 = WAIT
+ { 2460, 0, 0, 0, "WBINVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(9<<24), NULL, NULL, NULL, 0 }, // Inst #2460 = WBINVD
+ { 2461, 5, 0, 0, "WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo30 }, // Inst #2461 = WINCALL64m
+ { 2462, 1, 0, 0, "WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(232<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo5 }, // Inst #2462 = WINCALL64pcrel32
+ { 2463, 1, 0, 0, "WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo58 }, // Inst #2463 = WINCALL64r
+ { 2464, 0, 0, 0, "WRMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(48<<24), NULL, NULL, NULL, 0 }, // Inst #2464 = WRMSR
+ { 2465, 6, 0, 0, "XADD16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #2465 = XADD16rm
+ { 2466, 2, 1, 0, "XADD16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #2466 = XADD16rr
+ { 2467, 6, 0, 0, "XADD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2467 = XADD32rm
+ { 2468, 2, 1, 0, "XADD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2468 = XADD32rr
+ { 2469, 6, 0, 0, "XADD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2469 = XADD64rm
+ { 2470, 2, 1, 0, "XADD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2470 = XADD64rr
+ { 2471, 6, 0, 0, "XADD8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #2471 = XADD8rm
+ { 2472, 2, 1, 0, "XADD8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #2472 = XADD8rr
+ { 2473, 1, 0, 0, "XCHG16ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<6)|(144<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2473 = XCHG16ar
+ { 2474, 7, 1, 0, "XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo9 }, // Inst #2474 = XCHG16rm
+ { 2475, 3, 1, 0, "XCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo10 }, // Inst #2475 = XCHG16rr
+ { 2476, 1, 0, 0, "XCHG32ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(144<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2476 = XCHG32ar
+ { 2477, 7, 1, 0, "XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(135<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #2477 = XCHG32rm
+ { 2478, 3, 1, 0, "XCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(135<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #2478 = XCHG32rr
+ { 2479, 1, 0, 0, "XCHG64ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<12)|(144<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2479 = XCHG64ar
+ { 2480, 7, 1, 0, "XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #2480 = XCHG64rm
+ { 2481, 3, 1, 0, "XCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #2481 = XCHG64rr
+ { 2482, 7, 1, 0, "XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(134<<24), NULL, NULL, NULL, OperandInfo22 }, // Inst #2482 = XCHG8rm
+ { 2483, 3, 1, 0, "XCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(134<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2483 = XCHG8rr
+ { 2484, 1, 0, 0, "XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2484 = XCH_F
+ { 2485, 0, 0, 0, "XLAT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(215<<24), NULL, NULL, NULL, 0 }, // Inst #2485 = XLAT
+ { 2486, 1, 0, 0, "XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2486 = XOR16i16
+ { 2487, 6, 0, 0, "XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2487 = XOR16mi
+ { 2488, 6, 0, 0, "XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2488 = XOR16mi8
+ { 2489, 6, 0, 0, "XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2489 = XOR16mr
+ { 2490, 3, 1, 0, "XOR16ri", 0, 0|22|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2490 = XOR16ri
+ { 2491, 3, 1, 0, "XOR16ri8", 0, 0|22|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2491 = XOR16ri8
+ { 2492, 7, 1, 0, "XOR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2492 = XOR16rm
+ { 2493, 3, 1, 0, "XOR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2493 = XOR16rr
+ { 2494, 3, 1, 0, "XOR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2494 = XOR16rr_REV
+ { 2495, 1, 0, 0, "XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2495 = XOR32i32
+ { 2496, 6, 0, 0, "XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2496 = XOR32mi
+ { 2497, 6, 0, 0, "XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2497 = XOR32mi8
+ { 2498, 6, 0, 0, "XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2498 = XOR32mr
+ { 2499, 3, 1, 0, "XOR32ri", 0, 0|22|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2499 = XOR32ri
+ { 2500, 3, 1, 0, "XOR32ri8", 0, 0|22|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2500 = XOR32ri8
+ { 2501, 7, 1, 0, "XOR32rm", 0|(1<<TID::MayLoad), 0|6|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2501 = XOR32rm
+ { 2502, 3, 1, 0, "XOR32rr", 0|(1<<TID::Commutable), 0|3|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2502 = XOR32rr
+ { 2503, 3, 1, 0, "XOR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2503 = XOR32rr_REV
+ { 2504, 1, 0, 0, "XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2504 = XOR64i32
+ { 2505, 6, 0, 0, "XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2505 = XOR64mi32
+ { 2506, 6, 0, 0, "XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2506 = XOR64mi8
+ { 2507, 6, 0, 0, "XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2507 = XOR64mr
+ { 2508, 3, 1, 0, "XOR64ri32", 0, 0|22|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2508 = XOR64ri32
+ { 2509, 3, 1, 0, "XOR64ri8", 0, 0|22|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2509 = XOR64ri8
+ { 2510, 7, 1, 0, "XOR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2510 = XOR64rm
+ { 2511, 3, 1, 0, "XOR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2511 = XOR64rr
+ { 2512, 3, 1, 0, "XOR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2512 = XOR64rr_REV
+ { 2513, 1, 0, 0, "XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(52<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2513 = XOR8i8
+ { 2514, 6, 0, 0, "XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2514 = XOR8mi
+ { 2515, 6, 0, 0, "XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2515 = XOR8mr
+ { 2516, 3, 1, 0, "XOR8ri", 0, 0|22|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2516 = XOR8ri
+ { 2517, 7, 1, 0, "XOR8rm", 0|(1<<TID::MayLoad), 0|6|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2517 = XOR8rm
+ { 2518, 3, 1, 0, "XOR8rr", 0|(1<<TID::Commutable), 0|3|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2518 = XOR8rr
+ { 2519, 3, 1, 0, "XOR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2519 = XOR8rr_REV
+ { 2520, 7, 1, 0, "XORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2520 = XORPDrm
+ { 2521, 3, 1, 0, "XORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2521 = XORPDrr
+ { 2522, 7, 1, 0, "XORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2522 = XORPSrm
+ { 2523, 3, 1, 0, "XORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2523 = XORPSrr
};
} // End llvm namespace
diff --git a/libclamav/c++/X86GenInstrNames.inc b/libclamav/c++/X86GenInstrNames.inc
index 96aee25..f8ebc6b 100644
--- a/libclamav/c++/X86GenInstrNames.inc
+++ b/libclamav/c++/X86GenInstrNames.inc
@@ -1358,1191 +1358,1183 @@ namespace X86 {
MOVLHPSrr = 1345,
MOVLPDmr = 1346,
MOVLPDrm = 1347,
- MOVLPDrr = 1348,
- MOVLPSmr = 1349,
- MOVLPSrm = 1350,
- MOVLPSrr = 1351,
- MOVLQ128mr = 1352,
- MOVLSD2PDrr = 1353,
- MOVLSS2PSrr = 1354,
- MOVMSKPDrr = 1355,
- MOVMSKPSrr = 1356,
- MOVNTDQArm = 1357,
- MOVNTDQmr = 1358,
- MOVNTImr = 1359,
+ MOVLPSmr = 1348,
+ MOVLPSrm = 1349,
+ MOVLQ128mr = 1350,
+ MOVMSKPDrr = 1351,
+ MOVMSKPSrr = 1352,
+ MOVNTDQArm = 1353,
+ MOVNTDQ_64mr = 1354,
+ MOVNTDQmr = 1355,
+ MOVNTDQmr_Int = 1356,
+ MOVNTI_64mr = 1357,
+ MOVNTImr = 1358,
+ MOVNTImr_Int = 1359,
MOVNTPDmr = 1360,
- MOVNTPSmr = 1361,
- MOVPC32r = 1362,
- MOVPD2SDmr = 1363,
- MOVPD2SDrr = 1364,
+ MOVNTPDmr_Int = 1361,
+ MOVNTPSmr = 1362,
+ MOVNTPSmr_Int = 1363,
+ MOVPC32r = 1364,
MOVPDI2DImr = 1365,
MOVPDI2DIrr = 1366,
MOVPQI2QImr = 1367,
MOVPQIto64rr = 1368,
- MOVPS2SSmr = 1369,
- MOVPS2SSrr = 1370,
- MOVQI2PQIrm = 1371,
- MOVQxrxr = 1372,
- MOVSB = 1373,
- MOVSD = 1374,
- MOVSD2PDrm = 1375,
- MOVSD2PDrr = 1376,
- MOVSDmr = 1377,
- MOVSDrm = 1378,
- MOVSDrr = 1379,
- MOVSDto64mr = 1380,
- MOVSDto64rr = 1381,
- MOVSHDUPrm = 1382,
- MOVSHDUPrr = 1383,
- MOVSLDUPrm = 1384,
- MOVSLDUPrr = 1385,
- MOVSS2DImr = 1386,
- MOVSS2DIrr = 1387,
- MOVSS2PSrm = 1388,
- MOVSS2PSrr = 1389,
- MOVSSmr = 1390,
- MOVSSrm = 1391,
- MOVSSrr = 1392,
- MOVSW = 1393,
- MOVSX16rm8 = 1394,
- MOVSX16rm8W = 1395,
- MOVSX16rr8 = 1396,
- MOVSX16rr8W = 1397,
- MOVSX32rm16 = 1398,
- MOVSX32rm8 = 1399,
- MOVSX32rr16 = 1400,
- MOVSX32rr8 = 1401,
- MOVSX64rm16 = 1402,
- MOVSX64rm32 = 1403,
- MOVSX64rm8 = 1404,
- MOVSX64rr16 = 1405,
- MOVSX64rr32 = 1406,
- MOVSX64rr8 = 1407,
- MOVUPDmr = 1408,
- MOVUPDmr_Int = 1409,
- MOVUPDrm = 1410,
- MOVUPDrm_Int = 1411,
- MOVUPDrr = 1412,
- MOVUPSmr = 1413,
- MOVUPSmr_Int = 1414,
- MOVUPSrm = 1415,
- MOVUPSrm_Int = 1416,
- MOVUPSrr = 1417,
- MOVZDI2PDIrm = 1418,
- MOVZDI2PDIrr = 1419,
- MOVZPQILo2PQIrm = 1420,
- MOVZPQILo2PQIrr = 1421,
- MOVZQI2PQIrm = 1422,
- MOVZQI2PQIrr = 1423,
- MOVZSD2PDrm = 1424,
- MOVZSS2PSrm = 1425,
- MOVZX16rm8 = 1426,
- MOVZX16rm8W = 1427,
- MOVZX16rr8 = 1428,
- MOVZX16rr8W = 1429,
- MOVZX32_NOREXrm8 = 1430,
- MOVZX32_NOREXrr8 = 1431,
- MOVZX32rm16 = 1432,
- MOVZX32rm8 = 1433,
- MOVZX32rr16 = 1434,
- MOVZX32rr8 = 1435,
- MOVZX64rm16 = 1436,
- MOVZX64rm16_Q = 1437,
- MOVZX64rm32 = 1438,
- MOVZX64rm8 = 1439,
- MOVZX64rm8_Q = 1440,
- MOVZX64rr16 = 1441,
- MOVZX64rr16_Q = 1442,
- MOVZX64rr32 = 1443,
- MOVZX64rr8 = 1444,
- MOVZX64rr8_Q = 1445,
- MOV_Fp3232 = 1446,
- MOV_Fp3264 = 1447,
- MOV_Fp3280 = 1448,
- MOV_Fp6432 = 1449,
- MOV_Fp6464 = 1450,
- MOV_Fp6480 = 1451,
- MOV_Fp8032 = 1452,
- MOV_Fp8064 = 1453,
- MOV_Fp8080 = 1454,
- MPSADBWrmi = 1455,
- MPSADBWrri = 1456,
- MUL16m = 1457,
- MUL16r = 1458,
- MUL32m = 1459,
- MUL32r = 1460,
- MUL64m = 1461,
- MUL64r = 1462,
- MUL8m = 1463,
- MUL8r = 1464,
- MULPDrm = 1465,
- MULPDrr = 1466,
- MULPSrm = 1467,
- MULPSrr = 1468,
- MULSDrm = 1469,
- MULSDrm_Int = 1470,
- MULSDrr = 1471,
- MULSDrr_Int = 1472,
- MULSSrm = 1473,
- MULSSrm_Int = 1474,
- MULSSrr = 1475,
- MULSSrr_Int = 1476,
- MUL_F32m = 1477,
- MUL_F64m = 1478,
- MUL_FI16m = 1479,
- MUL_FI32m = 1480,
- MUL_FPrST0 = 1481,
- MUL_FST0r = 1482,
- MUL_Fp32 = 1483,
- MUL_Fp32m = 1484,
- MUL_Fp64 = 1485,
- MUL_Fp64m = 1486,
- MUL_Fp64m32 = 1487,
- MUL_Fp80 = 1488,
- MUL_Fp80m32 = 1489,
- MUL_Fp80m64 = 1490,
- MUL_FpI16m32 = 1491,
- MUL_FpI16m64 = 1492,
- MUL_FpI16m80 = 1493,
- MUL_FpI32m32 = 1494,
- MUL_FpI32m64 = 1495,
- MUL_FpI32m80 = 1496,
- MUL_FrST0 = 1497,
- MWAIT = 1498,
- NEG16m = 1499,
- NEG16r = 1500,
- NEG32m = 1501,
- NEG32r = 1502,
- NEG64m = 1503,
- NEG64r = 1504,
- NEG8m = 1505,
- NEG8r = 1506,
- NOOP = 1507,
- NOOPL = 1508,
- NOOPW = 1509,
- NOT16m = 1510,
- NOT16r = 1511,
- NOT32m = 1512,
- NOT32r = 1513,
- NOT64m = 1514,
- NOT64r = 1515,
- NOT8m = 1516,
- NOT8r = 1517,
- OR16i16 = 1518,
- OR16mi = 1519,
- OR16mi8 = 1520,
- OR16mr = 1521,
- OR16ri = 1522,
- OR16ri8 = 1523,
- OR16rm = 1524,
- OR16rr = 1525,
- OR16rr_REV = 1526,
- OR32i32 = 1527,
- OR32mi = 1528,
- OR32mi8 = 1529,
- OR32mr = 1530,
- OR32ri = 1531,
- OR32ri8 = 1532,
- OR32rm = 1533,
- OR32rr = 1534,
- OR32rr_REV = 1535,
- OR64i32 = 1536,
- OR64mi32 = 1537,
- OR64mi8 = 1538,
- OR64mr = 1539,
- OR64ri32 = 1540,
- OR64ri8 = 1541,
- OR64rm = 1542,
- OR64rr = 1543,
- OR64rr_REV = 1544,
- OR8i8 = 1545,
- OR8mi = 1546,
- OR8mr = 1547,
- OR8ri = 1548,
- OR8rm = 1549,
- OR8rr = 1550,
- OR8rr_REV = 1551,
- ORPDrm = 1552,
- ORPDrr = 1553,
- ORPSrm = 1554,
- ORPSrr = 1555,
- OUT16ir = 1556,
- OUT16rr = 1557,
- OUT32ir = 1558,
- OUT32rr = 1559,
- OUT8ir = 1560,
- OUT8rr = 1561,
- OUTSB = 1562,
- OUTSD = 1563,
- OUTSW = 1564,
- PABSBrm128 = 1565,
- PABSBrm64 = 1566,
- PABSBrr128 = 1567,
- PABSBrr64 = 1568,
- PABSDrm128 = 1569,
- PABSDrm64 = 1570,
- PABSDrr128 = 1571,
- PABSDrr64 = 1572,
- PABSWrm128 = 1573,
- PABSWrm64 = 1574,
- PABSWrr128 = 1575,
- PABSWrr64 = 1576,
- PACKSSDWrm = 1577,
- PACKSSDWrr = 1578,
- PACKSSWBrm = 1579,
- PACKSSWBrr = 1580,
- PACKUSDWrm = 1581,
- PACKUSDWrr = 1582,
- PACKUSWBrm = 1583,
- PACKUSWBrr = 1584,
- PADDBrm = 1585,
- PADDBrr = 1586,
- PADDDrm = 1587,
- PADDDrr = 1588,
- PADDQrm = 1589,
- PADDQrr = 1590,
- PADDSBrm = 1591,
- PADDSBrr = 1592,
- PADDSWrm = 1593,
- PADDSWrr = 1594,
- PADDUSBrm = 1595,
- PADDUSBrr = 1596,
- PADDUSWrm = 1597,
- PADDUSWrr = 1598,
- PADDWrm = 1599,
- PADDWrr = 1600,
- PALIGNR128rm = 1601,
- PALIGNR128rr = 1602,
- PALIGNR64rm = 1603,
- PALIGNR64rr = 1604,
- PANDNrm = 1605,
- PANDNrr = 1606,
- PANDrm = 1607,
- PANDrr = 1608,
- PAVGBrm = 1609,
- PAVGBrr = 1610,
- PAVGWrm = 1611,
- PAVGWrr = 1612,
- PBLENDVBrm0 = 1613,
- PBLENDVBrr0 = 1614,
- PBLENDWrmi = 1615,
- PBLENDWrri = 1616,
- PCMPEQBrm = 1617,
- PCMPEQBrr = 1618,
- PCMPEQDrm = 1619,
- PCMPEQDrr = 1620,
- PCMPEQQrm = 1621,
- PCMPEQQrr = 1622,
- PCMPEQWrm = 1623,
- PCMPEQWrr = 1624,
- PCMPESTRIArm = 1625,
- PCMPESTRIArr = 1626,
- PCMPESTRICrm = 1627,
- PCMPESTRICrr = 1628,
- PCMPESTRIOrm = 1629,
- PCMPESTRIOrr = 1630,
- PCMPESTRISrm = 1631,
- PCMPESTRISrr = 1632,
- PCMPESTRIZrm = 1633,
- PCMPESTRIZrr = 1634,
- PCMPESTRIrm = 1635,
- PCMPESTRIrr = 1636,
- PCMPESTRM128MEM = 1637,
- PCMPESTRM128REG = 1638,
- PCMPESTRM128rm = 1639,
- PCMPESTRM128rr = 1640,
- PCMPGTBrm = 1641,
- PCMPGTBrr = 1642,
- PCMPGTDrm = 1643,
- PCMPGTDrr = 1644,
- PCMPGTQrm = 1645,
- PCMPGTQrr = 1646,
- PCMPGTWrm = 1647,
- PCMPGTWrr = 1648,
- PCMPISTRIArm = 1649,
- PCMPISTRIArr = 1650,
- PCMPISTRICrm = 1651,
- PCMPISTRICrr = 1652,
- PCMPISTRIOrm = 1653,
- PCMPISTRIOrr = 1654,
- PCMPISTRISrm = 1655,
- PCMPISTRISrr = 1656,
- PCMPISTRIZrm = 1657,
- PCMPISTRIZrr = 1658,
- PCMPISTRIrm = 1659,
- PCMPISTRIrr = 1660,
- PCMPISTRM128MEM = 1661,
- PCMPISTRM128REG = 1662,
- PCMPISTRM128rm = 1663,
- PCMPISTRM128rr = 1664,
- PEXTRBmr = 1665,
- PEXTRBrr = 1666,
- PEXTRDmr = 1667,
- PEXTRDrr = 1668,
- PEXTRQmr = 1669,
- PEXTRQrr = 1670,
- PEXTRWmr = 1671,
- PEXTRWri = 1672,
- PHADDDrm128 = 1673,
- PHADDDrm64 = 1674,
- PHADDDrr128 = 1675,
- PHADDDrr64 = 1676,
- PHADDSWrm128 = 1677,
- PHADDSWrm64 = 1678,
- PHADDSWrr128 = 1679,
- PHADDSWrr64 = 1680,
- PHADDWrm128 = 1681,
- PHADDWrm64 = 1682,
- PHADDWrr128 = 1683,
- PHADDWrr64 = 1684,
- PHMINPOSUWrm128 = 1685,
- PHMINPOSUWrr128 = 1686,
- PHSUBDrm128 = 1687,
- PHSUBDrm64 = 1688,
- PHSUBDrr128 = 1689,
- PHSUBDrr64 = 1690,
- PHSUBSWrm128 = 1691,
- PHSUBSWrm64 = 1692,
- PHSUBSWrr128 = 1693,
- PHSUBSWrr64 = 1694,
- PHSUBWrm128 = 1695,
- PHSUBWrm64 = 1696,
- PHSUBWrr128 = 1697,
- PHSUBWrr64 = 1698,
- PINSRBrm = 1699,
- PINSRBrr = 1700,
- PINSRDrm = 1701,
- PINSRDrr = 1702,
- PINSRQrm = 1703,
- PINSRQrr = 1704,
- PINSRWrmi = 1705,
- PINSRWrri = 1706,
- PMADDUBSWrm128 = 1707,
- PMADDUBSWrm64 = 1708,
- PMADDUBSWrr128 = 1709,
- PMADDUBSWrr64 = 1710,
- PMADDWDrm = 1711,
- PMADDWDrr = 1712,
- PMAXSBrm = 1713,
- PMAXSBrr = 1714,
- PMAXSDrm = 1715,
- PMAXSDrr = 1716,
- PMAXSWrm = 1717,
- PMAXSWrr = 1718,
- PMAXUBrm = 1719,
- PMAXUBrr = 1720,
- PMAXUDrm = 1721,
- PMAXUDrr = 1722,
- PMAXUWrm = 1723,
- PMAXUWrr = 1724,
- PMINSBrm = 1725,
- PMINSBrr = 1726,
- PMINSDrm = 1727,
- PMINSDrr = 1728,
- PMINSWrm = 1729,
- PMINSWrr = 1730,
- PMINUBrm = 1731,
- PMINUBrr = 1732,
- PMINUDrm = 1733,
- PMINUDrr = 1734,
- PMINUWrm = 1735,
- PMINUWrr = 1736,
- PMOVMSKBrr = 1737,
- PMOVSXBDrm = 1738,
- PMOVSXBDrr = 1739,
- PMOVSXBQrm = 1740,
- PMOVSXBQrr = 1741,
- PMOVSXBWrm = 1742,
- PMOVSXBWrr = 1743,
- PMOVSXDQrm = 1744,
- PMOVSXDQrr = 1745,
- PMOVSXWDrm = 1746,
- PMOVSXWDrr = 1747,
- PMOVSXWQrm = 1748,
- PMOVSXWQrr = 1749,
- PMOVZXBDrm = 1750,
- PMOVZXBDrr = 1751,
- PMOVZXBQrm = 1752,
- PMOVZXBQrr = 1753,
- PMOVZXBWrm = 1754,
- PMOVZXBWrr = 1755,
- PMOVZXDQrm = 1756,
- PMOVZXDQrr = 1757,
- PMOVZXWDrm = 1758,
- PMOVZXWDrr = 1759,
- PMOVZXWQrm = 1760,
- PMOVZXWQrr = 1761,
- PMULDQrm = 1762,
- PMULDQrr = 1763,
- PMULHRSWrm128 = 1764,
- PMULHRSWrm64 = 1765,
- PMULHRSWrr128 = 1766,
- PMULHRSWrr64 = 1767,
- PMULHUWrm = 1768,
- PMULHUWrr = 1769,
- PMULHWrm = 1770,
- PMULHWrr = 1771,
- PMULLDrm = 1772,
- PMULLDrm_int = 1773,
- PMULLDrr = 1774,
- PMULLDrr_int = 1775,
- PMULLWrm = 1776,
- PMULLWrr = 1777,
- PMULUDQrm = 1778,
- PMULUDQrr = 1779,
- POP16r = 1780,
- POP16rmm = 1781,
- POP16rmr = 1782,
- POP32r = 1783,
- POP32rmm = 1784,
- POP32rmr = 1785,
- POP64r = 1786,
- POP64rmm = 1787,
- POP64rmr = 1788,
- POPCNT16rm = 1789,
- POPCNT16rr = 1790,
- POPCNT32rm = 1791,
- POPCNT32rr = 1792,
- POPCNT64rm = 1793,
- POPCNT64rr = 1794,
- POPF = 1795,
- POPFD = 1796,
- POPFQ = 1797,
- POPFS16 = 1798,
- POPFS32 = 1799,
- POPFS64 = 1800,
- POPGS16 = 1801,
- POPGS32 = 1802,
- POPGS64 = 1803,
- PORrm = 1804,
- PORrr = 1805,
- PREFETCHNTA = 1806,
- PREFETCHT0 = 1807,
- PREFETCHT1 = 1808,
- PREFETCHT2 = 1809,
- PSADBWrm = 1810,
- PSADBWrr = 1811,
- PSHUFBrm128 = 1812,
- PSHUFBrm64 = 1813,
- PSHUFBrr128 = 1814,
- PSHUFBrr64 = 1815,
- PSHUFDmi = 1816,
- PSHUFDri = 1817,
- PSHUFHWmi = 1818,
- PSHUFHWri = 1819,
- PSHUFLWmi = 1820,
- PSHUFLWri = 1821,
- PSIGNBrm128 = 1822,
- PSIGNBrm64 = 1823,
- PSIGNBrr128 = 1824,
- PSIGNBrr64 = 1825,
- PSIGNDrm128 = 1826,
- PSIGNDrm64 = 1827,
- PSIGNDrr128 = 1828,
- PSIGNDrr64 = 1829,
- PSIGNWrm128 = 1830,
- PSIGNWrm64 = 1831,
- PSIGNWrr128 = 1832,
- PSIGNWrr64 = 1833,
- PSLLDQri = 1834,
- PSLLDri = 1835,
- PSLLDrm = 1836,
- PSLLDrr = 1837,
- PSLLQri = 1838,
- PSLLQrm = 1839,
- PSLLQrr = 1840,
- PSLLWri = 1841,
- PSLLWrm = 1842,
- PSLLWrr = 1843,
- PSRADri = 1844,
- PSRADrm = 1845,
- PSRADrr = 1846,
- PSRAWri = 1847,
- PSRAWrm = 1848,
- PSRAWrr = 1849,
- PSRLDQri = 1850,
- PSRLDri = 1851,
- PSRLDrm = 1852,
- PSRLDrr = 1853,
- PSRLQri = 1854,
- PSRLQrm = 1855,
- PSRLQrr = 1856,
- PSRLWri = 1857,
- PSRLWrm = 1858,
- PSRLWrr = 1859,
- PSUBBrm = 1860,
- PSUBBrr = 1861,
- PSUBDrm = 1862,
- PSUBDrr = 1863,
- PSUBQrm = 1864,
- PSUBQrr = 1865,
- PSUBSBrm = 1866,
- PSUBSBrr = 1867,
- PSUBSWrm = 1868,
- PSUBSWrr = 1869,
- PSUBUSBrm = 1870,
- PSUBUSBrr = 1871,
- PSUBUSWrm = 1872,
- PSUBUSWrr = 1873,
- PSUBWrm = 1874,
- PSUBWrr = 1875,
- PTESTrm = 1876,
- PTESTrr = 1877,
- PUNPCKHBWrm = 1878,
- PUNPCKHBWrr = 1879,
- PUNPCKHDQrm = 1880,
- PUNPCKHDQrr = 1881,
- PUNPCKHQDQrm = 1882,
- PUNPCKHQDQrr = 1883,
- PUNPCKHWDrm = 1884,
- PUNPCKHWDrr = 1885,
- PUNPCKLBWrm = 1886,
- PUNPCKLBWrr = 1887,
- PUNPCKLDQrm = 1888,
- PUNPCKLDQrr = 1889,
- PUNPCKLQDQrm = 1890,
- PUNPCKLQDQrr = 1891,
- PUNPCKLWDrm = 1892,
- PUNPCKLWDrr = 1893,
- PUSH16r = 1894,
- PUSH16rmm = 1895,
- PUSH16rmr = 1896,
- PUSH32i16 = 1897,
- PUSH32i32 = 1898,
- PUSH32i8 = 1899,
- PUSH32r = 1900,
- PUSH32rmm = 1901,
- PUSH32rmr = 1902,
- PUSH64i16 = 1903,
- PUSH64i32 = 1904,
- PUSH64i8 = 1905,
- PUSH64r = 1906,
- PUSH64rmm = 1907,
- PUSH64rmr = 1908,
- PUSHF = 1909,
- PUSHFD = 1910,
- PUSHFQ64 = 1911,
- PUSHFS16 = 1912,
- PUSHFS32 = 1913,
- PUSHFS64 = 1914,
- PUSHGS16 = 1915,
- PUSHGS32 = 1916,
- PUSHGS64 = 1917,
- PXORrm = 1918,
- PXORrr = 1919,
- RCL16m1 = 1920,
- RCL16mCL = 1921,
- RCL16mi = 1922,
- RCL16r1 = 1923,
- RCL16rCL = 1924,
- RCL16ri = 1925,
- RCL32m1 = 1926,
- RCL32mCL = 1927,
- RCL32mi = 1928,
- RCL32r1 = 1929,
- RCL32rCL = 1930,
- RCL32ri = 1931,
- RCL64m1 = 1932,
- RCL64mCL = 1933,
- RCL64mi = 1934,
- RCL64r1 = 1935,
- RCL64rCL = 1936,
- RCL64ri = 1937,
- RCL8m1 = 1938,
- RCL8mCL = 1939,
- RCL8mi = 1940,
- RCL8r1 = 1941,
- RCL8rCL = 1942,
- RCL8ri = 1943,
- RCPPSm = 1944,
- RCPPSm_Int = 1945,
- RCPPSr = 1946,
- RCPPSr_Int = 1947,
- RCPSSm = 1948,
- RCPSSm_Int = 1949,
- RCPSSr = 1950,
- RCPSSr_Int = 1951,
- RCR16m1 = 1952,
- RCR16mCL = 1953,
- RCR16mi = 1954,
- RCR16r1 = 1955,
- RCR16rCL = 1956,
- RCR16ri = 1957,
- RCR32m1 = 1958,
- RCR32mCL = 1959,
- RCR32mi = 1960,
- RCR32r1 = 1961,
- RCR32rCL = 1962,
- RCR32ri = 1963,
- RCR64m1 = 1964,
- RCR64mCL = 1965,
- RCR64mi = 1966,
- RCR64r1 = 1967,
- RCR64rCL = 1968,
- RCR64ri = 1969,
- RCR8m1 = 1970,
- RCR8mCL = 1971,
- RCR8mi = 1972,
- RCR8r1 = 1973,
- RCR8rCL = 1974,
- RCR8ri = 1975,
- RDMSR = 1976,
- RDPMC = 1977,
- RDTSC = 1978,
- RDTSCP = 1979,
- REPNE_PREFIX = 1980,
- REP_MOVSB = 1981,
- REP_MOVSD = 1982,
- REP_MOVSQ = 1983,
- REP_MOVSW = 1984,
- REP_PREFIX = 1985,
- REP_STOSB = 1986,
- REP_STOSD = 1987,
- REP_STOSQ = 1988,
- REP_STOSW = 1989,
- RET = 1990,
- RETI = 1991,
- ROL16m1 = 1992,
- ROL16mCL = 1993,
- ROL16mi = 1994,
- ROL16r1 = 1995,
- ROL16rCL = 1996,
- ROL16ri = 1997,
- ROL32m1 = 1998,
- ROL32mCL = 1999,
- ROL32mi = 2000,
- ROL32r1 = 2001,
- ROL32rCL = 2002,
- ROL32ri = 2003,
- ROL64m1 = 2004,
- ROL64mCL = 2005,
- ROL64mi = 2006,
- ROL64r1 = 2007,
- ROL64rCL = 2008,
- ROL64ri = 2009,
- ROL8m1 = 2010,
- ROL8mCL = 2011,
- ROL8mi = 2012,
- ROL8r1 = 2013,
- ROL8rCL = 2014,
- ROL8ri = 2015,
- ROR16m1 = 2016,
- ROR16mCL = 2017,
- ROR16mi = 2018,
- ROR16r1 = 2019,
- ROR16rCL = 2020,
- ROR16ri = 2021,
- ROR32m1 = 2022,
- ROR32mCL = 2023,
- ROR32mi = 2024,
- ROR32r1 = 2025,
- ROR32rCL = 2026,
- ROR32ri = 2027,
- ROR64m1 = 2028,
- ROR64mCL = 2029,
- ROR64mi = 2030,
- ROR64r1 = 2031,
- ROR64rCL = 2032,
- ROR64ri = 2033,
- ROR8m1 = 2034,
- ROR8mCL = 2035,
- ROR8mi = 2036,
- ROR8r1 = 2037,
- ROR8rCL = 2038,
- ROR8ri = 2039,
- ROUNDPDm_Int = 2040,
- ROUNDPDr_Int = 2041,
- ROUNDPSm_Int = 2042,
- ROUNDPSr_Int = 2043,
- ROUNDSDm_Int = 2044,
- ROUNDSDr_Int = 2045,
- ROUNDSSm_Int = 2046,
- ROUNDSSr_Int = 2047,
- RSM = 2048,
- RSQRTPSm = 2049,
- RSQRTPSm_Int = 2050,
- RSQRTPSr = 2051,
- RSQRTPSr_Int = 2052,
- RSQRTSSm = 2053,
- RSQRTSSm_Int = 2054,
- RSQRTSSr = 2055,
- RSQRTSSr_Int = 2056,
- SAHF = 2057,
- SAR16m1 = 2058,
- SAR16mCL = 2059,
- SAR16mi = 2060,
- SAR16r1 = 2061,
- SAR16rCL = 2062,
- SAR16ri = 2063,
- SAR32m1 = 2064,
- SAR32mCL = 2065,
- SAR32mi = 2066,
- SAR32r1 = 2067,
- SAR32rCL = 2068,
- SAR32ri = 2069,
- SAR64m1 = 2070,
- SAR64mCL = 2071,
- SAR64mi = 2072,
- SAR64r1 = 2073,
- SAR64rCL = 2074,
- SAR64ri = 2075,
- SAR8m1 = 2076,
- SAR8mCL = 2077,
- SAR8mi = 2078,
- SAR8r1 = 2079,
- SAR8rCL = 2080,
- SAR8ri = 2081,
- SBB16i16 = 2082,
- SBB16mi = 2083,
- SBB16mi8 = 2084,
- SBB16mr = 2085,
- SBB16ri = 2086,
- SBB16ri8 = 2087,
- SBB16rm = 2088,
- SBB16rr = 2089,
- SBB16rr_REV = 2090,
- SBB32i32 = 2091,
- SBB32mi = 2092,
- SBB32mi8 = 2093,
- SBB32mr = 2094,
- SBB32ri = 2095,
- SBB32ri8 = 2096,
- SBB32rm = 2097,
- SBB32rr = 2098,
- SBB32rr_REV = 2099,
- SBB64i32 = 2100,
- SBB64mi32 = 2101,
- SBB64mi8 = 2102,
- SBB64mr = 2103,
- SBB64ri32 = 2104,
- SBB64ri8 = 2105,
- SBB64rm = 2106,
- SBB64rr = 2107,
- SBB64rr_REV = 2108,
- SBB8i8 = 2109,
- SBB8mi = 2110,
- SBB8mr = 2111,
- SBB8ri = 2112,
- SBB8rm = 2113,
- SBB8rr = 2114,
- SBB8rr_REV = 2115,
- SCAS16 = 2116,
- SCAS32 = 2117,
- SCAS64 = 2118,
- SCAS8 = 2119,
- SETAEm = 2120,
- SETAEr = 2121,
- SETAm = 2122,
- SETAr = 2123,
- SETBEm = 2124,
- SETBEr = 2125,
- SETB_C16r = 2126,
- SETB_C32r = 2127,
- SETB_C64r = 2128,
- SETB_C8r = 2129,
- SETBm = 2130,
- SETBr = 2131,
- SETEm = 2132,
- SETEr = 2133,
- SETGEm = 2134,
- SETGEr = 2135,
- SETGm = 2136,
- SETGr = 2137,
- SETLEm = 2138,
- SETLEr = 2139,
- SETLm = 2140,
- SETLr = 2141,
- SETNEm = 2142,
- SETNEr = 2143,
- SETNOm = 2144,
- SETNOr = 2145,
- SETNPm = 2146,
- SETNPr = 2147,
- SETNSm = 2148,
- SETNSr = 2149,
- SETOm = 2150,
- SETOr = 2151,
- SETPm = 2152,
- SETPr = 2153,
- SETSm = 2154,
- SETSr = 2155,
- SFENCE = 2156,
- SGDTm = 2157,
- SHL16m1 = 2158,
- SHL16mCL = 2159,
- SHL16mi = 2160,
- SHL16r1 = 2161,
- SHL16rCL = 2162,
- SHL16ri = 2163,
- SHL32m1 = 2164,
- SHL32mCL = 2165,
- SHL32mi = 2166,
- SHL32r1 = 2167,
- SHL32rCL = 2168,
- SHL32ri = 2169,
- SHL64m1 = 2170,
- SHL64mCL = 2171,
- SHL64mi = 2172,
- SHL64r1 = 2173,
- SHL64rCL = 2174,
- SHL64ri = 2175,
- SHL8m1 = 2176,
- SHL8mCL = 2177,
- SHL8mi = 2178,
- SHL8r1 = 2179,
- SHL8rCL = 2180,
- SHL8ri = 2181,
- SHLD16mrCL = 2182,
- SHLD16mri8 = 2183,
- SHLD16rrCL = 2184,
- SHLD16rri8 = 2185,
- SHLD32mrCL = 2186,
- SHLD32mri8 = 2187,
- SHLD32rrCL = 2188,
- SHLD32rri8 = 2189,
- SHLD64mrCL = 2190,
- SHLD64mri8 = 2191,
- SHLD64rrCL = 2192,
- SHLD64rri8 = 2193,
- SHR16m1 = 2194,
- SHR16mCL = 2195,
- SHR16mi = 2196,
- SHR16r1 = 2197,
- SHR16rCL = 2198,
- SHR16ri = 2199,
- SHR32m1 = 2200,
- SHR32mCL = 2201,
- SHR32mi = 2202,
- SHR32r1 = 2203,
- SHR32rCL = 2204,
- SHR32ri = 2205,
- SHR64m1 = 2206,
- SHR64mCL = 2207,
- SHR64mi = 2208,
- SHR64r1 = 2209,
- SHR64rCL = 2210,
- SHR64ri = 2211,
- SHR8m1 = 2212,
- SHR8mCL = 2213,
- SHR8mi = 2214,
- SHR8r1 = 2215,
- SHR8rCL = 2216,
- SHR8ri = 2217,
- SHRD16mrCL = 2218,
- SHRD16mri8 = 2219,
- SHRD16rrCL = 2220,
- SHRD16rri8 = 2221,
- SHRD32mrCL = 2222,
- SHRD32mri8 = 2223,
- SHRD32rrCL = 2224,
- SHRD32rri8 = 2225,
- SHRD64mrCL = 2226,
- SHRD64mri8 = 2227,
- SHRD64rrCL = 2228,
- SHRD64rri8 = 2229,
- SHUFPDrmi = 2230,
- SHUFPDrri = 2231,
- SHUFPSrmi = 2232,
- SHUFPSrri = 2233,
- SIDTm = 2234,
- SIN_F = 2235,
- SIN_Fp32 = 2236,
- SIN_Fp64 = 2237,
- SIN_Fp80 = 2238,
- SLDT16m = 2239,
- SLDT16r = 2240,
- SLDT64m = 2241,
- SLDT64r = 2242,
- SMSW16m = 2243,
- SMSW16r = 2244,
- SMSW32r = 2245,
- SMSW64r = 2246,
- SQRTPDm = 2247,
- SQRTPDm_Int = 2248,
- SQRTPDr = 2249,
- SQRTPDr_Int = 2250,
- SQRTPSm = 2251,
- SQRTPSm_Int = 2252,
- SQRTPSr = 2253,
- SQRTPSr_Int = 2254,
- SQRTSDm = 2255,
- SQRTSDm_Int = 2256,
- SQRTSDr = 2257,
- SQRTSDr_Int = 2258,
- SQRTSSm = 2259,
- SQRTSSm_Int = 2260,
- SQRTSSr = 2261,
- SQRTSSr_Int = 2262,
- SQRT_F = 2263,
- SQRT_Fp32 = 2264,
- SQRT_Fp64 = 2265,
- SQRT_Fp80 = 2266,
- SS_PREFIX = 2267,
- STC = 2268,
- STD = 2269,
- STI = 2270,
- STMXCSR = 2271,
- STOSB = 2272,
- STOSD = 2273,
- STOSW = 2274,
- STRm = 2275,
- STRr = 2276,
- ST_F32m = 2277,
- ST_F64m = 2278,
- ST_FP32m = 2279,
- ST_FP64m = 2280,
- ST_FP80m = 2281,
- ST_FPrr = 2282,
- ST_Fp32m = 2283,
- ST_Fp64m = 2284,
- ST_Fp64m32 = 2285,
- ST_Fp80m32 = 2286,
- ST_Fp80m64 = 2287,
- ST_FpP32m = 2288,
- ST_FpP64m = 2289,
- ST_FpP64m32 = 2290,
- ST_FpP80m = 2291,
- ST_FpP80m32 = 2292,
- ST_FpP80m64 = 2293,
- ST_Frr = 2294,
- SUB16i16 = 2295,
- SUB16mi = 2296,
- SUB16mi8 = 2297,
- SUB16mr = 2298,
- SUB16ri = 2299,
- SUB16ri8 = 2300,
- SUB16rm = 2301,
- SUB16rr = 2302,
- SUB16rr_REV = 2303,
- SUB32i32 = 2304,
- SUB32mi = 2305,
- SUB32mi8 = 2306,
- SUB32mr = 2307,
- SUB32ri = 2308,
- SUB32ri8 = 2309,
- SUB32rm = 2310,
- SUB32rr = 2311,
- SUB32rr_REV = 2312,
- SUB64i32 = 2313,
- SUB64mi32 = 2314,
- SUB64mi8 = 2315,
- SUB64mr = 2316,
- SUB64ri32 = 2317,
- SUB64ri8 = 2318,
- SUB64rm = 2319,
- SUB64rr = 2320,
- SUB64rr_REV = 2321,
- SUB8i8 = 2322,
- SUB8mi = 2323,
- SUB8mr = 2324,
- SUB8ri = 2325,
- SUB8rm = 2326,
- SUB8rr = 2327,
- SUB8rr_REV = 2328,
- SUBPDrm = 2329,
- SUBPDrr = 2330,
- SUBPSrm = 2331,
- SUBPSrr = 2332,
- SUBR_F32m = 2333,
- SUBR_F64m = 2334,
- SUBR_FI16m = 2335,
- SUBR_FI32m = 2336,
- SUBR_FPrST0 = 2337,
- SUBR_FST0r = 2338,
- SUBR_Fp32m = 2339,
- SUBR_Fp64m = 2340,
- SUBR_Fp64m32 = 2341,
- SUBR_Fp80m32 = 2342,
- SUBR_Fp80m64 = 2343,
- SUBR_FpI16m32 = 2344,
- SUBR_FpI16m64 = 2345,
- SUBR_FpI16m80 = 2346,
- SUBR_FpI32m32 = 2347,
- SUBR_FpI32m64 = 2348,
- SUBR_FpI32m80 = 2349,
- SUBR_FrST0 = 2350,
- SUBSDrm = 2351,
- SUBSDrm_Int = 2352,
- SUBSDrr = 2353,
- SUBSDrr_Int = 2354,
- SUBSSrm = 2355,
- SUBSSrm_Int = 2356,
- SUBSSrr = 2357,
- SUBSSrr_Int = 2358,
- SUB_F32m = 2359,
- SUB_F64m = 2360,
- SUB_FI16m = 2361,
- SUB_FI32m = 2362,
- SUB_FPrST0 = 2363,
- SUB_FST0r = 2364,
- SUB_Fp32 = 2365,
- SUB_Fp32m = 2366,
- SUB_Fp64 = 2367,
- SUB_Fp64m = 2368,
- SUB_Fp64m32 = 2369,
- SUB_Fp80 = 2370,
- SUB_Fp80m32 = 2371,
- SUB_Fp80m64 = 2372,
- SUB_FpI16m32 = 2373,
- SUB_FpI16m64 = 2374,
- SUB_FpI16m80 = 2375,
- SUB_FpI32m32 = 2376,
- SUB_FpI32m64 = 2377,
- SUB_FpI32m80 = 2378,
- SUB_FrST0 = 2379,
- SWAPGS = 2380,
- SYSCALL = 2381,
- SYSENTER = 2382,
- SYSEXIT = 2383,
- SYSEXIT64 = 2384,
- SYSRET = 2385,
- TAILJMPd = 2386,
- TAILJMPm = 2387,
- TAILJMPr = 2388,
- TAILJMPr64 = 2389,
- TCRETURNdi = 2390,
- TCRETURNdi64 = 2391,
- TCRETURNri = 2392,
- TCRETURNri64 = 2393,
- TEST16i16 = 2394,
- TEST16mi = 2395,
- TEST16ri = 2396,
- TEST16rm = 2397,
- TEST16rr = 2398,
- TEST32i32 = 2399,
- TEST32mi = 2400,
- TEST32ri = 2401,
- TEST32rm = 2402,
- TEST32rr = 2403,
- TEST64i32 = 2404,
- TEST64mi32 = 2405,
- TEST64ri32 = 2406,
- TEST64rm = 2407,
- TEST64rr = 2408,
- TEST8i8 = 2409,
- TEST8mi = 2410,
- TEST8ri = 2411,
- TEST8rm = 2412,
- TEST8rr = 2413,
- TLS_addr32 = 2414,
- TLS_addr64 = 2415,
- TRAP = 2416,
- TST_F = 2417,
- TST_Fp32 = 2418,
- TST_Fp64 = 2419,
- TST_Fp80 = 2420,
- UCOMISDrm = 2421,
- UCOMISDrr = 2422,
- UCOMISSrm = 2423,
- UCOMISSrr = 2424,
- UCOM_FIPr = 2425,
- UCOM_FIr = 2426,
- UCOM_FPPr = 2427,
- UCOM_FPr = 2428,
- UCOM_FpIr32 = 2429,
- UCOM_FpIr64 = 2430,
- UCOM_FpIr80 = 2431,
- UCOM_Fpr32 = 2432,
- UCOM_Fpr64 = 2433,
- UCOM_Fpr80 = 2434,
- UCOM_Fr = 2435,
- UNPCKHPDrm = 2436,
- UNPCKHPDrr = 2437,
- UNPCKHPSrm = 2438,
- UNPCKHPSrr = 2439,
- UNPCKLPDrm = 2440,
- UNPCKLPDrr = 2441,
- UNPCKLPSrm = 2442,
- UNPCKLPSrr = 2443,
- VASTART_SAVE_XMM_REGS = 2444,
- VERRm = 2445,
- VERRr = 2446,
- VERWm = 2447,
- VERWr = 2448,
- VMCALL = 2449,
- VMCLEARm = 2450,
- VMLAUNCH = 2451,
- VMPTRLDm = 2452,
- VMPTRSTm = 2453,
- VMREAD32rm = 2454,
- VMREAD32rr = 2455,
- VMREAD64rm = 2456,
- VMREAD64rr = 2457,
- VMRESUME = 2458,
- VMWRITE32rm = 2459,
- VMWRITE32rr = 2460,
- VMWRITE64rm = 2461,
- VMWRITE64rr = 2462,
- VMXOFF = 2463,
- VMXON = 2464,
- V_SET0 = 2465,
- V_SETALLONES = 2466,
- WAIT = 2467,
- WBINVD = 2468,
- WINCALL64m = 2469,
- WINCALL64pcrel32 = 2470,
- WINCALL64r = 2471,
- WRMSR = 2472,
- XADD16rm = 2473,
- XADD16rr = 2474,
- XADD32rm = 2475,
- XADD32rr = 2476,
- XADD64rm = 2477,
- XADD64rr = 2478,
- XADD8rm = 2479,
- XADD8rr = 2480,
- XCHG16ar = 2481,
- XCHG16rm = 2482,
- XCHG16rr = 2483,
- XCHG32ar = 2484,
- XCHG32rm = 2485,
- XCHG32rr = 2486,
- XCHG64ar = 2487,
- XCHG64rm = 2488,
- XCHG64rr = 2489,
- XCHG8rm = 2490,
- XCHG8rr = 2491,
- XCH_F = 2492,
- XLAT = 2493,
- XOR16i16 = 2494,
- XOR16mi = 2495,
- XOR16mi8 = 2496,
- XOR16mr = 2497,
- XOR16ri = 2498,
- XOR16ri8 = 2499,
- XOR16rm = 2500,
- XOR16rr = 2501,
- XOR16rr_REV = 2502,
- XOR32i32 = 2503,
- XOR32mi = 2504,
- XOR32mi8 = 2505,
- XOR32mr = 2506,
- XOR32ri = 2507,
- XOR32ri8 = 2508,
- XOR32rm = 2509,
- XOR32rr = 2510,
- XOR32rr_REV = 2511,
- XOR64i32 = 2512,
- XOR64mi32 = 2513,
- XOR64mi8 = 2514,
- XOR64mr = 2515,
- XOR64ri32 = 2516,
- XOR64ri8 = 2517,
- XOR64rm = 2518,
- XOR64rr = 2519,
- XOR64rr_REV = 2520,
- XOR8i8 = 2521,
- XOR8mi = 2522,
- XOR8mr = 2523,
- XOR8ri = 2524,
- XOR8rm = 2525,
- XOR8rr = 2526,
- XOR8rr_REV = 2527,
- XORPDrm = 2528,
- XORPDrr = 2529,
- XORPSrm = 2530,
- XORPSrr = 2531,
- INSTRUCTION_LIST_END = 2532
+ MOVQI2PQIrm = 1369,
+ MOVQxrxr = 1370,
+ MOVSB = 1371,
+ MOVSD = 1372,
+ MOVSDmr = 1373,
+ MOVSDrm = 1374,
+ MOVSDrr = 1375,
+ MOVSDto64mr = 1376,
+ MOVSDto64rr = 1377,
+ MOVSHDUPrm = 1378,
+ MOVSHDUPrr = 1379,
+ MOVSLDUPrm = 1380,
+ MOVSLDUPrr = 1381,
+ MOVSS2DImr = 1382,
+ MOVSS2DIrr = 1383,
+ MOVSSmr = 1384,
+ MOVSSrm = 1385,
+ MOVSSrr = 1386,
+ MOVSW = 1387,
+ MOVSX16rm8 = 1388,
+ MOVSX16rm8W = 1389,
+ MOVSX16rr8 = 1390,
+ MOVSX16rr8W = 1391,
+ MOVSX32rm16 = 1392,
+ MOVSX32rm8 = 1393,
+ MOVSX32rr16 = 1394,
+ MOVSX32rr8 = 1395,
+ MOVSX64rm16 = 1396,
+ MOVSX64rm32 = 1397,
+ MOVSX64rm8 = 1398,
+ MOVSX64rr16 = 1399,
+ MOVSX64rr32 = 1400,
+ MOVSX64rr8 = 1401,
+ MOVUPDmr = 1402,
+ MOVUPDmr_Int = 1403,
+ MOVUPDrm = 1404,
+ MOVUPDrm_Int = 1405,
+ MOVUPDrr = 1406,
+ MOVUPSmr = 1407,
+ MOVUPSmr_Int = 1408,
+ MOVUPSrm = 1409,
+ MOVUPSrm_Int = 1410,
+ MOVUPSrr = 1411,
+ MOVZDI2PDIrm = 1412,
+ MOVZDI2PDIrr = 1413,
+ MOVZPQILo2PQIrm = 1414,
+ MOVZPQILo2PQIrr = 1415,
+ MOVZQI2PQIrm = 1416,
+ MOVZQI2PQIrr = 1417,
+ MOVZX16rm8 = 1418,
+ MOVZX16rm8W = 1419,
+ MOVZX16rr8 = 1420,
+ MOVZX16rr8W = 1421,
+ MOVZX32_NOREXrm8 = 1422,
+ MOVZX32_NOREXrr8 = 1423,
+ MOVZX32rm16 = 1424,
+ MOVZX32rm8 = 1425,
+ MOVZX32rr16 = 1426,
+ MOVZX32rr8 = 1427,
+ MOVZX64rm16 = 1428,
+ MOVZX64rm16_Q = 1429,
+ MOVZX64rm32 = 1430,
+ MOVZX64rm8 = 1431,
+ MOVZX64rm8_Q = 1432,
+ MOVZX64rr16 = 1433,
+ MOVZX64rr16_Q = 1434,
+ MOVZX64rr32 = 1435,
+ MOVZX64rr8 = 1436,
+ MOVZX64rr8_Q = 1437,
+ MOV_Fp3232 = 1438,
+ MOV_Fp3264 = 1439,
+ MOV_Fp3280 = 1440,
+ MOV_Fp6432 = 1441,
+ MOV_Fp6464 = 1442,
+ MOV_Fp6480 = 1443,
+ MOV_Fp8032 = 1444,
+ MOV_Fp8064 = 1445,
+ MOV_Fp8080 = 1446,
+ MPSADBWrmi = 1447,
+ MPSADBWrri = 1448,
+ MUL16m = 1449,
+ MUL16r = 1450,
+ MUL32m = 1451,
+ MUL32r = 1452,
+ MUL64m = 1453,
+ MUL64r = 1454,
+ MUL8m = 1455,
+ MUL8r = 1456,
+ MULPDrm = 1457,
+ MULPDrr = 1458,
+ MULPSrm = 1459,
+ MULPSrr = 1460,
+ MULSDrm = 1461,
+ MULSDrm_Int = 1462,
+ MULSDrr = 1463,
+ MULSDrr_Int = 1464,
+ MULSSrm = 1465,
+ MULSSrm_Int = 1466,
+ MULSSrr = 1467,
+ MULSSrr_Int = 1468,
+ MUL_F32m = 1469,
+ MUL_F64m = 1470,
+ MUL_FI16m = 1471,
+ MUL_FI32m = 1472,
+ MUL_FPrST0 = 1473,
+ MUL_FST0r = 1474,
+ MUL_Fp32 = 1475,
+ MUL_Fp32m = 1476,
+ MUL_Fp64 = 1477,
+ MUL_Fp64m = 1478,
+ MUL_Fp64m32 = 1479,
+ MUL_Fp80 = 1480,
+ MUL_Fp80m32 = 1481,
+ MUL_Fp80m64 = 1482,
+ MUL_FpI16m32 = 1483,
+ MUL_FpI16m64 = 1484,
+ MUL_FpI16m80 = 1485,
+ MUL_FpI32m32 = 1486,
+ MUL_FpI32m64 = 1487,
+ MUL_FpI32m80 = 1488,
+ MUL_FrST0 = 1489,
+ MWAIT = 1490,
+ NEG16m = 1491,
+ NEG16r = 1492,
+ NEG32m = 1493,
+ NEG32r = 1494,
+ NEG64m = 1495,
+ NEG64r = 1496,
+ NEG8m = 1497,
+ NEG8r = 1498,
+ NOOP = 1499,
+ NOOPL = 1500,
+ NOOPW = 1501,
+ NOT16m = 1502,
+ NOT16r = 1503,
+ NOT32m = 1504,
+ NOT32r = 1505,
+ NOT64m = 1506,
+ NOT64r = 1507,
+ NOT8m = 1508,
+ NOT8r = 1509,
+ OR16i16 = 1510,
+ OR16mi = 1511,
+ OR16mi8 = 1512,
+ OR16mr = 1513,
+ OR16ri = 1514,
+ OR16ri8 = 1515,
+ OR16rm = 1516,
+ OR16rr = 1517,
+ OR16rr_REV = 1518,
+ OR32i32 = 1519,
+ OR32mi = 1520,
+ OR32mi8 = 1521,
+ OR32mr = 1522,
+ OR32ri = 1523,
+ OR32ri8 = 1524,
+ OR32rm = 1525,
+ OR32rr = 1526,
+ OR32rr_REV = 1527,
+ OR64i32 = 1528,
+ OR64mi32 = 1529,
+ OR64mi8 = 1530,
+ OR64mr = 1531,
+ OR64ri32 = 1532,
+ OR64ri8 = 1533,
+ OR64rm = 1534,
+ OR64rr = 1535,
+ OR64rr_REV = 1536,
+ OR8i8 = 1537,
+ OR8mi = 1538,
+ OR8mr = 1539,
+ OR8ri = 1540,
+ OR8rm = 1541,
+ OR8rr = 1542,
+ OR8rr_REV = 1543,
+ ORPDrm = 1544,
+ ORPDrr = 1545,
+ ORPSrm = 1546,
+ ORPSrr = 1547,
+ OUT16ir = 1548,
+ OUT16rr = 1549,
+ OUT32ir = 1550,
+ OUT32rr = 1551,
+ OUT8ir = 1552,
+ OUT8rr = 1553,
+ OUTSB = 1554,
+ OUTSD = 1555,
+ OUTSW = 1556,
+ PABSBrm128 = 1557,
+ PABSBrm64 = 1558,
+ PABSBrr128 = 1559,
+ PABSBrr64 = 1560,
+ PABSDrm128 = 1561,
+ PABSDrm64 = 1562,
+ PABSDrr128 = 1563,
+ PABSDrr64 = 1564,
+ PABSWrm128 = 1565,
+ PABSWrm64 = 1566,
+ PABSWrr128 = 1567,
+ PABSWrr64 = 1568,
+ PACKSSDWrm = 1569,
+ PACKSSDWrr = 1570,
+ PACKSSWBrm = 1571,
+ PACKSSWBrr = 1572,
+ PACKUSDWrm = 1573,
+ PACKUSDWrr = 1574,
+ PACKUSWBrm = 1575,
+ PACKUSWBrr = 1576,
+ PADDBrm = 1577,
+ PADDBrr = 1578,
+ PADDDrm = 1579,
+ PADDDrr = 1580,
+ PADDQrm = 1581,
+ PADDQrr = 1582,
+ PADDSBrm = 1583,
+ PADDSBrr = 1584,
+ PADDSWrm = 1585,
+ PADDSWrr = 1586,
+ PADDUSBrm = 1587,
+ PADDUSBrr = 1588,
+ PADDUSWrm = 1589,
+ PADDUSWrr = 1590,
+ PADDWrm = 1591,
+ PADDWrr = 1592,
+ PALIGNR128rm = 1593,
+ PALIGNR128rr = 1594,
+ PALIGNR64rm = 1595,
+ PALIGNR64rr = 1596,
+ PANDNrm = 1597,
+ PANDNrr = 1598,
+ PANDrm = 1599,
+ PANDrr = 1600,
+ PAVGBrm = 1601,
+ PAVGBrr = 1602,
+ PAVGWrm = 1603,
+ PAVGWrr = 1604,
+ PBLENDVBrm0 = 1605,
+ PBLENDVBrr0 = 1606,
+ PBLENDWrmi = 1607,
+ PBLENDWrri = 1608,
+ PCMPEQBrm = 1609,
+ PCMPEQBrr = 1610,
+ PCMPEQDrm = 1611,
+ PCMPEQDrr = 1612,
+ PCMPEQQrm = 1613,
+ PCMPEQQrr = 1614,
+ PCMPEQWrm = 1615,
+ PCMPEQWrr = 1616,
+ PCMPESTRIArm = 1617,
+ PCMPESTRIArr = 1618,
+ PCMPESTRICrm = 1619,
+ PCMPESTRICrr = 1620,
+ PCMPESTRIOrm = 1621,
+ PCMPESTRIOrr = 1622,
+ PCMPESTRISrm = 1623,
+ PCMPESTRISrr = 1624,
+ PCMPESTRIZrm = 1625,
+ PCMPESTRIZrr = 1626,
+ PCMPESTRIrm = 1627,
+ PCMPESTRIrr = 1628,
+ PCMPESTRM128MEM = 1629,
+ PCMPESTRM128REG = 1630,
+ PCMPESTRM128rm = 1631,
+ PCMPESTRM128rr = 1632,
+ PCMPGTBrm = 1633,
+ PCMPGTBrr = 1634,
+ PCMPGTDrm = 1635,
+ PCMPGTDrr = 1636,
+ PCMPGTQrm = 1637,
+ PCMPGTQrr = 1638,
+ PCMPGTWrm = 1639,
+ PCMPGTWrr = 1640,
+ PCMPISTRIArm = 1641,
+ PCMPISTRIArr = 1642,
+ PCMPISTRICrm = 1643,
+ PCMPISTRICrr = 1644,
+ PCMPISTRIOrm = 1645,
+ PCMPISTRIOrr = 1646,
+ PCMPISTRISrm = 1647,
+ PCMPISTRISrr = 1648,
+ PCMPISTRIZrm = 1649,
+ PCMPISTRIZrr = 1650,
+ PCMPISTRIrm = 1651,
+ PCMPISTRIrr = 1652,
+ PCMPISTRM128MEM = 1653,
+ PCMPISTRM128REG = 1654,
+ PCMPISTRM128rm = 1655,
+ PCMPISTRM128rr = 1656,
+ PEXTRBmr = 1657,
+ PEXTRBrr = 1658,
+ PEXTRDmr = 1659,
+ PEXTRDrr = 1660,
+ PEXTRQmr = 1661,
+ PEXTRQrr = 1662,
+ PEXTRWmr = 1663,
+ PEXTRWri = 1664,
+ PHADDDrm128 = 1665,
+ PHADDDrm64 = 1666,
+ PHADDDrr128 = 1667,
+ PHADDDrr64 = 1668,
+ PHADDSWrm128 = 1669,
+ PHADDSWrm64 = 1670,
+ PHADDSWrr128 = 1671,
+ PHADDSWrr64 = 1672,
+ PHADDWrm128 = 1673,
+ PHADDWrm64 = 1674,
+ PHADDWrr128 = 1675,
+ PHADDWrr64 = 1676,
+ PHMINPOSUWrm128 = 1677,
+ PHMINPOSUWrr128 = 1678,
+ PHSUBDrm128 = 1679,
+ PHSUBDrm64 = 1680,
+ PHSUBDrr128 = 1681,
+ PHSUBDrr64 = 1682,
+ PHSUBSWrm128 = 1683,
+ PHSUBSWrm64 = 1684,
+ PHSUBSWrr128 = 1685,
+ PHSUBSWrr64 = 1686,
+ PHSUBWrm128 = 1687,
+ PHSUBWrm64 = 1688,
+ PHSUBWrr128 = 1689,
+ PHSUBWrr64 = 1690,
+ PINSRBrm = 1691,
+ PINSRBrr = 1692,
+ PINSRDrm = 1693,
+ PINSRDrr = 1694,
+ PINSRQrm = 1695,
+ PINSRQrr = 1696,
+ PINSRWrmi = 1697,
+ PINSRWrri = 1698,
+ PMADDUBSWrm128 = 1699,
+ PMADDUBSWrm64 = 1700,
+ PMADDUBSWrr128 = 1701,
+ PMADDUBSWrr64 = 1702,
+ PMADDWDrm = 1703,
+ PMADDWDrr = 1704,
+ PMAXSBrm = 1705,
+ PMAXSBrr = 1706,
+ PMAXSDrm = 1707,
+ PMAXSDrr = 1708,
+ PMAXSWrm = 1709,
+ PMAXSWrr = 1710,
+ PMAXUBrm = 1711,
+ PMAXUBrr = 1712,
+ PMAXUDrm = 1713,
+ PMAXUDrr = 1714,
+ PMAXUWrm = 1715,
+ PMAXUWrr = 1716,
+ PMINSBrm = 1717,
+ PMINSBrr = 1718,
+ PMINSDrm = 1719,
+ PMINSDrr = 1720,
+ PMINSWrm = 1721,
+ PMINSWrr = 1722,
+ PMINUBrm = 1723,
+ PMINUBrr = 1724,
+ PMINUDrm = 1725,
+ PMINUDrr = 1726,
+ PMINUWrm = 1727,
+ PMINUWrr = 1728,
+ PMOVMSKBrr = 1729,
+ PMOVSXBDrm = 1730,
+ PMOVSXBDrr = 1731,
+ PMOVSXBQrm = 1732,
+ PMOVSXBQrr = 1733,
+ PMOVSXBWrm = 1734,
+ PMOVSXBWrr = 1735,
+ PMOVSXDQrm = 1736,
+ PMOVSXDQrr = 1737,
+ PMOVSXWDrm = 1738,
+ PMOVSXWDrr = 1739,
+ PMOVSXWQrm = 1740,
+ PMOVSXWQrr = 1741,
+ PMOVZXBDrm = 1742,
+ PMOVZXBDrr = 1743,
+ PMOVZXBQrm = 1744,
+ PMOVZXBQrr = 1745,
+ PMOVZXBWrm = 1746,
+ PMOVZXBWrr = 1747,
+ PMOVZXDQrm = 1748,
+ PMOVZXDQrr = 1749,
+ PMOVZXWDrm = 1750,
+ PMOVZXWDrr = 1751,
+ PMOVZXWQrm = 1752,
+ PMOVZXWQrr = 1753,
+ PMULDQrm = 1754,
+ PMULDQrr = 1755,
+ PMULHRSWrm128 = 1756,
+ PMULHRSWrm64 = 1757,
+ PMULHRSWrr128 = 1758,
+ PMULHRSWrr64 = 1759,
+ PMULHUWrm = 1760,
+ PMULHUWrr = 1761,
+ PMULHWrm = 1762,
+ PMULHWrr = 1763,
+ PMULLDrm = 1764,
+ PMULLDrm_int = 1765,
+ PMULLDrr = 1766,
+ PMULLDrr_int = 1767,
+ PMULLWrm = 1768,
+ PMULLWrr = 1769,
+ PMULUDQrm = 1770,
+ PMULUDQrr = 1771,
+ POP16r = 1772,
+ POP16rmm = 1773,
+ POP16rmr = 1774,
+ POP32r = 1775,
+ POP32rmm = 1776,
+ POP32rmr = 1777,
+ POP64r = 1778,
+ POP64rmm = 1779,
+ POP64rmr = 1780,
+ POPCNT16rm = 1781,
+ POPCNT16rr = 1782,
+ POPCNT32rm = 1783,
+ POPCNT32rr = 1784,
+ POPCNT64rm = 1785,
+ POPCNT64rr = 1786,
+ POPF = 1787,
+ POPFD = 1788,
+ POPFQ = 1789,
+ POPFS16 = 1790,
+ POPFS32 = 1791,
+ POPFS64 = 1792,
+ POPGS16 = 1793,
+ POPGS32 = 1794,
+ POPGS64 = 1795,
+ PORrm = 1796,
+ PORrr = 1797,
+ PREFETCHNTA = 1798,
+ PREFETCHT0 = 1799,
+ PREFETCHT1 = 1800,
+ PREFETCHT2 = 1801,
+ PSADBWrm = 1802,
+ PSADBWrr = 1803,
+ PSHUFBrm128 = 1804,
+ PSHUFBrm64 = 1805,
+ PSHUFBrr128 = 1806,
+ PSHUFBrr64 = 1807,
+ PSHUFDmi = 1808,
+ PSHUFDri = 1809,
+ PSHUFHWmi = 1810,
+ PSHUFHWri = 1811,
+ PSHUFLWmi = 1812,
+ PSHUFLWri = 1813,
+ PSIGNBrm128 = 1814,
+ PSIGNBrm64 = 1815,
+ PSIGNBrr128 = 1816,
+ PSIGNBrr64 = 1817,
+ PSIGNDrm128 = 1818,
+ PSIGNDrm64 = 1819,
+ PSIGNDrr128 = 1820,
+ PSIGNDrr64 = 1821,
+ PSIGNWrm128 = 1822,
+ PSIGNWrm64 = 1823,
+ PSIGNWrr128 = 1824,
+ PSIGNWrr64 = 1825,
+ PSLLDQri = 1826,
+ PSLLDri = 1827,
+ PSLLDrm = 1828,
+ PSLLDrr = 1829,
+ PSLLQri = 1830,
+ PSLLQrm = 1831,
+ PSLLQrr = 1832,
+ PSLLWri = 1833,
+ PSLLWrm = 1834,
+ PSLLWrr = 1835,
+ PSRADri = 1836,
+ PSRADrm = 1837,
+ PSRADrr = 1838,
+ PSRAWri = 1839,
+ PSRAWrm = 1840,
+ PSRAWrr = 1841,
+ PSRLDQri = 1842,
+ PSRLDri = 1843,
+ PSRLDrm = 1844,
+ PSRLDrr = 1845,
+ PSRLQri = 1846,
+ PSRLQrm = 1847,
+ PSRLQrr = 1848,
+ PSRLWri = 1849,
+ PSRLWrm = 1850,
+ PSRLWrr = 1851,
+ PSUBBrm = 1852,
+ PSUBBrr = 1853,
+ PSUBDrm = 1854,
+ PSUBDrr = 1855,
+ PSUBQrm = 1856,
+ PSUBQrr = 1857,
+ PSUBSBrm = 1858,
+ PSUBSBrr = 1859,
+ PSUBSWrm = 1860,
+ PSUBSWrr = 1861,
+ PSUBUSBrm = 1862,
+ PSUBUSBrr = 1863,
+ PSUBUSWrm = 1864,
+ PSUBUSWrr = 1865,
+ PSUBWrm = 1866,
+ PSUBWrr = 1867,
+ PTESTrm = 1868,
+ PTESTrr = 1869,
+ PUNPCKHBWrm = 1870,
+ PUNPCKHBWrr = 1871,
+ PUNPCKHDQrm = 1872,
+ PUNPCKHDQrr = 1873,
+ PUNPCKHQDQrm = 1874,
+ PUNPCKHQDQrr = 1875,
+ PUNPCKHWDrm = 1876,
+ PUNPCKHWDrr = 1877,
+ PUNPCKLBWrm = 1878,
+ PUNPCKLBWrr = 1879,
+ PUNPCKLDQrm = 1880,
+ PUNPCKLDQrr = 1881,
+ PUNPCKLQDQrm = 1882,
+ PUNPCKLQDQrr = 1883,
+ PUNPCKLWDrm = 1884,
+ PUNPCKLWDrr = 1885,
+ PUSH16r = 1886,
+ PUSH16rmm = 1887,
+ PUSH16rmr = 1888,
+ PUSH32i16 = 1889,
+ PUSH32i32 = 1890,
+ PUSH32i8 = 1891,
+ PUSH32r = 1892,
+ PUSH32rmm = 1893,
+ PUSH32rmr = 1894,
+ PUSH64i16 = 1895,
+ PUSH64i32 = 1896,
+ PUSH64i8 = 1897,
+ PUSH64r = 1898,
+ PUSH64rmm = 1899,
+ PUSH64rmr = 1900,
+ PUSHF = 1901,
+ PUSHFD = 1902,
+ PUSHFQ64 = 1903,
+ PUSHFS16 = 1904,
+ PUSHFS32 = 1905,
+ PUSHFS64 = 1906,
+ PUSHGS16 = 1907,
+ PUSHGS32 = 1908,
+ PUSHGS64 = 1909,
+ PXORrm = 1910,
+ PXORrr = 1911,
+ RCL16m1 = 1912,
+ RCL16mCL = 1913,
+ RCL16mi = 1914,
+ RCL16r1 = 1915,
+ RCL16rCL = 1916,
+ RCL16ri = 1917,
+ RCL32m1 = 1918,
+ RCL32mCL = 1919,
+ RCL32mi = 1920,
+ RCL32r1 = 1921,
+ RCL32rCL = 1922,
+ RCL32ri = 1923,
+ RCL64m1 = 1924,
+ RCL64mCL = 1925,
+ RCL64mi = 1926,
+ RCL64r1 = 1927,
+ RCL64rCL = 1928,
+ RCL64ri = 1929,
+ RCL8m1 = 1930,
+ RCL8mCL = 1931,
+ RCL8mi = 1932,
+ RCL8r1 = 1933,
+ RCL8rCL = 1934,
+ RCL8ri = 1935,
+ RCPPSm = 1936,
+ RCPPSm_Int = 1937,
+ RCPPSr = 1938,
+ RCPPSr_Int = 1939,
+ RCPSSm = 1940,
+ RCPSSm_Int = 1941,
+ RCPSSr = 1942,
+ RCPSSr_Int = 1943,
+ RCR16m1 = 1944,
+ RCR16mCL = 1945,
+ RCR16mi = 1946,
+ RCR16r1 = 1947,
+ RCR16rCL = 1948,
+ RCR16ri = 1949,
+ RCR32m1 = 1950,
+ RCR32mCL = 1951,
+ RCR32mi = 1952,
+ RCR32r1 = 1953,
+ RCR32rCL = 1954,
+ RCR32ri = 1955,
+ RCR64m1 = 1956,
+ RCR64mCL = 1957,
+ RCR64mi = 1958,
+ RCR64r1 = 1959,
+ RCR64rCL = 1960,
+ RCR64ri = 1961,
+ RCR8m1 = 1962,
+ RCR8mCL = 1963,
+ RCR8mi = 1964,
+ RCR8r1 = 1965,
+ RCR8rCL = 1966,
+ RCR8ri = 1967,
+ RDMSR = 1968,
+ RDPMC = 1969,
+ RDTSC = 1970,
+ RDTSCP = 1971,
+ REPNE_PREFIX = 1972,
+ REP_MOVSB = 1973,
+ REP_MOVSD = 1974,
+ REP_MOVSQ = 1975,
+ REP_MOVSW = 1976,
+ REP_PREFIX = 1977,
+ REP_STOSB = 1978,
+ REP_STOSD = 1979,
+ REP_STOSQ = 1980,
+ REP_STOSW = 1981,
+ RET = 1982,
+ RETI = 1983,
+ ROL16m1 = 1984,
+ ROL16mCL = 1985,
+ ROL16mi = 1986,
+ ROL16r1 = 1987,
+ ROL16rCL = 1988,
+ ROL16ri = 1989,
+ ROL32m1 = 1990,
+ ROL32mCL = 1991,
+ ROL32mi = 1992,
+ ROL32r1 = 1993,
+ ROL32rCL = 1994,
+ ROL32ri = 1995,
+ ROL64m1 = 1996,
+ ROL64mCL = 1997,
+ ROL64mi = 1998,
+ ROL64r1 = 1999,
+ ROL64rCL = 2000,
+ ROL64ri = 2001,
+ ROL8m1 = 2002,
+ ROL8mCL = 2003,
+ ROL8mi = 2004,
+ ROL8r1 = 2005,
+ ROL8rCL = 2006,
+ ROL8ri = 2007,
+ ROR16m1 = 2008,
+ ROR16mCL = 2009,
+ ROR16mi = 2010,
+ ROR16r1 = 2011,
+ ROR16rCL = 2012,
+ ROR16ri = 2013,
+ ROR32m1 = 2014,
+ ROR32mCL = 2015,
+ ROR32mi = 2016,
+ ROR32r1 = 2017,
+ ROR32rCL = 2018,
+ ROR32ri = 2019,
+ ROR64m1 = 2020,
+ ROR64mCL = 2021,
+ ROR64mi = 2022,
+ ROR64r1 = 2023,
+ ROR64rCL = 2024,
+ ROR64ri = 2025,
+ ROR8m1 = 2026,
+ ROR8mCL = 2027,
+ ROR8mi = 2028,
+ ROR8r1 = 2029,
+ ROR8rCL = 2030,
+ ROR8ri = 2031,
+ ROUNDPDm_Int = 2032,
+ ROUNDPDr_Int = 2033,
+ ROUNDPSm_Int = 2034,
+ ROUNDPSr_Int = 2035,
+ ROUNDSDm_Int = 2036,
+ ROUNDSDr_Int = 2037,
+ ROUNDSSm_Int = 2038,
+ ROUNDSSr_Int = 2039,
+ RSM = 2040,
+ RSQRTPSm = 2041,
+ RSQRTPSm_Int = 2042,
+ RSQRTPSr = 2043,
+ RSQRTPSr_Int = 2044,
+ RSQRTSSm = 2045,
+ RSQRTSSm_Int = 2046,
+ RSQRTSSr = 2047,
+ RSQRTSSr_Int = 2048,
+ SAHF = 2049,
+ SAR16m1 = 2050,
+ SAR16mCL = 2051,
+ SAR16mi = 2052,
+ SAR16r1 = 2053,
+ SAR16rCL = 2054,
+ SAR16ri = 2055,
+ SAR32m1 = 2056,
+ SAR32mCL = 2057,
+ SAR32mi = 2058,
+ SAR32r1 = 2059,
+ SAR32rCL = 2060,
+ SAR32ri = 2061,
+ SAR64m1 = 2062,
+ SAR64mCL = 2063,
+ SAR64mi = 2064,
+ SAR64r1 = 2065,
+ SAR64rCL = 2066,
+ SAR64ri = 2067,
+ SAR8m1 = 2068,
+ SAR8mCL = 2069,
+ SAR8mi = 2070,
+ SAR8r1 = 2071,
+ SAR8rCL = 2072,
+ SAR8ri = 2073,
+ SBB16i16 = 2074,
+ SBB16mi = 2075,
+ SBB16mi8 = 2076,
+ SBB16mr = 2077,
+ SBB16ri = 2078,
+ SBB16ri8 = 2079,
+ SBB16rm = 2080,
+ SBB16rr = 2081,
+ SBB16rr_REV = 2082,
+ SBB32i32 = 2083,
+ SBB32mi = 2084,
+ SBB32mi8 = 2085,
+ SBB32mr = 2086,
+ SBB32ri = 2087,
+ SBB32ri8 = 2088,
+ SBB32rm = 2089,
+ SBB32rr = 2090,
+ SBB32rr_REV = 2091,
+ SBB64i32 = 2092,
+ SBB64mi32 = 2093,
+ SBB64mi8 = 2094,
+ SBB64mr = 2095,
+ SBB64ri32 = 2096,
+ SBB64ri8 = 2097,
+ SBB64rm = 2098,
+ SBB64rr = 2099,
+ SBB64rr_REV = 2100,
+ SBB8i8 = 2101,
+ SBB8mi = 2102,
+ SBB8mr = 2103,
+ SBB8ri = 2104,
+ SBB8rm = 2105,
+ SBB8rr = 2106,
+ SBB8rr_REV = 2107,
+ SCAS16 = 2108,
+ SCAS32 = 2109,
+ SCAS64 = 2110,
+ SCAS8 = 2111,
+ SETAEm = 2112,
+ SETAEr = 2113,
+ SETAm = 2114,
+ SETAr = 2115,
+ SETBEm = 2116,
+ SETBEr = 2117,
+ SETB_C16r = 2118,
+ SETB_C32r = 2119,
+ SETB_C64r = 2120,
+ SETB_C8r = 2121,
+ SETBm = 2122,
+ SETBr = 2123,
+ SETEm = 2124,
+ SETEr = 2125,
+ SETGEm = 2126,
+ SETGEr = 2127,
+ SETGm = 2128,
+ SETGr = 2129,
+ SETLEm = 2130,
+ SETLEr = 2131,
+ SETLm = 2132,
+ SETLr = 2133,
+ SETNEm = 2134,
+ SETNEr = 2135,
+ SETNOm = 2136,
+ SETNOr = 2137,
+ SETNPm = 2138,
+ SETNPr = 2139,
+ SETNSm = 2140,
+ SETNSr = 2141,
+ SETOm = 2142,
+ SETOr = 2143,
+ SETPm = 2144,
+ SETPr = 2145,
+ SETSm = 2146,
+ SETSr = 2147,
+ SFENCE = 2148,
+ SGDTm = 2149,
+ SHL16m1 = 2150,
+ SHL16mCL = 2151,
+ SHL16mi = 2152,
+ SHL16r1 = 2153,
+ SHL16rCL = 2154,
+ SHL16ri = 2155,
+ SHL32m1 = 2156,
+ SHL32mCL = 2157,
+ SHL32mi = 2158,
+ SHL32r1 = 2159,
+ SHL32rCL = 2160,
+ SHL32ri = 2161,
+ SHL64m1 = 2162,
+ SHL64mCL = 2163,
+ SHL64mi = 2164,
+ SHL64r1 = 2165,
+ SHL64rCL = 2166,
+ SHL64ri = 2167,
+ SHL8m1 = 2168,
+ SHL8mCL = 2169,
+ SHL8mi = 2170,
+ SHL8r1 = 2171,
+ SHL8rCL = 2172,
+ SHL8ri = 2173,
+ SHLD16mrCL = 2174,
+ SHLD16mri8 = 2175,
+ SHLD16rrCL = 2176,
+ SHLD16rri8 = 2177,
+ SHLD32mrCL = 2178,
+ SHLD32mri8 = 2179,
+ SHLD32rrCL = 2180,
+ SHLD32rri8 = 2181,
+ SHLD64mrCL = 2182,
+ SHLD64mri8 = 2183,
+ SHLD64rrCL = 2184,
+ SHLD64rri8 = 2185,
+ SHR16m1 = 2186,
+ SHR16mCL = 2187,
+ SHR16mi = 2188,
+ SHR16r1 = 2189,
+ SHR16rCL = 2190,
+ SHR16ri = 2191,
+ SHR32m1 = 2192,
+ SHR32mCL = 2193,
+ SHR32mi = 2194,
+ SHR32r1 = 2195,
+ SHR32rCL = 2196,
+ SHR32ri = 2197,
+ SHR64m1 = 2198,
+ SHR64mCL = 2199,
+ SHR64mi = 2200,
+ SHR64r1 = 2201,
+ SHR64rCL = 2202,
+ SHR64ri = 2203,
+ SHR8m1 = 2204,
+ SHR8mCL = 2205,
+ SHR8mi = 2206,
+ SHR8r1 = 2207,
+ SHR8rCL = 2208,
+ SHR8ri = 2209,
+ SHRD16mrCL = 2210,
+ SHRD16mri8 = 2211,
+ SHRD16rrCL = 2212,
+ SHRD16rri8 = 2213,
+ SHRD32mrCL = 2214,
+ SHRD32mri8 = 2215,
+ SHRD32rrCL = 2216,
+ SHRD32rri8 = 2217,
+ SHRD64mrCL = 2218,
+ SHRD64mri8 = 2219,
+ SHRD64rrCL = 2220,
+ SHRD64rri8 = 2221,
+ SHUFPDrmi = 2222,
+ SHUFPDrri = 2223,
+ SHUFPSrmi = 2224,
+ SHUFPSrri = 2225,
+ SIDTm = 2226,
+ SIN_F = 2227,
+ SIN_Fp32 = 2228,
+ SIN_Fp64 = 2229,
+ SIN_Fp80 = 2230,
+ SLDT16m = 2231,
+ SLDT16r = 2232,
+ SLDT64m = 2233,
+ SLDT64r = 2234,
+ SMSW16m = 2235,
+ SMSW16r = 2236,
+ SMSW32r = 2237,
+ SMSW64r = 2238,
+ SQRTPDm = 2239,
+ SQRTPDm_Int = 2240,
+ SQRTPDr = 2241,
+ SQRTPDr_Int = 2242,
+ SQRTPSm = 2243,
+ SQRTPSm_Int = 2244,
+ SQRTPSr = 2245,
+ SQRTPSr_Int = 2246,
+ SQRTSDm = 2247,
+ SQRTSDm_Int = 2248,
+ SQRTSDr = 2249,
+ SQRTSDr_Int = 2250,
+ SQRTSSm = 2251,
+ SQRTSSm_Int = 2252,
+ SQRTSSr = 2253,
+ SQRTSSr_Int = 2254,
+ SQRT_F = 2255,
+ SQRT_Fp32 = 2256,
+ SQRT_Fp64 = 2257,
+ SQRT_Fp80 = 2258,
+ SS_PREFIX = 2259,
+ STC = 2260,
+ STD = 2261,
+ STI = 2262,
+ STMXCSR = 2263,
+ STOSB = 2264,
+ STOSD = 2265,
+ STOSW = 2266,
+ STRm = 2267,
+ STRr = 2268,
+ ST_F32m = 2269,
+ ST_F64m = 2270,
+ ST_FP32m = 2271,
+ ST_FP64m = 2272,
+ ST_FP80m = 2273,
+ ST_FPrr = 2274,
+ ST_Fp32m = 2275,
+ ST_Fp64m = 2276,
+ ST_Fp64m32 = 2277,
+ ST_Fp80m32 = 2278,
+ ST_Fp80m64 = 2279,
+ ST_FpP32m = 2280,
+ ST_FpP64m = 2281,
+ ST_FpP64m32 = 2282,
+ ST_FpP80m = 2283,
+ ST_FpP80m32 = 2284,
+ ST_FpP80m64 = 2285,
+ ST_Frr = 2286,
+ SUB16i16 = 2287,
+ SUB16mi = 2288,
+ SUB16mi8 = 2289,
+ SUB16mr = 2290,
+ SUB16ri = 2291,
+ SUB16ri8 = 2292,
+ SUB16rm = 2293,
+ SUB16rr = 2294,
+ SUB16rr_REV = 2295,
+ SUB32i32 = 2296,
+ SUB32mi = 2297,
+ SUB32mi8 = 2298,
+ SUB32mr = 2299,
+ SUB32ri = 2300,
+ SUB32ri8 = 2301,
+ SUB32rm = 2302,
+ SUB32rr = 2303,
+ SUB32rr_REV = 2304,
+ SUB64i32 = 2305,
+ SUB64mi32 = 2306,
+ SUB64mi8 = 2307,
+ SUB64mr = 2308,
+ SUB64ri32 = 2309,
+ SUB64ri8 = 2310,
+ SUB64rm = 2311,
+ SUB64rr = 2312,
+ SUB64rr_REV = 2313,
+ SUB8i8 = 2314,
+ SUB8mi = 2315,
+ SUB8mr = 2316,
+ SUB8ri = 2317,
+ SUB8rm = 2318,
+ SUB8rr = 2319,
+ SUB8rr_REV = 2320,
+ SUBPDrm = 2321,
+ SUBPDrr = 2322,
+ SUBPSrm = 2323,
+ SUBPSrr = 2324,
+ SUBR_F32m = 2325,
+ SUBR_F64m = 2326,
+ SUBR_FI16m = 2327,
+ SUBR_FI32m = 2328,
+ SUBR_FPrST0 = 2329,
+ SUBR_FST0r = 2330,
+ SUBR_Fp32m = 2331,
+ SUBR_Fp64m = 2332,
+ SUBR_Fp64m32 = 2333,
+ SUBR_Fp80m32 = 2334,
+ SUBR_Fp80m64 = 2335,
+ SUBR_FpI16m32 = 2336,
+ SUBR_FpI16m64 = 2337,
+ SUBR_FpI16m80 = 2338,
+ SUBR_FpI32m32 = 2339,
+ SUBR_FpI32m64 = 2340,
+ SUBR_FpI32m80 = 2341,
+ SUBR_FrST0 = 2342,
+ SUBSDrm = 2343,
+ SUBSDrm_Int = 2344,
+ SUBSDrr = 2345,
+ SUBSDrr_Int = 2346,
+ SUBSSrm = 2347,
+ SUBSSrm_Int = 2348,
+ SUBSSrr = 2349,
+ SUBSSrr_Int = 2350,
+ SUB_F32m = 2351,
+ SUB_F64m = 2352,
+ SUB_FI16m = 2353,
+ SUB_FI32m = 2354,
+ SUB_FPrST0 = 2355,
+ SUB_FST0r = 2356,
+ SUB_Fp32 = 2357,
+ SUB_Fp32m = 2358,
+ SUB_Fp64 = 2359,
+ SUB_Fp64m = 2360,
+ SUB_Fp64m32 = 2361,
+ SUB_Fp80 = 2362,
+ SUB_Fp80m32 = 2363,
+ SUB_Fp80m64 = 2364,
+ SUB_FpI16m32 = 2365,
+ SUB_FpI16m64 = 2366,
+ SUB_FpI16m80 = 2367,
+ SUB_FpI32m32 = 2368,
+ SUB_FpI32m64 = 2369,
+ SUB_FpI32m80 = 2370,
+ SUB_FrST0 = 2371,
+ SWAPGS = 2372,
+ SYSCALL = 2373,
+ SYSENTER = 2374,
+ SYSEXIT = 2375,
+ SYSEXIT64 = 2376,
+ SYSRET = 2377,
+ TAILJMPd = 2378,
+ TAILJMPm = 2379,
+ TAILJMPr = 2380,
+ TAILJMPr64 = 2381,
+ TCRETURNdi = 2382,
+ TCRETURNdi64 = 2383,
+ TCRETURNri = 2384,
+ TCRETURNri64 = 2385,
+ TEST16i16 = 2386,
+ TEST16mi = 2387,
+ TEST16ri = 2388,
+ TEST16rm = 2389,
+ TEST16rr = 2390,
+ TEST32i32 = 2391,
+ TEST32mi = 2392,
+ TEST32ri = 2393,
+ TEST32rm = 2394,
+ TEST32rr = 2395,
+ TEST64i32 = 2396,
+ TEST64mi32 = 2397,
+ TEST64ri32 = 2398,
+ TEST64rm = 2399,
+ TEST64rr = 2400,
+ TEST8i8 = 2401,
+ TEST8mi = 2402,
+ TEST8ri = 2403,
+ TEST8rm = 2404,
+ TEST8rr = 2405,
+ TLS_addr32 = 2406,
+ TLS_addr64 = 2407,
+ TRAP = 2408,
+ TST_F = 2409,
+ TST_Fp32 = 2410,
+ TST_Fp64 = 2411,
+ TST_Fp80 = 2412,
+ UCOMISDrm = 2413,
+ UCOMISDrr = 2414,
+ UCOMISSrm = 2415,
+ UCOMISSrr = 2416,
+ UCOM_FIPr = 2417,
+ UCOM_FIr = 2418,
+ UCOM_FPPr = 2419,
+ UCOM_FPr = 2420,
+ UCOM_FpIr32 = 2421,
+ UCOM_FpIr64 = 2422,
+ UCOM_FpIr80 = 2423,
+ UCOM_Fpr32 = 2424,
+ UCOM_Fpr64 = 2425,
+ UCOM_Fpr80 = 2426,
+ UCOM_Fr = 2427,
+ UNPCKHPDrm = 2428,
+ UNPCKHPDrr = 2429,
+ UNPCKHPSrm = 2430,
+ UNPCKHPSrr = 2431,
+ UNPCKLPDrm = 2432,
+ UNPCKLPDrr = 2433,
+ UNPCKLPSrm = 2434,
+ UNPCKLPSrr = 2435,
+ VASTART_SAVE_XMM_REGS = 2436,
+ VERRm = 2437,
+ VERRr = 2438,
+ VERWm = 2439,
+ VERWr = 2440,
+ VMCALL = 2441,
+ VMCLEARm = 2442,
+ VMLAUNCH = 2443,
+ VMPTRLDm = 2444,
+ VMPTRSTm = 2445,
+ VMREAD32rm = 2446,
+ VMREAD32rr = 2447,
+ VMREAD64rm = 2448,
+ VMREAD64rr = 2449,
+ VMRESUME = 2450,
+ VMWRITE32rm = 2451,
+ VMWRITE32rr = 2452,
+ VMWRITE64rm = 2453,
+ VMWRITE64rr = 2454,
+ VMXOFF = 2455,
+ VMXON = 2456,
+ V_SET0 = 2457,
+ V_SETALLONES = 2458,
+ WAIT = 2459,
+ WBINVD = 2460,
+ WINCALL64m = 2461,
+ WINCALL64pcrel32 = 2462,
+ WINCALL64r = 2463,
+ WRMSR = 2464,
+ XADD16rm = 2465,
+ XADD16rr = 2466,
+ XADD32rm = 2467,
+ XADD32rr = 2468,
+ XADD64rm = 2469,
+ XADD64rr = 2470,
+ XADD8rm = 2471,
+ XADD8rr = 2472,
+ XCHG16ar = 2473,
+ XCHG16rm = 2474,
+ XCHG16rr = 2475,
+ XCHG32ar = 2476,
+ XCHG32rm = 2477,
+ XCHG32rr = 2478,
+ XCHG64ar = 2479,
+ XCHG64rm = 2480,
+ XCHG64rr = 2481,
+ XCHG8rm = 2482,
+ XCHG8rr = 2483,
+ XCH_F = 2484,
+ XLAT = 2485,
+ XOR16i16 = 2486,
+ XOR16mi = 2487,
+ XOR16mi8 = 2488,
+ XOR16mr = 2489,
+ XOR16ri = 2490,
+ XOR16ri8 = 2491,
+ XOR16rm = 2492,
+ XOR16rr = 2493,
+ XOR16rr_REV = 2494,
+ XOR32i32 = 2495,
+ XOR32mi = 2496,
+ XOR32mi8 = 2497,
+ XOR32mr = 2498,
+ XOR32ri = 2499,
+ XOR32ri8 = 2500,
+ XOR32rm = 2501,
+ XOR32rr = 2502,
+ XOR32rr_REV = 2503,
+ XOR64i32 = 2504,
+ XOR64mi32 = 2505,
+ XOR64mi8 = 2506,
+ XOR64mr = 2507,
+ XOR64ri32 = 2508,
+ XOR64ri8 = 2509,
+ XOR64rm = 2510,
+ XOR64rr = 2511,
+ XOR64rr_REV = 2512,
+ XOR8i8 = 2513,
+ XOR8mi = 2514,
+ XOR8mr = 2515,
+ XOR8ri = 2516,
+ XOR8rm = 2517,
+ XOR8rr = 2518,
+ XOR8rr_REV = 2519,
+ XORPDrm = 2520,
+ XORPDrr = 2521,
+ XORPSrm = 2522,
+ XORPSrr = 2523,
+ INSTRUCTION_LIST_END = 2524
};
}
} // End llvm namespace
diff --git a/libclamav/c++/X86GenRegisterInfo.inc b/libclamav/c++/X86GenRegisterInfo.inc
index 33bfe18..d18e482 100644
--- a/libclamav/c++/X86GenRegisterInfo.inc
+++ b/libclamav/c++/X86GenRegisterInfo.inc
@@ -496,12 +496,12 @@ namespace X86 { // Register class instances
// VR128 Sub-register Classes...
static const TargetRegisterClass* const VR128SubRegClasses[] = {
- NULL
+ &X86::FR32RegClass, &X86::FR64RegClass, NULL
};
// VR256 Sub-register Classes...
static const TargetRegisterClass* const VR256SubRegClasses[] = {
- NULL
+ &X86::FR32RegClass, &X86::FR64RegClass, &X86::VR128RegClass, NULL
};
// VR64 Sub-register Classes...
@@ -531,12 +531,12 @@ namespace X86 { // Register class instances
// FR32 Super-register Classes...
static const TargetRegisterClass* const FR32SuperRegClasses[] = {
- NULL
+ &X86::VR128RegClass, &X86::VR256RegClass, NULL
};
// FR64 Super-register Classes...
static const TargetRegisterClass* const FR64SuperRegClasses[] = {
- NULL
+ &X86::VR128RegClass, &X86::VR256RegClass, NULL
};
// GR16 Super-register Classes...
@@ -651,7 +651,7 @@ namespace X86 { // Register class instances
// VR128 Super-register Classes...
static const TargetRegisterClass* const VR128SuperRegClasses[] = {
- NULL
+ &X86::VR256RegClass, NULL
};
// VR256 Super-register Classes...
@@ -1366,7 +1366,7 @@ namespace {
};
- // Number of hash collisions: 14
+ // Number of hash collisions: 20
const unsigned SubregHashTable[] = { X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1393,7 +1393,7 @@ namespace {
X86::R9, X86::R9W,
X86::NoRegister, X86::NoRegister,
X86::R9D, X86::R9W,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM2, X86::XMM2,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::EIP, X86::IP,
@@ -1437,7 +1437,7 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM3, X86::XMM3,
X86::RAX, X86::EAX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1469,7 +1469,7 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::RIP, X86::IP,
X86::EAX, X86::AL,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM4, X86::XMM4,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1507,7 +1507,7 @@ namespace {
X86::R11D, X86::R11W,
X86::EAX, X86::AX,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM5, X86::XMM5,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1545,7 +1545,7 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::EBX, X86::BH,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM6, X86::XMM6,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1585,7 +1585,7 @@ namespace {
X86::R12D, X86::R12B,
X86::R12W, X86::R12B,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM7, X86::XMM7,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1603,7 +1603,7 @@ namespace {
X86::R15D, X86::R15W,
X86::RSI, X86::SI,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM0, X86::XMM0,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1621,7 +1621,7 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::R12, X86::R12D,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM8, X86::XMM8,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1639,7 +1639,7 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::RSI, X86::SIL,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM1, X86::XMM1,
X86::SI, X86::SIL,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1659,7 +1659,7 @@ namespace {
X86::R12, X86::R12W,
X86::NoRegister, X86::NoRegister,
X86::R12D, X86::R12W,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM9, X86::XMM9,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1677,7 +1677,7 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::R8, X86::R8B,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM10, X86::XMM10,
X86::R8D, X86::R8B,
X86::R8W, X86::R8B,
X86::NoRegister, X86::NoRegister,
@@ -1717,7 +1717,7 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::RSP, X86::SPL,
X86::SP, X86::SPL,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM11, X86::XMM11,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1753,7 +1753,7 @@ namespace {
X86::R8, X86::R8W,
X86::NoRegister, X86::NoRegister,
X86::R8D, X86::R8W,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM12, X86::XMM12,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1793,7 +1793,7 @@ namespace {
X86::R10D, X86::R10B,
X86::R10W, X86::R10B,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM13, X86::XMM13,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1829,7 +1829,7 @@ namespace {
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::R9, X86::R9B,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM14, X86::XMM14,
X86::R9D, X86::R9B,
X86::R9W, X86::R9B,
X86::NoRegister, X86::NoRegister,
@@ -1867,7 +1867,7 @@ namespace {
X86::R10D, X86::R10W,
X86::R9, X86::R9D,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM15, X86::XMM15,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1882,7 +1882,7 @@ X86::NoRegister, X86::NoRegister };
const unsigned SubregHashTableSize = 512;
- // Number of hash collisions: 18
+ // Number of hash collisions: 23
const unsigned SuperregHashTable[] = { X86::DX, X86::RDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -1899,7 +1899,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::EDX, X86::RDX,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM14, X86::YMM14,
X86::NoRegister, X86::NoRegister,
X86::BP, X86::EBP,
X86::BPL, X86::EBP,
@@ -1935,7 +1935,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::BX, X86::RBX,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM15, X86::YMM15,
X86::BH, X86::EBX,
X86::BL, X86::EBX,
X86::EIP, X86::RIP,
@@ -1973,7 +1973,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM2, X86::YMM2,
X86::NoRegister, X86::NoRegister,
X86::ESI, X86::RSI,
X86::NoRegister, X86::NoRegister,
@@ -2011,7 +2011,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM3, X86::YMM3,
X86::NoRegister, X86::NoRegister,
X86::ESP, X86::RSP,
X86::NoRegister, X86::NoRegister,
@@ -2049,7 +2049,7 @@ X86::NoRegister, X86::NoRegister };
X86::SIL, X86::RSI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM4, X86::YMM4,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2087,7 +2087,7 @@ X86::NoRegister, X86::NoRegister };
X86::SP, X86::RSP,
X86::SPL, X86::RSP,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM5, X86::YMM5,
X86::NoRegister, X86::NoRegister,
X86::SI, X86::ESI,
X86::SIL, X86::ESI,
@@ -2125,7 +2125,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM6, X86::YMM6,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::SP, X86::ESP,
@@ -2163,7 +2163,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM7, X86::YMM7,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2181,7 +2181,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM0, X86::YMM0,
X86::NoRegister, X86::NoRegister,
X86::BH, X86::BX,
X86::BL, X86::BX,
@@ -2201,7 +2201,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM8, X86::YMM8,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2219,7 +2219,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM1, X86::YMM1,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2239,6 +2239,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::XMM9, X86::YMM9,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2256,8 +2257,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM10, X86::YMM10,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2295,7 +2295,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM11, X86::YMM11,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2335,7 +2335,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::ECX, X86::RCX,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM12, X86::YMM12,
X86::CH, X86::CX,
X86::CL, X86::CX,
X86::NoRegister, X86::NoRegister,
@@ -2383,7 +2383,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::DH, X86::RDX,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM13, X86::YMM13,
X86::R9B, X86::R9D,
X86::DL, X86::RDX,
X86::R9W, X86::R9D,
@@ -2398,7 +2398,7 @@ X86::NoRegister, X86::NoRegister };
const unsigned SuperregHashTableSize = 512;
- // Number of hash collisions: 23
+ // Number of hash collisions: 31
const unsigned AliasesHashTable[] = { X86::DX, X86::RDX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2425,7 +2425,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM2, X86::XMM2,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::EIP, X86::IP,
@@ -2469,7 +2469,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM3, X86::XMM3,
X86::RAX, X86::EAX,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2501,7 +2501,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::EAX, X86::AL,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM4, X86::XMM4,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2539,7 +2539,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::EAX, X86::AX,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM5, X86::XMM5,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2577,7 +2577,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::EBX, X86::BH,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM6, X86::XMM6,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2615,7 +2615,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::EBX, X86::BL,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM7, X86::XMM7,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2653,7 +2653,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM8, X86::XMM8,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2691,13 +2691,13 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::YMM9, X86::XMM9,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM0, X86::YMM0,
X86::NoRegister, X86::NoRegister,
X86::BH, X86::BX,
X86::BL, X86::BX,
@@ -2735,7 +2735,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM1, X86::YMM1,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2773,7 +2773,7 @@ X86::NoRegister, X86::NoRegister };
X86::ECX, X86::CH,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM10, X86::YMM10,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2811,7 +2811,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM11, X86::YMM11,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -2849,7 +2849,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM12, X86::YMM12,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::CH, X86::CX,
@@ -2893,7 +2893,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM13, X86::YMM13,
X86::R10, X86::R10W,
X86::R10B, X86::R10W,
X86::R10D, X86::R10W,
@@ -2925,7 +2925,7 @@ X86::NoRegister, X86::NoRegister };
X86::BP, X86::RBP,
X86::BPL, X86::RBP,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM14, X86::YMM14,
X86::NoRegister, X86::NoRegister,
X86::RDI, X86::EDI,
X86::NoRegister, X86::NoRegister,
@@ -2963,7 +2963,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::BX, X86::RBX,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM15, X86::YMM15,
X86::NoRegister, X86::NoRegister,
X86::RDX, X86::EDX,
X86::NoRegister, X86::NoRegister,
@@ -3001,7 +3001,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM2, X86::YMM2,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3039,7 +3039,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM3, X86::YMM3,
X86::RIP, X86::EIP,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3077,7 +3077,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM4, X86::YMM4,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3121,7 +3121,7 @@ X86::NoRegister, X86::NoRegister };
X86::SIL, X86::ESI,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM5, X86::YMM5,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::R12, X86::R12B,
@@ -3145,7 +3145,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM0, X86::XMM0,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3155,7 +3155,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::RSP, X86::ESP,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM6, X86::YMM6,
X86::SP, X86::ESP,
X86::SPL, X86::ESP,
X86::NoRegister, X86::NoRegister,
@@ -3183,6 +3183,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::YMM1, X86::XMM1,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3190,8 +3191,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM7, X86::YMM7,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3221,6 +3221,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::YMM10, X86::XMM10,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3228,8 +3229,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM8, X86::YMM8,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3259,6 +3259,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
+ X86::YMM11, X86::XMM11,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3266,8 +3267,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::XMM9, X86::YMM9,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3297,7 +3297,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM12, X86::XMM12,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3337,7 +3337,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::CX, X86::RCX,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM13, X86::XMM13,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
@@ -3373,7 +3373,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM14, X86::XMM14,
X86::DH, X86::DX,
X86::DIL, X86::RDI,
X86::DI, X86::RDI,
@@ -3411,7 +3411,7 @@ X86::NoRegister, X86::NoRegister };
X86::NoRegister, X86::NoRegister,
X86::NoRegister, X86::NoRegister,
X86::DH, X86::RDX,
- X86::NoRegister, X86::NoRegister,
+ X86::YMM15, X86::XMM15,
X86::NoRegister, X86::NoRegister,
X86::DL, X86::RDX,
X86::NoRegister, X86::NoRegister,
@@ -3554,38 +3554,38 @@ X86::NoRegister, X86::NoRegister };
const unsigned ST5_AliasSet[] = { 0 };
const unsigned ST6_AliasSet[] = { 0 };
const unsigned ST7_AliasSet[] = { 0 };
- const unsigned XMM0_AliasSet[] = { 0 };
- const unsigned XMM1_AliasSet[] = { 0 };
- const unsigned XMM10_AliasSet[] = { 0 };
- const unsigned XMM11_AliasSet[] = { 0 };
- const unsigned XMM12_AliasSet[] = { 0 };
- const unsigned XMM13_AliasSet[] = { 0 };
- const unsigned XMM14_AliasSet[] = { 0 };
- const unsigned XMM15_AliasSet[] = { 0 };
- const unsigned XMM2_AliasSet[] = { 0 };
- const unsigned XMM3_AliasSet[] = { 0 };
- const unsigned XMM4_AliasSet[] = { 0 };
- const unsigned XMM5_AliasSet[] = { 0 };
- const unsigned XMM6_AliasSet[] = { 0 };
- const unsigned XMM7_AliasSet[] = { 0 };
- const unsigned XMM8_AliasSet[] = { 0 };
- const unsigned XMM9_AliasSet[] = { 0 };
- const unsigned YMM0_AliasSet[] = { 0 };
- const unsigned YMM1_AliasSet[] = { 0 };
- const unsigned YMM10_AliasSet[] = { 0 };
- const unsigned YMM11_AliasSet[] = { 0 };
- const unsigned YMM12_AliasSet[] = { 0 };
- const unsigned YMM13_AliasSet[] = { 0 };
- const unsigned YMM14_AliasSet[] = { 0 };
- const unsigned YMM15_AliasSet[] = { 0 };
- const unsigned YMM2_AliasSet[] = { 0 };
- const unsigned YMM3_AliasSet[] = { 0 };
- const unsigned YMM4_AliasSet[] = { 0 };
- const unsigned YMM5_AliasSet[] = { 0 };
- const unsigned YMM6_AliasSet[] = { 0 };
- const unsigned YMM7_AliasSet[] = { 0 };
- const unsigned YMM8_AliasSet[] = { 0 };
- const unsigned YMM9_AliasSet[] = { 0 };
+ const unsigned XMM0_AliasSet[] = { X86::YMM0, 0 };
+ const unsigned XMM1_AliasSet[] = { X86::YMM1, 0 };
+ const unsigned XMM10_AliasSet[] = { X86::YMM10, 0 };
+ const unsigned XMM11_AliasSet[] = { X86::YMM11, 0 };
+ const unsigned XMM12_AliasSet[] = { X86::YMM12, 0 };
+ const unsigned XMM13_AliasSet[] = { X86::YMM13, 0 };
+ const unsigned XMM14_AliasSet[] = { X86::YMM14, 0 };
+ const unsigned XMM15_AliasSet[] = { X86::YMM15, 0 };
+ const unsigned XMM2_AliasSet[] = { X86::YMM2, 0 };
+ const unsigned XMM3_AliasSet[] = { X86::YMM3, 0 };
+ const unsigned XMM4_AliasSet[] = { X86::YMM4, 0 };
+ const unsigned XMM5_AliasSet[] = { X86::YMM5, 0 };
+ const unsigned XMM6_AliasSet[] = { X86::YMM6, 0 };
+ const unsigned XMM7_AliasSet[] = { X86::YMM7, 0 };
+ const unsigned XMM8_AliasSet[] = { X86::YMM8, 0 };
+ const unsigned XMM9_AliasSet[] = { X86::YMM9, 0 };
+ const unsigned YMM0_AliasSet[] = { X86::XMM0, 0 };
+ const unsigned YMM1_AliasSet[] = { X86::XMM1, 0 };
+ const unsigned YMM10_AliasSet[] = { X86::XMM10, 0 };
+ const unsigned YMM11_AliasSet[] = { X86::XMM11, 0 };
+ const unsigned YMM12_AliasSet[] = { X86::XMM12, 0 };
+ const unsigned YMM13_AliasSet[] = { X86::XMM13, 0 };
+ const unsigned YMM14_AliasSet[] = { X86::XMM14, 0 };
+ const unsigned YMM15_AliasSet[] = { X86::XMM15, 0 };
+ const unsigned YMM2_AliasSet[] = { X86::XMM2, 0 };
+ const unsigned YMM3_AliasSet[] = { X86::XMM3, 0 };
+ const unsigned YMM4_AliasSet[] = { X86::XMM4, 0 };
+ const unsigned YMM5_AliasSet[] = { X86::XMM5, 0 };
+ const unsigned YMM6_AliasSet[] = { X86::XMM6, 0 };
+ const unsigned YMM7_AliasSet[] = { X86::XMM7, 0 };
+ const unsigned YMM8_AliasSet[] = { X86::XMM8, 0 };
+ const unsigned YMM9_AliasSet[] = { X86::XMM9, 0 };
// Register Sub-registers Sets...
@@ -3732,22 +3732,22 @@ X86::NoRegister, X86::NoRegister };
const unsigned XMM7_SubRegsSet[] = { 0 };
const unsigned XMM8_SubRegsSet[] = { 0 };
const unsigned XMM9_SubRegsSet[] = { 0 };
- const unsigned YMM0_SubRegsSet[] = { 0 };
- const unsigned YMM1_SubRegsSet[] = { 0 };
- const unsigned YMM10_SubRegsSet[] = { 0 };
- const unsigned YMM11_SubRegsSet[] = { 0 };
- const unsigned YMM12_SubRegsSet[] = { 0 };
- const unsigned YMM13_SubRegsSet[] = { 0 };
- const unsigned YMM14_SubRegsSet[] = { 0 };
- const unsigned YMM15_SubRegsSet[] = { 0 };
- const unsigned YMM2_SubRegsSet[] = { 0 };
- const unsigned YMM3_SubRegsSet[] = { 0 };
- const unsigned YMM4_SubRegsSet[] = { 0 };
- const unsigned YMM5_SubRegsSet[] = { 0 };
- const unsigned YMM6_SubRegsSet[] = { 0 };
- const unsigned YMM7_SubRegsSet[] = { 0 };
- const unsigned YMM8_SubRegsSet[] = { 0 };
- const unsigned YMM9_SubRegsSet[] = { 0 };
+ const unsigned YMM0_SubRegsSet[] = { X86::XMM0, 0 };
+ const unsigned YMM1_SubRegsSet[] = { X86::XMM1, 0 };
+ const unsigned YMM10_SubRegsSet[] = { X86::XMM10, 0 };
+ const unsigned YMM11_SubRegsSet[] = { X86::XMM11, 0 };
+ const unsigned YMM12_SubRegsSet[] = { X86::XMM12, 0 };
+ const unsigned YMM13_SubRegsSet[] = { X86::XMM13, 0 };
+ const unsigned YMM14_SubRegsSet[] = { X86::XMM14, 0 };
+ const unsigned YMM15_SubRegsSet[] = { X86::XMM15, 0 };
+ const unsigned YMM2_SubRegsSet[] = { X86::XMM2, 0 };
+ const unsigned YMM3_SubRegsSet[] = { X86::XMM3, 0 };
+ const unsigned YMM4_SubRegsSet[] = { X86::XMM4, 0 };
+ const unsigned YMM5_SubRegsSet[] = { X86::XMM5, 0 };
+ const unsigned YMM6_SubRegsSet[] = { X86::XMM6, 0 };
+ const unsigned YMM7_SubRegsSet[] = { X86::XMM7, 0 };
+ const unsigned YMM8_SubRegsSet[] = { X86::XMM8, 0 };
+ const unsigned YMM9_SubRegsSet[] = { X86::XMM9, 0 };
// Register Super-registers Sets...
@@ -3878,22 +3878,22 @@ X86::NoRegister, X86::NoRegister };
const unsigned ST5_SuperRegsSet[] = { 0 };
const unsigned ST6_SuperRegsSet[] = { 0 };
const unsigned ST7_SuperRegsSet[] = { 0 };
- const unsigned XMM0_SuperRegsSet[] = { 0 };
- const unsigned XMM1_SuperRegsSet[] = { 0 };
- const unsigned XMM10_SuperRegsSet[] = { 0 };
- const unsigned XMM11_SuperRegsSet[] = { 0 };
- const unsigned XMM12_SuperRegsSet[] = { 0 };
- const unsigned XMM13_SuperRegsSet[] = { 0 };
- const unsigned XMM14_SuperRegsSet[] = { 0 };
- const unsigned XMM15_SuperRegsSet[] = { 0 };
- const unsigned XMM2_SuperRegsSet[] = { 0 };
- const unsigned XMM3_SuperRegsSet[] = { 0 };
- const unsigned XMM4_SuperRegsSet[] = { 0 };
- const unsigned XMM5_SuperRegsSet[] = { 0 };
- const unsigned XMM6_SuperRegsSet[] = { 0 };
- const unsigned XMM7_SuperRegsSet[] = { 0 };
- const unsigned XMM8_SuperRegsSet[] = { 0 };
- const unsigned XMM9_SuperRegsSet[] = { 0 };
+ const unsigned XMM0_SuperRegsSet[] = { X86::YMM0, 0 };
+ const unsigned XMM1_SuperRegsSet[] = { X86::YMM1, 0 };
+ const unsigned XMM10_SuperRegsSet[] = { X86::YMM10, 0 };
+ const unsigned XMM11_SuperRegsSet[] = { X86::YMM11, 0 };
+ const unsigned XMM12_SuperRegsSet[] = { X86::YMM12, 0 };
+ const unsigned XMM13_SuperRegsSet[] = { X86::YMM13, 0 };
+ const unsigned XMM14_SuperRegsSet[] = { X86::YMM14, 0 };
+ const unsigned XMM15_SuperRegsSet[] = { X86::YMM15, 0 };
+ const unsigned XMM2_SuperRegsSet[] = { X86::YMM2, 0 };
+ const unsigned XMM3_SuperRegsSet[] = { X86::YMM3, 0 };
+ const unsigned XMM4_SuperRegsSet[] = { X86::YMM4, 0 };
+ const unsigned XMM5_SuperRegsSet[] = { X86::YMM5, 0 };
+ const unsigned XMM6_SuperRegsSet[] = { X86::YMM6, 0 };
+ const unsigned XMM7_SuperRegsSet[] = { X86::YMM7, 0 };
+ const unsigned XMM8_SuperRegsSet[] = { X86::YMM8, 0 };
+ const unsigned XMM9_SuperRegsSet[] = { X86::YMM9, 0 };
const unsigned YMM0_SuperRegsSet[] = { 0 };
const unsigned YMM1_SuperRegsSet[] = { 0 };
const unsigned YMM10_SuperRegsSet[] = { 0 };
@@ -4426,100 +4426,244 @@ unsigned X86GenRegisterInfo::getSubReg(unsigned RegNo, unsigned Index) const {
case 4: return X86::R15D;
};
break;
+ case X86::XMM0:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM0;
+ case 2: return X86::XMM0;
+ };
+ break;
+ case X86::XMM1:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM1;
+ case 2: return X86::XMM1;
+ };
+ break;
+ case X86::XMM2:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM2;
+ case 2: return X86::XMM2;
+ };
+ break;
+ case X86::XMM3:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM3;
+ case 2: return X86::XMM3;
+ };
+ break;
+ case X86::XMM4:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM4;
+ case 2: return X86::XMM4;
+ };
+ break;
+ case X86::XMM5:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM5;
+ case 2: return X86::XMM5;
+ };
+ break;
+ case X86::XMM6:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM6;
+ case 2: return X86::XMM6;
+ };
+ break;
+ case X86::XMM7:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM7;
+ case 2: return X86::XMM7;
+ };
+ break;
+ case X86::XMM8:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM8;
+ case 2: return X86::XMM8;
+ };
+ break;
+ case X86::XMM9:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM9;
+ case 2: return X86::XMM9;
+ };
+ break;
+ case X86::XMM10:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM10;
+ case 2: return X86::XMM10;
+ };
+ break;
+ case X86::XMM11:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM11;
+ case 2: return X86::XMM11;
+ };
+ break;
+ case X86::XMM12:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM12;
+ case 2: return X86::XMM12;
+ };
+ break;
+ case X86::XMM13:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM13;
+ case 2: return X86::XMM13;
+ };
+ break;
+ case X86::XMM14:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM14;
+ case 2: return X86::XMM14;
+ };
+ break;
+ case X86::XMM15:
+ switch (Index) {
+ default: return 0;
+ case 1: return X86::XMM15;
+ case 2: return X86::XMM15;
+ };
+ break;
case X86::YMM0:
switch (Index) {
default: return 0;
case 1: return X86::XMM0;
+ case 2: return X86::XMM0;
+ case 3: return X86::XMM0;
};
break;
case X86::YMM1:
switch (Index) {
default: return 0;
case 1: return X86::XMM1;
+ case 2: return X86::XMM1;
+ case 3: return X86::XMM1;
};
break;
case X86::YMM2:
switch (Index) {
default: return 0;
case 1: return X86::XMM2;
+ case 2: return X86::XMM2;
+ case 3: return X86::XMM2;
};
break;
case X86::YMM3:
switch (Index) {
default: return 0;
case 1: return X86::XMM3;
+ case 2: return X86::XMM3;
+ case 3: return X86::XMM3;
};
break;
case X86::YMM4:
switch (Index) {
default: return 0;
case 1: return X86::XMM4;
+ case 2: return X86::XMM4;
+ case 3: return X86::XMM4;
};
break;
case X86::YMM5:
switch (Index) {
default: return 0;
case 1: return X86::XMM5;
+ case 2: return X86::XMM5;
+ case 3: return X86::XMM5;
};
break;
case X86::YMM6:
switch (Index) {
default: return 0;
case 1: return X86::XMM6;
+ case 2: return X86::XMM6;
+ case 3: return X86::XMM6;
};
break;
case X86::YMM7:
switch (Index) {
default: return 0;
case 1: return X86::XMM7;
+ case 2: return X86::XMM7;
+ case 3: return X86::XMM7;
};
break;
case X86::YMM8:
switch (Index) {
default: return 0;
case 1: return X86::XMM8;
+ case 2: return X86::XMM8;
+ case 3: return X86::XMM8;
};
break;
case X86::YMM9:
switch (Index) {
default: return 0;
case 1: return X86::XMM9;
+ case 2: return X86::XMM9;
+ case 3: return X86::XMM9;
};
break;
case X86::YMM10:
switch (Index) {
default: return 0;
case 1: return X86::XMM10;
+ case 2: return X86::XMM10;
+ case 3: return X86::XMM10;
};
break;
case X86::YMM11:
switch (Index) {
default: return 0;
case 1: return X86::XMM11;
+ case 2: return X86::XMM11;
+ case 3: return X86::XMM11;
};
break;
case X86::YMM12:
switch (Index) {
default: return 0;
case 1: return X86::XMM12;
+ case 2: return X86::XMM12;
+ case 3: return X86::XMM12;
};
break;
case X86::YMM13:
switch (Index) {
default: return 0;
case 1: return X86::XMM13;
+ case 2: return X86::XMM13;
+ case 3: return X86::XMM13;
};
break;
case X86::YMM14:
switch (Index) {
default: return 0;
case 1: return X86::XMM14;
+ case 2: return X86::XMM14;
+ case 3: return X86::XMM14;
};
break;
case X86::YMM15:
switch (Index) {
default: return 0;
case 1: return X86::XMM15;
+ case 2: return X86::XMM15;
+ case 3: return X86::XMM15;
};
break;
};
@@ -4734,53 +4878,149 @@ unsigned X86GenRegisterInfo::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) c
if (SubRegNo == X86::R15W) return 3;
if (SubRegNo == X86::R15D) return 4;
return 0;
+ case X86::XMM0:
+ if (SubRegNo == X86::XMM0) return 1;
+ if (SubRegNo == X86::XMM0) return 2;
+ return 0;
+ case X86::XMM1:
+ if (SubRegNo == X86::XMM1) return 1;
+ if (SubRegNo == X86::XMM1) return 2;
+ return 0;
+ case X86::XMM2:
+ if (SubRegNo == X86::XMM2) return 1;
+ if (SubRegNo == X86::XMM2) return 2;
+ return 0;
+ case X86::XMM3:
+ if (SubRegNo == X86::XMM3) return 1;
+ if (SubRegNo == X86::XMM3) return 2;
+ return 0;
+ case X86::XMM4:
+ if (SubRegNo == X86::XMM4) return 1;
+ if (SubRegNo == X86::XMM4) return 2;
+ return 0;
+ case X86::XMM5:
+ if (SubRegNo == X86::XMM5) return 1;
+ if (SubRegNo == X86::XMM5) return 2;
+ return 0;
+ case X86::XMM6:
+ if (SubRegNo == X86::XMM6) return 1;
+ if (SubRegNo == X86::XMM6) return 2;
+ return 0;
+ case X86::XMM7:
+ if (SubRegNo == X86::XMM7) return 1;
+ if (SubRegNo == X86::XMM7) return 2;
+ return 0;
+ case X86::XMM8:
+ if (SubRegNo == X86::XMM8) return 1;
+ if (SubRegNo == X86::XMM8) return 2;
+ return 0;
+ case X86::XMM9:
+ if (SubRegNo == X86::XMM9) return 1;
+ if (SubRegNo == X86::XMM9) return 2;
+ return 0;
+ case X86::XMM10:
+ if (SubRegNo == X86::XMM10) return 1;
+ if (SubRegNo == X86::XMM10) return 2;
+ return 0;
+ case X86::XMM11:
+ if (SubRegNo == X86::XMM11) return 1;
+ if (SubRegNo == X86::XMM11) return 2;
+ return 0;
+ case X86::XMM12:
+ if (SubRegNo == X86::XMM12) return 1;
+ if (SubRegNo == X86::XMM12) return 2;
+ return 0;
+ case X86::XMM13:
+ if (SubRegNo == X86::XMM13) return 1;
+ if (SubRegNo == X86::XMM13) return 2;
+ return 0;
+ case X86::XMM14:
+ if (SubRegNo == X86::XMM14) return 1;
+ if (SubRegNo == X86::XMM14) return 2;
+ return 0;
+ case X86::XMM15:
+ if (SubRegNo == X86::XMM15) return 1;
+ if (SubRegNo == X86::XMM15) return 2;
+ return 0;
case X86::YMM0:
if (SubRegNo == X86::XMM0) return 1;
+ if (SubRegNo == X86::XMM0) return 2;
+ if (SubRegNo == X86::XMM0) return 3;
return 0;
case X86::YMM1:
if (SubRegNo == X86::XMM1) return 1;
+ if (SubRegNo == X86::XMM1) return 2;
+ if (SubRegNo == X86::XMM1) return 3;
return 0;
case X86::YMM2:
if (SubRegNo == X86::XMM2) return 1;
+ if (SubRegNo == X86::XMM2) return 2;
+ if (SubRegNo == X86::XMM2) return 3;
return 0;
case X86::YMM3:
if (SubRegNo == X86::XMM3) return 1;
+ if (SubRegNo == X86::XMM3) return 2;
+ if (SubRegNo == X86::XMM3) return 3;
return 0;
case X86::YMM4:
if (SubRegNo == X86::XMM4) return 1;
+ if (SubRegNo == X86::XMM4) return 2;
+ if (SubRegNo == X86::XMM4) return 3;
return 0;
case X86::YMM5:
if (SubRegNo == X86::XMM5) return 1;
+ if (SubRegNo == X86::XMM5) return 2;
+ if (SubRegNo == X86::XMM5) return 3;
return 0;
case X86::YMM6:
if (SubRegNo == X86::XMM6) return 1;
+ if (SubRegNo == X86::XMM6) return 2;
+ if (SubRegNo == X86::XMM6) return 3;
return 0;
case X86::YMM7:
if (SubRegNo == X86::XMM7) return 1;
+ if (SubRegNo == X86::XMM7) return 2;
+ if (SubRegNo == X86::XMM7) return 3;
return 0;
case X86::YMM8:
if (SubRegNo == X86::XMM8) return 1;
+ if (SubRegNo == X86::XMM8) return 2;
+ if (SubRegNo == X86::XMM8) return 3;
return 0;
case X86::YMM9:
if (SubRegNo == X86::XMM9) return 1;
+ if (SubRegNo == X86::XMM9) return 2;
+ if (SubRegNo == X86::XMM9) return 3;
return 0;
case X86::YMM10:
if (SubRegNo == X86::XMM10) return 1;
+ if (SubRegNo == X86::XMM10) return 2;
+ if (SubRegNo == X86::XMM10) return 3;
return 0;
case X86::YMM11:
if (SubRegNo == X86::XMM11) return 1;
+ if (SubRegNo == X86::XMM11) return 2;
+ if (SubRegNo == X86::XMM11) return 3;
return 0;
case X86::YMM12:
if (SubRegNo == X86::XMM12) return 1;
+ if (SubRegNo == X86::XMM12) return 2;
+ if (SubRegNo == X86::XMM12) return 3;
return 0;
case X86::YMM13:
if (SubRegNo == X86::XMM13) return 1;
+ if (SubRegNo == X86::XMM13) return 2;
+ if (SubRegNo == X86::XMM13) return 3;
return 0;
case X86::YMM14:
if (SubRegNo == X86::XMM14) return 1;
+ if (SubRegNo == X86::XMM14) return 2;
+ if (SubRegNo == X86::XMM14) return 3;
return 0;
case X86::YMM15:
if (SubRegNo == X86::XMM15) return 1;
+ if (SubRegNo == X86::XMM15) return 2;
+ if (SubRegNo == X86::XMM15) return 3;
return 0;
};
return 0;
diff --git a/contrib/entitynorm/ChangeLog b/libclamav/c++/llvm/docs/doxygen.cfg.in
similarity index 100%
copy from contrib/entitynorm/ChangeLog
copy to libclamav/c++/llvm/docs/doxygen.cfg.in
diff --git a/libclamav/c++/strip-llvm.sh b/libclamav/c++/strip-llvm.sh
index 92f0244..663a3bb 100755
--- a/libclamav/c++/strip-llvm.sh
+++ b/libclamav/c++/strip-llvm.sh
@@ -8,6 +8,7 @@ for i in llvm/bindings/ llvm/examples/ llvm/projects/ llvm/runtime/\
llvm/lib/Target/CellSPU/ llvm/lib/Target/CppBackend/ llvm/lib/Target/Mips\
llvm/lib/Target/MSIL llvm/lib/Target/MSP430/ llvm/lib/Target/PIC16\
llvm/lib/Target/Sparc/ llvm/lib/Target/SystemZ llvm/lib/Target/XCore\
+ llvm/lib/Target/MBlaze/ llvm/lib/Target/PIC16/ llvm/lib/Target/MSP430\
llvm/test/Archive/ llvm/test/Bindings/ llvm/test/Bitcode/ llvm/test/DebugInfo/\
llvm/test/FrontendAda/ llvm/test/FrontendC llvm/test/FrontendC++/\
llvm/test/FrontendFortran/ llvm/test/FrontendObjC\
@@ -23,12 +24,13 @@ for i in llvm/bindings/ llvm/examples/ llvm/projects/ llvm/runtime/\
llvm/tools/llvm-extract llvm/tools/llvm-ld llvm/tools/llvm-link llvm/tools/llvm-mc\
llvm/tools/llvm-nm llvm/tools/llvm-prof llvm/tools/llvm-ranlib\
llvm/tools/llvm-stub llvm/tools/lto llvm/tools/opt llvm/lib/MC/MCParser\
- llvm/tools/llvm-dis/Makefile
+ llvm/tools/llvm-dis/Makefile llvm/tools/edis/ llvm/tools/llvm-shlib\
+ llvm/docs
do
git rm -rf $i;
done
-# LLVM's config.status depends on these files existing
-mkdir -p llvm/lib/Target/PIC16/AsmPrinter llvm/lib/Target/MSP430/AsmPrinter
-touch llvm/lib/Target/PIC16/AsmPrinter/Makefile llvm/lib/Target/MSP430/AsmPrinter/Makefile
-git add -f llvm/lib/Target/PIC16/AsmPrinter/Makefile llvm/lib/Target/MSP430/AsmPrinter/Makefile
+# config.status needs these
+mkdir -p llvm/docs/doxygen
+touch llvm/docs/doxygen.cfg.in
+git add llvm/docs/doxygen.cfg.in
mv ../../.git/SQUASH_MSG ../../.git/MERGE_MSG
--
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